1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm_adsp.c -- Wolfson ADSP support
5 * Copyright 2012 Wolfson Microelectronics plc
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
10 #include <linux/ctype.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/firmware.h>
16 #include <linux/list.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <linux/vmalloc.h>
23 #include <linux/workqueue.h>
24 #include <linux/debugfs.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
35 #define adsp_crit(_dsp, fmt, ...) \
36 dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
37 #define adsp_err(_dsp, fmt, ...) \
38 dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
39 #define adsp_warn(_dsp, fmt, ...) \
40 dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
41 #define adsp_info(_dsp, fmt, ...) \
42 dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
43 #define adsp_dbg(_dsp, fmt, ...) \
44 dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
46 #define compr_err(_obj, fmt, ...) \
47 adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
49 #define compr_dbg(_obj, fmt, ...) \
50 adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
53 #define ADSP1_CONTROL_1 0x00
54 #define ADSP1_CONTROL_2 0x02
55 #define ADSP1_CONTROL_3 0x03
56 #define ADSP1_CONTROL_4 0x04
57 #define ADSP1_CONTROL_5 0x06
58 #define ADSP1_CONTROL_6 0x07
59 #define ADSP1_CONTROL_7 0x08
60 #define ADSP1_CONTROL_8 0x09
61 #define ADSP1_CONTROL_9 0x0A
62 #define ADSP1_CONTROL_10 0x0B
63 #define ADSP1_CONTROL_11 0x0C
64 #define ADSP1_CONTROL_12 0x0D
65 #define ADSP1_CONTROL_13 0x0F
66 #define ADSP1_CONTROL_14 0x10
67 #define ADSP1_CONTROL_15 0x11
68 #define ADSP1_CONTROL_16 0x12
69 #define ADSP1_CONTROL_17 0x13
70 #define ADSP1_CONTROL_18 0x14
71 #define ADSP1_CONTROL_19 0x16
72 #define ADSP1_CONTROL_20 0x17
73 #define ADSP1_CONTROL_21 0x18
74 #define ADSP1_CONTROL_22 0x1A
75 #define ADSP1_CONTROL_23 0x1B
76 #define ADSP1_CONTROL_24 0x1C
77 #define ADSP1_CONTROL_25 0x1E
78 #define ADSP1_CONTROL_26 0x20
79 #define ADSP1_CONTROL_27 0x21
80 #define ADSP1_CONTROL_28 0x22
81 #define ADSP1_CONTROL_29 0x23
82 #define ADSP1_CONTROL_30 0x24
83 #define ADSP1_CONTROL_31 0x26
88 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
89 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
90 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
96 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
97 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
98 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
99 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
100 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
101 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
102 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
103 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
104 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
105 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
106 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
107 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
108 #define ADSP1_START 0x0001 /* DSP1_START */
109 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
110 #define ADSP1_START_SHIFT 0 /* DSP1_START */
111 #define ADSP1_START_WIDTH 1 /* DSP1_START */
116 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
117 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
118 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
120 #define ADSP2_CONTROL 0x0
121 #define ADSP2_CLOCKING 0x1
122 #define ADSP2V2_CLOCKING 0x2
123 #define ADSP2_STATUS1 0x4
124 #define ADSP2_WDMA_CONFIG_1 0x30
125 #define ADSP2_WDMA_CONFIG_2 0x31
126 #define ADSP2V2_WDMA_CONFIG_2 0x32
127 #define ADSP2_RDMA_CONFIG_1 0x34
129 #define ADSP2_SCRATCH0 0x40
130 #define ADSP2_SCRATCH1 0x41
131 #define ADSP2_SCRATCH2 0x42
132 #define ADSP2_SCRATCH3 0x43
134 #define ADSP2V2_SCRATCH0_1 0x40
135 #define ADSP2V2_SCRATCH2_3 0x42
141 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
142 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
143 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
144 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
145 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
146 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
147 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
148 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
149 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
150 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
151 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
152 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
153 #define ADSP2_START 0x0001 /* DSP1_START */
154 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
155 #define ADSP2_START_SHIFT 0 /* DSP1_START */
156 #define ADSP2_START_WIDTH 1 /* DSP1_START */
161 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
162 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
163 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
168 #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */
169 #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */
170 #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
172 #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */
173 #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */
174 #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */
179 #define ADSP2_RAM_RDY 0x0001
180 #define ADSP2_RAM_RDY_MASK 0x0001
181 #define ADSP2_RAM_RDY_SHIFT 0
182 #define ADSP2_RAM_RDY_WIDTH 1
187 #define ADSP2_LOCK_CODE_0 0x5555
188 #define ADSP2_LOCK_CODE_1 0xAAAA
190 #define ADSP2_WATCHDOG 0x0A
191 #define ADSP2_BUS_ERR_ADDR 0x52
192 #define ADSP2_REGION_LOCK_STATUS 0x64
193 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66
194 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68
195 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A
196 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C
197 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E
198 #define ADSP2_LOCK_REGION_CTRL 0x7A
199 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C
201 #define ADSP2_REGION_LOCK_ERR_MASK 0x8000
202 #define ADSP2_ADDR_ERR_MASK 0x4000
203 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000
204 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002
205 #define ADSP2_CTRL_ERR_EINT 0x0001
207 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF
208 #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF
209 #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000
210 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16
211 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD
213 #define ADSP2_LOCK_REGION_SHIFT 16
215 #define ADSP_MAX_STD_CTRL_SIZE 512
217 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
218 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
219 #define WM_ADSP_ACKED_CTL_MIN_VALUE 0
220 #define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF
223 * Event control messages
225 #define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
230 #define HALO_AHBM_WINDOW_DEBUG_0 0x02040
231 #define HALO_AHBM_WINDOW_DEBUG_1 0x02044
236 #define HALO_SCRATCH1 0x005c0
237 #define HALO_SCRATCH2 0x005c8
238 #define HALO_SCRATCH3 0x005d0
239 #define HALO_SCRATCH4 0x005d8
240 #define HALO_CCM_CORE_CONTROL 0x41000
241 #define HALO_CORE_SOFT_RESET 0x00010
242 #define HALO_WDT_CONTROL 0x47000
247 #define HALO_MPU_XMEM_ACCESS_0 0x43000
248 #define HALO_MPU_YMEM_ACCESS_0 0x43004
249 #define HALO_MPU_WINDOW_ACCESS_0 0x43008
250 #define HALO_MPU_XREG_ACCESS_0 0x4300C
251 #define HALO_MPU_YREG_ACCESS_0 0x43014
252 #define HALO_MPU_XMEM_ACCESS_1 0x43018
253 #define HALO_MPU_YMEM_ACCESS_1 0x4301C
254 #define HALO_MPU_WINDOW_ACCESS_1 0x43020
255 #define HALO_MPU_XREG_ACCESS_1 0x43024
256 #define HALO_MPU_YREG_ACCESS_1 0x4302C
257 #define HALO_MPU_XMEM_ACCESS_2 0x43030
258 #define HALO_MPU_YMEM_ACCESS_2 0x43034
259 #define HALO_MPU_WINDOW_ACCESS_2 0x43038
260 #define HALO_MPU_XREG_ACCESS_2 0x4303C
261 #define HALO_MPU_YREG_ACCESS_2 0x43044
262 #define HALO_MPU_XMEM_ACCESS_3 0x43048
263 #define HALO_MPU_YMEM_ACCESS_3 0x4304C
264 #define HALO_MPU_WINDOW_ACCESS_3 0x43050
265 #define HALO_MPU_XREG_ACCESS_3 0x43054
266 #define HALO_MPU_YREG_ACCESS_3 0x4305C
267 #define HALO_MPU_XM_VIO_ADDR 0x43100
268 #define HALO_MPU_XM_VIO_STATUS 0x43104
269 #define HALO_MPU_YM_VIO_ADDR 0x43108
270 #define HALO_MPU_YM_VIO_STATUS 0x4310C
271 #define HALO_MPU_PM_VIO_ADDR 0x43110
272 #define HALO_MPU_PM_VIO_STATUS 0x43114
273 #define HALO_MPU_LOCK_CONFIG 0x43140
276 * HALO_AHBM_WINDOW_DEBUG_1
278 #define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00
279 #define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8
280 #define HALO_AHBM_FLAGS_ERR_MASK 0x000000ff
283 * HALO_CCM_CORE_CONTROL
285 #define HALO_CORE_RESET 0x00000200
286 #define HALO_CORE_EN 0x00000001
289 * HALO_CORE_SOFT_RESET
291 #define HALO_CORE_SOFT_RESET_MASK 0x00000001
296 #define HALO_WDT_EN_MASK 0x00000001
299 * HALO_MPU_?M_VIO_STATUS
301 #define HALO_MPU_VIO_STS_MASK 0x007e0000
302 #define HALO_MPU_VIO_STS_SHIFT 17
303 #define HALO_MPU_VIO_ERR_WR_MASK 0x00008000
304 #define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff
305 #define HALO_MPU_VIO_ERR_SRC_SHIFT 0
307 static const struct wm_adsp_ops wm_adsp1_ops;
308 static const struct wm_adsp_ops wm_adsp2_ops[];
309 static const struct wm_adsp_ops wm_halo_ops;
312 struct list_head list;
316 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
317 struct list_head *list)
319 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
324 buf->buf = vmalloc(len);
329 memcpy(buf->buf, src, len);
332 list_add_tail(&buf->list, list);
337 static void wm_adsp_buf_free(struct list_head *list)
339 while (!list_empty(list)) {
340 struct wm_adsp_buf *buf = list_first_entry(list,
343 list_del(&buf->list);
349 #define WM_ADSP_FW_MBC_VSS 0
350 #define WM_ADSP_FW_HIFI 1
351 #define WM_ADSP_FW_TX 2
352 #define WM_ADSP_FW_TX_SPK 3
353 #define WM_ADSP_FW_RX 4
354 #define WM_ADSP_FW_RX_ANC 5
355 #define WM_ADSP_FW_CTRL 6
356 #define WM_ADSP_FW_ASR 7
357 #define WM_ADSP_FW_TRACE 8
358 #define WM_ADSP_FW_SPK_PROT 9
359 #define WM_ADSP_FW_SPK_CALI 10
360 #define WM_ADSP_FW_SPK_DIAG 11
361 #define WM_ADSP_FW_MISC 12
363 #define WM_ADSP_NUM_FW 13
365 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
366 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
367 [WM_ADSP_FW_HIFI] = "MasterHiFi",
368 [WM_ADSP_FW_TX] = "Tx",
369 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
370 [WM_ADSP_FW_RX] = "Rx",
371 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
372 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
373 [WM_ADSP_FW_ASR] = "ASR Assist",
374 [WM_ADSP_FW_TRACE] = "Dbg Trace",
375 [WM_ADSP_FW_SPK_PROT] = "Protection",
376 [WM_ADSP_FW_SPK_CALI] = "Calibration",
377 [WM_ADSP_FW_SPK_DIAG] = "Diagnostic",
378 [WM_ADSP_FW_MISC] = "Misc",
381 struct wm_adsp_system_config_xm_hdr {
387 __be32 dma_buffer_size;
390 __be32 build_job_name[3];
391 __be32 build_job_number;
394 struct wm_halo_system_config_xm_hdr {
395 __be32 halo_heartbeat;
396 __be32 build_job_name[3];
397 __be32 build_job_number;
400 struct wm_adsp_alg_xm_struct {
406 __be32 high_water_mark;
407 __be32 low_water_mark;
408 __be64 smoothed_power;
411 struct wm_adsp_host_buf_coeff_v1 {
412 __be32 host_buf_ptr; /* Host buffer pointer */
413 __be32 versions; /* Version numbers */
414 __be32 name[4]; /* The buffer name */
417 struct wm_adsp_buffer {
418 __be32 buf1_base; /* Base addr of first buffer area */
419 __be32 buf1_size; /* Size of buf1 area in DSP words */
420 __be32 buf2_base; /* Base addr of 2nd buffer area */
421 __be32 buf1_buf2_size; /* Size of buf1+buf2 in DSP words */
422 __be32 buf3_base; /* Base addr of buf3 area */
423 __be32 buf_total_size; /* Size of buf1+buf2+buf3 in DSP words */
424 __be32 high_water_mark; /* Point at which IRQ is asserted */
425 __be32 irq_count; /* bits 1-31 count IRQ assertions */
426 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
427 __be32 next_write_index; /* word index of next write */
428 __be32 next_read_index; /* word index of next read */
429 __be32 error; /* error if any */
430 __be32 oldest_block_index; /* word index of oldest surviving */
431 __be32 requested_rewind; /* how many blocks rewind was done */
432 __be32 reserved_space; /* internal */
433 __be32 min_free; /* min free space since stream start */
434 __be32 blocks_written[2]; /* total blocks written (64 bit) */
435 __be32 words_written[2]; /* total words written (64 bit) */
438 struct wm_adsp_compr;
440 struct wm_adsp_compr_buf {
441 struct list_head list;
443 struct wm_adsp_compr *compr;
445 struct wm_adsp_buffer_region *regions;
452 int host_buf_mem_type;
457 struct wm_adsp_compr {
458 struct list_head list;
460 struct wm_adsp_compr_buf *buf;
462 struct snd_compr_stream *stream;
463 struct snd_compressed_buffer size;
466 unsigned int copied_total;
468 unsigned int sample_rate;
473 #define WM_ADSP_DATA_WORD_SIZE 3
475 #define WM_ADSP_MIN_FRAGMENTS 1
476 #define WM_ADSP_MAX_FRAGMENTS 256
477 #define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
478 #define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
480 #define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
482 #define HOST_BUFFER_FIELD(field) \
483 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
485 #define ALG_XM_FIELD(field) \
486 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
488 #define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER 1
490 #define HOST_BUF_COEFF_COMPAT_VER_MASK 0xFF00
491 #define HOST_BUF_COEFF_COMPAT_VER_SHIFT 8
493 static int wm_adsp_buffer_init(struct wm_adsp *dsp);
494 static int wm_adsp_buffer_free(struct wm_adsp *dsp);
496 struct wm_adsp_buffer_region {
498 unsigned int cumulative_size;
499 unsigned int mem_type;
500 unsigned int base_addr;
503 struct wm_adsp_buffer_region_def {
504 unsigned int mem_type;
505 unsigned int base_offset;
506 unsigned int size_offset;
509 static const struct wm_adsp_buffer_region_def default_regions[] = {
511 .mem_type = WMFW_ADSP2_XM,
512 .base_offset = HOST_BUFFER_FIELD(buf1_base),
513 .size_offset = HOST_BUFFER_FIELD(buf1_size),
516 .mem_type = WMFW_ADSP2_XM,
517 .base_offset = HOST_BUFFER_FIELD(buf2_base),
518 .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size),
521 .mem_type = WMFW_ADSP2_YM,
522 .base_offset = HOST_BUFFER_FIELD(buf3_base),
523 .size_offset = HOST_BUFFER_FIELD(buf_total_size),
527 struct wm_adsp_fw_caps {
529 struct snd_codec_desc desc;
531 const struct wm_adsp_buffer_region_def *region_defs;
534 static const struct wm_adsp_fw_caps ctrl_caps[] = {
536 .id = SND_AUDIOCODEC_BESPOKE,
539 .sample_rates = { 16000 },
540 .num_sample_rates = 1,
541 .formats = SNDRV_PCM_FMTBIT_S16_LE,
543 .num_regions = ARRAY_SIZE(default_regions),
544 .region_defs = default_regions,
548 static const struct wm_adsp_fw_caps trace_caps[] = {
550 .id = SND_AUDIOCODEC_BESPOKE,
554 4000, 8000, 11025, 12000, 16000, 22050,
555 24000, 32000, 44100, 48000, 64000, 88200,
556 96000, 176400, 192000
558 .num_sample_rates = 15,
559 .formats = SNDRV_PCM_FMTBIT_S16_LE,
561 .num_regions = ARRAY_SIZE(default_regions),
562 .region_defs = default_regions,
566 static const struct {
570 const struct wm_adsp_fw_caps *caps;
572 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
573 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
574 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
575 [WM_ADSP_FW_TX] = { .file = "tx" },
576 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
577 [WM_ADSP_FW_RX] = { .file = "rx" },
578 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
579 [WM_ADSP_FW_CTRL] = {
581 .compr_direction = SND_COMPRESS_CAPTURE,
582 .num_caps = ARRAY_SIZE(ctrl_caps),
584 .voice_trigger = true,
586 [WM_ADSP_FW_ASR] = { .file = "asr" },
587 [WM_ADSP_FW_TRACE] = {
589 .compr_direction = SND_COMPRESS_CAPTURE,
590 .num_caps = ARRAY_SIZE(trace_caps),
593 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
594 [WM_ADSP_FW_SPK_CALI] = { .file = "spk-cali" },
595 [WM_ADSP_FW_SPK_DIAG] = { .file = "spk-diag" },
596 [WM_ADSP_FW_MISC] = { .file = "misc" },
599 struct wm_coeff_ctl {
602 /* Subname is needed to match with firmware */
604 unsigned int subname_len;
605 struct wm_adsp_alg_region alg_region;
607 unsigned int enabled:1;
608 struct list_head list;
613 struct soc_bytes_ext bytes_ext;
615 snd_ctl_elem_type_t type;
618 static const char *wm_adsp_mem_region_name(unsigned int type)
623 case WMFW_HALO_PM_PACKED:
629 case WMFW_HALO_XM_PACKED:
633 case WMFW_HALO_YM_PACKED:
642 #ifdef CONFIG_DEBUG_FS
643 static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
645 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
647 kfree(dsp->wmfw_file_name);
648 dsp->wmfw_file_name = tmp;
651 static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
653 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
655 kfree(dsp->bin_file_name);
656 dsp->bin_file_name = tmp;
659 static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
661 kfree(dsp->wmfw_file_name);
662 kfree(dsp->bin_file_name);
663 dsp->wmfw_file_name = NULL;
664 dsp->bin_file_name = NULL;
667 static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
668 char __user *user_buf,
669 size_t count, loff_t *ppos)
671 struct wm_adsp *dsp = file->private_data;
674 mutex_lock(&dsp->pwr_lock);
676 if (!dsp->wmfw_file_name || !dsp->booted)
679 ret = simple_read_from_buffer(user_buf, count, ppos,
681 strlen(dsp->wmfw_file_name));
683 mutex_unlock(&dsp->pwr_lock);
687 static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
688 char __user *user_buf,
689 size_t count, loff_t *ppos)
691 struct wm_adsp *dsp = file->private_data;
694 mutex_lock(&dsp->pwr_lock);
696 if (!dsp->bin_file_name || !dsp->booted)
699 ret = simple_read_from_buffer(user_buf, count, ppos,
701 strlen(dsp->bin_file_name));
703 mutex_unlock(&dsp->pwr_lock);
707 static const struct {
709 const struct file_operations fops;
710 } wm_adsp_debugfs_fops[] = {
712 .name = "wmfw_file_name",
715 .read = wm_adsp_debugfs_wmfw_read,
719 .name = "bin_file_name",
722 .read = wm_adsp_debugfs_bin_read,
727 static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
728 struct snd_soc_component *component)
730 struct dentry *root = NULL;
733 root = debugfs_create_dir(dsp->name, component->debugfs_root);
735 debugfs_create_bool("booted", 0444, root, &dsp->booted);
736 debugfs_create_bool("running", 0444, root, &dsp->running);
737 debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id);
738 debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version);
740 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i)
741 debugfs_create_file(wm_adsp_debugfs_fops[i].name, 0444, root,
742 dsp, &wm_adsp_debugfs_fops[i].fops);
744 dsp->debugfs_root = root;
747 static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
749 wm_adsp_debugfs_clear(dsp);
750 debugfs_remove_recursive(dsp->debugfs_root);
753 static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
754 struct snd_soc_component *component)
758 static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
762 static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
767 static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
772 static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
777 int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
778 struct snd_ctl_elem_value *ucontrol)
780 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
781 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
782 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
784 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
788 EXPORT_SYMBOL_GPL(wm_adsp_fw_get);
790 int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
791 struct snd_ctl_elem_value *ucontrol)
793 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
794 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
795 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
798 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
801 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
804 mutex_lock(&dsp[e->shift_l].pwr_lock);
806 if (dsp[e->shift_l].booted || !list_empty(&dsp[e->shift_l].compr_list))
809 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
811 mutex_unlock(&dsp[e->shift_l].pwr_lock);
815 EXPORT_SYMBOL_GPL(wm_adsp_fw_put);
817 const struct soc_enum wm_adsp_fw_enum[] = {
818 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
819 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
820 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
821 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
822 SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
823 SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
824 SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
826 EXPORT_SYMBOL_GPL(wm_adsp_fw_enum);
828 static const struct wm_adsp_region *wm_adsp_find_region(struct wm_adsp *dsp,
833 for (i = 0; i < dsp->num_mems; i++)
834 if (dsp->mem[i].type == type)
840 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
845 return mem->base + (offset * 3);
850 return mem->base + (offset * 2);
852 WARN(1, "Unknown memory region type");
857 static unsigned int wm_halo_region_to_reg(struct wm_adsp_region const *mem,
863 return mem->base + (offset * 4);
864 case WMFW_HALO_XM_PACKED:
865 case WMFW_HALO_YM_PACKED:
866 return (mem->base + (offset * 3)) & ~0x3;
867 case WMFW_HALO_PM_PACKED:
868 return mem->base + (offset * 5);
870 WARN(1, "Unknown memory region type");
875 static void wm_adsp_read_fw_status(struct wm_adsp *dsp,
876 int noffs, unsigned int *offs)
881 for (i = 0; i < noffs; ++i) {
882 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]);
884 adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret);
890 static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
892 unsigned int offs[] = {
893 ADSP2_SCRATCH0, ADSP2_SCRATCH1, ADSP2_SCRATCH2, ADSP2_SCRATCH3,
896 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
898 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
899 offs[0], offs[1], offs[2], offs[3]);
902 static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
904 unsigned int offs[] = { ADSP2V2_SCRATCH0_1, ADSP2V2_SCRATCH2_3 };
906 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
908 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
909 offs[0] & 0xFFFF, offs[0] >> 16,
910 offs[1] & 0xFFFF, offs[1] >> 16);
913 static void wm_halo_show_fw_status(struct wm_adsp *dsp)
915 unsigned int offs[] = {
916 HALO_SCRATCH1, HALO_SCRATCH2, HALO_SCRATCH3, HALO_SCRATCH4,
919 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
921 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
922 offs[0], offs[1], offs[2], offs[3]);
925 static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
927 return container_of(ext, struct wm_coeff_ctl, bytes_ext);
930 static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
932 const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
933 struct wm_adsp *dsp = ctl->dsp;
934 const struct wm_adsp_region *mem;
936 mem = wm_adsp_find_region(dsp, alg_region->type);
938 adsp_err(dsp, "No base for region %x\n",
943 *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset);
948 static int wm_coeff_info(struct snd_kcontrol *kctl,
949 struct snd_ctl_elem_info *uinfo)
951 struct soc_bytes_ext *bytes_ext =
952 (struct soc_bytes_ext *)kctl->private_value;
953 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
956 case WMFW_CTL_TYPE_ACKED:
957 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
958 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
959 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
960 uinfo->value.integer.step = 1;
964 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
965 uinfo->count = ctl->len;
972 static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
973 unsigned int event_id)
975 struct wm_adsp *dsp = ctl->dsp;
976 __be32 val = cpu_to_be32(event_id);
980 ret = wm_coeff_base_reg(ctl, ®);
984 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
985 event_id, ctl->alg_region.alg,
986 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
988 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
990 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
995 * Poll for ack, we initially poll at ~1ms intervals for firmwares
996 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
997 * to ack instantly so we do the first 1ms delay before reading the
998 * control to avoid a pointless bus transaction
1000 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
1002 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
1003 usleep_range(1000, 2000);
1007 usleep_range(10000, 20000);
1012 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
1014 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
1019 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
1024 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
1025 reg, ctl->alg_region.alg,
1026 wm_adsp_mem_region_name(ctl->alg_region.type),
1032 static int wm_coeff_write_ctrl_raw(struct wm_coeff_ctl *ctl,
1033 const void *buf, size_t len)
1035 struct wm_adsp *dsp = ctl->dsp;
1040 ret = wm_coeff_base_reg(ctl, ®);
1044 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
1048 ret = regmap_raw_write(dsp->regmap, reg, scratch,
1051 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
1056 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
1063 static int wm_coeff_write_ctrl(struct wm_coeff_ctl *ctl,
1064 const void *buf, size_t len)
1068 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1070 else if (buf != ctl->cache)
1071 memcpy(ctl->cache, buf, len);
1074 if (ctl->enabled && ctl->dsp->running)
1075 ret = wm_coeff_write_ctrl_raw(ctl, buf, len);
1080 static int wm_coeff_put(struct snd_kcontrol *kctl,
1081 struct snd_ctl_elem_value *ucontrol)
1083 struct soc_bytes_ext *bytes_ext =
1084 (struct soc_bytes_ext *)kctl->private_value;
1085 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1086 char *p = ucontrol->value.bytes.data;
1089 mutex_lock(&ctl->dsp->pwr_lock);
1090 ret = wm_coeff_write_ctrl(ctl, p, ctl->len);
1091 mutex_unlock(&ctl->dsp->pwr_lock);
1096 static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
1097 const unsigned int __user *bytes, unsigned int size)
1099 struct soc_bytes_ext *bytes_ext =
1100 (struct soc_bytes_ext *)kctl->private_value;
1101 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1104 mutex_lock(&ctl->dsp->pwr_lock);
1106 if (copy_from_user(ctl->cache, bytes, size))
1109 ret = wm_coeff_write_ctrl(ctl, ctl->cache, size);
1111 mutex_unlock(&ctl->dsp->pwr_lock);
1116 static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
1117 struct snd_ctl_elem_value *ucontrol)
1119 struct soc_bytes_ext *bytes_ext =
1120 (struct soc_bytes_ext *)kctl->private_value;
1121 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1122 unsigned int val = ucontrol->value.integer.value[0];
1126 return 0; /* 0 means no event */
1128 mutex_lock(&ctl->dsp->pwr_lock);
1130 if (ctl->enabled && ctl->dsp->running)
1131 ret = wm_coeff_write_acked_control(ctl, val);
1135 mutex_unlock(&ctl->dsp->pwr_lock);
1140 static int wm_coeff_read_ctrl_raw(struct wm_coeff_ctl *ctl,
1141 void *buf, size_t len)
1143 struct wm_adsp *dsp = ctl->dsp;
1148 ret = wm_coeff_base_reg(ctl, ®);
1152 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
1156 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
1158 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
1163 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
1165 memcpy(buf, scratch, len);
1171 static int wm_coeff_read_ctrl(struct wm_coeff_ctl *ctl, void *buf, size_t len)
1175 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1176 if (ctl->enabled && ctl->dsp->running)
1177 return wm_coeff_read_ctrl_raw(ctl, buf, len);
1181 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1182 ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len);
1184 if (buf != ctl->cache)
1185 memcpy(buf, ctl->cache, len);
1191 static int wm_coeff_get(struct snd_kcontrol *kctl,
1192 struct snd_ctl_elem_value *ucontrol)
1194 struct soc_bytes_ext *bytes_ext =
1195 (struct soc_bytes_ext *)kctl->private_value;
1196 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1197 char *p = ucontrol->value.bytes.data;
1200 mutex_lock(&ctl->dsp->pwr_lock);
1201 ret = wm_coeff_read_ctrl(ctl, p, ctl->len);
1202 mutex_unlock(&ctl->dsp->pwr_lock);
1207 static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1208 unsigned int __user *bytes, unsigned int size)
1210 struct soc_bytes_ext *bytes_ext =
1211 (struct soc_bytes_ext *)kctl->private_value;
1212 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1215 mutex_lock(&ctl->dsp->pwr_lock);
1217 ret = wm_coeff_read_ctrl(ctl, ctl->cache, size);
1219 if (!ret && copy_to_user(bytes, ctl->cache, size))
1222 mutex_unlock(&ctl->dsp->pwr_lock);
1227 static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1228 struct snd_ctl_elem_value *ucontrol)
1231 * Although it's not useful to read an acked control, we must satisfy
1232 * user-side assumptions that all controls are readable and that a
1233 * write of the same value should be filtered out (it's valid to send
1234 * the same event number again to the firmware). We therefore return 0,
1235 * meaning "no event" so valid event numbers will always be a change
1237 ucontrol->value.integer.value[0] = 0;
1242 struct wmfw_ctl_work {
1243 struct wm_adsp *dsp;
1244 struct wm_coeff_ctl *ctl;
1245 struct work_struct work;
1248 static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1250 unsigned int out, rd, wr, vol;
1252 if (len > ADSP_MAX_STD_CTRL_SIZE) {
1253 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1254 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1255 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1257 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1259 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1260 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1261 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1268 if (in & WMFW_CTL_FLAG_WRITEABLE)
1270 if (in & WMFW_CTL_FLAG_VOLATILE)
1273 out |= rd | wr | vol;
1279 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
1281 struct snd_kcontrol_new *kcontrol;
1284 if (!ctl || !ctl->name)
1287 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1291 kcontrol->name = ctl->name;
1292 kcontrol->info = wm_coeff_info;
1293 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1294 kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1295 kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
1296 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
1298 switch (ctl->type) {
1299 case WMFW_CTL_TYPE_ACKED:
1300 kcontrol->get = wm_coeff_get_acked;
1301 kcontrol->put = wm_coeff_put_acked;
1304 if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1305 ctl->bytes_ext.max = ctl->len;
1306 ctl->bytes_ext.get = wm_coeff_tlv_get;
1307 ctl->bytes_ext.put = wm_coeff_tlv_put;
1309 kcontrol->get = wm_coeff_get;
1310 kcontrol->put = wm_coeff_put;
1315 ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1);
1328 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1330 struct wm_coeff_ctl *ctl;
1333 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1334 if (!ctl->enabled || ctl->set)
1336 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1340 * For readable controls populate the cache from the DSP memory.
1341 * For non-readable controls the cache was zero-filled when
1342 * created so we don't need to do anything.
1344 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) {
1345 ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len);
1354 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1356 struct wm_coeff_ctl *ctl;
1359 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1362 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
1363 ret = wm_coeff_write_ctrl_raw(ctl, ctl->cache,
1373 static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1376 struct wm_coeff_ctl *ctl;
1379 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1380 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1386 ret = wm_coeff_write_acked_control(ctl, event);
1389 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1390 event, ctl->alg_region.alg, ret);
1394 static void wm_adsp_ctl_work(struct work_struct *work)
1396 struct wmfw_ctl_work *ctl_work = container_of(work,
1397 struct wmfw_ctl_work,
1400 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1404 static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1408 kfree(ctl->subname);
1412 static int wm_adsp_create_control(struct wm_adsp *dsp,
1413 const struct wm_adsp_alg_region *alg_region,
1414 unsigned int offset, unsigned int len,
1415 const char *subname, unsigned int subname_len,
1416 unsigned int flags, snd_ctl_elem_type_t type)
1418 struct wm_coeff_ctl *ctl;
1419 struct wmfw_ctl_work *ctl_work;
1420 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
1421 const char *region_name;
1424 region_name = wm_adsp_mem_region_name(alg_region->type);
1426 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
1430 switch (dsp->fw_ver) {
1433 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s %x",
1434 dsp->name, region_name, alg_region->alg);
1435 subname = NULL; /* don't append subname */
1438 ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1439 "%s%c %.12s %x", dsp->name, *region_name,
1440 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1443 ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1444 "%s %.12s %x", dsp->name,
1445 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1450 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1453 if (dsp->component->name_prefix)
1454 avail -= strlen(dsp->component->name_prefix) + 1;
1456 /* Truncate the subname from the start if it is too long */
1457 if (subname_len > avail)
1458 skip = subname_len - avail;
1460 snprintf(name + ret, SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret,
1461 " %.*s", subname_len - skip, subname + skip);
1464 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1465 if (!strcmp(ctl->name, name)) {
1472 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1475 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
1476 ctl->alg_region = *alg_region;
1477 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1483 ctl->subname_len = subname_len;
1484 ctl->subname = kmemdup(subname,
1485 strlen(subname) + 1, GFP_KERNEL);
1486 if (!ctl->subname) {
1497 ctl->offset = offset;
1499 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1502 goto err_ctl_subname;
1505 list_add(&ctl->list, &dsp->ctl_list);
1507 if (flags & WMFW_CTL_FLAG_SYS)
1510 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1516 ctl_work->dsp = dsp;
1517 ctl_work->ctl = ctl;
1518 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1519 schedule_work(&ctl_work->work);
1524 list_del(&ctl->list);
1527 kfree(ctl->subname);
1536 struct wm_coeff_parsed_alg {
1543 struct wm_coeff_parsed_coeff {
1548 snd_ctl_elem_type_t ctl_type;
1553 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1562 length = le16_to_cpu(*((__le16 *)*pos));
1569 *str = *pos + bytes;
1571 *pos += ((length + bytes) + 3) & ~0x03;
1576 static int wm_coeff_parse_int(int bytes, const u8 **pos)
1582 val = le16_to_cpu(*((__le16 *)*pos));
1585 val = le32_to_cpu(*((__le32 *)*pos));
1596 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1597 struct wm_coeff_parsed_alg *blk)
1599 const struct wmfw_adsp_alg_data *raw;
1601 switch (dsp->fw_ver) {
1604 raw = (const struct wmfw_adsp_alg_data *)*data;
1607 blk->id = le32_to_cpu(raw->id);
1608 blk->name = raw->name;
1609 blk->name_len = strlen(raw->name);
1610 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1613 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1614 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1616 wm_coeff_parse_string(sizeof(u16), data, NULL);
1617 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1621 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1622 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1623 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1626 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1627 struct wm_coeff_parsed_coeff *blk)
1629 const struct wmfw_adsp_coeff_data *raw;
1633 switch (dsp->fw_ver) {
1636 raw = (const struct wmfw_adsp_coeff_data *)*data;
1637 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1639 blk->offset = le16_to_cpu(raw->hdr.offset);
1640 blk->mem_type = le16_to_cpu(raw->hdr.type);
1641 blk->name = raw->name;
1642 blk->name_len = strlen(raw->name);
1643 blk->ctl_type = (__force snd_ctl_elem_type_t)le16_to_cpu(raw->ctl_type);
1644 blk->flags = le16_to_cpu(raw->flags);
1645 blk->len = le32_to_cpu(raw->len);
1649 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1650 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1651 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1652 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1654 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1655 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1657 (__force snd_ctl_elem_type_t)wm_coeff_parse_int(sizeof(raw->ctl_type),
1659 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1660 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1662 *data = *data + sizeof(raw->hdr) + length;
1666 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1667 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1668 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1669 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1670 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1671 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1674 static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1675 const struct wm_coeff_parsed_coeff *coeff_blk,
1676 unsigned int f_required,
1677 unsigned int f_illegal)
1679 if ((coeff_blk->flags & f_illegal) ||
1680 ((coeff_blk->flags & f_required) != f_required)) {
1681 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1682 coeff_blk->flags, coeff_blk->ctl_type);
1689 static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1690 const struct wmfw_region *region)
1692 struct wm_adsp_alg_region alg_region = {};
1693 struct wm_coeff_parsed_alg alg_blk;
1694 struct wm_coeff_parsed_coeff coeff_blk;
1695 const u8 *data = region->data;
1698 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1699 for (i = 0; i < alg_blk.ncoeff; i++) {
1700 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1702 switch (coeff_blk.ctl_type) {
1703 case SNDRV_CTL_ELEM_TYPE_BYTES:
1705 case WMFW_CTL_TYPE_ACKED:
1706 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1707 continue; /* ignore */
1709 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1710 WMFW_CTL_FLAG_VOLATILE |
1711 WMFW_CTL_FLAG_WRITEABLE |
1712 WMFW_CTL_FLAG_READABLE,
1717 case WMFW_CTL_TYPE_HOSTEVENT:
1718 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1720 WMFW_CTL_FLAG_VOLATILE |
1721 WMFW_CTL_FLAG_WRITEABLE |
1722 WMFW_CTL_FLAG_READABLE,
1727 case WMFW_CTL_TYPE_HOST_BUFFER:
1728 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1730 WMFW_CTL_FLAG_VOLATILE |
1731 WMFW_CTL_FLAG_READABLE,
1737 adsp_err(dsp, "Unknown control type: %d\n",
1738 coeff_blk.ctl_type);
1742 alg_region.type = coeff_blk.mem_type;
1743 alg_region.alg = alg_blk.id;
1745 ret = wm_adsp_create_control(dsp, &alg_region,
1751 coeff_blk.ctl_type);
1753 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1754 coeff_blk.name_len, coeff_blk.name, ret);
1760 static unsigned int wm_adsp1_parse_sizes(struct wm_adsp *dsp,
1761 const char * const file,
1763 const struct firmware *firmware)
1765 const struct wmfw_adsp1_sizes *adsp1_sizes;
1767 adsp1_sizes = (void *)&firmware->data[pos];
1769 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file,
1770 le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm),
1771 le32_to_cpu(adsp1_sizes->zm));
1773 return pos + sizeof(*adsp1_sizes);
1776 static unsigned int wm_adsp2_parse_sizes(struct wm_adsp *dsp,
1777 const char * const file,
1779 const struct firmware *firmware)
1781 const struct wmfw_adsp2_sizes *adsp2_sizes;
1783 adsp2_sizes = (void *)&firmware->data[pos];
1785 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file,
1786 le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym),
1787 le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm));
1789 return pos + sizeof(*adsp2_sizes);
1792 static bool wm_adsp_validate_version(struct wm_adsp *dsp, unsigned int version)
1796 adsp_warn(dsp, "Deprecated file format %d\n", version);
1806 static bool wm_halo_validate_version(struct wm_adsp *dsp, unsigned int version)
1816 static int wm_adsp_load(struct wm_adsp *dsp)
1818 LIST_HEAD(buf_list);
1819 const struct firmware *firmware;
1820 struct regmap *regmap = dsp->regmap;
1821 unsigned int pos = 0;
1822 const struct wmfw_header *header;
1823 const struct wmfw_adsp1_sizes *adsp1_sizes;
1824 const struct wmfw_footer *footer;
1825 const struct wmfw_region *region;
1826 const struct wm_adsp_region *mem;
1827 const char *region_name;
1828 char *file, *text = NULL;
1829 struct wm_adsp_buf *buf;
1832 int ret, offset, type;
1834 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1838 snprintf(file, PAGE_SIZE, "%s-%s-%s.wmfw", dsp->part, dsp->fwf_name,
1839 wm_adsp_fw[dsp->fw].file);
1840 file[PAGE_SIZE - 1] = '\0';
1842 ret = request_firmware(&firmware, file, dsp->dev);
1844 adsp_err(dsp, "Failed to request '%s'\n", file);
1849 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1850 if (pos >= firmware->size) {
1851 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1852 file, firmware->size);
1856 header = (void *)&firmware->data[0];
1858 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1859 adsp_err(dsp, "%s: invalid magic\n", file);
1863 if (!dsp->ops->validate_version(dsp, header->ver)) {
1864 adsp_err(dsp, "%s: unknown file format %d\n",
1869 adsp_info(dsp, "Firmware version: %d\n", header->ver);
1870 dsp->fw_ver = header->ver;
1872 if (header->core != dsp->type) {
1873 adsp_err(dsp, "%s: invalid core %d != %d\n",
1874 file, header->core, dsp->type);
1878 pos = sizeof(*header);
1879 pos = dsp->ops->parse_sizes(dsp, file, pos, firmware);
1881 footer = (void *)&firmware->data[pos];
1882 pos += sizeof(*footer);
1884 if (le32_to_cpu(header->len) != pos) {
1885 adsp_err(dsp, "%s: unexpected header length %d\n",
1886 file, le32_to_cpu(header->len));
1890 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1891 le64_to_cpu(footer->timestamp));
1893 while (pos < firmware->size &&
1894 sizeof(*region) < firmware->size - pos) {
1895 region = (void *)&(firmware->data[pos]);
1896 region_name = "Unknown";
1899 offset = le32_to_cpu(region->offset) & 0xffffff;
1900 type = be32_to_cpu(region->type) & 0xff;
1903 case WMFW_NAME_TEXT:
1904 region_name = "Firmware name";
1905 text = kzalloc(le32_to_cpu(region->len) + 1,
1908 case WMFW_ALGORITHM_DATA:
1909 region_name = "Algorithm";
1910 ret = wm_adsp_parse_coeff(dsp, region);
1914 case WMFW_INFO_TEXT:
1915 region_name = "Information";
1916 text = kzalloc(le32_to_cpu(region->len) + 1,
1920 region_name = "Absolute";
1928 case WMFW_HALO_PM_PACKED:
1929 case WMFW_HALO_XM_PACKED:
1930 case WMFW_HALO_YM_PACKED:
1931 mem = wm_adsp_find_region(dsp, type);
1933 adsp_err(dsp, "No region of type: %x\n", type);
1938 region_name = wm_adsp_mem_region_name(type);
1939 reg = dsp->ops->region_to_reg(mem, offset);
1943 "%s.%d: Unknown region type %x at %d(%x)\n",
1944 file, regions, type, pos, pos);
1948 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1949 regions, le32_to_cpu(region->len), offset,
1952 if (le32_to_cpu(region->len) >
1953 firmware->size - pos - sizeof(*region)) {
1955 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1956 file, regions, region_name,
1957 le32_to_cpu(region->len), firmware->size);
1963 memcpy(text, region->data, le32_to_cpu(region->len));
1964 adsp_info(dsp, "%s: %s\n", file, text);
1970 buf = wm_adsp_buf_alloc(region->data,
1971 le32_to_cpu(region->len),
1974 adsp_err(dsp, "Out of memory\n");
1979 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1980 le32_to_cpu(region->len));
1983 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1985 le32_to_cpu(region->len), offset,
1991 pos += le32_to_cpu(region->len) + sizeof(*region);
1995 ret = regmap_async_complete(regmap);
1997 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2001 if (pos > firmware->size)
2002 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2003 file, regions, pos - firmware->size);
2005 wm_adsp_debugfs_save_wmfwname(dsp, file);
2008 regmap_async_complete(regmap);
2009 wm_adsp_buf_free(&buf_list);
2010 release_firmware(firmware);
2019 * Find wm_coeff_ctl with input name as its subname
2020 * If not found, return NULL
2022 static struct wm_coeff_ctl *wm_adsp_get_ctl(struct wm_adsp *dsp,
2023 const char *name, int type,
2026 struct wm_coeff_ctl *pos, *rslt = NULL;
2027 const char *fw_txt = wm_adsp_fw_text[dsp->fw];
2029 list_for_each_entry(pos, &dsp->ctl_list, list) {
2032 if (strncmp(pos->subname, name, pos->subname_len) == 0 &&
2033 strncmp(pos->fw_name, fw_txt,
2034 SNDRV_CTL_ELEM_ID_NAME_MAXLEN) == 0 &&
2035 pos->alg_region.alg == alg &&
2036 pos->alg_region.type == type) {
2045 int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, int type,
2046 unsigned int alg, void *buf, size_t len)
2048 struct wm_coeff_ctl *ctl;
2049 struct snd_kcontrol *kcontrol;
2050 char ctl_name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
2053 ctl = wm_adsp_get_ctl(dsp, name, type, alg);
2060 ret = wm_coeff_write_ctrl(ctl, buf, len);
2064 if (ctl->flags & WMFW_CTL_FLAG_SYS)
2067 if (dsp->component->name_prefix)
2068 snprintf(ctl_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s",
2069 dsp->component->name_prefix, ctl->name);
2071 snprintf(ctl_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s",
2074 kcontrol = snd_soc_card_get_kcontrol(dsp->component->card, ctl_name);
2076 adsp_err(dsp, "Can't find kcontrol %s\n", ctl_name);
2080 snd_ctl_notify(dsp->component->card->snd_card,
2081 SNDRV_CTL_EVENT_MASK_VALUE, &kcontrol->id);
2085 EXPORT_SYMBOL_GPL(wm_adsp_write_ctl);
2087 int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, int type,
2088 unsigned int alg, void *buf, size_t len)
2090 struct wm_coeff_ctl *ctl;
2092 ctl = wm_adsp_get_ctl(dsp, name, type, alg);
2099 return wm_coeff_read_ctrl(ctl, buf, len);
2101 EXPORT_SYMBOL_GPL(wm_adsp_read_ctl);
2103 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
2104 const struct wm_adsp_alg_region *alg_region)
2106 struct wm_coeff_ctl *ctl;
2108 list_for_each_entry(ctl, &dsp->ctl_list, list) {
2109 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
2110 alg_region->alg == ctl->alg_region.alg &&
2111 alg_region->type == ctl->alg_region.type) {
2112 ctl->alg_region.base = alg_region->base;
2117 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
2118 const struct wm_adsp_region *mem,
2119 unsigned int pos, unsigned int len)
2127 adsp_err(dsp, "No algorithms\n");
2128 return ERR_PTR(-EINVAL);
2131 if (n_algs > 1024) {
2132 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
2133 return ERR_PTR(-EINVAL);
2136 /* Read the terminator first to validate the length */
2137 reg = dsp->ops->region_to_reg(mem, pos + len);
2139 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
2141 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
2143 return ERR_PTR(ret);
2146 if (be32_to_cpu(val) != 0xbedead)
2147 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n",
2148 reg, be32_to_cpu(val));
2150 /* Convert length from DSP words to bytes */
2153 alg = kzalloc(len, GFP_KERNEL | GFP_DMA);
2155 return ERR_PTR(-ENOMEM);
2157 reg = dsp->ops->region_to_reg(mem, pos);
2159 ret = regmap_raw_read(dsp->regmap, reg, alg, len);
2161 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
2163 return ERR_PTR(ret);
2169 static struct wm_adsp_alg_region *
2170 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
2172 struct wm_adsp_alg_region *alg_region;
2174 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
2175 if (id == alg_region->alg && type == alg_region->type)
2182 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
2183 int type, __be32 id,
2186 struct wm_adsp_alg_region *alg_region;
2188 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
2190 return ERR_PTR(-ENOMEM);
2192 alg_region->type = type;
2193 alg_region->alg = be32_to_cpu(id);
2194 alg_region->base = be32_to_cpu(base);
2196 list_add_tail(&alg_region->list, &dsp->alg_regions);
2198 if (dsp->fw_ver > 0)
2199 wm_adsp_ctl_fixup_base(dsp, alg_region);
2204 static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
2206 struct wm_adsp_alg_region *alg_region;
2208 while (!list_empty(&dsp->alg_regions)) {
2209 alg_region = list_first_entry(&dsp->alg_regions,
2210 struct wm_adsp_alg_region,
2212 list_del(&alg_region->list);
2217 static void wmfw_parse_id_header(struct wm_adsp *dsp,
2218 struct wmfw_id_hdr *fw, int nalgs)
2220 dsp->fw_id = be32_to_cpu(fw->id);
2221 dsp->fw_id_version = be32_to_cpu(fw->ver);
2223 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n",
2224 dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16,
2225 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
2229 static void wmfw_v3_parse_id_header(struct wm_adsp *dsp,
2230 struct wmfw_v3_id_hdr *fw, int nalgs)
2232 dsp->fw_id = be32_to_cpu(fw->id);
2233 dsp->fw_id_version = be32_to_cpu(fw->ver);
2234 dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id);
2236 adsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n",
2237 dsp->fw_id, dsp->fw_vendor_id,
2238 (dsp->fw_id_version & 0xff0000) >> 16,
2239 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
2243 static int wm_adsp_create_regions(struct wm_adsp *dsp, __be32 id, int nregions,
2244 const int *type, __be32 *base)
2246 struct wm_adsp_alg_region *alg_region;
2249 for (i = 0; i < nregions; i++) {
2250 alg_region = wm_adsp_create_region(dsp, type[i], id, base[i]);
2251 if (IS_ERR(alg_region))
2252 return PTR_ERR(alg_region);
2258 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
2260 struct wmfw_adsp1_id_hdr adsp1_id;
2261 struct wmfw_adsp1_alg_hdr *adsp1_alg;
2262 struct wm_adsp_alg_region *alg_region;
2263 const struct wm_adsp_region *mem;
2264 unsigned int pos, len;
2268 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
2272 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
2275 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2280 n_algs = be32_to_cpu(adsp1_id.n_algs);
2282 wmfw_parse_id_header(dsp, &adsp1_id.fw, n_algs);
2284 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2285 adsp1_id.fw.id, adsp1_id.zm);
2286 if (IS_ERR(alg_region))
2287 return PTR_ERR(alg_region);
2289 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2290 adsp1_id.fw.id, adsp1_id.dm);
2291 if (IS_ERR(alg_region))
2292 return PTR_ERR(alg_region);
2294 /* Calculate offset and length in DSP words */
2295 pos = sizeof(adsp1_id) / sizeof(u32);
2296 len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32);
2298 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2299 if (IS_ERR(adsp1_alg))
2300 return PTR_ERR(adsp1_alg);
2302 for (i = 0; i < n_algs; i++) {
2303 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2304 i, be32_to_cpu(adsp1_alg[i].alg.id),
2305 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
2306 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
2307 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
2308 be32_to_cpu(adsp1_alg[i].dm),
2309 be32_to_cpu(adsp1_alg[i].zm));
2311 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2312 adsp1_alg[i].alg.id,
2314 if (IS_ERR(alg_region)) {
2315 ret = PTR_ERR(alg_region);
2318 if (dsp->fw_ver == 0) {
2319 if (i + 1 < n_algs) {
2320 len = be32_to_cpu(adsp1_alg[i + 1].dm);
2321 len -= be32_to_cpu(adsp1_alg[i].dm);
2323 wm_adsp_create_control(dsp, alg_region, 0,
2325 SNDRV_CTL_ELEM_TYPE_BYTES);
2327 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
2328 be32_to_cpu(adsp1_alg[i].alg.id));
2332 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2333 adsp1_alg[i].alg.id,
2335 if (IS_ERR(alg_region)) {
2336 ret = PTR_ERR(alg_region);
2339 if (dsp->fw_ver == 0) {
2340 if (i + 1 < n_algs) {
2341 len = be32_to_cpu(adsp1_alg[i + 1].zm);
2342 len -= be32_to_cpu(adsp1_alg[i].zm);
2344 wm_adsp_create_control(dsp, alg_region, 0,
2346 SNDRV_CTL_ELEM_TYPE_BYTES);
2348 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2349 be32_to_cpu(adsp1_alg[i].alg.id));
2359 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
2361 struct wmfw_adsp2_id_hdr adsp2_id;
2362 struct wmfw_adsp2_alg_hdr *adsp2_alg;
2363 struct wm_adsp_alg_region *alg_region;
2364 const struct wm_adsp_region *mem;
2365 unsigned int pos, len;
2369 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2373 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2376 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2381 n_algs = be32_to_cpu(adsp2_id.n_algs);
2383 wmfw_parse_id_header(dsp, &adsp2_id.fw, n_algs);
2385 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2386 adsp2_id.fw.id, adsp2_id.xm);
2387 if (IS_ERR(alg_region))
2388 return PTR_ERR(alg_region);
2390 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2391 adsp2_id.fw.id, adsp2_id.ym);
2392 if (IS_ERR(alg_region))
2393 return PTR_ERR(alg_region);
2395 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2396 adsp2_id.fw.id, adsp2_id.zm);
2397 if (IS_ERR(alg_region))
2398 return PTR_ERR(alg_region);
2400 /* Calculate offset and length in DSP words */
2401 pos = sizeof(adsp2_id) / sizeof(u32);
2402 len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32);
2404 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2405 if (IS_ERR(adsp2_alg))
2406 return PTR_ERR(adsp2_alg);
2408 for (i = 0; i < n_algs; i++) {
2410 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2411 i, be32_to_cpu(adsp2_alg[i].alg.id),
2412 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2413 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2414 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2415 be32_to_cpu(adsp2_alg[i].xm),
2416 be32_to_cpu(adsp2_alg[i].ym),
2417 be32_to_cpu(adsp2_alg[i].zm));
2419 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2420 adsp2_alg[i].alg.id,
2422 if (IS_ERR(alg_region)) {
2423 ret = PTR_ERR(alg_region);
2426 if (dsp->fw_ver == 0) {
2427 if (i + 1 < n_algs) {
2428 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2429 len -= be32_to_cpu(adsp2_alg[i].xm);
2431 wm_adsp_create_control(dsp, alg_region, 0,
2433 SNDRV_CTL_ELEM_TYPE_BYTES);
2435 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2436 be32_to_cpu(adsp2_alg[i].alg.id));
2440 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2441 adsp2_alg[i].alg.id,
2443 if (IS_ERR(alg_region)) {
2444 ret = PTR_ERR(alg_region);
2447 if (dsp->fw_ver == 0) {
2448 if (i + 1 < n_algs) {
2449 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2450 len -= be32_to_cpu(adsp2_alg[i].ym);
2452 wm_adsp_create_control(dsp, alg_region, 0,
2454 SNDRV_CTL_ELEM_TYPE_BYTES);
2456 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2457 be32_to_cpu(adsp2_alg[i].alg.id));
2461 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2462 adsp2_alg[i].alg.id,
2464 if (IS_ERR(alg_region)) {
2465 ret = PTR_ERR(alg_region);
2468 if (dsp->fw_ver == 0) {
2469 if (i + 1 < n_algs) {
2470 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2471 len -= be32_to_cpu(adsp2_alg[i].zm);
2473 wm_adsp_create_control(dsp, alg_region, 0,
2475 SNDRV_CTL_ELEM_TYPE_BYTES);
2477 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2478 be32_to_cpu(adsp2_alg[i].alg.id));
2488 static int wm_halo_create_regions(struct wm_adsp *dsp, __be32 id,
2489 __be32 xm_base, __be32 ym_base)
2491 static const int types[] = {
2492 WMFW_ADSP2_XM, WMFW_HALO_XM_PACKED,
2493 WMFW_ADSP2_YM, WMFW_HALO_YM_PACKED
2495 __be32 bases[] = { xm_base, xm_base, ym_base, ym_base };
2497 return wm_adsp_create_regions(dsp, id, ARRAY_SIZE(types), types, bases);
2500 static int wm_halo_setup_algs(struct wm_adsp *dsp)
2502 struct wmfw_halo_id_hdr halo_id;
2503 struct wmfw_halo_alg_hdr *halo_alg;
2504 const struct wm_adsp_region *mem;
2505 unsigned int pos, len;
2509 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2513 ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id,
2516 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2521 n_algs = be32_to_cpu(halo_id.n_algs);
2523 wmfw_v3_parse_id_header(dsp, &halo_id.fw, n_algs);
2525 ret = wm_halo_create_regions(dsp, halo_id.fw.id,
2526 halo_id.xm_base, halo_id.ym_base);
2530 /* Calculate offset and length in DSP words */
2531 pos = sizeof(halo_id) / sizeof(u32);
2532 len = (sizeof(*halo_alg) * n_algs) / sizeof(u32);
2534 halo_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2535 if (IS_ERR(halo_alg))
2536 return PTR_ERR(halo_alg);
2538 for (i = 0; i < n_algs; i++) {
2540 "%d: ID %x v%d.%d.%d XM@%x YM@%x\n",
2541 i, be32_to_cpu(halo_alg[i].alg.id),
2542 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16,
2543 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8,
2544 be32_to_cpu(halo_alg[i].alg.ver) & 0xff,
2545 be32_to_cpu(halo_alg[i].xm_base),
2546 be32_to_cpu(halo_alg[i].ym_base));
2548 ret = wm_halo_create_regions(dsp, halo_alg[i].alg.id,
2549 halo_alg[i].xm_base,
2550 halo_alg[i].ym_base);
2560 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2562 LIST_HEAD(buf_list);
2563 struct regmap *regmap = dsp->regmap;
2564 struct wmfw_coeff_hdr *hdr;
2565 struct wmfw_coeff_item *blk;
2566 const struct firmware *firmware;
2567 const struct wm_adsp_region *mem;
2568 struct wm_adsp_alg_region *alg_region;
2569 const char *region_name;
2570 int ret, pos, blocks, type, offset, reg;
2572 struct wm_adsp_buf *buf;
2574 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2578 snprintf(file, PAGE_SIZE, "%s-%s-%s.bin", dsp->part, dsp->fwf_name,
2579 wm_adsp_fw[dsp->fw].file);
2580 file[PAGE_SIZE - 1] = '\0';
2582 ret = request_firmware(&firmware, file, dsp->dev);
2584 adsp_warn(dsp, "Failed to request '%s'\n", file);
2590 if (sizeof(*hdr) >= firmware->size) {
2591 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2592 file, firmware->size);
2596 hdr = (void *)&firmware->data[0];
2597 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2598 adsp_err(dsp, "%s: invalid magic\n", file);
2602 switch (be32_to_cpu(hdr->rev) & 0xff) {
2606 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2607 file, be32_to_cpu(hdr->rev) & 0xff);
2612 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2613 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2614 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2615 le32_to_cpu(hdr->ver) & 0xff);
2617 pos = le32_to_cpu(hdr->len);
2620 while (pos < firmware->size &&
2621 sizeof(*blk) < firmware->size - pos) {
2622 blk = (void *)(&firmware->data[pos]);
2624 type = le16_to_cpu(blk->type);
2625 offset = le16_to_cpu(blk->offset);
2627 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2628 file, blocks, le32_to_cpu(blk->id),
2629 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2630 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2631 le32_to_cpu(blk->ver) & 0xff);
2632 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2633 file, blocks, le32_to_cpu(blk->len), offset, type);
2636 region_name = "Unknown";
2638 case (WMFW_NAME_TEXT << 8):
2639 case (WMFW_INFO_TEXT << 8):
2640 case (WMFW_METADATA << 8):
2642 case (WMFW_ABSOLUTE << 8):
2644 * Old files may use this for global
2647 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2649 region_name = "global coefficients";
2650 mem = wm_adsp_find_region(dsp, type);
2652 adsp_err(dsp, "No ZM\n");
2655 reg = dsp->ops->region_to_reg(mem, 0);
2658 region_name = "register";
2667 case WMFW_HALO_XM_PACKED:
2668 case WMFW_HALO_YM_PACKED:
2669 case WMFW_HALO_PM_PACKED:
2670 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2671 file, blocks, le32_to_cpu(blk->len),
2672 type, le32_to_cpu(blk->id));
2674 mem = wm_adsp_find_region(dsp, type);
2676 adsp_err(dsp, "No base for region %x\n", type);
2680 alg_region = wm_adsp_find_alg_region(dsp, type,
2681 le32_to_cpu(blk->id));
2683 reg = alg_region->base;
2684 reg = dsp->ops->region_to_reg(mem, reg);
2687 adsp_err(dsp, "No %x for algorithm %x\n",
2688 type, le32_to_cpu(blk->id));
2693 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2694 file, blocks, type, pos);
2699 if (le32_to_cpu(blk->len) >
2700 firmware->size - pos - sizeof(*blk)) {
2702 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2703 file, blocks, region_name,
2704 le32_to_cpu(blk->len),
2710 buf = wm_adsp_buf_alloc(blk->data,
2711 le32_to_cpu(blk->len),
2714 adsp_err(dsp, "Out of memory\n");
2719 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2720 file, blocks, le32_to_cpu(blk->len),
2722 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2723 le32_to_cpu(blk->len));
2726 "%s.%d: Failed to write to %x in %s: %d\n",
2727 file, blocks, reg, region_name, ret);
2731 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2735 ret = regmap_async_complete(regmap);
2737 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2739 if (pos > firmware->size)
2740 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2741 file, blocks, pos - firmware->size);
2743 wm_adsp_debugfs_save_binname(dsp, file);
2746 regmap_async_complete(regmap);
2747 release_firmware(firmware);
2748 wm_adsp_buf_free(&buf_list);
2754 static int wm_adsp_create_name(struct wm_adsp *dsp)
2759 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d",
2765 if (!dsp->fwf_name) {
2766 p = devm_kstrdup(dsp->dev, dsp->name, GFP_KERNEL);
2771 for (; *p != 0; ++p)
2778 static int wm_adsp_common_init(struct wm_adsp *dsp)
2782 ret = wm_adsp_create_name(dsp);
2786 INIT_LIST_HEAD(&dsp->alg_regions);
2787 INIT_LIST_HEAD(&dsp->ctl_list);
2788 INIT_LIST_HEAD(&dsp->compr_list);
2789 INIT_LIST_HEAD(&dsp->buffer_list);
2791 mutex_init(&dsp->pwr_lock);
2796 int wm_adsp1_init(struct wm_adsp *dsp)
2798 dsp->ops = &wm_adsp1_ops;
2800 return wm_adsp_common_init(dsp);
2802 EXPORT_SYMBOL_GPL(wm_adsp1_init);
2804 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2805 struct snd_kcontrol *kcontrol,
2808 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2809 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2810 struct wm_adsp *dsp = &dsps[w->shift];
2811 struct wm_coeff_ctl *ctl;
2815 dsp->component = component;
2817 mutex_lock(&dsp->pwr_lock);
2820 case SND_SOC_DAPM_POST_PMU:
2821 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2822 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2825 * For simplicity set the DSP clock rate to be the
2826 * SYSCLK rate rather than making it configurable.
2828 if (dsp->sysclk_reg) {
2829 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2831 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2836 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
2838 ret = regmap_update_bits(dsp->regmap,
2839 dsp->base + ADSP1_CONTROL_31,
2840 ADSP1_CLK_SEL_MASK, val);
2842 adsp_err(dsp, "Failed to set clock rate: %d\n",
2848 ret = wm_adsp_load(dsp);
2852 ret = wm_adsp1_setup_algs(dsp);
2856 ret = wm_adsp_load_coeff(dsp);
2860 /* Initialize caches for enabled and unset controls */
2861 ret = wm_coeff_init_control_caches(dsp);
2865 /* Sync set controls */
2866 ret = wm_coeff_sync_controls(dsp);
2872 /* Start the core running */
2873 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2874 ADSP1_CORE_ENA | ADSP1_START,
2875 ADSP1_CORE_ENA | ADSP1_START);
2877 dsp->running = true;
2880 case SND_SOC_DAPM_PRE_PMD:
2881 dsp->running = false;
2882 dsp->booted = false;
2885 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2886 ADSP1_CORE_ENA | ADSP1_START, 0);
2888 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2889 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2891 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2894 list_for_each_entry(ctl, &dsp->ctl_list, list)
2898 wm_adsp_free_alg_regions(dsp);
2905 mutex_unlock(&dsp->pwr_lock);
2910 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2913 mutex_unlock(&dsp->pwr_lock);
2917 EXPORT_SYMBOL_GPL(wm_adsp1_event);
2919 static int wm_adsp2v2_enable_core(struct wm_adsp *dsp)
2924 /* Wait for the RAM to start, should be near instantaneous */
2925 for (count = 0; count < 10; ++count) {
2926 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2930 if (val & ADSP2_RAM_RDY)
2933 usleep_range(250, 500);
2936 if (!(val & ADSP2_RAM_RDY)) {
2937 adsp_err(dsp, "Failed to start DSP RAM\n");
2941 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2946 static int wm_adsp2_enable_core(struct wm_adsp *dsp)
2950 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2951 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2955 return wm_adsp2v2_enable_core(dsp);
2958 static int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions)
2960 struct regmap *regmap = dsp->regmap;
2961 unsigned int code0, code1, lock_reg;
2963 if (!(lock_regions & WM_ADSP2_REGION_ALL))
2966 lock_regions &= WM_ADSP2_REGION_ALL;
2967 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
2969 while (lock_regions) {
2971 if (lock_regions & BIT(0)) {
2972 code0 = ADSP2_LOCK_CODE_0;
2973 code1 = ADSP2_LOCK_CODE_1;
2975 if (lock_regions & BIT(1)) {
2976 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
2977 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
2979 regmap_write(regmap, lock_reg, code0);
2980 regmap_write(regmap, lock_reg, code1);
2988 static int wm_adsp2_enable_memory(struct wm_adsp *dsp)
2990 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2991 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2994 static void wm_adsp2_disable_memory(struct wm_adsp *dsp)
2996 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3000 static void wm_adsp2_disable_core(struct wm_adsp *dsp)
3002 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
3003 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
3004 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
3006 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3010 static void wm_adsp2v2_disable_core(struct wm_adsp *dsp)
3012 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
3013 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
3014 regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
3017 static void wm_adsp_boot_work(struct work_struct *work)
3019 struct wm_adsp *dsp = container_of(work,
3024 mutex_lock(&dsp->pwr_lock);
3026 if (dsp->ops->enable_memory) {
3027 ret = dsp->ops->enable_memory(dsp);
3032 if (dsp->ops->enable_core) {
3033 ret = dsp->ops->enable_core(dsp);
3038 ret = wm_adsp_load(dsp);
3042 ret = dsp->ops->setup_algs(dsp);
3046 ret = wm_adsp_load_coeff(dsp);
3050 /* Initialize caches for enabled and unset controls */
3051 ret = wm_coeff_init_control_caches(dsp);
3055 if (dsp->ops->disable_core)
3056 dsp->ops->disable_core(dsp);
3060 mutex_unlock(&dsp->pwr_lock);
3065 if (dsp->ops->disable_core)
3066 dsp->ops->disable_core(dsp);
3068 if (dsp->ops->disable_memory)
3069 dsp->ops->disable_memory(dsp);
3071 mutex_unlock(&dsp->pwr_lock);
3074 static int wm_halo_configure_mpu(struct wm_adsp *dsp, unsigned int lock_regions)
3076 struct reg_sequence config[] = {
3077 { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 },
3078 { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA },
3079 { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF },
3080 { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF },
3081 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions },
3082 { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions },
3083 { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions },
3084 { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF },
3085 { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF },
3086 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions },
3087 { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions },
3088 { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions },
3089 { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF },
3090 { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF },
3091 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions },
3092 { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions },
3093 { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions },
3094 { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF },
3095 { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF },
3096 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions },
3097 { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions },
3098 { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions },
3099 { dsp->base + HALO_MPU_LOCK_CONFIG, 0 },
3102 return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config));
3105 int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq)
3107 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3108 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3109 struct wm_adsp *dsp = &dsps[w->shift];
3112 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING,
3114 freq << ADSP2_CLK_SEL_SHIFT);
3116 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
3120 EXPORT_SYMBOL_GPL(wm_adsp2_set_dspclk);
3122 int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
3123 struct snd_ctl_elem_value *ucontrol)
3125 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3126 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3127 struct soc_mixer_control *mc =
3128 (struct soc_mixer_control *)kcontrol->private_value;
3129 struct wm_adsp *dsp = &dsps[mc->shift - 1];
3131 ucontrol->value.integer.value[0] = dsp->preloaded;
3135 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
3137 int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
3138 struct snd_ctl_elem_value *ucontrol)
3140 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3141 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3142 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3143 struct soc_mixer_control *mc =
3144 (struct soc_mixer_control *)kcontrol->private_value;
3145 struct wm_adsp *dsp = &dsps[mc->shift - 1];
3148 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
3150 dsp->preloaded = ucontrol->value.integer.value[0];
3152 if (ucontrol->value.integer.value[0])
3153 snd_soc_component_force_enable_pin(component, preload);
3155 snd_soc_component_disable_pin(component, preload);
3157 snd_soc_dapm_sync(dapm);
3159 flush_work(&dsp->boot_work);
3163 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
3165 static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
3167 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
3168 ADSP2_WDT_ENA_MASK, 0);
3171 static void wm_halo_stop_watchdog(struct wm_adsp *dsp)
3173 regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL,
3174 HALO_WDT_EN_MASK, 0);
3177 int wm_adsp_early_event(struct snd_soc_dapm_widget *w,
3178 struct snd_kcontrol *kcontrol, int event)
3180 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3181 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3182 struct wm_adsp *dsp = &dsps[w->shift];
3183 struct wm_coeff_ctl *ctl;
3186 case SND_SOC_DAPM_PRE_PMU:
3187 queue_work(system_unbound_wq, &dsp->boot_work);
3189 case SND_SOC_DAPM_PRE_PMD:
3190 mutex_lock(&dsp->pwr_lock);
3192 wm_adsp_debugfs_clear(dsp);
3195 dsp->fw_id_version = 0;
3197 dsp->booted = false;
3199 if (dsp->ops->disable_memory)
3200 dsp->ops->disable_memory(dsp);
3202 list_for_each_entry(ctl, &dsp->ctl_list, list)
3205 wm_adsp_free_alg_regions(dsp);
3207 mutex_unlock(&dsp->pwr_lock);
3209 adsp_dbg(dsp, "Shutdown complete\n");
3217 EXPORT_SYMBOL_GPL(wm_adsp_early_event);
3219 static int wm_adsp2_start_core(struct wm_adsp *dsp)
3221 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3222 ADSP2_CORE_ENA | ADSP2_START,
3223 ADSP2_CORE_ENA | ADSP2_START);
3226 static void wm_adsp2_stop_core(struct wm_adsp *dsp)
3228 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3229 ADSP2_CORE_ENA | ADSP2_START, 0);
3232 int wm_adsp_event(struct snd_soc_dapm_widget *w,
3233 struct snd_kcontrol *kcontrol, int event)
3235 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3236 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3237 struct wm_adsp *dsp = &dsps[w->shift];
3241 case SND_SOC_DAPM_POST_PMU:
3242 flush_work(&dsp->boot_work);
3244 mutex_lock(&dsp->pwr_lock);
3251 if (dsp->ops->enable_core) {
3252 ret = dsp->ops->enable_core(dsp);
3257 /* Sync set controls */
3258 ret = wm_coeff_sync_controls(dsp);
3262 if (dsp->ops->lock_memory) {
3263 ret = dsp->ops->lock_memory(dsp, dsp->lock_regions);
3265 adsp_err(dsp, "Error configuring MPU: %d\n",
3271 if (dsp->ops->start_core) {
3272 ret = dsp->ops->start_core(dsp);
3277 if (wm_adsp_fw[dsp->fw].num_caps != 0) {
3278 ret = wm_adsp_buffer_init(dsp);
3283 dsp->running = true;
3285 mutex_unlock(&dsp->pwr_lock);
3288 case SND_SOC_DAPM_PRE_PMD:
3289 /* Tell the firmware to cleanup */
3290 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
3292 if (dsp->ops->stop_watchdog)
3293 dsp->ops->stop_watchdog(dsp);
3295 /* Log firmware state, it can be useful for analysis */
3296 if (dsp->ops->show_fw_status)
3297 dsp->ops->show_fw_status(dsp);
3299 mutex_lock(&dsp->pwr_lock);
3301 dsp->running = false;
3303 if (dsp->ops->stop_core)
3304 dsp->ops->stop_core(dsp);
3305 if (dsp->ops->disable_core)
3306 dsp->ops->disable_core(dsp);
3308 if (wm_adsp_fw[dsp->fw].num_caps != 0)
3309 wm_adsp_buffer_free(dsp);
3311 dsp->fatal_error = false;
3313 mutex_unlock(&dsp->pwr_lock);
3315 adsp_dbg(dsp, "Execution stopped\n");
3324 if (dsp->ops->stop_core)
3325 dsp->ops->stop_core(dsp);
3326 if (dsp->ops->disable_core)
3327 dsp->ops->disable_core(dsp);
3328 mutex_unlock(&dsp->pwr_lock);
3331 EXPORT_SYMBOL_GPL(wm_adsp_event);
3333 static int wm_halo_start_core(struct wm_adsp *dsp)
3335 return regmap_update_bits(dsp->regmap,
3336 dsp->base + HALO_CCM_CORE_CONTROL,
3337 HALO_CORE_RESET | HALO_CORE_EN,
3338 HALO_CORE_RESET | HALO_CORE_EN);
3341 static void wm_halo_stop_core(struct wm_adsp *dsp)
3343 regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
3346 /* reset halo core with CORE_SOFT_RESET */
3347 regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET,
3348 HALO_CORE_SOFT_RESET_MASK, 1);
3351 int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component)
3355 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
3356 snd_soc_component_disable_pin(component, preload);
3358 wm_adsp2_init_debugfs(dsp, component);
3360 dsp->component = component;
3364 EXPORT_SYMBOL_GPL(wm_adsp2_component_probe);
3366 int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component)
3368 wm_adsp2_cleanup_debugfs(dsp);
3372 EXPORT_SYMBOL_GPL(wm_adsp2_component_remove);
3374 int wm_adsp2_init(struct wm_adsp *dsp)
3378 ret = wm_adsp_common_init(dsp);
3385 * Disable the DSP memory by default when in reset for a small
3388 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3392 "Failed to clear memory retention: %d\n", ret);
3396 dsp->ops = &wm_adsp2_ops[0];
3399 dsp->ops = &wm_adsp2_ops[1];
3402 dsp->ops = &wm_adsp2_ops[2];
3406 INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
3410 EXPORT_SYMBOL_GPL(wm_adsp2_init);
3412 int wm_halo_init(struct wm_adsp *dsp)
3416 ret = wm_adsp_common_init(dsp);
3420 dsp->ops = &wm_halo_ops;
3422 INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
3426 EXPORT_SYMBOL_GPL(wm_halo_init);
3428 void wm_adsp2_remove(struct wm_adsp *dsp)
3430 struct wm_coeff_ctl *ctl;
3432 while (!list_empty(&dsp->ctl_list)) {
3433 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
3435 list_del(&ctl->list);
3436 wm_adsp_free_ctl_blk(ctl);
3439 EXPORT_SYMBOL_GPL(wm_adsp2_remove);
3441 static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
3443 return compr->buf != NULL;
3446 static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
3448 struct wm_adsp_compr_buf *buf = NULL, *tmp;
3450 if (compr->dsp->fatal_error)
3453 list_for_each_entry(tmp, &compr->dsp->buffer_list, list) {
3454 if (!tmp->name || !strcmp(compr->name, tmp->name)) {
3469 static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
3474 /* Wake the poll so it can see buffer is no longer attached */
3476 snd_compr_fragment_elapsed(compr->stream);
3478 if (wm_adsp_compr_attached(compr)) {
3479 compr->buf->compr = NULL;
3484 int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
3486 struct wm_adsp_compr *compr, *tmp;
3487 struct snd_soc_pcm_runtime *rtd = stream->private_data;
3490 mutex_lock(&dsp->pwr_lock);
3492 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
3493 adsp_err(dsp, "%s: Firmware does not support compressed API\n",
3494 asoc_rtd_to_codec(rtd, 0)->name);
3499 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
3500 adsp_err(dsp, "%s: Firmware does not support stream direction\n",
3501 asoc_rtd_to_codec(rtd, 0)->name);
3506 list_for_each_entry(tmp, &dsp->compr_list, list) {
3507 if (!strcmp(tmp->name, asoc_rtd_to_codec(rtd, 0)->name)) {
3508 adsp_err(dsp, "%s: Only a single stream supported per dai\n",
3509 asoc_rtd_to_codec(rtd, 0)->name);
3515 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
3522 compr->stream = stream;
3523 compr->name = asoc_rtd_to_codec(rtd, 0)->name;
3525 list_add_tail(&compr->list, &dsp->compr_list);
3527 stream->runtime->private_data = compr;
3530 mutex_unlock(&dsp->pwr_lock);
3534 EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
3536 int wm_adsp_compr_free(struct snd_soc_component *component,
3537 struct snd_compr_stream *stream)
3539 struct wm_adsp_compr *compr = stream->runtime->private_data;
3540 struct wm_adsp *dsp = compr->dsp;
3542 mutex_lock(&dsp->pwr_lock);
3544 wm_adsp_compr_detach(compr);
3545 list_del(&compr->list);
3547 kfree(compr->raw_buf);
3550 mutex_unlock(&dsp->pwr_lock);
3554 EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
3556 static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
3557 struct snd_compr_params *params)
3559 struct wm_adsp_compr *compr = stream->runtime->private_data;
3560 struct wm_adsp *dsp = compr->dsp;
3561 const struct wm_adsp_fw_caps *caps;
3562 const struct snd_codec_desc *desc;
3565 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
3566 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
3567 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
3568 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
3569 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
3570 compr_err(compr, "Invalid buffer fragsize=%d fragments=%d\n",
3571 params->buffer.fragment_size,
3572 params->buffer.fragments);
3577 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
3578 caps = &wm_adsp_fw[dsp->fw].caps[i];
3581 if (caps->id != params->codec.id)
3584 if (stream->direction == SND_COMPRESS_PLAYBACK) {
3585 if (desc->max_ch < params->codec.ch_out)
3588 if (desc->max_ch < params->codec.ch_in)
3592 if (!(desc->formats & (1 << params->codec.format)))
3595 for (j = 0; j < desc->num_sample_rates; ++j)
3596 if (desc->sample_rates[j] == params->codec.sample_rate)
3600 compr_err(compr, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3601 params->codec.id, params->codec.ch_in, params->codec.ch_out,
3602 params->codec.sample_rate, params->codec.format);
3606 static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
3608 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
3611 int wm_adsp_compr_set_params(struct snd_soc_component *component,
3612 struct snd_compr_stream *stream,
3613 struct snd_compr_params *params)
3615 struct wm_adsp_compr *compr = stream->runtime->private_data;
3619 ret = wm_adsp_compr_check_params(stream, params);
3623 compr->size = params->buffer;
3625 compr_dbg(compr, "fragment_size=%d fragments=%d\n",
3626 compr->size.fragment_size, compr->size.fragments);
3628 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
3629 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
3630 if (!compr->raw_buf)
3633 compr->sample_rate = params->codec.sample_rate;
3637 EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
3639 int wm_adsp_compr_get_caps(struct snd_soc_component *component,
3640 struct snd_compr_stream *stream,
3641 struct snd_compr_caps *caps)
3643 struct wm_adsp_compr *compr = stream->runtime->private_data;
3644 int fw = compr->dsp->fw;
3647 if (wm_adsp_fw[fw].caps) {
3648 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
3649 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
3651 caps->num_codecs = i;
3652 caps->direction = wm_adsp_fw[fw].compr_direction;
3654 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
3655 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
3656 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
3657 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
3662 EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
3664 static int wm_adsp_read_raw_data_block(struct wm_adsp *dsp, int mem_type,
3665 unsigned int mem_addr,
3666 unsigned int num_words, __be32 *data)
3668 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3675 reg = dsp->ops->region_to_reg(mem, mem_addr);
3677 ret = regmap_raw_read(dsp->regmap, reg, data,
3678 sizeof(*data) * num_words);
3685 static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
3686 unsigned int mem_addr, u32 *data)
3691 ret = wm_adsp_read_raw_data_block(dsp, mem_type, mem_addr, 1, &raw);
3695 *data = be32_to_cpu(raw) & 0x00ffffffu;
3700 static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
3701 unsigned int mem_addr, u32 data)
3703 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3704 __be32 val = cpu_to_be32(data & 0x00ffffffu);
3710 reg = dsp->ops->region_to_reg(mem, mem_addr);
3712 return regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
3715 static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
3716 unsigned int field_offset, u32 *data)
3718 return wm_adsp_read_data_word(buf->dsp, buf->host_buf_mem_type,
3719 buf->host_buf_ptr + field_offset, data);
3722 static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
3723 unsigned int field_offset, u32 data)
3725 return wm_adsp_write_data_word(buf->dsp, buf->host_buf_mem_type,
3726 buf->host_buf_ptr + field_offset, data);
3729 static void wm_adsp_remove_padding(u32 *buf, int nwords)
3731 const __be32 *pack_in = (__be32 *)buf;
3732 u8 *pack_out = (u8 *)buf;
3736 * DSP words from the register map have pad bytes and the data bytes
3737 * are in swapped order. This swaps back to the original little-endian
3738 * order and strips the pad bytes.
3740 for (i = 0; i < nwords; i++) {
3741 u32 word = be32_to_cpu(*pack_in++);
3742 *pack_out++ = (u8)word;
3743 *pack_out++ = (u8)(word >> 8);
3744 *pack_out++ = (u8)(word >> 16);
3748 static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
3750 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
3751 struct wm_adsp_buffer_region *region;
3755 buf->regions = kcalloc(caps->num_regions, sizeof(*buf->regions),
3760 for (i = 0; i < caps->num_regions; ++i) {
3761 region = &buf->regions[i];
3763 region->offset = offset;
3764 region->mem_type = caps->region_defs[i].mem_type;
3766 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
3767 ®ion->base_addr);
3771 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
3776 region->cumulative_size = offset;
3779 "region=%d type=%d base=%08x off=%08x size=%08x\n",
3780 i, region->mem_type, region->base_addr,
3781 region->offset, region->cumulative_size);
3787 static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf)
3789 buf->irq_count = 0xFFFFFFFF;
3790 buf->read_index = -1;
3794 static struct wm_adsp_compr_buf *wm_adsp_buffer_alloc(struct wm_adsp *dsp)
3796 struct wm_adsp_compr_buf *buf;
3798 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
3804 wm_adsp_buffer_clear(buf);
3806 list_add_tail(&buf->list, &dsp->buffer_list);
3811 static int wm_adsp_buffer_parse_legacy(struct wm_adsp *dsp)
3813 struct wm_adsp_alg_region *alg_region;
3814 struct wm_adsp_compr_buf *buf;
3815 u32 xmalg, addr, magic;
3818 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
3820 adsp_err(dsp, "No algorithm region found\n");
3824 buf = wm_adsp_buffer_alloc(dsp);
3828 xmalg = dsp->ops->sys_config_size / sizeof(__be32);
3830 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3831 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
3835 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
3838 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
3839 for (i = 0; i < 5; ++i) {
3840 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
3841 &buf->host_buf_ptr);
3845 if (buf->host_buf_ptr)
3848 usleep_range(1000, 2000);
3851 if (!buf->host_buf_ptr)
3854 buf->host_buf_mem_type = WMFW_ADSP2_XM;
3856 ret = wm_adsp_buffer_populate(buf);
3860 compr_dbg(buf, "legacy host_buf_ptr=%x\n", buf->host_buf_ptr);
3865 static int wm_adsp_buffer_parse_coeff(struct wm_coeff_ctl *ctl)
3867 struct wm_adsp_host_buf_coeff_v1 coeff_v1;
3868 struct wm_adsp_compr_buf *buf;
3869 unsigned int reg, version;
3873 ret = wm_coeff_base_reg(ctl, ®);
3877 for (i = 0; i < 5; ++i) {
3878 ret = regmap_raw_read(ctl->dsp->regmap, reg, &bufp, sizeof(bufp));
3885 usleep_range(1000, 2000);
3889 adsp_err(ctl->dsp, "Failed to acquire host buffer\n");
3893 buf = wm_adsp_buffer_alloc(ctl->dsp);
3897 buf->host_buf_mem_type = ctl->alg_region.type;
3898 buf->host_buf_ptr = be32_to_cpu(bufp);
3900 ret = wm_adsp_buffer_populate(buf);
3905 * v0 host_buffer coefficients didn't have versioning, so if the
3906 * control is one word, assume version 0.
3908 if (ctl->len == 4) {
3909 compr_dbg(buf, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3913 ret = regmap_raw_read(ctl->dsp->regmap, reg, &coeff_v1,
3918 version = be32_to_cpu(coeff_v1.versions) & HOST_BUF_COEFF_COMPAT_VER_MASK;
3919 version >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT;
3921 if (version > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) {
3923 "Host buffer coeff ver %u > supported version %u\n",
3924 version, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER);
3928 wm_adsp_remove_padding((u32 *)&coeff_v1.name, ARRAY_SIZE(coeff_v1.name));
3930 buf->name = kasprintf(GFP_KERNEL, "%s-dsp-%s", ctl->dsp->part,
3931 (char *)&coeff_v1.name);
3933 compr_dbg(buf, "host_buf_ptr=%x coeff version %u\n",
3934 buf->host_buf_ptr, version);
3939 static int wm_adsp_buffer_init(struct wm_adsp *dsp)
3941 struct wm_coeff_ctl *ctl;
3944 list_for_each_entry(ctl, &dsp->ctl_list, list) {
3945 if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER)
3951 ret = wm_adsp_buffer_parse_coeff(ctl);
3953 adsp_err(dsp, "Failed to parse coeff: %d\n", ret);
3955 } else if (ret == 0) {
3956 /* Only one buffer supported for version 0 */
3961 if (list_empty(&dsp->buffer_list)) {
3962 /* Fall back to legacy support */
3963 ret = wm_adsp_buffer_parse_legacy(dsp);
3965 adsp_err(dsp, "Failed to parse legacy: %d\n", ret);
3973 wm_adsp_buffer_free(dsp);
3977 static int wm_adsp_buffer_free(struct wm_adsp *dsp)
3979 struct wm_adsp_compr_buf *buf, *tmp;
3981 list_for_each_entry_safe(buf, tmp, &dsp->buffer_list, list) {
3982 wm_adsp_compr_detach(buf->compr);
3985 kfree(buf->regions);
3986 list_del(&buf->list);
3993 static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3997 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3999 compr_err(buf, "Failed to check buffer error: %d\n", ret);
4002 if (buf->error != 0) {
4003 compr_err(buf, "Buffer error occurred: %d\n", buf->error);
4010 int wm_adsp_compr_trigger(struct snd_soc_component *component,
4011 struct snd_compr_stream *stream, int cmd)
4013 struct wm_adsp_compr *compr = stream->runtime->private_data;
4014 struct wm_adsp *dsp = compr->dsp;
4017 compr_dbg(compr, "Trigger: %d\n", cmd);
4019 mutex_lock(&dsp->pwr_lock);
4022 case SNDRV_PCM_TRIGGER_START:
4023 if (!wm_adsp_compr_attached(compr)) {
4024 ret = wm_adsp_compr_attach(compr);
4026 compr_err(compr, "Failed to link buffer and stream: %d\n",
4032 ret = wm_adsp_buffer_get_error(compr->buf);
4036 /* Trigger the IRQ at one fragment of data */
4037 ret = wm_adsp_buffer_write(compr->buf,
4038 HOST_BUFFER_FIELD(high_water_mark),
4039 wm_adsp_compr_frag_words(compr));
4041 compr_err(compr, "Failed to set high water mark: %d\n",
4046 case SNDRV_PCM_TRIGGER_STOP:
4047 if (wm_adsp_compr_attached(compr))
4048 wm_adsp_buffer_clear(compr->buf);
4055 mutex_unlock(&dsp->pwr_lock);
4059 EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
4061 static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
4063 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
4065 return buf->regions[last_region].cumulative_size;
4068 static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
4070 u32 next_read_index, next_write_index;
4071 int write_index, read_index, avail;
4074 /* Only sync read index if we haven't already read a valid index */
4075 if (buf->read_index < 0) {
4076 ret = wm_adsp_buffer_read(buf,
4077 HOST_BUFFER_FIELD(next_read_index),
4082 read_index = sign_extend32(next_read_index, 23);
4084 if (read_index < 0) {
4085 compr_dbg(buf, "Avail check on unstarted stream\n");
4089 buf->read_index = read_index;
4092 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
4097 write_index = sign_extend32(next_write_index, 23);
4099 avail = write_index - buf->read_index;
4101 avail += wm_adsp_buffer_size(buf);
4103 compr_dbg(buf, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
4104 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
4111 int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
4113 struct wm_adsp_compr_buf *buf;
4114 struct wm_adsp_compr *compr;
4117 mutex_lock(&dsp->pwr_lock);
4119 if (list_empty(&dsp->buffer_list)) {
4124 adsp_dbg(dsp, "Handling buffer IRQ\n");
4126 list_for_each_entry(buf, &dsp->buffer_list, list) {
4129 ret = wm_adsp_buffer_get_error(buf);
4131 goto out_notify; /* Wake poll to report error */
4133 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
4136 compr_err(buf, "Failed to get irq_count: %d\n", ret);
4140 ret = wm_adsp_buffer_update_avail(buf);
4142 compr_err(buf, "Error reading avail: %d\n", ret);
4146 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
4147 ret = WM_ADSP_COMPR_VOICE_TRIGGER;
4150 if (compr && compr->stream)
4151 snd_compr_fragment_elapsed(compr->stream);
4155 mutex_unlock(&dsp->pwr_lock);
4159 EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
4161 static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
4163 if (buf->irq_count & 0x01)
4166 compr_dbg(buf, "Enable IRQ(0x%x) for next fragment\n", buf->irq_count);
4168 buf->irq_count |= 0x01;
4170 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
4174 int wm_adsp_compr_pointer(struct snd_soc_component *component,
4175 struct snd_compr_stream *stream,
4176 struct snd_compr_tstamp *tstamp)
4178 struct wm_adsp_compr *compr = stream->runtime->private_data;
4179 struct wm_adsp *dsp = compr->dsp;
4180 struct wm_adsp_compr_buf *buf;
4183 compr_dbg(compr, "Pointer request\n");
4185 mutex_lock(&dsp->pwr_lock);
4189 if (dsp->fatal_error || !buf || buf->error) {
4190 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
4195 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
4196 ret = wm_adsp_buffer_update_avail(buf);
4198 compr_err(compr, "Error reading avail: %d\n", ret);
4203 * If we really have less than 1 fragment available tell the
4204 * DSP to inform us once a whole fragment is available.
4206 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
4207 ret = wm_adsp_buffer_get_error(buf);
4210 snd_compr_stop_error(stream,
4211 SNDRV_PCM_STATE_XRUN);
4215 ret = wm_adsp_buffer_reenable_irq(buf);
4217 compr_err(compr, "Failed to re-enable buffer IRQ: %d\n",
4224 tstamp->copied_total = compr->copied_total;
4225 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
4226 tstamp->sampling_rate = compr->sample_rate;
4229 mutex_unlock(&dsp->pwr_lock);
4233 EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
4235 static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
4237 struct wm_adsp_compr_buf *buf = compr->buf;
4238 unsigned int adsp_addr;
4239 int mem_type, nwords, max_read;
4242 /* Calculate read parameters */
4243 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
4244 if (buf->read_index < buf->regions[i].cumulative_size)
4247 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
4250 mem_type = buf->regions[i].mem_type;
4251 adsp_addr = buf->regions[i].base_addr +
4252 (buf->read_index - buf->regions[i].offset);
4254 max_read = wm_adsp_compr_frag_words(compr);
4255 nwords = buf->regions[i].cumulative_size - buf->read_index;
4257 if (nwords > target)
4259 if (nwords > buf->avail)
4260 nwords = buf->avail;
4261 if (nwords > max_read)
4266 /* Read data from DSP */
4267 ret = wm_adsp_read_raw_data_block(buf->dsp, mem_type, adsp_addr,
4268 nwords, (__be32 *)compr->raw_buf);
4272 wm_adsp_remove_padding(compr->raw_buf, nwords);
4274 /* update read index to account for words read */
4275 buf->read_index += nwords;
4276 if (buf->read_index == wm_adsp_buffer_size(buf))
4277 buf->read_index = 0;
4279 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
4284 /* update avail to account for words read */
4285 buf->avail -= nwords;
4290 static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
4291 char __user *buf, size_t count)
4293 struct wm_adsp *dsp = compr->dsp;
4297 compr_dbg(compr, "Requested read of %zu bytes\n", count);
4299 if (dsp->fatal_error || !compr->buf || compr->buf->error) {
4300 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
4304 count /= WM_ADSP_DATA_WORD_SIZE;
4307 nwords = wm_adsp_buffer_capture_block(compr, count);
4309 compr_err(compr, "Failed to capture block: %d\n",
4314 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
4316 compr_dbg(compr, "Read %d bytes\n", nbytes);
4318 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
4319 compr_err(compr, "Failed to copy data to user: %d, %d\n",
4326 } while (nwords > 0 && count > 0);
4328 compr->copied_total += ntotal;
4333 int wm_adsp_compr_copy(struct snd_soc_component *component,
4334 struct snd_compr_stream *stream, char __user *buf,
4337 struct wm_adsp_compr *compr = stream->runtime->private_data;
4338 struct wm_adsp *dsp = compr->dsp;
4341 mutex_lock(&dsp->pwr_lock);
4343 if (stream->direction == SND_COMPRESS_CAPTURE)
4344 ret = wm_adsp_compr_read(compr, buf, count);
4348 mutex_unlock(&dsp->pwr_lock);
4352 EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
4354 static void wm_adsp_fatal_error(struct wm_adsp *dsp)
4356 struct wm_adsp_compr *compr;
4358 dsp->fatal_error = true;
4360 list_for_each_entry(compr, &dsp->compr_list, list) {
4362 snd_compr_fragment_elapsed(compr->stream);
4366 irqreturn_t wm_adsp2_bus_error(int irq, void *data)
4368 struct wm_adsp *dsp = (struct wm_adsp *)data;
4370 struct regmap *regmap = dsp->regmap;
4373 mutex_lock(&dsp->pwr_lock);
4375 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
4378 "Failed to read Region Lock Ctrl register: %d\n", ret);
4382 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
4383 adsp_err(dsp, "watchdog timeout error\n");
4384 dsp->ops->stop_watchdog(dsp);
4385 wm_adsp_fatal_error(dsp);
4388 if (val & (ADSP2_ADDR_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
4389 if (val & ADSP2_ADDR_ERR_MASK)
4390 adsp_err(dsp, "bus error: address error\n");
4392 adsp_err(dsp, "bus error: region lock error\n");
4394 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
4397 "Failed to read Bus Err Addr register: %d\n",
4402 adsp_err(dsp, "bus error address = 0x%x\n",
4403 val & ADSP2_BUS_ERR_ADDR_MASK);
4405 ret = regmap_read(regmap,
4406 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
4410 "Failed to read Pmem Xmem Err Addr register: %d\n",
4415 adsp_err(dsp, "xmem error address = 0x%x\n",
4416 val & ADSP2_XMEM_ERR_ADDR_MASK);
4417 adsp_err(dsp, "pmem error address = 0x%x\n",
4418 (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
4419 ADSP2_PMEM_ERR_ADDR_SHIFT);
4422 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
4423 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
4426 mutex_unlock(&dsp->pwr_lock);
4430 EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
4432 irqreturn_t wm_halo_bus_error(int irq, void *data)
4434 struct wm_adsp *dsp = (struct wm_adsp *)data;
4435 struct regmap *regmap = dsp->regmap;
4436 unsigned int fault[6];
4437 struct reg_sequence clear[] = {
4438 { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 },
4439 { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 },
4440 { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 },
4444 mutex_lock(&dsp->pwr_lock);
4446 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1,
4449 adsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret);
4453 adsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n",
4454 *fault & HALO_AHBM_FLAGS_ERR_MASK,
4455 (*fault & HALO_AHBM_CORE_ERR_ADDR_MASK) >>
4456 HALO_AHBM_CORE_ERR_ADDR_SHIFT);
4458 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0,
4461 adsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret);
4465 adsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault);
4467 ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR,
4468 fault, ARRAY_SIZE(fault));
4470 adsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret);
4474 adsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]);
4475 adsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]);
4476 adsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]);
4478 ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear));
4480 adsp_warn(dsp, "Failed to clear MPU status: %d\n", ret);
4483 mutex_unlock(&dsp->pwr_lock);
4487 EXPORT_SYMBOL_GPL(wm_halo_bus_error);
4489 irqreturn_t wm_halo_wdt_expire(int irq, void *data)
4491 struct wm_adsp *dsp = data;
4493 mutex_lock(&dsp->pwr_lock);
4495 adsp_warn(dsp, "WDT Expiry Fault\n");
4496 dsp->ops->stop_watchdog(dsp);
4497 wm_adsp_fatal_error(dsp);
4499 mutex_unlock(&dsp->pwr_lock);
4503 EXPORT_SYMBOL_GPL(wm_halo_wdt_expire);
4505 static const struct wm_adsp_ops wm_adsp1_ops = {
4506 .validate_version = wm_adsp_validate_version,
4507 .parse_sizes = wm_adsp1_parse_sizes,
4508 .region_to_reg = wm_adsp_region_to_reg,
4511 static const struct wm_adsp_ops wm_adsp2_ops[] = {
4513 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4514 .parse_sizes = wm_adsp2_parse_sizes,
4515 .validate_version = wm_adsp_validate_version,
4516 .setup_algs = wm_adsp2_setup_algs,
4517 .region_to_reg = wm_adsp_region_to_reg,
4519 .show_fw_status = wm_adsp2_show_fw_status,
4521 .enable_memory = wm_adsp2_enable_memory,
4522 .disable_memory = wm_adsp2_disable_memory,
4524 .enable_core = wm_adsp2_enable_core,
4525 .disable_core = wm_adsp2_disable_core,
4527 .start_core = wm_adsp2_start_core,
4528 .stop_core = wm_adsp2_stop_core,
4532 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4533 .parse_sizes = wm_adsp2_parse_sizes,
4534 .validate_version = wm_adsp_validate_version,
4535 .setup_algs = wm_adsp2_setup_algs,
4536 .region_to_reg = wm_adsp_region_to_reg,
4538 .show_fw_status = wm_adsp2v2_show_fw_status,
4540 .enable_memory = wm_adsp2_enable_memory,
4541 .disable_memory = wm_adsp2_disable_memory,
4542 .lock_memory = wm_adsp2_lock,
4544 .enable_core = wm_adsp2v2_enable_core,
4545 .disable_core = wm_adsp2v2_disable_core,
4547 .start_core = wm_adsp2_start_core,
4548 .stop_core = wm_adsp2_stop_core,
4551 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4552 .parse_sizes = wm_adsp2_parse_sizes,
4553 .validate_version = wm_adsp_validate_version,
4554 .setup_algs = wm_adsp2_setup_algs,
4555 .region_to_reg = wm_adsp_region_to_reg,
4557 .show_fw_status = wm_adsp2v2_show_fw_status,
4558 .stop_watchdog = wm_adsp_stop_watchdog,
4560 .enable_memory = wm_adsp2_enable_memory,
4561 .disable_memory = wm_adsp2_disable_memory,
4562 .lock_memory = wm_adsp2_lock,
4564 .enable_core = wm_adsp2v2_enable_core,
4565 .disable_core = wm_adsp2v2_disable_core,
4567 .start_core = wm_adsp2_start_core,
4568 .stop_core = wm_adsp2_stop_core,
4572 static const struct wm_adsp_ops wm_halo_ops = {
4573 .sys_config_size = sizeof(struct wm_halo_system_config_xm_hdr),
4574 .parse_sizes = wm_adsp2_parse_sizes,
4575 .validate_version = wm_halo_validate_version,
4576 .setup_algs = wm_halo_setup_algs,
4577 .region_to_reg = wm_halo_region_to_reg,
4579 .show_fw_status = wm_halo_show_fw_status,
4580 .stop_watchdog = wm_halo_stop_watchdog,
4582 .lock_memory = wm_halo_configure_mpu,
4584 .start_core = wm_halo_start_core,
4585 .stop_core = wm_halo_stop_core,
4588 MODULE_LICENSE("GPL v2");