1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm_adsp.c -- Wolfson ADSP support
5 * Copyright 2012 Wolfson Microelectronics plc
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
10 #include <linux/ctype.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/firmware.h>
16 #include <linux/list.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <linux/vmalloc.h>
23 #include <linux/workqueue.h>
24 #include <linux/debugfs.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
35 #define adsp_crit(_dsp, fmt, ...) \
36 dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
37 #define adsp_err(_dsp, fmt, ...) \
38 dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
39 #define adsp_warn(_dsp, fmt, ...) \
40 dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
41 #define adsp_info(_dsp, fmt, ...) \
42 dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
43 #define adsp_dbg(_dsp, fmt, ...) \
44 dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
46 #define compr_err(_obj, fmt, ...) \
47 adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
49 #define compr_dbg(_obj, fmt, ...) \
50 adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
53 #define ADSP1_CONTROL_1 0x00
54 #define ADSP1_CONTROL_2 0x02
55 #define ADSP1_CONTROL_3 0x03
56 #define ADSP1_CONTROL_4 0x04
57 #define ADSP1_CONTROL_5 0x06
58 #define ADSP1_CONTROL_6 0x07
59 #define ADSP1_CONTROL_7 0x08
60 #define ADSP1_CONTROL_8 0x09
61 #define ADSP1_CONTROL_9 0x0A
62 #define ADSP1_CONTROL_10 0x0B
63 #define ADSP1_CONTROL_11 0x0C
64 #define ADSP1_CONTROL_12 0x0D
65 #define ADSP1_CONTROL_13 0x0F
66 #define ADSP1_CONTROL_14 0x10
67 #define ADSP1_CONTROL_15 0x11
68 #define ADSP1_CONTROL_16 0x12
69 #define ADSP1_CONTROL_17 0x13
70 #define ADSP1_CONTROL_18 0x14
71 #define ADSP1_CONTROL_19 0x16
72 #define ADSP1_CONTROL_20 0x17
73 #define ADSP1_CONTROL_21 0x18
74 #define ADSP1_CONTROL_22 0x1A
75 #define ADSP1_CONTROL_23 0x1B
76 #define ADSP1_CONTROL_24 0x1C
77 #define ADSP1_CONTROL_25 0x1E
78 #define ADSP1_CONTROL_26 0x20
79 #define ADSP1_CONTROL_27 0x21
80 #define ADSP1_CONTROL_28 0x22
81 #define ADSP1_CONTROL_29 0x23
82 #define ADSP1_CONTROL_30 0x24
83 #define ADSP1_CONTROL_31 0x26
88 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
89 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
90 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
96 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
97 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
98 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
99 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
100 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
101 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
102 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
103 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
104 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
105 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
106 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
107 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
108 #define ADSP1_START 0x0001 /* DSP1_START */
109 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
110 #define ADSP1_START_SHIFT 0 /* DSP1_START */
111 #define ADSP1_START_WIDTH 1 /* DSP1_START */
116 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
117 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
118 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
120 #define ADSP2_CONTROL 0x0
121 #define ADSP2_CLOCKING 0x1
122 #define ADSP2V2_CLOCKING 0x2
123 #define ADSP2_STATUS1 0x4
124 #define ADSP2_WDMA_CONFIG_1 0x30
125 #define ADSP2_WDMA_CONFIG_2 0x31
126 #define ADSP2V2_WDMA_CONFIG_2 0x32
127 #define ADSP2_RDMA_CONFIG_1 0x34
129 #define ADSP2_SCRATCH0 0x40
130 #define ADSP2_SCRATCH1 0x41
131 #define ADSP2_SCRATCH2 0x42
132 #define ADSP2_SCRATCH3 0x43
134 #define ADSP2V2_SCRATCH0_1 0x40
135 #define ADSP2V2_SCRATCH2_3 0x42
141 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
142 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
143 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
144 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
145 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
146 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
147 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
148 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
149 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
150 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
151 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
152 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
153 #define ADSP2_START 0x0001 /* DSP1_START */
154 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
155 #define ADSP2_START_SHIFT 0 /* DSP1_START */
156 #define ADSP2_START_WIDTH 1 /* DSP1_START */
161 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
162 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
163 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
168 #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */
169 #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */
170 #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
172 #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */
173 #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */
174 #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */
179 #define ADSP2_RAM_RDY 0x0001
180 #define ADSP2_RAM_RDY_MASK 0x0001
181 #define ADSP2_RAM_RDY_SHIFT 0
182 #define ADSP2_RAM_RDY_WIDTH 1
187 #define ADSP2_LOCK_CODE_0 0x5555
188 #define ADSP2_LOCK_CODE_1 0xAAAA
190 #define ADSP2_WATCHDOG 0x0A
191 #define ADSP2_BUS_ERR_ADDR 0x52
192 #define ADSP2_REGION_LOCK_STATUS 0x64
193 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66
194 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68
195 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A
196 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C
197 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E
198 #define ADSP2_LOCK_REGION_CTRL 0x7A
199 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C
201 #define ADSP2_REGION_LOCK_ERR_MASK 0x8000
202 #define ADSP2_SLAVE_ERR_MASK 0x4000
203 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000
204 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002
205 #define ADSP2_CTRL_ERR_EINT 0x0001
207 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF
208 #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF
209 #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000
210 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16
211 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD
213 #define ADSP2_LOCK_REGION_SHIFT 16
215 #define ADSP_MAX_STD_CTRL_SIZE 512
217 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
218 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
219 #define WM_ADSP_ACKED_CTL_MIN_VALUE 0
220 #define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF
223 * Event control messages
225 #define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
230 #define HALO_AHBM_WINDOW_DEBUG_0 0x02040
231 #define HALO_AHBM_WINDOW_DEBUG_1 0x02044
236 #define HALO_SCRATCH1 0x005c0
237 #define HALO_SCRATCH2 0x005c8
238 #define HALO_SCRATCH3 0x005d0
239 #define HALO_SCRATCH4 0x005d8
240 #define HALO_CCM_CORE_CONTROL 0x41000
241 #define HALO_CORE_SOFT_RESET 0x00010
242 #define HALO_WDT_CONTROL 0x47000
247 #define HALO_MPU_XMEM_ACCESS_0 0x43000
248 #define HALO_MPU_YMEM_ACCESS_0 0x43004
249 #define HALO_MPU_WINDOW_ACCESS_0 0x43008
250 #define HALO_MPU_XREG_ACCESS_0 0x4300C
251 #define HALO_MPU_YREG_ACCESS_0 0x43014
252 #define HALO_MPU_XMEM_ACCESS_1 0x43018
253 #define HALO_MPU_YMEM_ACCESS_1 0x4301C
254 #define HALO_MPU_WINDOW_ACCESS_1 0x43020
255 #define HALO_MPU_XREG_ACCESS_1 0x43024
256 #define HALO_MPU_YREG_ACCESS_1 0x4302C
257 #define HALO_MPU_XMEM_ACCESS_2 0x43030
258 #define HALO_MPU_YMEM_ACCESS_2 0x43034
259 #define HALO_MPU_WINDOW_ACCESS_2 0x43038
260 #define HALO_MPU_XREG_ACCESS_2 0x4303C
261 #define HALO_MPU_YREG_ACCESS_2 0x43044
262 #define HALO_MPU_XMEM_ACCESS_3 0x43048
263 #define HALO_MPU_YMEM_ACCESS_3 0x4304C
264 #define HALO_MPU_WINDOW_ACCESS_3 0x43050
265 #define HALO_MPU_XREG_ACCESS_3 0x43054
266 #define HALO_MPU_YREG_ACCESS_3 0x4305C
267 #define HALO_MPU_XM_VIO_ADDR 0x43100
268 #define HALO_MPU_XM_VIO_STATUS 0x43104
269 #define HALO_MPU_YM_VIO_ADDR 0x43108
270 #define HALO_MPU_YM_VIO_STATUS 0x4310C
271 #define HALO_MPU_PM_VIO_ADDR 0x43110
272 #define HALO_MPU_PM_VIO_STATUS 0x43114
273 #define HALO_MPU_LOCK_CONFIG 0x43140
276 * HALO_AHBM_WINDOW_DEBUG_1
278 #define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00
279 #define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8
280 #define HALO_AHBM_FLAGS_ERR_MASK 0x000000ff
283 * HALO_CCM_CORE_CONTROL
285 #define HALO_CORE_EN 0x00000001
288 * HALO_CORE_SOFT_RESET
290 #define HALO_CORE_SOFT_RESET_MASK 0x00000001
295 #define HALO_WDT_EN_MASK 0x00000001
298 * HALO_MPU_?M_VIO_STATUS
300 #define HALO_MPU_VIO_STS_MASK 0x007e0000
301 #define HALO_MPU_VIO_STS_SHIFT 17
302 #define HALO_MPU_VIO_ERR_WR_MASK 0x00008000
303 #define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff
304 #define HALO_MPU_VIO_ERR_SRC_SHIFT 0
306 static struct wm_adsp_ops wm_adsp1_ops;
307 static struct wm_adsp_ops wm_adsp2_ops[];
308 static struct wm_adsp_ops wm_halo_ops;
311 struct list_head list;
315 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
316 struct list_head *list)
318 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
323 buf->buf = vmalloc(len);
328 memcpy(buf->buf, src, len);
331 list_add_tail(&buf->list, list);
336 static void wm_adsp_buf_free(struct list_head *list)
338 while (!list_empty(list)) {
339 struct wm_adsp_buf *buf = list_first_entry(list,
342 list_del(&buf->list);
348 #define WM_ADSP_FW_MBC_VSS 0
349 #define WM_ADSP_FW_HIFI 1
350 #define WM_ADSP_FW_TX 2
351 #define WM_ADSP_FW_TX_SPK 3
352 #define WM_ADSP_FW_RX 4
353 #define WM_ADSP_FW_RX_ANC 5
354 #define WM_ADSP_FW_CTRL 6
355 #define WM_ADSP_FW_ASR 7
356 #define WM_ADSP_FW_TRACE 8
357 #define WM_ADSP_FW_SPK_PROT 9
358 #define WM_ADSP_FW_MISC 10
360 #define WM_ADSP_NUM_FW 11
362 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
363 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
364 [WM_ADSP_FW_HIFI] = "MasterHiFi",
365 [WM_ADSP_FW_TX] = "Tx",
366 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
367 [WM_ADSP_FW_RX] = "Rx",
368 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
369 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
370 [WM_ADSP_FW_ASR] = "ASR Assist",
371 [WM_ADSP_FW_TRACE] = "Dbg Trace",
372 [WM_ADSP_FW_SPK_PROT] = "Protection",
373 [WM_ADSP_FW_MISC] = "Misc",
376 struct wm_adsp_system_config_xm_hdr {
382 __be32 dma_buffer_size;
385 __be32 build_job_name[3];
386 __be32 build_job_number;
389 struct wm_halo_system_config_xm_hdr {
390 __be32 halo_heartbeat;
391 __be32 build_job_name[3];
392 __be32 build_job_number;
395 struct wm_adsp_alg_xm_struct {
401 __be32 high_water_mark;
402 __be32 low_water_mark;
403 __be64 smoothed_power;
406 struct wm_adsp_host_buf_coeff_v1 {
407 __be32 host_buf_ptr; /* Host buffer pointer */
408 __be32 versions; /* Version numbers */
409 __be32 name[4]; /* The buffer name */
412 struct wm_adsp_buffer {
413 __be32 buf1_base; /* Base addr of first buffer area */
414 __be32 buf1_size; /* Size of buf1 area in DSP words */
415 __be32 buf2_base; /* Base addr of 2nd buffer area */
416 __be32 buf1_buf2_size; /* Size of buf1+buf2 in DSP words */
417 __be32 buf3_base; /* Base addr of buf3 area */
418 __be32 buf_total_size; /* Size of buf1+buf2+buf3 in DSP words */
419 __be32 high_water_mark; /* Point at which IRQ is asserted */
420 __be32 irq_count; /* bits 1-31 count IRQ assertions */
421 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
422 __be32 next_write_index; /* word index of next write */
423 __be32 next_read_index; /* word index of next read */
424 __be32 error; /* error if any */
425 __be32 oldest_block_index; /* word index of oldest surviving */
426 __be32 requested_rewind; /* how many blocks rewind was done */
427 __be32 reserved_space; /* internal */
428 __be32 min_free; /* min free space since stream start */
429 __be32 blocks_written[2]; /* total blocks written (64 bit) */
430 __be32 words_written[2]; /* total words written (64 bit) */
433 struct wm_adsp_compr;
435 struct wm_adsp_compr_buf {
436 struct list_head list;
438 struct wm_adsp_compr *compr;
440 struct wm_adsp_buffer_region *regions;
447 int host_buf_mem_type;
452 struct wm_adsp_compr {
453 struct list_head list;
455 struct wm_adsp_compr_buf *buf;
457 struct snd_compr_stream *stream;
458 struct snd_compressed_buffer size;
461 unsigned int copied_total;
463 unsigned int sample_rate;
468 #define WM_ADSP_DATA_WORD_SIZE 3
470 #define WM_ADSP_MIN_FRAGMENTS 1
471 #define WM_ADSP_MAX_FRAGMENTS 256
472 #define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
473 #define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
475 #define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
477 #define HOST_BUFFER_FIELD(field) \
478 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
480 #define ALG_XM_FIELD(field) \
481 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
483 #define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER 1
485 #define HOST_BUF_COEFF_COMPAT_VER_MASK 0xFF00
486 #define HOST_BUF_COEFF_COMPAT_VER_SHIFT 8
488 static int wm_adsp_buffer_init(struct wm_adsp *dsp);
489 static int wm_adsp_buffer_free(struct wm_adsp *dsp);
491 struct wm_adsp_buffer_region {
493 unsigned int cumulative_size;
494 unsigned int mem_type;
495 unsigned int base_addr;
498 struct wm_adsp_buffer_region_def {
499 unsigned int mem_type;
500 unsigned int base_offset;
501 unsigned int size_offset;
504 static const struct wm_adsp_buffer_region_def default_regions[] = {
506 .mem_type = WMFW_ADSP2_XM,
507 .base_offset = HOST_BUFFER_FIELD(buf1_base),
508 .size_offset = HOST_BUFFER_FIELD(buf1_size),
511 .mem_type = WMFW_ADSP2_XM,
512 .base_offset = HOST_BUFFER_FIELD(buf2_base),
513 .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size),
516 .mem_type = WMFW_ADSP2_YM,
517 .base_offset = HOST_BUFFER_FIELD(buf3_base),
518 .size_offset = HOST_BUFFER_FIELD(buf_total_size),
522 struct wm_adsp_fw_caps {
524 struct snd_codec_desc desc;
526 const struct wm_adsp_buffer_region_def *region_defs;
529 static const struct wm_adsp_fw_caps ctrl_caps[] = {
531 .id = SND_AUDIOCODEC_BESPOKE,
534 .sample_rates = { 16000 },
535 .num_sample_rates = 1,
536 .formats = SNDRV_PCM_FMTBIT_S16_LE,
538 .num_regions = ARRAY_SIZE(default_regions),
539 .region_defs = default_regions,
543 static const struct wm_adsp_fw_caps trace_caps[] = {
545 .id = SND_AUDIOCODEC_BESPOKE,
549 4000, 8000, 11025, 12000, 16000, 22050,
550 24000, 32000, 44100, 48000, 64000, 88200,
551 96000, 176400, 192000
553 .num_sample_rates = 15,
554 .formats = SNDRV_PCM_FMTBIT_S16_LE,
556 .num_regions = ARRAY_SIZE(default_regions),
557 .region_defs = default_regions,
561 static const struct {
565 const struct wm_adsp_fw_caps *caps;
567 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
568 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
569 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
570 [WM_ADSP_FW_TX] = { .file = "tx" },
571 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
572 [WM_ADSP_FW_RX] = { .file = "rx" },
573 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
574 [WM_ADSP_FW_CTRL] = {
576 .compr_direction = SND_COMPRESS_CAPTURE,
577 .num_caps = ARRAY_SIZE(ctrl_caps),
579 .voice_trigger = true,
581 [WM_ADSP_FW_ASR] = { .file = "asr" },
582 [WM_ADSP_FW_TRACE] = {
584 .compr_direction = SND_COMPRESS_CAPTURE,
585 .num_caps = ARRAY_SIZE(trace_caps),
588 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
589 [WM_ADSP_FW_MISC] = { .file = "misc" },
592 struct wm_coeff_ctl_ops {
593 int (*xget)(struct snd_kcontrol *kcontrol,
594 struct snd_ctl_elem_value *ucontrol);
595 int (*xput)(struct snd_kcontrol *kcontrol,
596 struct snd_ctl_elem_value *ucontrol);
599 struct wm_coeff_ctl {
602 /* Subname is needed to match with firmware */
604 unsigned int subname_len;
605 struct wm_adsp_alg_region alg_region;
606 struct wm_coeff_ctl_ops ops;
608 unsigned int enabled:1;
609 struct list_head list;
614 struct soc_bytes_ext bytes_ext;
619 static const char *wm_adsp_mem_region_name(unsigned int type)
624 case WMFW_HALO_PM_PACKED:
630 case WMFW_HALO_XM_PACKED:
634 case WMFW_HALO_YM_PACKED:
643 #ifdef CONFIG_DEBUG_FS
644 static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
646 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
648 kfree(dsp->wmfw_file_name);
649 dsp->wmfw_file_name = tmp;
652 static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
654 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
656 kfree(dsp->bin_file_name);
657 dsp->bin_file_name = tmp;
660 static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
662 kfree(dsp->wmfw_file_name);
663 kfree(dsp->bin_file_name);
664 dsp->wmfw_file_name = NULL;
665 dsp->bin_file_name = NULL;
668 static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
669 char __user *user_buf,
670 size_t count, loff_t *ppos)
672 struct wm_adsp *dsp = file->private_data;
675 mutex_lock(&dsp->pwr_lock);
677 if (!dsp->wmfw_file_name || !dsp->booted)
680 ret = simple_read_from_buffer(user_buf, count, ppos,
682 strlen(dsp->wmfw_file_name));
684 mutex_unlock(&dsp->pwr_lock);
688 static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
689 char __user *user_buf,
690 size_t count, loff_t *ppos)
692 struct wm_adsp *dsp = file->private_data;
695 mutex_lock(&dsp->pwr_lock);
697 if (!dsp->bin_file_name || !dsp->booted)
700 ret = simple_read_from_buffer(user_buf, count, ppos,
702 strlen(dsp->bin_file_name));
704 mutex_unlock(&dsp->pwr_lock);
708 static const struct {
710 const struct file_operations fops;
711 } wm_adsp_debugfs_fops[] = {
713 .name = "wmfw_file_name",
716 .read = wm_adsp_debugfs_wmfw_read,
720 .name = "bin_file_name",
723 .read = wm_adsp_debugfs_bin_read,
728 static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
729 struct snd_soc_component *component)
731 struct dentry *root = NULL;
734 root = debugfs_create_dir(dsp->name, component->debugfs_root);
736 debugfs_create_bool("booted", 0444, root, &dsp->booted);
737 debugfs_create_bool("running", 0444, root, &dsp->running);
738 debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id);
739 debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version);
741 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i)
742 debugfs_create_file(wm_adsp_debugfs_fops[i].name, 0444, root,
743 dsp, &wm_adsp_debugfs_fops[i].fops);
745 dsp->debugfs_root = root;
748 static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
750 wm_adsp_debugfs_clear(dsp);
751 debugfs_remove_recursive(dsp->debugfs_root);
754 static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
755 struct snd_soc_component *component)
759 static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
763 static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
768 static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
773 static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
778 int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
779 struct snd_ctl_elem_value *ucontrol)
781 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
782 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
783 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
785 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
789 EXPORT_SYMBOL_GPL(wm_adsp_fw_get);
791 int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
792 struct snd_ctl_elem_value *ucontrol)
794 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
795 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
796 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
799 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
802 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
805 mutex_lock(&dsp[e->shift_l].pwr_lock);
807 if (dsp[e->shift_l].booted || !list_empty(&dsp[e->shift_l].compr_list))
810 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
812 mutex_unlock(&dsp[e->shift_l].pwr_lock);
816 EXPORT_SYMBOL_GPL(wm_adsp_fw_put);
818 const struct soc_enum wm_adsp_fw_enum[] = {
819 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
820 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
821 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
822 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
823 SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
824 SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
825 SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
827 EXPORT_SYMBOL_GPL(wm_adsp_fw_enum);
829 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
834 for (i = 0; i < dsp->num_mems; i++)
835 if (dsp->mem[i].type == type)
841 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
846 return mem->base + (offset * 3);
851 return mem->base + (offset * 2);
853 WARN(1, "Unknown memory region type");
858 static unsigned int wm_halo_region_to_reg(struct wm_adsp_region const *mem,
864 return mem->base + (offset * 4);
865 case WMFW_HALO_XM_PACKED:
866 case WMFW_HALO_YM_PACKED:
867 return (mem->base + (offset * 3)) & ~0x3;
868 case WMFW_HALO_PM_PACKED:
869 return mem->base + (offset * 5);
871 WARN(1, "Unknown memory region type");
876 static void wm_adsp_read_fw_status(struct wm_adsp *dsp,
877 int noffs, unsigned int *offs)
882 for (i = 0; i < noffs; ++i) {
883 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]);
885 adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret);
891 static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
893 unsigned int offs[] = {
894 ADSP2_SCRATCH0, ADSP2_SCRATCH1, ADSP2_SCRATCH2, ADSP2_SCRATCH3,
897 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
899 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
900 offs[0], offs[1], offs[2], offs[3]);
903 static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
905 unsigned int offs[] = { ADSP2V2_SCRATCH0_1, ADSP2V2_SCRATCH2_3 };
907 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
909 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
910 offs[0] & 0xFFFF, offs[0] >> 16,
911 offs[1] & 0xFFFF, offs[1] >> 16);
914 static void wm_halo_show_fw_status(struct wm_adsp *dsp)
916 unsigned int offs[] = {
917 HALO_SCRATCH1, HALO_SCRATCH2, HALO_SCRATCH3, HALO_SCRATCH4,
920 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs);
922 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
923 offs[0], offs[1], offs[2], offs[3]);
926 static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
928 return container_of(ext, struct wm_coeff_ctl, bytes_ext);
931 static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
933 const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
934 struct wm_adsp *dsp = ctl->dsp;
935 const struct wm_adsp_region *mem;
937 mem = wm_adsp_find_region(dsp, alg_region->type);
939 adsp_err(dsp, "No base for region %x\n",
944 *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset);
949 static int wm_coeff_info(struct snd_kcontrol *kctl,
950 struct snd_ctl_elem_info *uinfo)
952 struct soc_bytes_ext *bytes_ext =
953 (struct soc_bytes_ext *)kctl->private_value;
954 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
957 case WMFW_CTL_TYPE_ACKED:
958 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
959 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
960 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
961 uinfo->value.integer.step = 1;
965 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
966 uinfo->count = ctl->len;
973 static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
974 unsigned int event_id)
976 struct wm_adsp *dsp = ctl->dsp;
977 u32 val = cpu_to_be32(event_id);
981 ret = wm_coeff_base_reg(ctl, ®);
985 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
986 event_id, ctl->alg_region.alg,
987 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
989 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
991 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
996 * Poll for ack, we initially poll at ~1ms intervals for firmwares
997 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
998 * to ack instantly so we do the first 1ms delay before reading the
999 * control to avoid a pointless bus transaction
1001 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
1003 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
1004 usleep_range(1000, 2000);
1008 usleep_range(10000, 20000);
1013 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
1015 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
1020 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
1025 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
1026 reg, ctl->alg_region.alg,
1027 wm_adsp_mem_region_name(ctl->alg_region.type),
1033 static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
1034 const void *buf, size_t len)
1036 struct wm_adsp *dsp = ctl->dsp;
1041 ret = wm_coeff_base_reg(ctl, ®);
1045 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
1049 ret = regmap_raw_write(dsp->regmap, reg, scratch,
1052 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
1057 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
1064 static int wm_coeff_put(struct snd_kcontrol *kctl,
1065 struct snd_ctl_elem_value *ucontrol)
1067 struct soc_bytes_ext *bytes_ext =
1068 (struct soc_bytes_ext *)kctl->private_value;
1069 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1070 char *p = ucontrol->value.bytes.data;
1073 mutex_lock(&ctl->dsp->pwr_lock);
1075 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1078 memcpy(ctl->cache, p, ctl->len);
1081 if (ctl->enabled && ctl->dsp->running)
1082 ret = wm_coeff_write_control(ctl, p, ctl->len);
1084 mutex_unlock(&ctl->dsp->pwr_lock);
1089 static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
1090 const unsigned int __user *bytes, unsigned int size)
1092 struct soc_bytes_ext *bytes_ext =
1093 (struct soc_bytes_ext *)kctl->private_value;
1094 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1097 mutex_lock(&ctl->dsp->pwr_lock);
1099 if (copy_from_user(ctl->cache, bytes, size)) {
1103 if (ctl->enabled && ctl->dsp->running)
1104 ret = wm_coeff_write_control(ctl, ctl->cache, size);
1105 else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1109 mutex_unlock(&ctl->dsp->pwr_lock);
1114 static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
1115 struct snd_ctl_elem_value *ucontrol)
1117 struct soc_bytes_ext *bytes_ext =
1118 (struct soc_bytes_ext *)kctl->private_value;
1119 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1120 unsigned int val = ucontrol->value.integer.value[0];
1124 return 0; /* 0 means no event */
1126 mutex_lock(&ctl->dsp->pwr_lock);
1128 if (ctl->enabled && ctl->dsp->running)
1129 ret = wm_coeff_write_acked_control(ctl, val);
1133 mutex_unlock(&ctl->dsp->pwr_lock);
1138 static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
1139 void *buf, size_t len)
1141 struct wm_adsp *dsp = ctl->dsp;
1146 ret = wm_coeff_base_reg(ctl, ®);
1150 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
1154 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
1156 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
1161 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
1163 memcpy(buf, scratch, len);
1169 static int wm_coeff_get(struct snd_kcontrol *kctl,
1170 struct snd_ctl_elem_value *ucontrol)
1172 struct soc_bytes_ext *bytes_ext =
1173 (struct soc_bytes_ext *)kctl->private_value;
1174 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1175 char *p = ucontrol->value.bytes.data;
1178 mutex_lock(&ctl->dsp->pwr_lock);
1180 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1181 if (ctl->enabled && ctl->dsp->running)
1182 ret = wm_coeff_read_control(ctl, p, ctl->len);
1186 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1187 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1189 memcpy(p, ctl->cache, ctl->len);
1192 mutex_unlock(&ctl->dsp->pwr_lock);
1197 static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1198 unsigned int __user *bytes, unsigned int size)
1200 struct soc_bytes_ext *bytes_ext =
1201 (struct soc_bytes_ext *)kctl->private_value;
1202 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1205 mutex_lock(&ctl->dsp->pwr_lock);
1207 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1208 if (ctl->enabled && ctl->dsp->running)
1209 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1213 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1214 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1217 if (!ret && copy_to_user(bytes, ctl->cache, size))
1220 mutex_unlock(&ctl->dsp->pwr_lock);
1225 static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1226 struct snd_ctl_elem_value *ucontrol)
1229 * Although it's not useful to read an acked control, we must satisfy
1230 * user-side assumptions that all controls are readable and that a
1231 * write of the same value should be filtered out (it's valid to send
1232 * the same event number again to the firmware). We therefore return 0,
1233 * meaning "no event" so valid event numbers will always be a change
1235 ucontrol->value.integer.value[0] = 0;
1240 struct wmfw_ctl_work {
1241 struct wm_adsp *dsp;
1242 struct wm_coeff_ctl *ctl;
1243 struct work_struct work;
1246 static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1248 unsigned int out, rd, wr, vol;
1250 if (len > ADSP_MAX_STD_CTRL_SIZE) {
1251 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1252 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1253 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1255 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1257 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1258 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1259 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1266 if (in & WMFW_CTL_FLAG_WRITEABLE)
1268 if (in & WMFW_CTL_FLAG_VOLATILE)
1271 out |= rd | wr | vol;
1277 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
1279 struct snd_kcontrol_new *kcontrol;
1282 if (!ctl || !ctl->name)
1285 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1289 kcontrol->name = ctl->name;
1290 kcontrol->info = wm_coeff_info;
1291 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1292 kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1293 kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
1294 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
1296 switch (ctl->type) {
1297 case WMFW_CTL_TYPE_ACKED:
1298 kcontrol->get = wm_coeff_get_acked;
1299 kcontrol->put = wm_coeff_put_acked;
1302 if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1303 ctl->bytes_ext.max = ctl->len;
1304 ctl->bytes_ext.get = wm_coeff_tlv_get;
1305 ctl->bytes_ext.put = wm_coeff_tlv_put;
1307 kcontrol->get = wm_coeff_get;
1308 kcontrol->put = wm_coeff_put;
1313 ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1);
1326 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1328 struct wm_coeff_ctl *ctl;
1331 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1332 if (!ctl->enabled || ctl->set)
1334 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1338 * For readable controls populate the cache from the DSP memory.
1339 * For non-readable controls the cache was zero-filled when
1340 * created so we don't need to do anything.
1342 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) {
1343 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1352 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1354 struct wm_coeff_ctl *ctl;
1357 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1360 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
1361 ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
1370 static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1373 struct wm_coeff_ctl *ctl;
1376 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1377 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1383 ret = wm_coeff_write_acked_control(ctl, event);
1386 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1387 event, ctl->alg_region.alg, ret);
1391 static void wm_adsp_ctl_work(struct work_struct *work)
1393 struct wmfw_ctl_work *ctl_work = container_of(work,
1394 struct wmfw_ctl_work,
1397 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1401 static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1405 kfree(ctl->subname);
1409 static int wm_adsp_create_control(struct wm_adsp *dsp,
1410 const struct wm_adsp_alg_region *alg_region,
1411 unsigned int offset, unsigned int len,
1412 const char *subname, unsigned int subname_len,
1413 unsigned int flags, unsigned int type)
1415 struct wm_coeff_ctl *ctl;
1416 struct wmfw_ctl_work *ctl_work;
1417 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
1418 const char *region_name;
1421 region_name = wm_adsp_mem_region_name(alg_region->type);
1423 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
1427 switch (dsp->fw_ver) {
1430 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s %x",
1431 dsp->name, region_name, alg_region->alg);
1432 subname = NULL; /* don't append subname */
1435 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1436 "%s%c %.12s %x", dsp->name, *region_name,
1437 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1440 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1441 "%s %.12s %x", dsp->name,
1442 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1447 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1450 if (dsp->component->name_prefix)
1451 avail -= strlen(dsp->component->name_prefix) + 1;
1453 /* Truncate the subname from the start if it is too long */
1454 if (subname_len > avail)
1455 skip = subname_len - avail;
1457 snprintf(name + ret, SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret,
1458 " %.*s", subname_len - skip, subname + skip);
1461 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1462 if (!strcmp(ctl->name, name)) {
1469 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1472 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
1473 ctl->alg_region = *alg_region;
1474 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1480 ctl->subname_len = subname_len;
1481 ctl->subname = kmemdup(subname,
1482 strlen(subname) + 1, GFP_KERNEL);
1483 if (!ctl->subname) {
1490 ctl->ops.xget = wm_coeff_get;
1491 ctl->ops.xput = wm_coeff_put;
1496 ctl->offset = offset;
1498 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1501 goto err_ctl_subname;
1504 list_add(&ctl->list, &dsp->ctl_list);
1506 if (flags & WMFW_CTL_FLAG_SYS)
1509 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1515 ctl_work->dsp = dsp;
1516 ctl_work->ctl = ctl;
1517 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1518 schedule_work(&ctl_work->work);
1525 kfree(ctl->subname);
1534 struct wm_coeff_parsed_alg {
1541 struct wm_coeff_parsed_coeff {
1551 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1560 length = le16_to_cpu(*((__le16 *)*pos));
1567 *str = *pos + bytes;
1569 *pos += ((length + bytes) + 3) & ~0x03;
1574 static int wm_coeff_parse_int(int bytes, const u8 **pos)
1580 val = le16_to_cpu(*((__le16 *)*pos));
1583 val = le32_to_cpu(*((__le32 *)*pos));
1594 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1595 struct wm_coeff_parsed_alg *blk)
1597 const struct wmfw_adsp_alg_data *raw;
1599 switch (dsp->fw_ver) {
1602 raw = (const struct wmfw_adsp_alg_data *)*data;
1605 blk->id = le32_to_cpu(raw->id);
1606 blk->name = raw->name;
1607 blk->name_len = strlen(raw->name);
1608 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1611 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1612 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1614 wm_coeff_parse_string(sizeof(u16), data, NULL);
1615 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1619 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1620 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1621 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1624 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1625 struct wm_coeff_parsed_coeff *blk)
1627 const struct wmfw_adsp_coeff_data *raw;
1631 switch (dsp->fw_ver) {
1634 raw = (const struct wmfw_adsp_coeff_data *)*data;
1635 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1637 blk->offset = le16_to_cpu(raw->hdr.offset);
1638 blk->mem_type = le16_to_cpu(raw->hdr.type);
1639 blk->name = raw->name;
1640 blk->name_len = strlen(raw->name);
1641 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1642 blk->flags = le16_to_cpu(raw->flags);
1643 blk->len = le32_to_cpu(raw->len);
1647 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1648 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1649 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1650 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1652 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1653 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1654 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1655 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1656 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1658 *data = *data + sizeof(raw->hdr) + length;
1662 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1663 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1664 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1665 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1666 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1667 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1670 static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1671 const struct wm_coeff_parsed_coeff *coeff_blk,
1672 unsigned int f_required,
1673 unsigned int f_illegal)
1675 if ((coeff_blk->flags & f_illegal) ||
1676 ((coeff_blk->flags & f_required) != f_required)) {
1677 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1678 coeff_blk->flags, coeff_blk->ctl_type);
1685 static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1686 const struct wmfw_region *region)
1688 struct wm_adsp_alg_region alg_region = {};
1689 struct wm_coeff_parsed_alg alg_blk;
1690 struct wm_coeff_parsed_coeff coeff_blk;
1691 const u8 *data = region->data;
1694 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1695 for (i = 0; i < alg_blk.ncoeff; i++) {
1696 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1698 switch (coeff_blk.ctl_type) {
1699 case SNDRV_CTL_ELEM_TYPE_BYTES:
1701 case WMFW_CTL_TYPE_ACKED:
1702 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1703 continue; /* ignore */
1705 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1706 WMFW_CTL_FLAG_VOLATILE |
1707 WMFW_CTL_FLAG_WRITEABLE |
1708 WMFW_CTL_FLAG_READABLE,
1713 case WMFW_CTL_TYPE_HOSTEVENT:
1714 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1716 WMFW_CTL_FLAG_VOLATILE |
1717 WMFW_CTL_FLAG_WRITEABLE |
1718 WMFW_CTL_FLAG_READABLE,
1723 case WMFW_CTL_TYPE_HOST_BUFFER:
1724 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1726 WMFW_CTL_FLAG_VOLATILE |
1727 WMFW_CTL_FLAG_READABLE,
1733 adsp_err(dsp, "Unknown control type: %d\n",
1734 coeff_blk.ctl_type);
1738 alg_region.type = coeff_blk.mem_type;
1739 alg_region.alg = alg_blk.id;
1741 ret = wm_adsp_create_control(dsp, &alg_region,
1747 coeff_blk.ctl_type);
1749 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1750 coeff_blk.name_len, coeff_blk.name, ret);
1756 static unsigned int wm_adsp1_parse_sizes(struct wm_adsp *dsp,
1757 const char * const file,
1759 const struct firmware *firmware)
1761 const struct wmfw_adsp1_sizes *adsp1_sizes;
1763 adsp1_sizes = (void *)&firmware->data[pos];
1765 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file,
1766 le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm),
1767 le32_to_cpu(adsp1_sizes->zm));
1769 return pos + sizeof(*adsp1_sizes);
1772 static unsigned int wm_adsp2_parse_sizes(struct wm_adsp *dsp,
1773 const char * const file,
1775 const struct firmware *firmware)
1777 const struct wmfw_adsp2_sizes *adsp2_sizes;
1779 adsp2_sizes = (void *)&firmware->data[pos];
1781 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file,
1782 le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym),
1783 le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm));
1785 return pos + sizeof(*adsp2_sizes);
1788 static bool wm_adsp_validate_version(struct wm_adsp *dsp, unsigned int version)
1792 adsp_warn(dsp, "Deprecated file format %d\n", version);
1802 static bool wm_halo_validate_version(struct wm_adsp *dsp, unsigned int version)
1812 static int wm_adsp_load(struct wm_adsp *dsp)
1814 LIST_HEAD(buf_list);
1815 const struct firmware *firmware;
1816 struct regmap *regmap = dsp->regmap;
1817 unsigned int pos = 0;
1818 const struct wmfw_header *header;
1819 const struct wmfw_adsp1_sizes *adsp1_sizes;
1820 const struct wmfw_footer *footer;
1821 const struct wmfw_region *region;
1822 const struct wm_adsp_region *mem;
1823 const char *region_name;
1824 char *file, *text = NULL;
1825 struct wm_adsp_buf *buf;
1828 int ret, offset, type;
1830 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1834 snprintf(file, PAGE_SIZE, "%s-%s-%s.wmfw", dsp->part, dsp->fwf_name,
1835 wm_adsp_fw[dsp->fw].file);
1836 file[PAGE_SIZE - 1] = '\0';
1838 ret = request_firmware(&firmware, file, dsp->dev);
1840 adsp_err(dsp, "Failed to request '%s'\n", file);
1845 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1846 if (pos >= firmware->size) {
1847 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1848 file, firmware->size);
1852 header = (void *)&firmware->data[0];
1854 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1855 adsp_err(dsp, "%s: invalid magic\n", file);
1859 if (!dsp->ops->validate_version(dsp, header->ver)) {
1860 adsp_err(dsp, "%s: unknown file format %d\n",
1865 adsp_info(dsp, "Firmware version: %d\n", header->ver);
1866 dsp->fw_ver = header->ver;
1868 if (header->core != dsp->type) {
1869 adsp_err(dsp, "%s: invalid core %d != %d\n",
1870 file, header->core, dsp->type);
1874 pos = sizeof(*header);
1875 pos = dsp->ops->parse_sizes(dsp, file, pos, firmware);
1877 footer = (void *)&firmware->data[pos];
1878 pos += sizeof(*footer);
1880 if (le32_to_cpu(header->len) != pos) {
1881 adsp_err(dsp, "%s: unexpected header length %d\n",
1882 file, le32_to_cpu(header->len));
1886 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1887 le64_to_cpu(footer->timestamp));
1889 while (pos < firmware->size &&
1890 sizeof(*region) < firmware->size - pos) {
1891 region = (void *)&(firmware->data[pos]);
1892 region_name = "Unknown";
1895 offset = le32_to_cpu(region->offset) & 0xffffff;
1896 type = be32_to_cpu(region->type) & 0xff;
1899 case WMFW_NAME_TEXT:
1900 region_name = "Firmware name";
1901 text = kzalloc(le32_to_cpu(region->len) + 1,
1904 case WMFW_ALGORITHM_DATA:
1905 region_name = "Algorithm";
1906 ret = wm_adsp_parse_coeff(dsp, region);
1910 case WMFW_INFO_TEXT:
1911 region_name = "Information";
1912 text = kzalloc(le32_to_cpu(region->len) + 1,
1916 region_name = "Absolute";
1924 case WMFW_HALO_PM_PACKED:
1925 case WMFW_HALO_XM_PACKED:
1926 case WMFW_HALO_YM_PACKED:
1927 mem = wm_adsp_find_region(dsp, type);
1929 adsp_err(dsp, "No region of type: %x\n", type);
1933 region_name = wm_adsp_mem_region_name(type);
1934 reg = dsp->ops->region_to_reg(mem, offset);
1938 "%s.%d: Unknown region type %x at %d(%x)\n",
1939 file, regions, type, pos, pos);
1943 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1944 regions, le32_to_cpu(region->len), offset,
1947 if (le32_to_cpu(region->len) >
1948 firmware->size - pos - sizeof(*region)) {
1950 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1951 file, regions, region_name,
1952 le32_to_cpu(region->len), firmware->size);
1958 memcpy(text, region->data, le32_to_cpu(region->len));
1959 adsp_info(dsp, "%s: %s\n", file, text);
1965 buf = wm_adsp_buf_alloc(region->data,
1966 le32_to_cpu(region->len),
1969 adsp_err(dsp, "Out of memory\n");
1974 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1975 le32_to_cpu(region->len));
1978 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1980 le32_to_cpu(region->len), offset,
1986 pos += le32_to_cpu(region->len) + sizeof(*region);
1990 ret = regmap_async_complete(regmap);
1992 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1996 if (pos > firmware->size)
1997 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1998 file, regions, pos - firmware->size);
2000 wm_adsp_debugfs_save_wmfwname(dsp, file);
2003 regmap_async_complete(regmap);
2004 wm_adsp_buf_free(&buf_list);
2005 release_firmware(firmware);
2014 * Find wm_coeff_ctl with input name as its subname
2015 * If not found, return NULL
2017 static struct wm_coeff_ctl *wm_adsp_get_ctl(struct wm_adsp *dsp,
2018 const char *name, int type,
2021 struct wm_coeff_ctl *pos, *rslt = NULL;
2023 list_for_each_entry(pos, &dsp->ctl_list, list) {
2026 if (strncmp(pos->subname, name, pos->subname_len) == 0 &&
2027 pos->alg_region.alg == alg &&
2028 pos->alg_region.type == type) {
2037 int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, int type,
2038 unsigned int alg, void *buf, size_t len)
2040 struct wm_coeff_ctl *ctl;
2041 struct snd_kcontrol *kcontrol;
2044 ctl = wm_adsp_get_ctl(dsp, name, type, alg);
2051 ret = wm_coeff_write_control(ctl, buf, len);
2053 kcontrol = snd_soc_card_get_kcontrol(dsp->component->card, ctl->name);
2054 snd_ctl_notify(dsp->component->card->snd_card,
2055 SNDRV_CTL_EVENT_MASK_VALUE, &kcontrol->id);
2059 EXPORT_SYMBOL_GPL(wm_adsp_write_ctl);
2061 int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, int type,
2062 unsigned int alg, void *buf, size_t len)
2064 struct wm_coeff_ctl *ctl;
2066 ctl = wm_adsp_get_ctl(dsp, name, type, alg);
2073 return wm_coeff_read_control(ctl, buf, len);
2075 EXPORT_SYMBOL_GPL(wm_adsp_read_ctl);
2077 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
2078 const struct wm_adsp_alg_region *alg_region)
2080 struct wm_coeff_ctl *ctl;
2082 list_for_each_entry(ctl, &dsp->ctl_list, list) {
2083 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
2084 alg_region->alg == ctl->alg_region.alg &&
2085 alg_region->type == ctl->alg_region.type) {
2086 ctl->alg_region.base = alg_region->base;
2091 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
2092 const struct wm_adsp_region *mem,
2093 unsigned int pos, unsigned int len)
2101 adsp_err(dsp, "No algorithms\n");
2102 return ERR_PTR(-EINVAL);
2105 if (n_algs > 1024) {
2106 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
2107 return ERR_PTR(-EINVAL);
2110 /* Read the terminator first to validate the length */
2111 reg = dsp->ops->region_to_reg(mem, pos + len);
2113 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
2115 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
2117 return ERR_PTR(ret);
2120 if (be32_to_cpu(val) != 0xbedead)
2121 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n",
2122 reg, be32_to_cpu(val));
2124 /* Convert length from DSP words to bytes */
2127 alg = kzalloc(len, GFP_KERNEL | GFP_DMA);
2129 return ERR_PTR(-ENOMEM);
2131 reg = dsp->ops->region_to_reg(mem, pos);
2133 ret = regmap_raw_read(dsp->regmap, reg, alg, len);
2135 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
2137 return ERR_PTR(ret);
2143 static struct wm_adsp_alg_region *
2144 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
2146 struct wm_adsp_alg_region *alg_region;
2148 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
2149 if (id == alg_region->alg && type == alg_region->type)
2156 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
2157 int type, __be32 id,
2160 struct wm_adsp_alg_region *alg_region;
2162 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
2164 return ERR_PTR(-ENOMEM);
2166 alg_region->type = type;
2167 alg_region->alg = be32_to_cpu(id);
2168 alg_region->base = be32_to_cpu(base);
2170 list_add_tail(&alg_region->list, &dsp->alg_regions);
2172 if (dsp->fw_ver > 0)
2173 wm_adsp_ctl_fixup_base(dsp, alg_region);
2178 static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
2180 struct wm_adsp_alg_region *alg_region;
2182 while (!list_empty(&dsp->alg_regions)) {
2183 alg_region = list_first_entry(&dsp->alg_regions,
2184 struct wm_adsp_alg_region,
2186 list_del(&alg_region->list);
2191 static void wmfw_parse_id_header(struct wm_adsp *dsp,
2192 struct wmfw_id_hdr *fw, int nalgs)
2194 dsp->fw_id = be32_to_cpu(fw->id);
2195 dsp->fw_id_version = be32_to_cpu(fw->ver);
2197 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n",
2198 dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16,
2199 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
2203 static void wmfw_v3_parse_id_header(struct wm_adsp *dsp,
2204 struct wmfw_v3_id_hdr *fw, int nalgs)
2206 dsp->fw_id = be32_to_cpu(fw->id);
2207 dsp->fw_id_version = be32_to_cpu(fw->ver);
2208 dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id);
2210 adsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n",
2211 dsp->fw_id, dsp->fw_vendor_id,
2212 (dsp->fw_id_version & 0xff0000) >> 16,
2213 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff,
2217 static int wm_adsp_create_regions(struct wm_adsp *dsp, __be32 id, int nregions,
2218 int *type, __be32 *base)
2220 struct wm_adsp_alg_region *alg_region;
2223 for (i = 0; i < nregions; i++) {
2224 alg_region = wm_adsp_create_region(dsp, type[i], id, base[i]);
2225 if (IS_ERR(alg_region))
2226 return PTR_ERR(alg_region);
2232 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
2234 struct wmfw_adsp1_id_hdr adsp1_id;
2235 struct wmfw_adsp1_alg_hdr *adsp1_alg;
2236 struct wm_adsp_alg_region *alg_region;
2237 const struct wm_adsp_region *mem;
2238 unsigned int pos, len;
2242 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
2246 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
2249 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2254 n_algs = be32_to_cpu(adsp1_id.n_algs);
2256 wmfw_parse_id_header(dsp, &adsp1_id.fw, n_algs);
2258 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2259 adsp1_id.fw.id, adsp1_id.zm);
2260 if (IS_ERR(alg_region))
2261 return PTR_ERR(alg_region);
2263 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2264 adsp1_id.fw.id, adsp1_id.dm);
2265 if (IS_ERR(alg_region))
2266 return PTR_ERR(alg_region);
2268 /* Calculate offset and length in DSP words */
2269 pos = sizeof(adsp1_id) / sizeof(u32);
2270 len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32);
2272 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2273 if (IS_ERR(adsp1_alg))
2274 return PTR_ERR(adsp1_alg);
2276 for (i = 0; i < n_algs; i++) {
2277 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2278 i, be32_to_cpu(adsp1_alg[i].alg.id),
2279 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
2280 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
2281 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
2282 be32_to_cpu(adsp1_alg[i].dm),
2283 be32_to_cpu(adsp1_alg[i].zm));
2285 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2286 adsp1_alg[i].alg.id,
2288 if (IS_ERR(alg_region)) {
2289 ret = PTR_ERR(alg_region);
2292 if (dsp->fw_ver == 0) {
2293 if (i + 1 < n_algs) {
2294 len = be32_to_cpu(adsp1_alg[i + 1].dm);
2295 len -= be32_to_cpu(adsp1_alg[i].dm);
2297 wm_adsp_create_control(dsp, alg_region, 0,
2299 SNDRV_CTL_ELEM_TYPE_BYTES);
2301 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
2302 be32_to_cpu(adsp1_alg[i].alg.id));
2306 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2307 adsp1_alg[i].alg.id,
2309 if (IS_ERR(alg_region)) {
2310 ret = PTR_ERR(alg_region);
2313 if (dsp->fw_ver == 0) {
2314 if (i + 1 < n_algs) {
2315 len = be32_to_cpu(adsp1_alg[i + 1].zm);
2316 len -= be32_to_cpu(adsp1_alg[i].zm);
2318 wm_adsp_create_control(dsp, alg_region, 0,
2320 SNDRV_CTL_ELEM_TYPE_BYTES);
2322 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2323 be32_to_cpu(adsp1_alg[i].alg.id));
2333 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
2335 struct wmfw_adsp2_id_hdr adsp2_id;
2336 struct wmfw_adsp2_alg_hdr *adsp2_alg;
2337 struct wm_adsp_alg_region *alg_region;
2338 const struct wm_adsp_region *mem;
2339 unsigned int pos, len;
2343 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2347 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2350 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2355 n_algs = be32_to_cpu(adsp2_id.n_algs);
2357 wmfw_parse_id_header(dsp, &adsp2_id.fw, n_algs);
2359 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2360 adsp2_id.fw.id, adsp2_id.xm);
2361 if (IS_ERR(alg_region))
2362 return PTR_ERR(alg_region);
2364 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2365 adsp2_id.fw.id, adsp2_id.ym);
2366 if (IS_ERR(alg_region))
2367 return PTR_ERR(alg_region);
2369 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2370 adsp2_id.fw.id, adsp2_id.zm);
2371 if (IS_ERR(alg_region))
2372 return PTR_ERR(alg_region);
2374 /* Calculate offset and length in DSP words */
2375 pos = sizeof(adsp2_id) / sizeof(u32);
2376 len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32);
2378 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2379 if (IS_ERR(adsp2_alg))
2380 return PTR_ERR(adsp2_alg);
2382 for (i = 0; i < n_algs; i++) {
2384 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2385 i, be32_to_cpu(adsp2_alg[i].alg.id),
2386 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2387 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2388 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2389 be32_to_cpu(adsp2_alg[i].xm),
2390 be32_to_cpu(adsp2_alg[i].ym),
2391 be32_to_cpu(adsp2_alg[i].zm));
2393 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2394 adsp2_alg[i].alg.id,
2396 if (IS_ERR(alg_region)) {
2397 ret = PTR_ERR(alg_region);
2400 if (dsp->fw_ver == 0) {
2401 if (i + 1 < n_algs) {
2402 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2403 len -= be32_to_cpu(adsp2_alg[i].xm);
2405 wm_adsp_create_control(dsp, alg_region, 0,
2407 SNDRV_CTL_ELEM_TYPE_BYTES);
2409 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2410 be32_to_cpu(adsp2_alg[i].alg.id));
2414 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2415 adsp2_alg[i].alg.id,
2417 if (IS_ERR(alg_region)) {
2418 ret = PTR_ERR(alg_region);
2421 if (dsp->fw_ver == 0) {
2422 if (i + 1 < n_algs) {
2423 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2424 len -= be32_to_cpu(adsp2_alg[i].ym);
2426 wm_adsp_create_control(dsp, alg_region, 0,
2428 SNDRV_CTL_ELEM_TYPE_BYTES);
2430 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2431 be32_to_cpu(adsp2_alg[i].alg.id));
2435 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2436 adsp2_alg[i].alg.id,
2438 if (IS_ERR(alg_region)) {
2439 ret = PTR_ERR(alg_region);
2442 if (dsp->fw_ver == 0) {
2443 if (i + 1 < n_algs) {
2444 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2445 len -= be32_to_cpu(adsp2_alg[i].zm);
2447 wm_adsp_create_control(dsp, alg_region, 0,
2449 SNDRV_CTL_ELEM_TYPE_BYTES);
2451 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2452 be32_to_cpu(adsp2_alg[i].alg.id));
2462 static int wm_halo_create_regions(struct wm_adsp *dsp, __be32 id,
2463 __be32 xm_base, __be32 ym_base)
2466 WMFW_ADSP2_XM, WMFW_HALO_XM_PACKED,
2467 WMFW_ADSP2_YM, WMFW_HALO_YM_PACKED
2469 __be32 bases[] = { xm_base, xm_base, ym_base, ym_base };
2471 return wm_adsp_create_regions(dsp, id, ARRAY_SIZE(types), types, bases);
2474 static int wm_halo_setup_algs(struct wm_adsp *dsp)
2476 struct wmfw_halo_id_hdr halo_id;
2477 struct wmfw_halo_alg_hdr *halo_alg;
2478 const struct wm_adsp_region *mem;
2479 unsigned int pos, len;
2483 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2487 ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id,
2490 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2495 n_algs = be32_to_cpu(halo_id.n_algs);
2497 wmfw_v3_parse_id_header(dsp, &halo_id.fw, n_algs);
2499 ret = wm_halo_create_regions(dsp, halo_id.fw.id,
2500 halo_id.xm_base, halo_id.ym_base);
2504 /* Calculate offset and length in DSP words */
2505 pos = sizeof(halo_id) / sizeof(u32);
2506 len = (sizeof(*halo_alg) * n_algs) / sizeof(u32);
2508 halo_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2509 if (IS_ERR(halo_alg))
2510 return PTR_ERR(halo_alg);
2512 for (i = 0; i < n_algs; i++) {
2514 "%d: ID %x v%d.%d.%d XM@%x YM@%x\n",
2515 i, be32_to_cpu(halo_alg[i].alg.id),
2516 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16,
2517 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8,
2518 be32_to_cpu(halo_alg[i].alg.ver) & 0xff,
2519 be32_to_cpu(halo_alg[i].xm_base),
2520 be32_to_cpu(halo_alg[i].ym_base));
2522 ret = wm_halo_create_regions(dsp, halo_alg[i].alg.id,
2523 halo_alg[i].xm_base,
2524 halo_alg[i].ym_base);
2534 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2536 LIST_HEAD(buf_list);
2537 struct regmap *regmap = dsp->regmap;
2538 struct wmfw_coeff_hdr *hdr;
2539 struct wmfw_coeff_item *blk;
2540 const struct firmware *firmware;
2541 const struct wm_adsp_region *mem;
2542 struct wm_adsp_alg_region *alg_region;
2543 const char *region_name;
2544 int ret, pos, blocks, type, offset, reg;
2546 struct wm_adsp_buf *buf;
2548 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2552 snprintf(file, PAGE_SIZE, "%s-%s-%s.bin", dsp->part, dsp->fwf_name,
2553 wm_adsp_fw[dsp->fw].file);
2554 file[PAGE_SIZE - 1] = '\0';
2556 ret = request_firmware(&firmware, file, dsp->dev);
2558 adsp_warn(dsp, "Failed to request '%s'\n", file);
2564 if (sizeof(*hdr) >= firmware->size) {
2565 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2566 file, firmware->size);
2570 hdr = (void *)&firmware->data[0];
2571 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2572 adsp_err(dsp, "%s: invalid magic\n", file);
2576 switch (be32_to_cpu(hdr->rev) & 0xff) {
2580 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2581 file, be32_to_cpu(hdr->rev) & 0xff);
2586 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2587 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2588 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2589 le32_to_cpu(hdr->ver) & 0xff);
2591 pos = le32_to_cpu(hdr->len);
2594 while (pos < firmware->size &&
2595 sizeof(*blk) < firmware->size - pos) {
2596 blk = (void *)(&firmware->data[pos]);
2598 type = le16_to_cpu(blk->type);
2599 offset = le16_to_cpu(blk->offset);
2601 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2602 file, blocks, le32_to_cpu(blk->id),
2603 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2604 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2605 le32_to_cpu(blk->ver) & 0xff);
2606 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2607 file, blocks, le32_to_cpu(blk->len), offset, type);
2610 region_name = "Unknown";
2612 case (WMFW_NAME_TEXT << 8):
2613 case (WMFW_INFO_TEXT << 8):
2615 case (WMFW_ABSOLUTE << 8):
2617 * Old files may use this for global
2620 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2622 region_name = "global coefficients";
2623 mem = wm_adsp_find_region(dsp, type);
2625 adsp_err(dsp, "No ZM\n");
2628 reg = dsp->ops->region_to_reg(mem, 0);
2631 region_name = "register";
2640 case WMFW_HALO_XM_PACKED:
2641 case WMFW_HALO_YM_PACKED:
2642 case WMFW_HALO_PM_PACKED:
2643 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2644 file, blocks, le32_to_cpu(blk->len),
2645 type, le32_to_cpu(blk->id));
2647 mem = wm_adsp_find_region(dsp, type);
2649 adsp_err(dsp, "No base for region %x\n", type);
2653 alg_region = wm_adsp_find_alg_region(dsp, type,
2654 le32_to_cpu(blk->id));
2656 reg = alg_region->base;
2657 reg = dsp->ops->region_to_reg(mem, reg);
2660 adsp_err(dsp, "No %x for algorithm %x\n",
2661 type, le32_to_cpu(blk->id));
2666 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2667 file, blocks, type, pos);
2672 if (le32_to_cpu(blk->len) >
2673 firmware->size - pos - sizeof(*blk)) {
2675 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2676 file, blocks, region_name,
2677 le32_to_cpu(blk->len),
2683 buf = wm_adsp_buf_alloc(blk->data,
2684 le32_to_cpu(blk->len),
2687 adsp_err(dsp, "Out of memory\n");
2692 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2693 file, blocks, le32_to_cpu(blk->len),
2695 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2696 le32_to_cpu(blk->len));
2699 "%s.%d: Failed to write to %x in %s: %d\n",
2700 file, blocks, reg, region_name, ret);
2704 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2708 ret = regmap_async_complete(regmap);
2710 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2712 if (pos > firmware->size)
2713 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2714 file, blocks, pos - firmware->size);
2716 wm_adsp_debugfs_save_binname(dsp, file);
2719 regmap_async_complete(regmap);
2720 release_firmware(firmware);
2721 wm_adsp_buf_free(&buf_list);
2727 static int wm_adsp_create_name(struct wm_adsp *dsp)
2732 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d",
2738 if (!dsp->fwf_name) {
2739 p = devm_kstrdup(dsp->dev, dsp->name, GFP_KERNEL);
2744 for (; *p != 0; ++p)
2751 static int wm_adsp_common_init(struct wm_adsp *dsp)
2755 ret = wm_adsp_create_name(dsp);
2759 INIT_LIST_HEAD(&dsp->alg_regions);
2760 INIT_LIST_HEAD(&dsp->ctl_list);
2761 INIT_LIST_HEAD(&dsp->compr_list);
2762 INIT_LIST_HEAD(&dsp->buffer_list);
2764 mutex_init(&dsp->pwr_lock);
2769 int wm_adsp1_init(struct wm_adsp *dsp)
2771 dsp->ops = &wm_adsp1_ops;
2773 return wm_adsp_common_init(dsp);
2775 EXPORT_SYMBOL_GPL(wm_adsp1_init);
2777 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2778 struct snd_kcontrol *kcontrol,
2781 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2782 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2783 struct wm_adsp *dsp = &dsps[w->shift];
2784 struct wm_coeff_ctl *ctl;
2788 dsp->component = component;
2790 mutex_lock(&dsp->pwr_lock);
2793 case SND_SOC_DAPM_POST_PMU:
2794 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2795 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2798 * For simplicity set the DSP clock rate to be the
2799 * SYSCLK rate rather than making it configurable.
2801 if (dsp->sysclk_reg) {
2802 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2804 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2809 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
2811 ret = regmap_update_bits(dsp->regmap,
2812 dsp->base + ADSP1_CONTROL_31,
2813 ADSP1_CLK_SEL_MASK, val);
2815 adsp_err(dsp, "Failed to set clock rate: %d\n",
2821 ret = wm_adsp_load(dsp);
2825 ret = wm_adsp1_setup_algs(dsp);
2829 ret = wm_adsp_load_coeff(dsp);
2833 /* Initialize caches for enabled and unset controls */
2834 ret = wm_coeff_init_control_caches(dsp);
2838 /* Sync set controls */
2839 ret = wm_coeff_sync_controls(dsp);
2845 /* Start the core running */
2846 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2847 ADSP1_CORE_ENA | ADSP1_START,
2848 ADSP1_CORE_ENA | ADSP1_START);
2850 dsp->running = true;
2853 case SND_SOC_DAPM_PRE_PMD:
2854 dsp->running = false;
2855 dsp->booted = false;
2858 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2859 ADSP1_CORE_ENA | ADSP1_START, 0);
2861 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2862 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2864 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2867 list_for_each_entry(ctl, &dsp->ctl_list, list)
2871 wm_adsp_free_alg_regions(dsp);
2878 mutex_unlock(&dsp->pwr_lock);
2883 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2886 mutex_unlock(&dsp->pwr_lock);
2890 EXPORT_SYMBOL_GPL(wm_adsp1_event);
2892 static int wm_adsp2v2_enable_core(struct wm_adsp *dsp)
2897 /* Wait for the RAM to start, should be near instantaneous */
2898 for (count = 0; count < 10; ++count) {
2899 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2903 if (val & ADSP2_RAM_RDY)
2906 usleep_range(250, 500);
2909 if (!(val & ADSP2_RAM_RDY)) {
2910 adsp_err(dsp, "Failed to start DSP RAM\n");
2914 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2919 static int wm_adsp2_enable_core(struct wm_adsp *dsp)
2923 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
2924 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2928 return wm_adsp2v2_enable_core(dsp);
2931 static int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions)
2933 struct regmap *regmap = dsp->regmap;
2934 unsigned int code0, code1, lock_reg;
2936 if (!(lock_regions & WM_ADSP2_REGION_ALL))
2939 lock_regions &= WM_ADSP2_REGION_ALL;
2940 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
2942 while (lock_regions) {
2944 if (lock_regions & BIT(0)) {
2945 code0 = ADSP2_LOCK_CODE_0;
2946 code1 = ADSP2_LOCK_CODE_1;
2948 if (lock_regions & BIT(1)) {
2949 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
2950 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
2952 regmap_write(regmap, lock_reg, code0);
2953 regmap_write(regmap, lock_reg, code1);
2961 static int wm_adsp2_enable_memory(struct wm_adsp *dsp)
2963 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2964 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2967 static void wm_adsp2_disable_memory(struct wm_adsp *dsp)
2969 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2973 static void wm_adsp2_disable_core(struct wm_adsp *dsp)
2975 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2976 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2977 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2979 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2983 static void wm_adsp2v2_disable_core(struct wm_adsp *dsp)
2985 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2986 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2987 regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
2990 static void wm_adsp_boot_work(struct work_struct *work)
2992 struct wm_adsp *dsp = container_of(work,
2997 mutex_lock(&dsp->pwr_lock);
2999 if (dsp->ops->enable_memory) {
3000 ret = dsp->ops->enable_memory(dsp);
3005 if (dsp->ops->enable_core) {
3006 ret = dsp->ops->enable_core(dsp);
3011 ret = wm_adsp_load(dsp);
3015 ret = dsp->ops->setup_algs(dsp);
3019 ret = wm_adsp_load_coeff(dsp);
3023 /* Initialize caches for enabled and unset controls */
3024 ret = wm_coeff_init_control_caches(dsp);
3028 if (dsp->ops->disable_core)
3029 dsp->ops->disable_core(dsp);
3033 mutex_unlock(&dsp->pwr_lock);
3038 if (dsp->ops->disable_core)
3039 dsp->ops->disable_core(dsp);
3041 if (dsp->ops->disable_memory)
3042 dsp->ops->disable_memory(dsp);
3044 mutex_unlock(&dsp->pwr_lock);
3047 static int wm_halo_configure_mpu(struct wm_adsp *dsp, unsigned int lock_regions)
3049 struct reg_sequence config[] = {
3050 { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 },
3051 { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA },
3052 { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF },
3053 { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF },
3054 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions },
3055 { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions },
3056 { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions },
3057 { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF },
3058 { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF },
3059 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions },
3060 { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions },
3061 { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions },
3062 { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF },
3063 { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF },
3064 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions },
3065 { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions },
3066 { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions },
3067 { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF },
3068 { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF },
3069 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions },
3070 { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions },
3071 { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions },
3072 { dsp->base + HALO_MPU_LOCK_CONFIG, 0 },
3075 return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config));
3078 int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq)
3080 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3081 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3082 struct wm_adsp *dsp = &dsps[w->shift];
3085 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING,
3087 freq << ADSP2_CLK_SEL_SHIFT);
3089 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
3093 EXPORT_SYMBOL_GPL(wm_adsp2_set_dspclk);
3095 int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
3096 struct snd_ctl_elem_value *ucontrol)
3098 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3099 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3100 struct soc_mixer_control *mc =
3101 (struct soc_mixer_control *)kcontrol->private_value;
3102 struct wm_adsp *dsp = &dsps[mc->shift - 1];
3104 ucontrol->value.integer.value[0] = dsp->preloaded;
3108 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
3110 int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
3111 struct snd_ctl_elem_value *ucontrol)
3113 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3114 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3115 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3116 struct soc_mixer_control *mc =
3117 (struct soc_mixer_control *)kcontrol->private_value;
3118 struct wm_adsp *dsp = &dsps[mc->shift - 1];
3121 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
3123 dsp->preloaded = ucontrol->value.integer.value[0];
3125 if (ucontrol->value.integer.value[0])
3126 snd_soc_component_force_enable_pin(component, preload);
3128 snd_soc_component_disable_pin(component, preload);
3130 snd_soc_dapm_sync(dapm);
3132 flush_work(&dsp->boot_work);
3136 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
3138 static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
3140 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
3141 ADSP2_WDT_ENA_MASK, 0);
3144 static void wm_halo_stop_watchdog(struct wm_adsp *dsp)
3146 regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL,
3147 HALO_WDT_EN_MASK, 0);
3150 int wm_adsp_early_event(struct snd_soc_dapm_widget *w,
3151 struct snd_kcontrol *kcontrol, int event)
3153 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3154 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3155 struct wm_adsp *dsp = &dsps[w->shift];
3156 struct wm_coeff_ctl *ctl;
3159 case SND_SOC_DAPM_PRE_PMU:
3160 queue_work(system_unbound_wq, &dsp->boot_work);
3162 case SND_SOC_DAPM_PRE_PMD:
3163 mutex_lock(&dsp->pwr_lock);
3165 wm_adsp_debugfs_clear(dsp);
3168 dsp->fw_id_version = 0;
3170 dsp->booted = false;
3172 if (dsp->ops->disable_memory)
3173 dsp->ops->disable_memory(dsp);
3175 list_for_each_entry(ctl, &dsp->ctl_list, list)
3178 wm_adsp_free_alg_regions(dsp);
3180 mutex_unlock(&dsp->pwr_lock);
3182 adsp_dbg(dsp, "Shutdown complete\n");
3190 EXPORT_SYMBOL_GPL(wm_adsp_early_event);
3192 static int wm_adsp2_start_core(struct wm_adsp *dsp)
3194 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3195 ADSP2_CORE_ENA | ADSP2_START,
3196 ADSP2_CORE_ENA | ADSP2_START);
3199 static void wm_adsp2_stop_core(struct wm_adsp *dsp)
3201 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3202 ADSP2_CORE_ENA | ADSP2_START, 0);
3205 int wm_adsp_event(struct snd_soc_dapm_widget *w,
3206 struct snd_kcontrol *kcontrol, int event)
3208 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
3209 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
3210 struct wm_adsp *dsp = &dsps[w->shift];
3214 case SND_SOC_DAPM_POST_PMU:
3215 flush_work(&dsp->boot_work);
3217 mutex_lock(&dsp->pwr_lock);
3224 if (dsp->ops->enable_core) {
3225 ret = dsp->ops->enable_core(dsp);
3230 /* Sync set controls */
3231 ret = wm_coeff_sync_controls(dsp);
3235 if (dsp->ops->lock_memory) {
3236 ret = dsp->ops->lock_memory(dsp, dsp->lock_regions);
3238 adsp_err(dsp, "Error configuring MPU: %d\n",
3244 if (dsp->ops->start_core) {
3245 ret = dsp->ops->start_core(dsp);
3250 if (wm_adsp_fw[dsp->fw].num_caps != 0) {
3251 ret = wm_adsp_buffer_init(dsp);
3256 dsp->running = true;
3258 mutex_unlock(&dsp->pwr_lock);
3261 case SND_SOC_DAPM_PRE_PMD:
3262 /* Tell the firmware to cleanup */
3263 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
3265 if (dsp->ops->stop_watchdog)
3266 dsp->ops->stop_watchdog(dsp);
3268 /* Log firmware state, it can be useful for analysis */
3269 if (dsp->ops->show_fw_status)
3270 dsp->ops->show_fw_status(dsp);
3272 mutex_lock(&dsp->pwr_lock);
3274 dsp->running = false;
3276 if (dsp->ops->stop_core)
3277 dsp->ops->stop_core(dsp);
3278 if (dsp->ops->disable_core)
3279 dsp->ops->disable_core(dsp);
3281 if (wm_adsp_fw[dsp->fw].num_caps != 0)
3282 wm_adsp_buffer_free(dsp);
3284 dsp->fatal_error = false;
3286 mutex_unlock(&dsp->pwr_lock);
3288 adsp_dbg(dsp, "Execution stopped\n");
3297 if (dsp->ops->stop_core)
3298 dsp->ops->stop_core(dsp);
3299 if (dsp->ops->disable_core)
3300 dsp->ops->disable_core(dsp);
3301 mutex_unlock(&dsp->pwr_lock);
3304 EXPORT_SYMBOL_GPL(wm_adsp_event);
3306 static int wm_halo_start_core(struct wm_adsp *dsp)
3308 return regmap_update_bits(dsp->regmap,
3309 dsp->base + HALO_CCM_CORE_CONTROL,
3310 HALO_CORE_EN, HALO_CORE_EN);
3313 static void wm_halo_stop_core(struct wm_adsp *dsp)
3315 regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL,
3318 /* reset halo core with CORE_SOFT_RESET */
3319 regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET,
3320 HALO_CORE_SOFT_RESET_MASK, 1);
3323 int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component)
3327 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
3328 snd_soc_component_disable_pin(component, preload);
3330 wm_adsp2_init_debugfs(dsp, component);
3332 dsp->component = component;
3336 EXPORT_SYMBOL_GPL(wm_adsp2_component_probe);
3338 int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component)
3340 wm_adsp2_cleanup_debugfs(dsp);
3344 EXPORT_SYMBOL_GPL(wm_adsp2_component_remove);
3346 int wm_adsp2_init(struct wm_adsp *dsp)
3350 ret = wm_adsp_common_init(dsp);
3357 * Disable the DSP memory by default when in reset for a small
3360 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
3364 "Failed to clear memory retention: %d\n", ret);
3368 dsp->ops = &wm_adsp2_ops[0];
3371 dsp->ops = &wm_adsp2_ops[1];
3374 dsp->ops = &wm_adsp2_ops[2];
3378 INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
3382 EXPORT_SYMBOL_GPL(wm_adsp2_init);
3384 int wm_halo_init(struct wm_adsp *dsp)
3388 ret = wm_adsp_common_init(dsp);
3392 dsp->ops = &wm_halo_ops;
3394 INIT_WORK(&dsp->boot_work, wm_adsp_boot_work);
3398 EXPORT_SYMBOL_GPL(wm_halo_init);
3400 void wm_adsp2_remove(struct wm_adsp *dsp)
3402 struct wm_coeff_ctl *ctl;
3404 while (!list_empty(&dsp->ctl_list)) {
3405 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
3407 list_del(&ctl->list);
3408 wm_adsp_free_ctl_blk(ctl);
3411 EXPORT_SYMBOL_GPL(wm_adsp2_remove);
3413 static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
3415 return compr->buf != NULL;
3418 static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
3420 struct wm_adsp_compr_buf *buf = NULL, *tmp;
3422 if (compr->dsp->fatal_error)
3425 list_for_each_entry(tmp, &compr->dsp->buffer_list, list) {
3426 if (!tmp->name || !strcmp(compr->name, tmp->name)) {
3441 static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
3446 /* Wake the poll so it can see buffer is no longer attached */
3448 snd_compr_fragment_elapsed(compr->stream);
3450 if (wm_adsp_compr_attached(compr)) {
3451 compr->buf->compr = NULL;
3456 int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
3458 struct wm_adsp_compr *compr, *tmp;
3459 struct snd_soc_pcm_runtime *rtd = stream->private_data;
3462 mutex_lock(&dsp->pwr_lock);
3464 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
3465 adsp_err(dsp, "%s: Firmware does not support compressed API\n",
3466 rtd->codec_dai->name);
3471 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
3472 adsp_err(dsp, "%s: Firmware does not support stream direction\n",
3473 rtd->codec_dai->name);
3478 list_for_each_entry(tmp, &dsp->compr_list, list) {
3479 if (!strcmp(tmp->name, rtd->codec_dai->name)) {
3480 adsp_err(dsp, "%s: Only a single stream supported per dai\n",
3481 rtd->codec_dai->name);
3487 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
3494 compr->stream = stream;
3495 compr->name = rtd->codec_dai->name;
3497 list_add_tail(&compr->list, &dsp->compr_list);
3499 stream->runtime->private_data = compr;
3502 mutex_unlock(&dsp->pwr_lock);
3506 EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
3508 int wm_adsp_compr_free(struct snd_compr_stream *stream)
3510 struct wm_adsp_compr *compr = stream->runtime->private_data;
3511 struct wm_adsp *dsp = compr->dsp;
3513 mutex_lock(&dsp->pwr_lock);
3515 wm_adsp_compr_detach(compr);
3516 list_del(&compr->list);
3518 kfree(compr->raw_buf);
3521 mutex_unlock(&dsp->pwr_lock);
3525 EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
3527 static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
3528 struct snd_compr_params *params)
3530 struct wm_adsp_compr *compr = stream->runtime->private_data;
3531 struct wm_adsp *dsp = compr->dsp;
3532 const struct wm_adsp_fw_caps *caps;
3533 const struct snd_codec_desc *desc;
3536 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
3537 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
3538 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
3539 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
3540 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
3541 compr_err(compr, "Invalid buffer fragsize=%d fragments=%d\n",
3542 params->buffer.fragment_size,
3543 params->buffer.fragments);
3548 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
3549 caps = &wm_adsp_fw[dsp->fw].caps[i];
3552 if (caps->id != params->codec.id)
3555 if (stream->direction == SND_COMPRESS_PLAYBACK) {
3556 if (desc->max_ch < params->codec.ch_out)
3559 if (desc->max_ch < params->codec.ch_in)
3563 if (!(desc->formats & (1 << params->codec.format)))
3566 for (j = 0; j < desc->num_sample_rates; ++j)
3567 if (desc->sample_rates[j] == params->codec.sample_rate)
3571 compr_err(compr, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3572 params->codec.id, params->codec.ch_in, params->codec.ch_out,
3573 params->codec.sample_rate, params->codec.format);
3577 static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
3579 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
3582 int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
3583 struct snd_compr_params *params)
3585 struct wm_adsp_compr *compr = stream->runtime->private_data;
3589 ret = wm_adsp_compr_check_params(stream, params);
3593 compr->size = params->buffer;
3595 compr_dbg(compr, "fragment_size=%d fragments=%d\n",
3596 compr->size.fragment_size, compr->size.fragments);
3598 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
3599 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
3600 if (!compr->raw_buf)
3603 compr->sample_rate = params->codec.sample_rate;
3607 EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
3609 int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
3610 struct snd_compr_caps *caps)
3612 struct wm_adsp_compr *compr = stream->runtime->private_data;
3613 int fw = compr->dsp->fw;
3616 if (wm_adsp_fw[fw].caps) {
3617 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
3618 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
3620 caps->num_codecs = i;
3621 caps->direction = wm_adsp_fw[fw].compr_direction;
3623 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
3624 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
3625 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
3626 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
3631 EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
3633 static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
3634 unsigned int mem_addr,
3635 unsigned int num_words, u32 *data)
3637 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3638 unsigned int i, reg;
3644 reg = dsp->ops->region_to_reg(mem, mem_addr);
3646 ret = regmap_raw_read(dsp->regmap, reg, data,
3647 sizeof(*data) * num_words);
3651 for (i = 0; i < num_words; ++i)
3652 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
3657 static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
3658 unsigned int mem_addr, u32 *data)
3660 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
3663 static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
3664 unsigned int mem_addr, u32 data)
3666 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3672 reg = dsp->ops->region_to_reg(mem, mem_addr);
3674 data = cpu_to_be32(data & 0x00ffffffu);
3676 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
3679 static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
3680 unsigned int field_offset, u32 *data)
3682 return wm_adsp_read_data_word(buf->dsp, buf->host_buf_mem_type,
3683 buf->host_buf_ptr + field_offset, data);
3686 static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
3687 unsigned int field_offset, u32 data)
3689 return wm_adsp_write_data_word(buf->dsp, buf->host_buf_mem_type,
3690 buf->host_buf_ptr + field_offset, data);
3693 static void wm_adsp_remove_padding(u32 *buf, int nwords, int data_word_size)
3695 u8 *pack_in = (u8 *)buf;
3696 u8 *pack_out = (u8 *)buf;
3699 /* Remove the padding bytes from the data read from the DSP */
3700 for (i = 0; i < nwords; i++) {
3701 for (j = 0; j < data_word_size; j++)
3702 *pack_out++ = *pack_in++;
3704 pack_in += sizeof(*buf) - data_word_size;
3708 static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
3710 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
3711 struct wm_adsp_buffer_region *region;
3715 buf->regions = kcalloc(caps->num_regions, sizeof(*buf->regions),
3720 for (i = 0; i < caps->num_regions; ++i) {
3721 region = &buf->regions[i];
3723 region->offset = offset;
3724 region->mem_type = caps->region_defs[i].mem_type;
3726 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
3727 ®ion->base_addr);
3731 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
3736 region->cumulative_size = offset;
3739 "region=%d type=%d base=%08x off=%08x size=%08x\n",
3740 i, region->mem_type, region->base_addr,
3741 region->offset, region->cumulative_size);
3747 static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf)
3749 buf->irq_count = 0xFFFFFFFF;
3750 buf->read_index = -1;
3754 static struct wm_adsp_compr_buf *wm_adsp_buffer_alloc(struct wm_adsp *dsp)
3756 struct wm_adsp_compr_buf *buf;
3758 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
3764 wm_adsp_buffer_clear(buf);
3766 list_add_tail(&buf->list, &dsp->buffer_list);
3771 static int wm_adsp_buffer_parse_legacy(struct wm_adsp *dsp)
3773 struct wm_adsp_alg_region *alg_region;
3774 struct wm_adsp_compr_buf *buf;
3775 u32 xmalg, addr, magic;
3778 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
3780 adsp_err(dsp, "No algorithm region found\n");
3784 buf = wm_adsp_buffer_alloc(dsp);
3788 xmalg = dsp->ops->sys_config_size / sizeof(__be32);
3790 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3791 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
3795 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
3798 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
3799 for (i = 0; i < 5; ++i) {
3800 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
3801 &buf->host_buf_ptr);
3805 if (buf->host_buf_ptr)
3808 usleep_range(1000, 2000);
3811 if (!buf->host_buf_ptr)
3814 buf->host_buf_mem_type = WMFW_ADSP2_XM;
3816 ret = wm_adsp_buffer_populate(buf);
3820 compr_dbg(buf, "legacy host_buf_ptr=%x\n", buf->host_buf_ptr);
3825 static int wm_adsp_buffer_parse_coeff(struct wm_coeff_ctl *ctl)
3827 struct wm_adsp_host_buf_coeff_v1 coeff_v1;
3828 struct wm_adsp_compr_buf *buf;
3829 unsigned int val, reg;
3832 ret = wm_coeff_base_reg(ctl, ®);
3836 for (i = 0; i < 5; ++i) {
3837 ret = regmap_raw_read(ctl->dsp->regmap, reg, &val, sizeof(val));
3844 usleep_range(1000, 2000);
3848 adsp_err(ctl->dsp, "Failed to acquire host buffer\n");
3852 buf = wm_adsp_buffer_alloc(ctl->dsp);
3856 buf->host_buf_mem_type = ctl->alg_region.type;
3857 buf->host_buf_ptr = be32_to_cpu(val);
3859 ret = wm_adsp_buffer_populate(buf);
3864 * v0 host_buffer coefficients didn't have versioning, so if the
3865 * control is one word, assume version 0.
3867 if (ctl->len == 4) {
3868 compr_dbg(buf, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3872 ret = regmap_raw_read(ctl->dsp->regmap, reg, &coeff_v1,
3877 coeff_v1.versions = be32_to_cpu(coeff_v1.versions);
3878 val = coeff_v1.versions & HOST_BUF_COEFF_COMPAT_VER_MASK;
3879 val >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT;
3881 if (val > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) {
3883 "Host buffer coeff ver %u > supported version %u\n",
3884 val, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER);
3888 for (i = 0; i < ARRAY_SIZE(coeff_v1.name); i++)
3889 coeff_v1.name[i] = be32_to_cpu(coeff_v1.name[i]);
3891 wm_adsp_remove_padding((u32 *)&coeff_v1.name,
3892 ARRAY_SIZE(coeff_v1.name),
3893 WM_ADSP_DATA_WORD_SIZE);
3895 buf->name = kasprintf(GFP_KERNEL, "%s-dsp-%s", ctl->dsp->part,
3896 (char *)&coeff_v1.name);
3898 compr_dbg(buf, "host_buf_ptr=%x coeff version %u\n",
3899 buf->host_buf_ptr, val);
3904 static int wm_adsp_buffer_init(struct wm_adsp *dsp)
3906 struct wm_coeff_ctl *ctl;
3909 list_for_each_entry(ctl, &dsp->ctl_list, list) {
3910 if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER)
3916 ret = wm_adsp_buffer_parse_coeff(ctl);
3918 adsp_err(dsp, "Failed to parse coeff: %d\n", ret);
3920 } else if (ret == 0) {
3921 /* Only one buffer supported for version 0 */
3926 if (list_empty(&dsp->buffer_list)) {
3927 /* Fall back to legacy support */
3928 ret = wm_adsp_buffer_parse_legacy(dsp);
3930 adsp_err(dsp, "Failed to parse legacy: %d\n", ret);
3938 wm_adsp_buffer_free(dsp);
3942 static int wm_adsp_buffer_free(struct wm_adsp *dsp)
3944 struct wm_adsp_compr_buf *buf, *tmp;
3946 list_for_each_entry_safe(buf, tmp, &dsp->buffer_list, list) {
3947 wm_adsp_compr_detach(buf->compr);
3950 kfree(buf->regions);
3951 list_del(&buf->list);
3958 static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3962 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3964 compr_err(buf, "Failed to check buffer error: %d\n", ret);
3967 if (buf->error != 0) {
3968 compr_err(buf, "Buffer error occurred: %d\n", buf->error);
3975 int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
3977 struct wm_adsp_compr *compr = stream->runtime->private_data;
3978 struct wm_adsp *dsp = compr->dsp;
3981 compr_dbg(compr, "Trigger: %d\n", cmd);
3983 mutex_lock(&dsp->pwr_lock);
3986 case SNDRV_PCM_TRIGGER_START:
3987 if (!wm_adsp_compr_attached(compr)) {
3988 ret = wm_adsp_compr_attach(compr);
3990 compr_err(compr, "Failed to link buffer and stream: %d\n",
3996 ret = wm_adsp_buffer_get_error(compr->buf);
4000 /* Trigger the IRQ at one fragment of data */
4001 ret = wm_adsp_buffer_write(compr->buf,
4002 HOST_BUFFER_FIELD(high_water_mark),
4003 wm_adsp_compr_frag_words(compr));
4005 compr_err(compr, "Failed to set high water mark: %d\n",
4010 case SNDRV_PCM_TRIGGER_STOP:
4011 if (wm_adsp_compr_attached(compr))
4012 wm_adsp_buffer_clear(compr->buf);
4019 mutex_unlock(&dsp->pwr_lock);
4023 EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
4025 static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
4027 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
4029 return buf->regions[last_region].cumulative_size;
4032 static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
4034 u32 next_read_index, next_write_index;
4035 int write_index, read_index, avail;
4038 /* Only sync read index if we haven't already read a valid index */
4039 if (buf->read_index < 0) {
4040 ret = wm_adsp_buffer_read(buf,
4041 HOST_BUFFER_FIELD(next_read_index),
4046 read_index = sign_extend32(next_read_index, 23);
4048 if (read_index < 0) {
4049 compr_dbg(buf, "Avail check on unstarted stream\n");
4053 buf->read_index = read_index;
4056 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
4061 write_index = sign_extend32(next_write_index, 23);
4063 avail = write_index - buf->read_index;
4065 avail += wm_adsp_buffer_size(buf);
4067 compr_dbg(buf, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
4068 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
4075 int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
4077 struct wm_adsp_compr_buf *buf;
4078 struct wm_adsp_compr *compr;
4081 mutex_lock(&dsp->pwr_lock);
4083 if (list_empty(&dsp->buffer_list)) {
4088 adsp_dbg(dsp, "Handling buffer IRQ\n");
4090 list_for_each_entry(buf, &dsp->buffer_list, list) {
4093 ret = wm_adsp_buffer_get_error(buf);
4095 goto out_notify; /* Wake poll to report error */
4097 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
4100 compr_err(buf, "Failed to get irq_count: %d\n", ret);
4104 ret = wm_adsp_buffer_update_avail(buf);
4106 compr_err(buf, "Error reading avail: %d\n", ret);
4110 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
4111 ret = WM_ADSP_COMPR_VOICE_TRIGGER;
4114 if (compr && compr->stream)
4115 snd_compr_fragment_elapsed(compr->stream);
4119 mutex_unlock(&dsp->pwr_lock);
4123 EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
4125 static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
4127 if (buf->irq_count & 0x01)
4130 compr_dbg(buf, "Enable IRQ(0x%x) for next fragment\n", buf->irq_count);
4132 buf->irq_count |= 0x01;
4134 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
4138 int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
4139 struct snd_compr_tstamp *tstamp)
4141 struct wm_adsp_compr *compr = stream->runtime->private_data;
4142 struct wm_adsp *dsp = compr->dsp;
4143 struct wm_adsp_compr_buf *buf;
4146 compr_dbg(compr, "Pointer request\n");
4148 mutex_lock(&dsp->pwr_lock);
4152 if (dsp->fatal_error || !buf || buf->error) {
4153 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
4158 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
4159 ret = wm_adsp_buffer_update_avail(buf);
4161 compr_err(compr, "Error reading avail: %d\n", ret);
4166 * If we really have less than 1 fragment available tell the
4167 * DSP to inform us once a whole fragment is available.
4169 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
4170 ret = wm_adsp_buffer_get_error(buf);
4173 snd_compr_stop_error(stream,
4174 SNDRV_PCM_STATE_XRUN);
4178 ret = wm_adsp_buffer_reenable_irq(buf);
4180 compr_err(compr, "Failed to re-enable buffer IRQ: %d\n",
4187 tstamp->copied_total = compr->copied_total;
4188 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
4189 tstamp->sampling_rate = compr->sample_rate;
4192 mutex_unlock(&dsp->pwr_lock);
4196 EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
4198 static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
4200 struct wm_adsp_compr_buf *buf = compr->buf;
4201 unsigned int adsp_addr;
4202 int mem_type, nwords, max_read;
4205 /* Calculate read parameters */
4206 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
4207 if (buf->read_index < buf->regions[i].cumulative_size)
4210 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
4213 mem_type = buf->regions[i].mem_type;
4214 adsp_addr = buf->regions[i].base_addr +
4215 (buf->read_index - buf->regions[i].offset);
4217 max_read = wm_adsp_compr_frag_words(compr);
4218 nwords = buf->regions[i].cumulative_size - buf->read_index;
4220 if (nwords > target)
4222 if (nwords > buf->avail)
4223 nwords = buf->avail;
4224 if (nwords > max_read)
4229 /* Read data from DSP */
4230 ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
4231 nwords, compr->raw_buf);
4235 wm_adsp_remove_padding(compr->raw_buf, nwords, WM_ADSP_DATA_WORD_SIZE);
4237 /* update read index to account for words read */
4238 buf->read_index += nwords;
4239 if (buf->read_index == wm_adsp_buffer_size(buf))
4240 buf->read_index = 0;
4242 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
4247 /* update avail to account for words read */
4248 buf->avail -= nwords;
4253 static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
4254 char __user *buf, size_t count)
4256 struct wm_adsp *dsp = compr->dsp;
4260 compr_dbg(compr, "Requested read of %zu bytes\n", count);
4262 if (dsp->fatal_error || !compr->buf || compr->buf->error) {
4263 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
4267 count /= WM_ADSP_DATA_WORD_SIZE;
4270 nwords = wm_adsp_buffer_capture_block(compr, count);
4272 compr_err(compr, "Failed to capture block: %d\n",
4277 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
4279 compr_dbg(compr, "Read %d bytes\n", nbytes);
4281 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
4282 compr_err(compr, "Failed to copy data to user: %d, %d\n",
4289 } while (nwords > 0 && count > 0);
4291 compr->copied_total += ntotal;
4296 int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
4299 struct wm_adsp_compr *compr = stream->runtime->private_data;
4300 struct wm_adsp *dsp = compr->dsp;
4303 mutex_lock(&dsp->pwr_lock);
4305 if (stream->direction == SND_COMPRESS_CAPTURE)
4306 ret = wm_adsp_compr_read(compr, buf, count);
4310 mutex_unlock(&dsp->pwr_lock);
4314 EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
4316 static void wm_adsp_fatal_error(struct wm_adsp *dsp)
4318 struct wm_adsp_compr *compr;
4320 dsp->fatal_error = true;
4322 list_for_each_entry(compr, &dsp->compr_list, list) {
4324 snd_compr_fragment_elapsed(compr->stream);
4328 irqreturn_t wm_adsp2_bus_error(int irq, void *data)
4330 struct wm_adsp *dsp = (struct wm_adsp *)data;
4332 struct regmap *regmap = dsp->regmap;
4335 mutex_lock(&dsp->pwr_lock);
4337 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
4340 "Failed to read Region Lock Ctrl register: %d\n", ret);
4344 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
4345 adsp_err(dsp, "watchdog timeout error\n");
4346 dsp->ops->stop_watchdog(dsp);
4347 wm_adsp_fatal_error(dsp);
4350 if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
4351 if (val & ADSP2_SLAVE_ERR_MASK)
4352 adsp_err(dsp, "bus error: slave error\n");
4354 adsp_err(dsp, "bus error: region lock error\n");
4356 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
4359 "Failed to read Bus Err Addr register: %d\n",
4364 adsp_err(dsp, "bus error address = 0x%x\n",
4365 val & ADSP2_BUS_ERR_ADDR_MASK);
4367 ret = regmap_read(regmap,
4368 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
4372 "Failed to read Pmem Xmem Err Addr register: %d\n",
4377 adsp_err(dsp, "xmem error address = 0x%x\n",
4378 val & ADSP2_XMEM_ERR_ADDR_MASK);
4379 adsp_err(dsp, "pmem error address = 0x%x\n",
4380 (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
4381 ADSP2_PMEM_ERR_ADDR_SHIFT);
4384 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
4385 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
4388 mutex_unlock(&dsp->pwr_lock);
4392 EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
4394 irqreturn_t wm_halo_bus_error(int irq, void *data)
4396 struct wm_adsp *dsp = (struct wm_adsp *)data;
4397 struct regmap *regmap = dsp->regmap;
4398 unsigned int fault[6];
4399 struct reg_sequence clear[] = {
4400 { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 },
4401 { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 },
4402 { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 },
4406 mutex_lock(&dsp->pwr_lock);
4408 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1,
4411 adsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret);
4415 adsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n",
4416 *fault & HALO_AHBM_FLAGS_ERR_MASK,
4417 (*fault & HALO_AHBM_CORE_ERR_ADDR_MASK) >>
4418 HALO_AHBM_CORE_ERR_ADDR_SHIFT);
4420 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0,
4423 adsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret);
4427 adsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault);
4429 ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR,
4430 fault, ARRAY_SIZE(fault));
4432 adsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret);
4436 adsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]);
4437 adsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]);
4438 adsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]);
4440 ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear));
4442 adsp_warn(dsp, "Failed to clear MPU status: %d\n", ret);
4445 mutex_unlock(&dsp->pwr_lock);
4449 EXPORT_SYMBOL_GPL(wm_halo_bus_error);
4451 irqreturn_t wm_halo_wdt_expire(int irq, void *data)
4453 struct wm_adsp *dsp = data;
4455 mutex_lock(&dsp->pwr_lock);
4457 adsp_warn(dsp, "WDT Expiry Fault\n");
4458 dsp->ops->stop_watchdog(dsp);
4459 wm_adsp_fatal_error(dsp);
4461 mutex_unlock(&dsp->pwr_lock);
4465 EXPORT_SYMBOL_GPL(wm_halo_wdt_expire);
4467 static struct wm_adsp_ops wm_adsp1_ops = {
4468 .validate_version = wm_adsp_validate_version,
4469 .parse_sizes = wm_adsp1_parse_sizes,
4470 .region_to_reg = wm_adsp_region_to_reg,
4473 static struct wm_adsp_ops wm_adsp2_ops[] = {
4475 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4476 .parse_sizes = wm_adsp2_parse_sizes,
4477 .validate_version = wm_adsp_validate_version,
4478 .setup_algs = wm_adsp2_setup_algs,
4479 .region_to_reg = wm_adsp_region_to_reg,
4481 .show_fw_status = wm_adsp2_show_fw_status,
4483 .enable_memory = wm_adsp2_enable_memory,
4484 .disable_memory = wm_adsp2_disable_memory,
4486 .enable_core = wm_adsp2_enable_core,
4487 .disable_core = wm_adsp2_disable_core,
4489 .start_core = wm_adsp2_start_core,
4490 .stop_core = wm_adsp2_stop_core,
4494 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4495 .parse_sizes = wm_adsp2_parse_sizes,
4496 .validate_version = wm_adsp_validate_version,
4497 .setup_algs = wm_adsp2_setup_algs,
4498 .region_to_reg = wm_adsp_region_to_reg,
4500 .show_fw_status = wm_adsp2v2_show_fw_status,
4502 .enable_memory = wm_adsp2_enable_memory,
4503 .disable_memory = wm_adsp2_disable_memory,
4504 .lock_memory = wm_adsp2_lock,
4506 .enable_core = wm_adsp2v2_enable_core,
4507 .disable_core = wm_adsp2v2_disable_core,
4509 .start_core = wm_adsp2_start_core,
4510 .stop_core = wm_adsp2_stop_core,
4513 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr),
4514 .parse_sizes = wm_adsp2_parse_sizes,
4515 .validate_version = wm_adsp_validate_version,
4516 .setup_algs = wm_adsp2_setup_algs,
4517 .region_to_reg = wm_adsp_region_to_reg,
4519 .show_fw_status = wm_adsp2v2_show_fw_status,
4520 .stop_watchdog = wm_adsp_stop_watchdog,
4522 .enable_memory = wm_adsp2_enable_memory,
4523 .disable_memory = wm_adsp2_disable_memory,
4524 .lock_memory = wm_adsp2_lock,
4526 .enable_core = wm_adsp2v2_enable_core,
4527 .disable_core = wm_adsp2v2_disable_core,
4529 .start_core = wm_adsp2_start_core,
4530 .stop_core = wm_adsp2_stop_core,
4534 static struct wm_adsp_ops wm_halo_ops = {
4535 .sys_config_size = sizeof(struct wm_halo_system_config_xm_hdr),
4536 .parse_sizes = wm_adsp2_parse_sizes,
4537 .validate_version = wm_halo_validate_version,
4538 .setup_algs = wm_halo_setup_algs,
4539 .region_to_reg = wm_halo_region_to_reg,
4541 .show_fw_status = wm_halo_show_fw_status,
4542 .stop_watchdog = wm_halo_stop_watchdog,
4544 .lock_memory = wm_halo_configure_mpu,
4546 .start_core = wm_halo_start_core,
4547 .stop_core = wm_halo_stop_core,
4550 MODULE_LICENSE("GPL v2");