1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8994.c -- WM8994 ALSA SoC Audio driver
5 * Copyright 2009-12 Wolfson Microelectronics plc
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
15 #include <linux/gcd.h>
16 #include <linux/i2c.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/slab.h>
21 #include <sound/core.h>
22 #include <sound/jack.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28 #include <trace/events/asoc.h>
30 #include <linux/mfd/wm8994/core.h>
31 #include <linux/mfd/wm8994/registers.h>
32 #include <linux/mfd/wm8994/pdata.h>
33 #include <linux/mfd/wm8994/gpio.h>
38 #define WM1811_JACKDET_MODE_NONE 0x0000
39 #define WM1811_JACKDET_MODE_JACK 0x0100
40 #define WM1811_JACKDET_MODE_MIC 0x0080
41 #define WM1811_JACKDET_MODE_AUDIO 0x0180
43 #define WM8994_NUM_DRC 3
44 #define WM8994_NUM_EQ 3
49 } wm8994_vu_bits[] = {
50 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
51 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
52 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
53 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
54 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
55 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
56 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
57 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
58 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
59 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
61 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
62 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
63 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
64 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
65 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
66 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
67 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
68 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
69 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
70 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
71 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
72 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
73 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
74 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
75 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
76 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
79 static int wm8994_drc_base[] = {
85 static int wm8994_retune_mobile_base[] = {
86 WM8994_AIF1_DAC1_EQ_GAINS_1,
87 WM8994_AIF1_DAC2_EQ_GAINS_1,
88 WM8994_AIF2_EQ_GAINS_1,
91 static const struct wm8958_micd_rate micdet_rates[] = {
92 { 32768, true, 1, 4 },
93 { 32768, false, 1, 1 },
94 { 44100 * 256, true, 7, 10 },
95 { 44100 * 256, false, 7, 10 },
98 static const struct wm8958_micd_rate jackdet_rates[] = {
99 { 32768, true, 0, 1 },
100 { 32768, false, 0, 1 },
101 { 44100 * 256, true, 10, 10 },
102 { 44100 * 256, false, 7, 8 },
105 static void wm8958_micd_set_rate(struct snd_soc_component *component)
107 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
108 struct wm8994 *control = wm8994->wm8994;
109 int best, i, sysclk, val;
111 const struct wm8958_micd_rate *rates;
114 idle = !wm8994->jack_mic;
116 sysclk = snd_soc_component_read(component, WM8994_CLOCKING_1);
117 if (sysclk & WM8994_SYSCLK_SRC)
118 sysclk = wm8994->aifclk[1];
120 sysclk = wm8994->aifclk[0];
122 if (control->pdata.micd_rates) {
123 rates = control->pdata.micd_rates;
124 num_rates = control->pdata.num_micd_rates;
125 } else if (wm8994->jackdet) {
126 rates = jackdet_rates;
127 num_rates = ARRAY_SIZE(jackdet_rates);
129 rates = micdet_rates;
130 num_rates = ARRAY_SIZE(micdet_rates);
134 for (i = 0; i < num_rates; i++) {
135 if (rates[i].idle != idle)
137 if (abs(rates[i].sysclk - sysclk) <
138 abs(rates[best].sysclk - sysclk))
140 else if (rates[best].idle != idle)
144 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
145 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
147 dev_dbg(component->dev, "MICD rate %d,%d for %dHz %s\n",
148 rates[best].start, rates[best].rate, sysclk,
149 idle ? "idle" : "active");
151 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
152 WM8958_MICD_BIAS_STARTTIME_MASK |
153 WM8958_MICD_RATE_MASK, val);
156 static int configure_aif_clock(struct snd_soc_component *component, int aif)
158 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
168 switch (wm8994->sysclk[aif]) {
169 case WM8994_SYSCLK_MCLK1:
170 rate = wm8994->mclk_rate[0];
173 case WM8994_SYSCLK_MCLK2:
175 rate = wm8994->mclk_rate[1];
178 case WM8994_SYSCLK_FLL1:
180 rate = wm8994->fll[0].out;
183 case WM8994_SYSCLK_FLL2:
185 rate = wm8994->fll[1].out;
192 if (rate >= 13500000) {
194 reg1 |= WM8994_AIF1CLK_DIV;
196 dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n",
200 wm8994->aifclk[aif] = rate;
202 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1 + offset,
203 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
209 static int configure_clock(struct snd_soc_component *component)
211 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
212 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
215 /* Bring up the AIF clocks first */
216 configure_aif_clock(component, 0);
217 configure_aif_clock(component, 1);
219 /* Then switch CLK_SYS over to the higher of them; a change
220 * can only happen as a result of a clocking change which can
221 * only be made outside of DAPM so we can safely redo the
225 /* If they're equal it doesn't matter which is used */
226 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
227 wm8958_micd_set_rate(component);
231 if (wm8994->aifclk[0] < wm8994->aifclk[1])
232 new = WM8994_SYSCLK_SRC;
236 change = snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
237 WM8994_SYSCLK_SRC, new);
239 snd_soc_dapm_sync(dapm);
241 wm8958_micd_set_rate(component);
246 static int check_clk_sys(struct snd_soc_dapm_widget *source,
247 struct snd_soc_dapm_widget *sink)
249 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
250 int reg = snd_soc_component_read(component, WM8994_CLOCKING_1);
253 /* Check what we're currently using for CLK_SYS */
254 if (reg & WM8994_SYSCLK_SRC)
259 return strcmp(source->name, clk) == 0;
262 static const char *sidetone_hpf_text[] = {
263 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
266 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
267 WM8994_SIDETONE, 7, sidetone_hpf_text);
269 static const char *adc_hpf_text[] = {
270 "HiFi", "Voice 1", "Voice 2", "Voice 3"
273 static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
274 WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
276 static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
277 WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
279 static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
280 WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
282 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
283 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
284 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
285 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
286 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
287 static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
289 #define WM8994_DRC_SWITCH(xname, reg, shift) \
290 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
291 snd_soc_get_volsw, wm8994_put_drc_sw)
293 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
294 struct snd_ctl_elem_value *ucontrol)
296 struct soc_mixer_control *mc =
297 (struct soc_mixer_control *)kcontrol->private_value;
298 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
301 /* Can't enable both ADC and DAC paths simultaneously */
302 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
303 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
304 WM8994_AIF1ADC1R_DRC_ENA_MASK;
306 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
308 ret = snd_soc_component_read(component, mc->reg);
314 return snd_soc_put_volsw(kcontrol, ucontrol);
317 static void wm8994_set_drc(struct snd_soc_component *component, int drc)
319 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
320 struct wm8994 *control = wm8994->wm8994;
321 struct wm8994_pdata *pdata = &control->pdata;
322 int base = wm8994_drc_base[drc];
323 int cfg = wm8994->drc_cfg[drc];
326 /* Save any enables; the configuration should clear them. */
327 save = snd_soc_component_read(component, base);
328 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
329 WM8994_AIF1ADC1R_DRC_ENA;
331 for (i = 0; i < WM8994_DRC_REGS; i++)
332 snd_soc_component_update_bits(component, base + i, 0xffff,
333 pdata->drc_cfgs[cfg].regs[i]);
335 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_DRC_ENA |
336 WM8994_AIF1ADC1L_DRC_ENA |
337 WM8994_AIF1ADC1R_DRC_ENA, save);
340 /* Icky as hell but saves code duplication */
341 static int wm8994_get_drc(const char *name)
343 if (strcmp(name, "AIF1DRC1 Mode") == 0)
345 if (strcmp(name, "AIF1DRC2 Mode") == 0)
347 if (strcmp(name, "AIF2DRC Mode") == 0)
352 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
353 struct snd_ctl_elem_value *ucontrol)
355 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
356 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
357 struct wm8994 *control = wm8994->wm8994;
358 struct wm8994_pdata *pdata = &control->pdata;
359 int drc = wm8994_get_drc(kcontrol->id.name);
360 int value = ucontrol->value.enumerated.item[0];
365 if (value >= pdata->num_drc_cfgs)
368 wm8994->drc_cfg[drc] = value;
370 wm8994_set_drc(component, drc);
375 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
376 struct snd_ctl_elem_value *ucontrol)
378 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
379 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
380 int drc = wm8994_get_drc(kcontrol->id.name);
384 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
389 static void wm8994_set_retune_mobile(struct snd_soc_component *component, int block)
391 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
392 struct wm8994 *control = wm8994->wm8994;
393 struct wm8994_pdata *pdata = &control->pdata;
394 int base = wm8994_retune_mobile_base[block];
395 int iface, best, best_val, save, i, cfg;
397 if (!pdata || !wm8994->num_retune_mobile_texts)
412 /* Find the version of the currently selected configuration
413 * with the nearest sample rate. */
414 cfg = wm8994->retune_mobile_cfg[block];
417 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
418 if (strcmp(pdata->retune_mobile_cfgs[i].name,
419 wm8994->retune_mobile_texts[cfg]) == 0 &&
420 abs(pdata->retune_mobile_cfgs[i].rate
421 - wm8994->dac_rates[iface]) < best_val) {
423 best_val = abs(pdata->retune_mobile_cfgs[i].rate
424 - wm8994->dac_rates[iface]);
428 dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
430 pdata->retune_mobile_cfgs[best].name,
431 pdata->retune_mobile_cfgs[best].rate,
432 wm8994->dac_rates[iface]);
434 /* The EQ will be disabled while reconfiguring it, remember the
435 * current configuration.
437 save = snd_soc_component_read(component, base);
438 save &= WM8994_AIF1DAC1_EQ_ENA;
440 for (i = 0; i < WM8994_EQ_REGS; i++)
441 snd_soc_component_update_bits(component, base + i, 0xffff,
442 pdata->retune_mobile_cfgs[best].regs[i]);
444 snd_soc_component_update_bits(component, base, WM8994_AIF1DAC1_EQ_ENA, save);
447 /* Icky as hell but saves code duplication */
448 static int wm8994_get_retune_mobile_block(const char *name)
450 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
452 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
454 if (strcmp(name, "AIF2 EQ Mode") == 0)
459 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
460 struct snd_ctl_elem_value *ucontrol)
462 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
463 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
464 struct wm8994 *control = wm8994->wm8994;
465 struct wm8994_pdata *pdata = &control->pdata;
466 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
467 int value = ucontrol->value.enumerated.item[0];
472 if (value >= pdata->num_retune_mobile_cfgs)
475 wm8994->retune_mobile_cfg[block] = value;
477 wm8994_set_retune_mobile(component, block);
482 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
483 struct snd_ctl_elem_value *ucontrol)
485 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
486 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
487 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
492 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
497 static const char *aif_chan_src_text[] = {
501 static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
502 WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
504 static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
505 WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
507 static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
508 WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
510 static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
511 WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
513 static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
514 WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
516 static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
517 WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
519 static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
520 WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
522 static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
523 WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
525 static const char *osr_text[] = {
526 "Low Power", "High Performance",
529 static SOC_ENUM_SINGLE_DECL(dac_osr,
530 WM8994_OVERSAMPLING, 0, osr_text);
532 static SOC_ENUM_SINGLE_DECL(adc_osr,
533 WM8994_OVERSAMPLING, 1, osr_text);
535 static const struct snd_kcontrol_new wm8994_common_snd_controls[] = {
536 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
537 WM8994_AIF1_ADC1_RIGHT_VOLUME,
538 1, 119, 0, digital_tlv),
539 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
540 WM8994_AIF2_ADC_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
543 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
544 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
545 SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
546 SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
548 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
549 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
550 SOC_ENUM("AIF2DACL Source", aif2dacl_src),
551 SOC_ENUM("AIF2DACR Source", aif2dacr_src),
553 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
554 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
555 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
556 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
558 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
559 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
561 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
562 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
564 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
565 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
566 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
568 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
569 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
570 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
572 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
574 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
576 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
578 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
580 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
581 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
583 SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
584 SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
586 SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
587 SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
589 SOC_ENUM("ADC OSR", adc_osr),
590 SOC_ENUM("DAC OSR", dac_osr),
592 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
593 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
594 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
595 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
597 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
598 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
599 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
600 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
602 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
603 6, 1, 1, wm_hubs_spkmix_tlv),
604 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
605 2, 1, 1, wm_hubs_spkmix_tlv),
607 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
608 6, 1, 1, wm_hubs_spkmix_tlv),
609 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
610 2, 1, 1, wm_hubs_spkmix_tlv),
612 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
613 10, 15, 0, wm8994_3d_tlv),
614 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
616 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
617 10, 15, 0, wm8994_3d_tlv),
618 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
620 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
621 10, 15, 0, wm8994_3d_tlv),
622 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
626 /* Controls not available on WM1811 */
627 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
628 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
629 WM8994_AIF1_ADC2_RIGHT_VOLUME,
630 1, 119, 0, digital_tlv),
631 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
632 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
634 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
636 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
637 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
638 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
640 SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
641 SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
644 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
645 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
647 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
649 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
651 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
653 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
656 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
658 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
660 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
662 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
664 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
667 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
669 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
671 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
673 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
675 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
679 static const struct snd_kcontrol_new wm8994_drc_controls[] = {
680 SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
681 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
682 WM8994_AIF1ADC1R_DRC_ENA),
683 SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
684 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
685 WM8994_AIF1ADC2R_DRC_ENA),
686 SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
687 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
688 WM8994_AIF2ADCR_DRC_ENA),
691 static const char *wm8958_ng_text[] = {
692 "30ms", "125ms", "250ms", "500ms",
695 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
696 WM8958_AIF1_DAC1_NOISE_GATE,
697 WM8958_AIF1DAC1_NG_THR_SHIFT,
700 static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
701 WM8958_AIF1_DAC2_NOISE_GATE,
702 WM8958_AIF1DAC2_NG_THR_SHIFT,
705 static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
706 WM8958_AIF2_DAC_NOISE_GATE,
707 WM8958_AIF2DAC_NG_THR_SHIFT,
710 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
711 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
713 SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
714 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
715 SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
716 SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
717 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
720 SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
721 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
722 SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
723 SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
724 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
727 SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
728 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
729 SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
730 SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
731 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
735 /* We run all mode setting through a function to enforce audio mode */
736 static void wm1811_jackdet_set_mode(struct snd_soc_component *component, u16 mode)
738 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
740 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
743 if (wm8994->active_refcount)
744 mode = WM1811_JACKDET_MODE_AUDIO;
746 if (mode == wm8994->jackdet_mode)
749 wm8994->jackdet_mode = mode;
751 /* Always use audio mode to detect while the system is active */
752 if (mode != WM1811_JACKDET_MODE_NONE)
753 mode = WM1811_JACKDET_MODE_AUDIO;
755 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
756 WM1811_JACKDET_MODE_MASK, mode);
759 static void active_reference(struct snd_soc_component *component)
761 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
763 mutex_lock(&wm8994->accdet_lock);
765 wm8994->active_refcount++;
767 dev_dbg(component->dev, "Active refcount incremented, now %d\n",
768 wm8994->active_refcount);
770 /* If we're using jack detection go into audio mode */
771 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_AUDIO);
773 mutex_unlock(&wm8994->accdet_lock);
776 static void active_dereference(struct snd_soc_component *component)
778 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
781 mutex_lock(&wm8994->accdet_lock);
783 wm8994->active_refcount--;
785 dev_dbg(component->dev, "Active refcount decremented, now %d\n",
786 wm8994->active_refcount);
788 if (wm8994->active_refcount == 0) {
789 /* Go into appropriate detection only mode */
790 if (wm8994->jack_mic || wm8994->mic_detecting)
791 mode = WM1811_JACKDET_MODE_MIC;
793 mode = WM1811_JACKDET_MODE_JACK;
795 wm1811_jackdet_set_mode(component, mode);
798 mutex_unlock(&wm8994->accdet_lock);
801 static int clk_sys_event(struct snd_soc_dapm_widget *w,
802 struct snd_kcontrol *kcontrol, int event)
804 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
805 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
808 case SND_SOC_DAPM_PRE_PMU:
809 return configure_clock(component);
811 case SND_SOC_DAPM_POST_PMU:
813 * JACKDET won't run until we start the clock and it
814 * only reports deltas, make sure we notify the state
815 * up the stack on startup. Use a *very* generous
816 * timeout for paranoia, there's no urgency and we
817 * don't want false reports.
819 if (wm8994->jackdet && !wm8994->clk_has_run) {
820 queue_delayed_work(system_power_efficient_wq,
821 &wm8994->jackdet_bootstrap,
822 msecs_to_jiffies(1000));
823 wm8994->clk_has_run = true;
827 case SND_SOC_DAPM_POST_PMD:
828 configure_clock(component);
835 static void vmid_reference(struct snd_soc_component *component)
837 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
839 pm_runtime_get_sync(component->dev);
841 wm8994->vmid_refcount++;
843 dev_dbg(component->dev, "Referencing VMID, refcount is now %d\n",
844 wm8994->vmid_refcount);
846 if (wm8994->vmid_refcount == 1) {
847 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
848 WM8994_LINEOUT1_DISCH |
849 WM8994_LINEOUT2_DISCH, 0);
851 wm_hubs_vmid_ena(component);
853 switch (wm8994->vmid_mode) {
855 WARN_ON(NULL == "Invalid VMID mode");
857 case WM8994_VMID_NORMAL:
858 /* Startup bias, VMID ramp & buffer */
859 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
862 WM8994_STARTUP_BIAS_ENA |
863 WM8994_VMID_BUF_ENA |
864 WM8994_VMID_RAMP_MASK,
866 WM8994_STARTUP_BIAS_ENA |
867 WM8994_VMID_BUF_ENA |
868 (0x2 << WM8994_VMID_RAMP_SHIFT));
870 /* Main bias enable, VMID=2x40k */
871 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
873 WM8994_VMID_SEL_MASK,
874 WM8994_BIAS_ENA | 0x2);
878 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
879 WM8994_VMID_RAMP_MASK |
884 case WM8994_VMID_FORCE:
885 /* Startup bias, slow VMID ramp & buffer */
886 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
889 WM8994_STARTUP_BIAS_ENA |
890 WM8994_VMID_BUF_ENA |
891 WM8994_VMID_RAMP_MASK,
893 WM8994_STARTUP_BIAS_ENA |
894 WM8994_VMID_BUF_ENA |
895 (0x2 << WM8994_VMID_RAMP_SHIFT));
897 /* Main bias enable, VMID=2x40k */
898 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
900 WM8994_VMID_SEL_MASK,
901 WM8994_BIAS_ENA | 0x2);
905 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
906 WM8994_VMID_RAMP_MASK |
914 static void vmid_dereference(struct snd_soc_component *component)
916 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
918 wm8994->vmid_refcount--;
920 dev_dbg(component->dev, "Dereferencing VMID, refcount is now %d\n",
921 wm8994->vmid_refcount);
923 if (wm8994->vmid_refcount == 0) {
924 if (wm8994->hubs.lineout1_se)
925 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
926 WM8994_LINEOUT1N_ENA |
927 WM8994_LINEOUT1P_ENA,
928 WM8994_LINEOUT1N_ENA |
929 WM8994_LINEOUT1P_ENA);
931 if (wm8994->hubs.lineout2_se)
932 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
933 WM8994_LINEOUT2N_ENA |
934 WM8994_LINEOUT2P_ENA,
935 WM8994_LINEOUT2N_ENA |
936 WM8994_LINEOUT2P_ENA);
938 /* Start discharging VMID */
939 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
945 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
946 WM8994_VMID_SEL_MASK, 0);
950 /* Active discharge */
951 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
952 WM8994_LINEOUT1_DISCH |
953 WM8994_LINEOUT2_DISCH,
954 WM8994_LINEOUT1_DISCH |
955 WM8994_LINEOUT2_DISCH);
957 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_3,
958 WM8994_LINEOUT1N_ENA |
959 WM8994_LINEOUT1P_ENA |
960 WM8994_LINEOUT2N_ENA |
961 WM8994_LINEOUT2P_ENA, 0);
963 /* Switch off startup biases */
964 snd_soc_component_update_bits(component, WM8994_ANTIPOP_2,
966 WM8994_STARTUP_BIAS_ENA |
967 WM8994_VMID_BUF_ENA |
968 WM8994_VMID_RAMP_MASK, 0);
970 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_1,
971 WM8994_VMID_SEL_MASK, 0);
974 pm_runtime_put(component->dev);
977 static int vmid_event(struct snd_soc_dapm_widget *w,
978 struct snd_kcontrol *kcontrol, int event)
980 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
983 case SND_SOC_DAPM_PRE_PMU:
984 vmid_reference(component);
987 case SND_SOC_DAPM_POST_PMD:
988 vmid_dereference(component);
995 static bool wm8994_check_class_w_digital(struct snd_soc_component *component)
997 int source = 0; /* GCC flow analysis can't track enable */
1000 /* We also need the same AIF source for L/R and only one path */
1001 reg = snd_soc_component_read(component, WM8994_DAC1_LEFT_MIXER_ROUTING);
1003 case WM8994_AIF2DACL_TO_DAC1L:
1004 dev_vdbg(component->dev, "Class W source AIF2DAC\n");
1005 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1007 case WM8994_AIF1DAC2L_TO_DAC1L:
1008 dev_vdbg(component->dev, "Class W source AIF1DAC2\n");
1009 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011 case WM8994_AIF1DAC1L_TO_DAC1L:
1012 dev_vdbg(component->dev, "Class W source AIF1DAC1\n");
1013 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1016 dev_vdbg(component->dev, "DAC mixer setting: %x\n", reg);
1020 reg_r = snd_soc_component_read(component, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1022 dev_vdbg(component->dev, "Left and right DAC mixers different\n");
1026 /* Set the source up */
1027 snd_soc_component_update_bits(component, WM8994_CLASS_W_1,
1028 WM8994_CP_DYN_SRC_SEL_MASK, source);
1033 static int aif_mclk_set(struct snd_soc_component *component, int aif, bool enable)
1035 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1036 unsigned int offset, val, clk_idx;
1044 val = snd_soc_component_read(component, WM8994_AIF1_CLOCKING_1 + offset);
1045 val &= WM8994_AIF1CLK_SRC_MASK;
1049 clk_idx = WM8994_MCLK1;
1052 clk_idx = WM8994_MCLK2;
1059 ret = clk_prepare_enable(wm8994->mclk[clk_idx].clk);
1061 dev_err(component->dev, "Failed to enable MCLK%d\n",
1066 clk_disable_unprepare(wm8994->mclk[clk_idx].clk);
1072 static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1073 struct snd_kcontrol *kcontrol, int event)
1075 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1076 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1077 struct wm8994 *control = wm8994->wm8994;
1078 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1084 switch (control->type) {
1087 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1094 case SND_SOC_DAPM_PRE_PMU:
1095 ret = aif_mclk_set(component, 0, true);
1099 /* Don't enable timeslot 2 if not in use */
1100 if (wm8994->channels[0] <= 2)
1101 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1103 val = snd_soc_component_read(component, WM8994_AIF1_CONTROL_1);
1104 if ((val & WM8994_AIF1ADCL_SRC) &&
1105 (val & WM8994_AIF1ADCR_SRC))
1106 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1107 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1108 !(val & WM8994_AIF1ADCR_SRC))
1109 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1111 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1112 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1114 val = snd_soc_component_read(component, WM8994_AIF1_CONTROL_2);
1115 if ((val & WM8994_AIF1DACL_SRC) &&
1116 (val & WM8994_AIF1DACR_SRC))
1117 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1118 else if (!(val & WM8994_AIF1DACL_SRC) &&
1119 !(val & WM8994_AIF1DACR_SRC))
1120 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1122 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1123 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1125 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1127 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1129 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1130 WM8994_AIF1DSPCLK_ENA |
1131 WM8994_SYSDSPCLK_ENA,
1132 WM8994_AIF1DSPCLK_ENA |
1133 WM8994_SYSDSPCLK_ENA);
1134 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4, mask,
1135 WM8994_AIF1ADC1R_ENA |
1136 WM8994_AIF1ADC1L_ENA |
1137 WM8994_AIF1ADC2R_ENA |
1138 WM8994_AIF1ADC2L_ENA);
1139 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5, mask,
1140 WM8994_AIF1DAC1R_ENA |
1141 WM8994_AIF1DAC1L_ENA |
1142 WM8994_AIF1DAC2R_ENA |
1143 WM8994_AIF1DAC2L_ENA);
1146 case SND_SOC_DAPM_POST_PMU:
1147 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1148 snd_soc_component_write(component, wm8994_vu_bits[i].reg,
1149 snd_soc_component_read(component,
1150 wm8994_vu_bits[i].reg));
1153 case SND_SOC_DAPM_PRE_PMD:
1154 case SND_SOC_DAPM_POST_PMD:
1155 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1157 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1160 val = snd_soc_component_read(component, WM8994_CLOCKING_1);
1161 if (val & WM8994_AIF2DSPCLK_ENA)
1162 val = WM8994_SYSDSPCLK_ENA;
1165 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1166 WM8994_SYSDSPCLK_ENA |
1167 WM8994_AIF1DSPCLK_ENA, val);
1172 case SND_SOC_DAPM_POST_PMD:
1173 aif_mclk_set(component, 0, false);
1180 static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1181 struct snd_kcontrol *kcontrol, int event)
1183 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1190 case SND_SOC_DAPM_PRE_PMU:
1191 ret = aif_mclk_set(component, 1, true);
1195 val = snd_soc_component_read(component, WM8994_AIF2_CONTROL_1);
1196 if ((val & WM8994_AIF2ADCL_SRC) &&
1197 (val & WM8994_AIF2ADCR_SRC))
1198 adc = WM8994_AIF2ADCR_ENA;
1199 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1200 !(val & WM8994_AIF2ADCR_SRC))
1201 adc = WM8994_AIF2ADCL_ENA;
1203 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1206 val = snd_soc_component_read(component, WM8994_AIF2_CONTROL_2);
1207 if ((val & WM8994_AIF2DACL_SRC) &&
1208 (val & WM8994_AIF2DACR_SRC))
1209 dac = WM8994_AIF2DACR_ENA;
1210 else if (!(val & WM8994_AIF2DACL_SRC) &&
1211 !(val & WM8994_AIF2DACR_SRC))
1212 dac = WM8994_AIF2DACL_ENA;
1214 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1216 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1217 WM8994_AIF2ADCL_ENA |
1218 WM8994_AIF2ADCR_ENA, adc);
1219 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1220 WM8994_AIF2DACL_ENA |
1221 WM8994_AIF2DACR_ENA, dac);
1222 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1223 WM8994_AIF2DSPCLK_ENA |
1224 WM8994_SYSDSPCLK_ENA,
1225 WM8994_AIF2DSPCLK_ENA |
1226 WM8994_SYSDSPCLK_ENA);
1227 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1228 WM8994_AIF2ADCL_ENA |
1229 WM8994_AIF2ADCR_ENA,
1230 WM8994_AIF2ADCL_ENA |
1231 WM8994_AIF2ADCR_ENA);
1232 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1233 WM8994_AIF2DACL_ENA |
1234 WM8994_AIF2DACR_ENA,
1235 WM8994_AIF2DACL_ENA |
1236 WM8994_AIF2DACR_ENA);
1239 case SND_SOC_DAPM_POST_PMU:
1240 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1241 snd_soc_component_write(component, wm8994_vu_bits[i].reg,
1242 snd_soc_component_read(component,
1243 wm8994_vu_bits[i].reg));
1246 case SND_SOC_DAPM_PRE_PMD:
1247 case SND_SOC_DAPM_POST_PMD:
1248 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1249 WM8994_AIF2DACL_ENA |
1250 WM8994_AIF2DACR_ENA, 0);
1251 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_4,
1252 WM8994_AIF2ADCL_ENA |
1253 WM8994_AIF2ADCR_ENA, 0);
1255 val = snd_soc_component_read(component, WM8994_CLOCKING_1);
1256 if (val & WM8994_AIF1DSPCLK_ENA)
1257 val = WM8994_SYSDSPCLK_ENA;
1260 snd_soc_component_update_bits(component, WM8994_CLOCKING_1,
1261 WM8994_SYSDSPCLK_ENA |
1262 WM8994_AIF2DSPCLK_ENA, val);
1267 case SND_SOC_DAPM_POST_PMD:
1268 aif_mclk_set(component, 1, false);
1275 static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1276 struct snd_kcontrol *kcontrol, int event)
1278 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1279 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1282 case SND_SOC_DAPM_PRE_PMU:
1283 wm8994->aif1clk_enable = 1;
1285 case SND_SOC_DAPM_POST_PMD:
1286 wm8994->aif1clk_disable = 1;
1293 static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1294 struct snd_kcontrol *kcontrol, int event)
1296 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1297 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1300 case SND_SOC_DAPM_PRE_PMU:
1301 wm8994->aif2clk_enable = 1;
1303 case SND_SOC_DAPM_POST_PMD:
1304 wm8994->aif2clk_disable = 1;
1311 static int late_enable_ev(struct snd_soc_dapm_widget *w,
1312 struct snd_kcontrol *kcontrol, int event)
1314 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1315 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1318 case SND_SOC_DAPM_PRE_PMU:
1319 if (wm8994->aif1clk_enable) {
1320 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1321 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
1322 WM8994_AIF1CLK_ENA_MASK,
1323 WM8994_AIF1CLK_ENA);
1324 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1325 wm8994->aif1clk_enable = 0;
1327 if (wm8994->aif2clk_enable) {
1328 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1329 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
1330 WM8994_AIF2CLK_ENA_MASK,
1331 WM8994_AIF2CLK_ENA);
1332 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1333 wm8994->aif2clk_enable = 0;
1338 /* We may also have postponed startup of DSP, handle that. */
1339 wm8958_aif_ev(w, kcontrol, event);
1344 static int late_disable_ev(struct snd_soc_dapm_widget *w,
1345 struct snd_kcontrol *kcontrol, int event)
1347 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1348 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
1351 case SND_SOC_DAPM_POST_PMD:
1352 if (wm8994->aif1clk_disable) {
1353 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1354 snd_soc_component_update_bits(component, WM8994_AIF1_CLOCKING_1,
1355 WM8994_AIF1CLK_ENA_MASK, 0);
1356 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1357 wm8994->aif1clk_disable = 0;
1359 if (wm8994->aif2clk_disable) {
1360 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1361 snd_soc_component_update_bits(component, WM8994_AIF2_CLOCKING_1,
1362 WM8994_AIF2CLK_ENA_MASK, 0);
1363 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1364 wm8994->aif2clk_disable = 0;
1372 static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1373 struct snd_kcontrol *kcontrol, int event)
1375 late_enable_ev(w, kcontrol, event);
1379 static int micbias_ev(struct snd_soc_dapm_widget *w,
1380 struct snd_kcontrol *kcontrol, int event)
1382 late_enable_ev(w, kcontrol, event);
1386 static int dac_ev(struct snd_soc_dapm_widget *w,
1387 struct snd_kcontrol *kcontrol, int event)
1389 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1390 unsigned int mask = 1 << w->shift;
1392 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_5,
1397 static const char *adc_mux_text[] = {
1402 static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1404 static const struct snd_kcontrol_new adcl_mux =
1405 SOC_DAPM_ENUM("ADCL Mux", adc_enum);
1407 static const struct snd_kcontrol_new adcr_mux =
1408 SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1410 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1411 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1412 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1413 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1414 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1415 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1418 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1419 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1420 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1421 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1422 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1423 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1426 /* Debugging; dump chip status after DAPM transitions */
1427 static int post_ev(struct snd_soc_dapm_widget *w,
1428 struct snd_kcontrol *kcontrol, int event)
1430 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1431 dev_dbg(component->dev, "SRC status: %x\n",
1432 snd_soc_component_read(component,
1433 WM8994_RATE_STATUS));
1437 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1438 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1440 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1444 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1445 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1447 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1451 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1452 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1454 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1458 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1459 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1461 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1465 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1466 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1468 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1470 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1472 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1474 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1478 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1479 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1481 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1483 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1485 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1487 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1491 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1492 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1493 snd_soc_dapm_get_volsw, wm8994_put_class_w)
1495 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1496 struct snd_ctl_elem_value *ucontrol)
1498 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
1501 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1503 wm_hubs_update_class_w(component);
1508 static const struct snd_kcontrol_new dac1l_mix[] = {
1509 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1511 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1513 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1515 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1517 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1521 static const struct snd_kcontrol_new dac1r_mix[] = {
1522 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1524 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1526 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1528 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1530 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1534 static const char *sidetone_text[] = {
1535 "ADC/DMIC1", "DMIC2",
1538 static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1539 WM8994_SIDETONE, 0, sidetone_text);
1541 static const struct snd_kcontrol_new sidetone1_mux =
1542 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1544 static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1545 WM8994_SIDETONE, 1, sidetone_text);
1547 static const struct snd_kcontrol_new sidetone2_mux =
1548 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1550 static const char *aif1dac_text[] = {
1551 "AIF1DACDAT", "AIF3DACDAT",
1554 static const char *loopback_text[] = {
1558 static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1559 WM8994_AIF1_CONTROL_2,
1560 WM8994_AIF1_LOOPBACK_SHIFT,
1563 static const struct snd_kcontrol_new aif1_loopback =
1564 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1566 static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1567 WM8994_AIF2_CONTROL_2,
1568 WM8994_AIF2_LOOPBACK_SHIFT,
1571 static const struct snd_kcontrol_new aif2_loopback =
1572 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1574 static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1575 WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
1577 static const struct snd_kcontrol_new aif1dac_mux =
1578 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1580 static const char *aif2dac_text[] = {
1581 "AIF2DACDAT", "AIF3DACDAT",
1584 static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1585 WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
1587 static const struct snd_kcontrol_new aif2dac_mux =
1588 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1590 static const char *aif2adc_text[] = {
1591 "AIF2ADCDAT", "AIF3DACDAT",
1594 static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1595 WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
1597 static const struct snd_kcontrol_new aif2adc_mux =
1598 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1600 static const char *aif3adc_text[] = {
1601 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1604 static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1605 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1607 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1608 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1610 static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1611 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1613 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1614 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1616 static const char *mono_pcm_out_text[] = {
1617 "None", "AIF2ADCL", "AIF2ADCR",
1620 static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1621 WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
1623 static const struct snd_kcontrol_new mono_pcm_out_mux =
1624 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1626 static const char *aif2dac_src_text[] = {
1630 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1631 static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1632 WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
1634 static const struct snd_kcontrol_new aif2dacl_src_mux =
1635 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1637 static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1638 WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
1640 static const struct snd_kcontrol_new aif2dacr_src_mux =
1641 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1643 static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1644 SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1645 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1646 SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1647 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1649 SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1650 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1651 SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1652 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1653 SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1654 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1655 SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1656 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1657 SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1658 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1660 SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1661 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1662 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1663 SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1664 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1665 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1666 SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1667 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1668 SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1669 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1671 SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1674 static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1675 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1676 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1677 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1678 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1679 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1680 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1681 SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1682 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1683 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1684 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1685 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1686 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1687 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1690 static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1691 SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1692 dac_ev, SND_SOC_DAPM_PRE_PMU),
1693 SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1694 dac_ev, SND_SOC_DAPM_PRE_PMU),
1695 SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1696 dac_ev, SND_SOC_DAPM_PRE_PMU),
1697 SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1698 dac_ev, SND_SOC_DAPM_PRE_PMU),
1701 static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1702 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1703 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1704 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1705 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1708 static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1709 SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1710 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1711 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1712 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1715 static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1716 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1717 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1720 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1721 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1722 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1723 SND_SOC_DAPM_INPUT("Clock"),
1725 SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1726 SND_SOC_DAPM_PRE_PMU),
1727 SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1728 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1730 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1731 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1732 SND_SOC_DAPM_PRE_PMD),
1734 SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1735 SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1736 SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1738 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1739 0, SND_SOC_NOPM, 9, 0),
1740 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1741 0, SND_SOC_NOPM, 8, 0),
1742 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1743 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1744 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1745 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1746 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1747 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1749 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1750 0, SND_SOC_NOPM, 11, 0),
1751 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1752 0, SND_SOC_NOPM, 10, 0),
1753 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1754 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1755 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1756 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1757 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1758 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1760 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1761 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1762 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1763 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1765 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1766 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1767 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1768 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1770 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1771 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1772 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1773 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1775 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1776 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1778 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1779 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1780 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1781 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1783 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1784 SND_SOC_NOPM, 13, 0),
1785 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1786 SND_SOC_NOPM, 12, 0),
1787 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1788 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1789 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1790 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1791 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1792 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1794 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1795 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1796 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1797 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1799 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1800 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1801 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1803 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1804 SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1806 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1808 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1809 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1810 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1811 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1813 /* Power is done with the muxes since the ADC power also controls the
1814 * downsampling chain, the chip will automatically manage the analogue
1815 * specific portions.
1817 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1818 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1820 SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1821 SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1823 SND_SOC_DAPM_POST("Debug log", post_ev),
1826 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1827 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1830 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1831 SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1832 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1833 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1834 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1835 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1838 static const struct snd_soc_dapm_route intercon[] = {
1839 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1840 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1842 { "DSP1CLK", NULL, "CLK_SYS" },
1843 { "DSP2CLK", NULL, "CLK_SYS" },
1844 { "DSPINTCLK", NULL, "CLK_SYS" },
1846 { "AIF1ADC1L", NULL, "AIF1CLK" },
1847 { "AIF1ADC1L", NULL, "DSP1CLK" },
1848 { "AIF1ADC1R", NULL, "AIF1CLK" },
1849 { "AIF1ADC1R", NULL, "DSP1CLK" },
1850 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1852 { "AIF1DAC1L", NULL, "AIF1CLK" },
1853 { "AIF1DAC1L", NULL, "DSP1CLK" },
1854 { "AIF1DAC1R", NULL, "AIF1CLK" },
1855 { "AIF1DAC1R", NULL, "DSP1CLK" },
1856 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1858 { "AIF1ADC2L", NULL, "AIF1CLK" },
1859 { "AIF1ADC2L", NULL, "DSP1CLK" },
1860 { "AIF1ADC2R", NULL, "AIF1CLK" },
1861 { "AIF1ADC2R", NULL, "DSP1CLK" },
1862 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1864 { "AIF1DAC2L", NULL, "AIF1CLK" },
1865 { "AIF1DAC2L", NULL, "DSP1CLK" },
1866 { "AIF1DAC2R", NULL, "AIF1CLK" },
1867 { "AIF1DAC2R", NULL, "DSP1CLK" },
1868 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1870 { "AIF2ADCL", NULL, "AIF2CLK" },
1871 { "AIF2ADCL", NULL, "DSP2CLK" },
1872 { "AIF2ADCR", NULL, "AIF2CLK" },
1873 { "AIF2ADCR", NULL, "DSP2CLK" },
1874 { "AIF2ADCR", NULL, "DSPINTCLK" },
1876 { "AIF2DACL", NULL, "AIF2CLK" },
1877 { "AIF2DACL", NULL, "DSP2CLK" },
1878 { "AIF2DACR", NULL, "AIF2CLK" },
1879 { "AIF2DACR", NULL, "DSP2CLK" },
1880 { "AIF2DACR", NULL, "DSPINTCLK" },
1882 { "DMIC1L", NULL, "DMIC1DAT" },
1883 { "DMIC1L", NULL, "CLK_SYS" },
1884 { "DMIC1R", NULL, "DMIC1DAT" },
1885 { "DMIC1R", NULL, "CLK_SYS" },
1886 { "DMIC2L", NULL, "DMIC2DAT" },
1887 { "DMIC2L", NULL, "CLK_SYS" },
1888 { "DMIC2R", NULL, "DMIC2DAT" },
1889 { "DMIC2R", NULL, "CLK_SYS" },
1891 { "ADCL", NULL, "AIF1CLK" },
1892 { "ADCL", NULL, "DSP1CLK" },
1893 { "ADCL", NULL, "DSPINTCLK" },
1895 { "ADCR", NULL, "AIF1CLK" },
1896 { "ADCR", NULL, "DSP1CLK" },
1897 { "ADCR", NULL, "DSPINTCLK" },
1899 { "ADCL Mux", "ADC", "ADCL" },
1900 { "ADCL Mux", "DMIC", "DMIC1L" },
1901 { "ADCR Mux", "ADC", "ADCR" },
1902 { "ADCR Mux", "DMIC", "DMIC1R" },
1904 { "DAC1L", NULL, "AIF1CLK" },
1905 { "DAC1L", NULL, "DSP1CLK" },
1906 { "DAC1L", NULL, "DSPINTCLK" },
1908 { "DAC1R", NULL, "AIF1CLK" },
1909 { "DAC1R", NULL, "DSP1CLK" },
1910 { "DAC1R", NULL, "DSPINTCLK" },
1912 { "DAC2L", NULL, "AIF2CLK" },
1913 { "DAC2L", NULL, "DSP2CLK" },
1914 { "DAC2L", NULL, "DSPINTCLK" },
1916 { "DAC2R", NULL, "AIF2DACR" },
1917 { "DAC2R", NULL, "AIF2CLK" },
1918 { "DAC2R", NULL, "DSP2CLK" },
1919 { "DAC2R", NULL, "DSPINTCLK" },
1921 { "TOCLK", NULL, "CLK_SYS" },
1923 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1924 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1925 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1927 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1928 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1929 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1932 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1933 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1934 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1936 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1937 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1938 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1940 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1941 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1942 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1944 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1945 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1946 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1948 /* Pin level routing for AIF3 */
1949 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1950 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1951 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1952 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1954 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1955 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1956 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1957 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1958 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1959 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1960 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1963 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1964 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1965 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1966 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1967 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1969 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1970 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1971 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1972 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1973 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1975 /* DAC2/AIF2 outputs */
1976 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1977 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1978 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1979 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1980 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1981 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1983 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1984 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1985 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1986 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1987 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1988 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1990 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1991 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1992 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1993 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1995 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1998 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1L" },
1999 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC1R" },
2000 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2L" },
2001 { "AIF3ADC Mux", "AIF1ADCDAT", "AIF1ADC2R" },
2002 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
2003 { "AIF3ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
2004 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACL" },
2005 { "AIF3ADC Mux", "AIF2DACDAT", "AIF2DACR" },
2007 { "AIF3ADCDAT", NULL, "AIF3ADC Mux" },
2010 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
2011 { "AIF1 Loopback", "None", "AIF1DACDAT" },
2012 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
2013 { "AIF2 Loopback", "None", "AIF2DACDAT" },
2016 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
2017 { "Left Sidetone", "DMIC2", "DMIC2L" },
2018 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
2019 { "Right Sidetone", "DMIC2", "DMIC2R" },
2022 { "Left Output Mixer", "DAC Switch", "DAC1L" },
2023 { "Right Output Mixer", "DAC Switch", "DAC1R" },
2025 { "SPKL", "DAC1 Switch", "DAC1L" },
2026 { "SPKL", "DAC2 Switch", "DAC2L" },
2028 { "SPKR", "DAC1 Switch", "DAC1R" },
2029 { "SPKR", "DAC2 Switch", "DAC2R" },
2031 { "Left Headphone Mux", "DAC", "DAC1L" },
2032 { "Right Headphone Mux", "DAC", "DAC1R" },
2035 static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
2036 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
2037 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
2038 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
2039 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
2040 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
2041 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
2042 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
2043 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
2046 static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
2047 { "DAC1L", NULL, "DAC1L Mixer" },
2048 { "DAC1R", NULL, "DAC1R Mixer" },
2049 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
2050 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
2053 static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
2054 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
2055 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
2056 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2057 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2058 { "MICBIAS1", NULL, "CLK_SYS" },
2059 { "MICBIAS1", NULL, "MICBIAS Supply" },
2060 { "MICBIAS2", NULL, "CLK_SYS" },
2061 { "MICBIAS2", NULL, "MICBIAS Supply" },
2064 static const struct snd_soc_dapm_route wm8994_intercon[] = {
2065 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2066 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2067 { "MICBIAS1", NULL, "VMID" },
2068 { "MICBIAS2", NULL, "VMID" },
2071 static const struct snd_soc_dapm_route wm8958_intercon[] = {
2072 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2073 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2075 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2076 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2077 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2078 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2080 { "AIF3DACDAT", NULL, "AIF3" },
2081 { "AIF3ADCDAT", NULL, "AIF3" },
2083 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2084 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2086 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2089 /* The size in bits of the FLL divide multiplied by 10
2090 * to allow rounding later */
2091 #define FIXED_FLL_SIZE ((1 << 16) * 10)
2102 static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2103 int freq_in, int freq_out)
2106 unsigned int K, Ndiv, Nmod, gcd_fll;
2108 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2110 /* Scale the input frequency down to <= 13.5MHz */
2111 fll->clk_ref_div = 0;
2112 while (freq_in > 13500000) {
2116 if (fll->clk_ref_div > 3)
2119 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2121 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2123 while (freq_out * (fll->outdiv + 1) < 90000000) {
2125 if (fll->outdiv > 63)
2128 freq_out *= fll->outdiv + 1;
2129 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2131 if (freq_in > 1000000) {
2132 fll->fll_fratio = 0;
2133 } else if (freq_in > 256000) {
2134 fll->fll_fratio = 1;
2136 } else if (freq_in > 128000) {
2137 fll->fll_fratio = 2;
2139 } else if (freq_in > 64000) {
2140 fll->fll_fratio = 3;
2143 fll->fll_fratio = 4;
2146 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2148 /* Now, calculate N.K */
2149 Ndiv = freq_out / freq_in;
2152 Nmod = freq_out % freq_in;
2153 pr_debug("Nmod=%d\n", Nmod);
2155 switch (control->type) {
2157 /* Calculate fractional part - scale up so we can round. */
2158 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2160 do_div(Kpart, freq_in);
2162 K = Kpart & 0xFFFFFFFF;
2167 /* Move down to proper range now rounding is done */
2171 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2175 gcd_fll = gcd(freq_out, freq_in);
2177 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2178 fll->lambda = freq_in / gcd_fll;
2185 static int _wm8994_set_fll(struct snd_soc_component *component, int id, int src,
2186 unsigned int freq_in, unsigned int freq_out)
2188 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2189 struct wm8994 *control = wm8994->wm8994;
2190 int reg_offset, ret;
2192 u16 reg, clk1, aif_reg, aif_src;
2193 unsigned long timeout;
2212 reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_1 + reg_offset);
2213 was_enabled = reg & WM8994_FLL1_ENA;
2217 /* Allow no source specification when stopping */
2220 src = wm8994->fll[id].src;
2222 case WM8994_FLL_SRC_MCLK1:
2223 case WM8994_FLL_SRC_MCLK2:
2224 case WM8994_FLL_SRC_LRCLK:
2225 case WM8994_FLL_SRC_BCLK:
2227 case WM8994_FLL_SRC_INTERNAL:
2229 freq_out = 12000000;
2235 /* Are we changing anything? */
2236 if (wm8994->fll[id].src == src &&
2237 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2240 /* If we're stopping the FLL redo the old config - no
2241 * registers will actually be written but we avoid GCC flow
2242 * analysis bugs spewing warnings.
2245 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2247 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2248 wm8994->fll[id].out);
2252 /* Make sure that we're not providing SYSCLK right now */
2253 clk1 = snd_soc_component_read(component, WM8994_CLOCKING_1);
2254 if (clk1 & WM8994_SYSCLK_SRC)
2255 aif_reg = WM8994_AIF2_CLOCKING_1;
2257 aif_reg = WM8994_AIF1_CLOCKING_1;
2258 reg = snd_soc_component_read(component, aif_reg);
2260 if ((reg & WM8994_AIF1CLK_ENA) &&
2261 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2262 dev_err(component->dev, "FLL%d is currently providing SYSCLK\n",
2267 /* We always need to disable the FLL while reconfiguring */
2268 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
2269 WM8994_FLL1_ENA, 0);
2271 /* Disable MCLK if needed before we possibly change to new clock parent */
2273 reg = snd_soc_component_read(component, WM8994_FLL1_CONTROL_5
2275 reg = ((reg & WM8994_FLL1_REFCLK_SRC_MASK)
2276 >> WM8994_FLL1_REFCLK_SRC_SHIFT) + 1;
2279 case WM8994_FLL_SRC_MCLK1:
2280 mclk = wm8994->mclk[WM8994_MCLK1].clk;
2282 case WM8994_FLL_SRC_MCLK2:
2283 mclk = wm8994->mclk[WM8994_MCLK2].clk;
2289 clk_disable_unprepare(mclk);
2292 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2293 freq_in == freq_out && freq_out) {
2294 dev_dbg(component->dev, "Bypassing FLL%d\n", id + 1);
2295 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
2296 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2300 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2301 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2302 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_2 + reg_offset,
2303 WM8994_FLL1_OUTDIV_MASK |
2304 WM8994_FLL1_FRATIO_MASK, reg);
2306 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_3 + reg_offset,
2307 WM8994_FLL1_K_MASK, fll.k);
2309 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_4 + reg_offset,
2311 fll.n << WM8994_FLL1_N_SHIFT);
2314 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_1 + reg_offset,
2315 WM8958_FLL1_LAMBDA_MASK,
2317 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
2318 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2320 snd_soc_component_update_bits(component, WM8958_FLL1_EFS_2 + reg_offset,
2321 WM8958_FLL1_EFS_ENA, 0);
2324 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_5 + reg_offset,
2325 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2326 WM8994_FLL1_REFCLK_DIV_MASK |
2327 WM8994_FLL1_REFCLK_SRC_MASK,
2328 ((src == WM8994_FLL_SRC_INTERNAL)
2329 << WM8994_FLL1_FRC_NCO_SHIFT) |
2330 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2333 /* Clear any pending completion from a previous failure */
2334 try_wait_for_completion(&wm8994->fll_locked[id]);
2337 case WM8994_FLL_SRC_MCLK1:
2338 mclk = wm8994->mclk[WM8994_MCLK1].clk;
2340 case WM8994_FLL_SRC_MCLK2:
2341 mclk = wm8994->mclk[WM8994_MCLK2].clk;
2347 /* Enable (with fractional mode if required) */
2349 ret = clk_prepare_enable(mclk);
2351 dev_err(component->dev, "Failed to enable MCLK for FLL%d\n",
2356 /* Enable VMID if we need it */
2359 active_reference(component);
2361 switch (control->type) {
2363 vmid_reference(component);
2366 if (control->revision < 1)
2367 vmid_reference(component);
2374 reg = WM8994_FLL1_ENA;
2377 reg |= WM8994_FLL1_FRAC;
2378 if (src == WM8994_FLL_SRC_INTERNAL)
2379 reg |= WM8994_FLL1_OSC_ENA;
2381 snd_soc_component_update_bits(component, WM8994_FLL1_CONTROL_1 + reg_offset,
2382 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2383 WM8994_FLL1_FRAC, reg);
2385 if (wm8994->fll_locked_irq) {
2386 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2387 msecs_to_jiffies(10));
2389 dev_warn(component->dev,
2390 "Timed out waiting for FLL lock\n");
2396 switch (control->type) {
2398 vmid_dereference(component);
2401 if (control->revision < 1)
2402 vmid_dereference(component);
2408 active_dereference(component);
2413 wm8994->fll[id].in = freq_in;
2414 wm8994->fll[id].out = freq_out;
2415 wm8994->fll[id].src = src;
2417 configure_clock(component);
2420 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2423 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2424 dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
2426 wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE)
2427 & WM8994_AIF1CLK_RATE_MASK;
2428 wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE)
2429 & WM8994_AIF1CLK_RATE_MASK;
2431 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2432 WM8994_AIF1CLK_RATE_MASK, 0x1);
2433 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2434 WM8994_AIF2CLK_RATE_MASK, 0x1);
2435 } else if (wm8994->aifdiv[0]) {
2436 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2437 WM8994_AIF1CLK_RATE_MASK,
2439 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2440 WM8994_AIF2CLK_RATE_MASK,
2443 wm8994->aifdiv[0] = 0;
2444 wm8994->aifdiv[1] = 0;
2450 static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2452 struct completion *completion = data;
2454 complete(completion);
2459 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2461 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2462 unsigned int freq_in, unsigned int freq_out)
2464 return _wm8994_set_fll(dai->component, id, src, freq_in, freq_out);
2467 static int wm8994_set_mclk_rate(struct wm8994_priv *wm8994, unsigned int id,
2472 if (!wm8994->mclk[id].clk || *freq == wm8994->mclk_rate[id])
2475 ret = clk_set_rate(wm8994->mclk[id].clk, *freq);
2479 *freq = clk_get_rate(wm8994->mclk[id].clk);
2484 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2485 int clk_id, unsigned int freq, int dir)
2487 struct snd_soc_component *component = dai->component;
2488 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2497 /* AIF3 shares clocking with AIF1/2 */
2502 case WM8994_SYSCLK_MCLK1:
2503 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2505 ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
2509 wm8994->mclk_rate[0] = freq;
2510 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2514 case WM8994_SYSCLK_MCLK2:
2515 /* TODO: Set GPIO AF */
2516 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2518 ret = wm8994_set_mclk_rate(wm8994, dai->id - 1, &freq);
2522 wm8994->mclk_rate[1] = freq;
2523 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2527 case WM8994_SYSCLK_FLL1:
2528 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2529 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2532 case WM8994_SYSCLK_FLL2:
2533 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2534 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2537 case WM8994_SYSCLK_OPCLK:
2538 /* Special case - a division (times 10) is given and
2539 * no effect on main clocking.
2542 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2543 if (opclk_divs[i] == freq)
2545 if (i == ARRAY_SIZE(opclk_divs))
2547 snd_soc_component_update_bits(component, WM8994_CLOCKING_2,
2548 WM8994_OPCLK_DIV_MASK, i);
2549 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
2550 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2552 snd_soc_component_update_bits(component, WM8994_POWER_MANAGEMENT_2,
2553 WM8994_OPCLK_ENA, 0);
2561 configure_clock(component);
2564 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2567 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2568 dev_dbg(component->dev, "Configuring AIFs for 128fs\n");
2570 wm8994->aifdiv[0] = snd_soc_component_read(component, WM8994_AIF1_RATE)
2571 & WM8994_AIF1CLK_RATE_MASK;
2572 wm8994->aifdiv[1] = snd_soc_component_read(component, WM8994_AIF2_RATE)
2573 & WM8994_AIF1CLK_RATE_MASK;
2575 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2576 WM8994_AIF1CLK_RATE_MASK, 0x1);
2577 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2578 WM8994_AIF2CLK_RATE_MASK, 0x1);
2579 } else if (wm8994->aifdiv[0]) {
2580 snd_soc_component_update_bits(component, WM8994_AIF1_RATE,
2581 WM8994_AIF1CLK_RATE_MASK,
2583 snd_soc_component_update_bits(component, WM8994_AIF2_RATE,
2584 WM8994_AIF2CLK_RATE_MASK,
2587 wm8994->aifdiv[0] = 0;
2588 wm8994->aifdiv[1] = 0;
2594 static int wm8994_set_bias_level(struct snd_soc_component *component,
2595 enum snd_soc_bias_level level)
2597 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2598 struct wm8994 *control = wm8994->wm8994;
2600 wm_hubs_set_bias_level(component, level);
2603 case SND_SOC_BIAS_ON:
2606 case SND_SOC_BIAS_PREPARE:
2607 /* MICBIAS into regulating mode */
2608 switch (control->type) {
2611 snd_soc_component_update_bits(component, WM8958_MICBIAS1,
2612 WM8958_MICB1_MODE, 0);
2613 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
2614 WM8958_MICB2_MODE, 0);
2620 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
2621 active_reference(component);
2624 case SND_SOC_BIAS_STANDBY:
2625 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
2626 switch (control->type) {
2628 if (control->revision == 0) {
2629 /* Optimise performance for rev A */
2630 snd_soc_component_update_bits(component,
2631 WM8958_CHARGE_PUMP_2,
2641 /* Discharge LINEOUT1 & 2 */
2642 snd_soc_component_update_bits(component, WM8994_ANTIPOP_1,
2643 WM8994_LINEOUT1_DISCH |
2644 WM8994_LINEOUT2_DISCH,
2645 WM8994_LINEOUT1_DISCH |
2646 WM8994_LINEOUT2_DISCH);
2649 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE)
2650 active_dereference(component);
2652 /* MICBIAS into bypass mode on newer devices */
2653 switch (control->type) {
2656 snd_soc_component_update_bits(component, WM8958_MICBIAS1,
2659 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
2668 case SND_SOC_BIAS_OFF:
2669 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
2670 wm8994->cur_fw = NULL;
2677 int wm8994_vmid_mode(struct snd_soc_component *component, enum wm8994_vmid_mode mode)
2679 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2680 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2683 case WM8994_VMID_NORMAL:
2684 snd_soc_dapm_mutex_lock(dapm);
2686 if (wm8994->hubs.lineout1_se) {
2687 snd_soc_dapm_disable_pin_unlocked(dapm,
2688 "LINEOUT1N Driver");
2689 snd_soc_dapm_disable_pin_unlocked(dapm,
2690 "LINEOUT1P Driver");
2692 if (wm8994->hubs.lineout2_se) {
2693 snd_soc_dapm_disable_pin_unlocked(dapm,
2694 "LINEOUT2N Driver");
2695 snd_soc_dapm_disable_pin_unlocked(dapm,
2696 "LINEOUT2P Driver");
2699 /* Do the sync with the old mode to allow it to clean up */
2700 snd_soc_dapm_sync_unlocked(dapm);
2701 wm8994->vmid_mode = mode;
2703 snd_soc_dapm_mutex_unlock(dapm);
2706 case WM8994_VMID_FORCE:
2707 snd_soc_dapm_mutex_lock(dapm);
2709 if (wm8994->hubs.lineout1_se) {
2710 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2711 "LINEOUT1N Driver");
2712 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2713 "LINEOUT1P Driver");
2715 if (wm8994->hubs.lineout2_se) {
2716 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2717 "LINEOUT2N Driver");
2718 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2719 "LINEOUT2P Driver");
2722 wm8994->vmid_mode = mode;
2723 snd_soc_dapm_sync_unlocked(dapm);
2725 snd_soc_dapm_mutex_unlock(dapm);
2735 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2737 struct snd_soc_component *component = dai->component;
2738 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2739 struct wm8994 *control = wm8994->wm8994;
2750 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2751 aif1_reg = WM8994_AIF1_CONTROL_1;
2752 dac_reg = WM8994_AIF1DAC_LRCLK;
2753 adc_reg = WM8994_AIF1ADC_LRCLK;
2756 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2757 aif1_reg = WM8994_AIF2_CONTROL_1;
2758 dac_reg = WM8994_AIF1DAC_LRCLK;
2759 adc_reg = WM8994_AIF1ADC_LRCLK;
2765 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2766 case SND_SOC_DAIFMT_CBS_CFS:
2768 case SND_SOC_DAIFMT_CBM_CFM:
2769 ms = WM8994_AIF1_MSTR;
2775 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2776 case SND_SOC_DAIFMT_DSP_B:
2777 aif1 |= WM8994_AIF1_LRCLK_INV;
2778 lrclk |= WM8958_AIF1_LRCLK_INV;
2780 case SND_SOC_DAIFMT_DSP_A:
2783 case SND_SOC_DAIFMT_I2S:
2786 case SND_SOC_DAIFMT_RIGHT_J:
2788 case SND_SOC_DAIFMT_LEFT_J:
2795 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2796 case SND_SOC_DAIFMT_DSP_A:
2797 case SND_SOC_DAIFMT_DSP_B:
2798 /* frame inversion not valid for DSP modes */
2799 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2800 case SND_SOC_DAIFMT_NB_NF:
2802 case SND_SOC_DAIFMT_IB_NF:
2803 aif1 |= WM8994_AIF1_BCLK_INV;
2810 case SND_SOC_DAIFMT_I2S:
2811 case SND_SOC_DAIFMT_RIGHT_J:
2812 case SND_SOC_DAIFMT_LEFT_J:
2813 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2814 case SND_SOC_DAIFMT_NB_NF:
2816 case SND_SOC_DAIFMT_IB_IF:
2817 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2818 lrclk |= WM8958_AIF1_LRCLK_INV;
2820 case SND_SOC_DAIFMT_IB_NF:
2821 aif1 |= WM8994_AIF1_BCLK_INV;
2823 case SND_SOC_DAIFMT_NB_IF:
2824 aif1 |= WM8994_AIF1_LRCLK_INV;
2825 lrclk |= WM8958_AIF1_LRCLK_INV;
2835 /* The AIF2 format configuration needs to be mirrored to AIF3
2836 * on WM8958 if it's in use so just do it all the time. */
2837 switch (control->type) {
2841 snd_soc_component_update_bits(component, WM8958_AIF3_CONTROL_1,
2842 WM8994_AIF1_LRCLK_INV |
2843 WM8958_AIF3_FMT_MASK, aif1);
2850 snd_soc_component_update_bits(component, aif1_reg,
2851 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2852 WM8994_AIF1_FMT_MASK,
2854 snd_soc_component_update_bits(component, ms_reg, WM8994_AIF1_MSTR,
2856 snd_soc_component_update_bits(component, dac_reg,
2857 WM8958_AIF1_LRCLK_INV, lrclk);
2858 snd_soc_component_update_bits(component, adc_reg,
2859 WM8958_AIF1_LRCLK_INV, lrclk);
2880 static int fs_ratios[] = {
2881 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536
2884 static int bclk_divs[] = {
2885 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2886 640, 880, 960, 1280, 1760, 1920
2889 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2890 struct snd_pcm_hw_params *params,
2891 struct snd_soc_dai *dai)
2893 struct snd_soc_component *component = dai->component;
2894 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
2895 struct wm8994 *control = wm8994->wm8994;
2896 struct wm8994_pdata *pdata = &control->pdata;
2907 int id = dai->id - 1;
2909 int i, cur_val, best_val, bclk_rate, best;
2913 aif1_reg = WM8994_AIF1_CONTROL_1;
2914 aif2_reg = WM8994_AIF1_CONTROL_2;
2915 bclk_reg = WM8994_AIF1_BCLK;
2916 rate_reg = WM8994_AIF1_RATE;
2917 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2918 wm8994->lrclk_shared[0]) {
2919 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2921 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2922 dev_dbg(component->dev, "AIF1 using split LRCLK\n");
2926 aif1_reg = WM8994_AIF2_CONTROL_1;
2927 aif2_reg = WM8994_AIF2_CONTROL_2;
2928 bclk_reg = WM8994_AIF2_BCLK;
2929 rate_reg = WM8994_AIF2_RATE;
2930 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2931 wm8994->lrclk_shared[1]) {
2932 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2934 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2935 dev_dbg(component->dev, "AIF2 using split LRCLK\n");
2942 bclk_rate = params_rate(params);
2943 switch (params_width(params)) {
2963 wm8994->channels[id] = params_channels(params);
2964 if (pdata->max_channels_clocked[id] &&
2965 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2966 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2967 pdata->max_channels_clocked[id], wm8994->channels[id]);
2968 wm8994->channels[id] = pdata->max_channels_clocked[id];
2971 switch (wm8994->channels[id]) {
2981 /* Try to find an appropriate sample rate; look for an exact match. */
2982 for (i = 0; i < ARRAY_SIZE(srs); i++)
2983 if (srs[i].rate == params_rate(params))
2985 if (i == ARRAY_SIZE(srs))
2987 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2989 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2990 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2991 dai->id, wm8994->aifclk[id], bclk_rate);
2993 if (wm8994->channels[id] == 1 &&
2994 (snd_soc_component_read(component, aif1_reg) & 0x18) == 0x18)
2995 aif2 |= WM8994_AIF1_MONO;
2997 if (wm8994->aifclk[id] == 0) {
2998 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
3002 /* AIFCLK/fs ratio; look for a close match in either direction */
3004 best_val = abs((fs_ratios[0] * params_rate(params))
3005 - wm8994->aifclk[id]);
3006 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
3007 cur_val = abs((fs_ratios[i] * params_rate(params))
3008 - wm8994->aifclk[id]);
3009 if (cur_val >= best_val)
3014 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
3015 dai->id, fs_ratios[best]);
3018 /* We may not get quite the right frequency if using
3019 * approximate clocks so look for the closest match that is
3020 * higher than the target (we need to ensure that there enough
3021 * BCLKs to clock out the samples).
3024 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
3025 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
3026 if (cur_val < 0) /* BCLK table is sorted */
3030 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
3031 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
3032 bclk_divs[best], bclk_rate);
3033 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
3035 lrclk = bclk_rate / params_rate(params);
3037 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
3041 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
3042 lrclk, bclk_rate / lrclk);
3044 snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
3045 snd_soc_component_update_bits(component, aif2_reg, WM8994_AIF1_MONO, aif2);
3046 snd_soc_component_update_bits(component, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
3047 snd_soc_component_update_bits(component, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
3049 snd_soc_component_update_bits(component, rate_reg, WM8994_AIF1_SR_MASK |
3050 WM8994_AIF1CLK_RATE_MASK, rate_val);
3052 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3055 wm8994->dac_rates[0] = params_rate(params);
3056 wm8994_set_retune_mobile(component, 0);
3057 wm8994_set_retune_mobile(component, 1);
3060 wm8994->dac_rates[1] = params_rate(params);
3061 wm8994_set_retune_mobile(component, 2);
3069 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
3070 struct snd_pcm_hw_params *params,
3071 struct snd_soc_dai *dai)
3073 struct snd_soc_component *component = dai->component;
3074 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3075 struct wm8994 *control = wm8994->wm8994;
3081 switch (control->type) {
3084 aif1_reg = WM8958_AIF3_CONTROL_1;
3094 switch (params_width(params)) {
3110 return snd_soc_component_update_bits(component, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
3113 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute,
3116 struct snd_soc_component *component = codec_dai->component;
3120 switch (codec_dai->id) {
3122 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
3125 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
3132 reg = WM8994_AIF1DAC1_MUTE;
3136 snd_soc_component_update_bits(component, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3141 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3143 struct snd_soc_component *component = codec_dai->component;
3146 switch (codec_dai->id) {
3148 reg = WM8994_AIF1_MASTER_SLAVE;
3149 mask = WM8994_AIF1_TRI;
3152 reg = WM8994_AIF2_MASTER_SLAVE;
3153 mask = WM8994_AIF2_TRI;
3164 return snd_soc_component_update_bits(component, reg, mask, val);
3167 static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3169 struct snd_soc_component *component = dai->component;
3171 /* Disable the pulls on the AIF if we're using it to save power. */
3172 snd_soc_component_update_bits(component, WM8994_GPIO_3,
3173 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3174 snd_soc_component_update_bits(component, WM8994_GPIO_4,
3175 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3176 snd_soc_component_update_bits(component, WM8994_GPIO_5,
3177 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3182 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3184 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3185 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3187 static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3188 .set_sysclk = wm8994_set_dai_sysclk,
3189 .set_fmt = wm8994_set_dai_fmt,
3190 .hw_params = wm8994_hw_params,
3191 .mute_stream = wm8994_aif_mute,
3192 .set_pll = wm8994_set_fll,
3193 .set_tristate = wm8994_set_tristate,
3194 .no_capture_mute = 1,
3197 static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3198 .set_sysclk = wm8994_set_dai_sysclk,
3199 .set_fmt = wm8994_set_dai_fmt,
3200 .hw_params = wm8994_hw_params,
3201 .mute_stream = wm8994_aif_mute,
3202 .set_pll = wm8994_set_fll,
3203 .set_tristate = wm8994_set_tristate,
3204 .no_capture_mute = 1,
3207 static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3208 .hw_params = wm8994_aif3_hw_params,
3211 static struct snd_soc_dai_driver wm8994_dai[] = {
3213 .name = "wm8994-aif1",
3216 .stream_name = "AIF1 Playback",
3219 .rates = WM8994_RATES,
3220 .formats = WM8994_FORMATS,
3224 .stream_name = "AIF1 Capture",
3227 .rates = WM8994_RATES,
3228 .formats = WM8994_FORMATS,
3231 .ops = &wm8994_aif1_dai_ops,
3234 .name = "wm8994-aif2",
3237 .stream_name = "AIF2 Playback",
3240 .rates = WM8994_RATES,
3241 .formats = WM8994_FORMATS,
3245 .stream_name = "AIF2 Capture",
3248 .rates = WM8994_RATES,
3249 .formats = WM8994_FORMATS,
3252 .probe = wm8994_aif2_probe,
3253 .ops = &wm8994_aif2_dai_ops,
3256 .name = "wm8994-aif3",
3259 .stream_name = "AIF3 Playback",
3262 .rates = WM8994_RATES,
3263 .formats = WM8994_FORMATS,
3267 .stream_name = "AIF3 Capture",
3270 .rates = WM8994_RATES,
3271 .formats = WM8994_FORMATS,
3274 .ops = &wm8994_aif3_dai_ops,
3279 static int wm8994_component_suspend(struct snd_soc_component *component)
3281 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3284 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3285 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3286 sizeof(struct wm8994_fll_config));
3287 ret = _wm8994_set_fll(component, i + 1, 0, 0, 0);
3289 dev_warn(component->dev, "Failed to stop FLL%d: %d\n",
3293 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
3298 static int wm8994_component_resume(struct snd_soc_component *component)
3300 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3303 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3304 if (!wm8994->fll_suspend[i].out)
3307 ret = _wm8994_set_fll(component, i + 1,
3308 wm8994->fll_suspend[i].src,
3309 wm8994->fll_suspend[i].in,
3310 wm8994->fll_suspend[i].out);
3312 dev_warn(component->dev, "Failed to restore FLL%d: %d\n",
3319 #define wm8994_component_suspend NULL
3320 #define wm8994_component_resume NULL
3323 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3325 struct snd_soc_component *component = wm8994->hubs.component;
3326 struct wm8994 *control = wm8994->wm8994;
3327 struct wm8994_pdata *pdata = &control->pdata;
3328 struct snd_kcontrol_new controls[] = {
3329 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3330 wm8994->retune_mobile_enum,
3331 wm8994_get_retune_mobile_enum,
3332 wm8994_put_retune_mobile_enum),
3333 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3334 wm8994->retune_mobile_enum,
3335 wm8994_get_retune_mobile_enum,
3336 wm8994_put_retune_mobile_enum),
3337 SOC_ENUM_EXT("AIF2 EQ Mode",
3338 wm8994->retune_mobile_enum,
3339 wm8994_get_retune_mobile_enum,
3340 wm8994_put_retune_mobile_enum),
3345 /* We need an array of texts for the enum API but the number
3346 * of texts is likely to be less than the number of
3347 * configurations due to the sample rate dependency of the
3348 * configurations. */
3349 wm8994->num_retune_mobile_texts = 0;
3350 wm8994->retune_mobile_texts = NULL;
3351 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3352 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3353 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3354 wm8994->retune_mobile_texts[j]) == 0)
3358 if (j != wm8994->num_retune_mobile_texts)
3361 /* Expand the array... */
3362 t = krealloc(wm8994->retune_mobile_texts,
3364 (wm8994->num_retune_mobile_texts + 1),
3369 /* ...store the new entry... */
3370 t[wm8994->num_retune_mobile_texts] =
3371 pdata->retune_mobile_cfgs[i].name;
3373 /* ...and remember the new version. */
3374 wm8994->num_retune_mobile_texts++;
3375 wm8994->retune_mobile_texts = t;
3378 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
3379 wm8994->num_retune_mobile_texts);
3381 wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
3382 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3384 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
3385 ARRAY_SIZE(controls));
3387 dev_err(wm8994->hubs.component->dev,
3388 "Failed to add ReTune Mobile controls: %d\n", ret);
3391 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3393 struct snd_soc_component *component = wm8994->hubs.component;
3394 struct wm8994 *control = wm8994->wm8994;
3395 struct wm8994_pdata *pdata = &control->pdata;
3401 wm_hubs_handle_analogue_pdata(component, pdata->lineout1_diff,
3402 pdata->lineout2_diff,
3409 pdata->micbias1_lvl,
3410 pdata->micbias2_lvl);
3412 dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3414 if (pdata->num_drc_cfgs) {
3415 struct snd_kcontrol_new controls[] = {
3416 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3417 wm8994_get_drc_enum, wm8994_put_drc_enum),
3418 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3419 wm8994_get_drc_enum, wm8994_put_drc_enum),
3420 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3421 wm8994_get_drc_enum, wm8994_put_drc_enum),
3424 /* We need an array of texts for the enum API */
3425 wm8994->drc_texts = devm_kcalloc(wm8994->hubs.component->dev,
3426 pdata->num_drc_cfgs, sizeof(char *), GFP_KERNEL);
3427 if (!wm8994->drc_texts)
3430 for (i = 0; i < pdata->num_drc_cfgs; i++)
3431 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3433 wm8994->drc_enum.items = pdata->num_drc_cfgs;
3434 wm8994->drc_enum.texts = wm8994->drc_texts;
3436 ret = snd_soc_add_component_controls(wm8994->hubs.component, controls,
3437 ARRAY_SIZE(controls));
3438 for (i = 0; i < WM8994_NUM_DRC; i++)
3439 wm8994_set_drc(component, i);
3441 ret = snd_soc_add_component_controls(wm8994->hubs.component,
3442 wm8994_drc_controls,
3443 ARRAY_SIZE(wm8994_drc_controls));
3447 dev_err(wm8994->hubs.component->dev,
3448 "Failed to add DRC mode controls: %d\n", ret);
3451 dev_dbg(component->dev, "%d ReTune Mobile configurations\n",
3452 pdata->num_retune_mobile_cfgs);
3454 if (pdata->num_retune_mobile_cfgs)
3455 wm8994_handle_retune_mobile_pdata(wm8994);
3457 snd_soc_add_component_controls(wm8994->hubs.component, wm8994_eq_controls,
3458 ARRAY_SIZE(wm8994_eq_controls));
3460 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3461 if (pdata->micbias[i]) {
3462 snd_soc_component_write(component, WM8958_MICBIAS1 + i,
3463 pdata->micbias[i] & 0xffff);
3469 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3471 * @component: WM8994 component
3472 * @jack: jack to report detection events on
3473 * @micbias: microphone bias to detect on
3475 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3476 * being used to bring out signals to the processor then only platform
3477 * data configuration is needed for WM8994 and processor GPIOs should
3478 * be configured using snd_soc_jack_add_gpios() instead.
3480 * Configuration of detection levels is available via the micbias1_lvl
3481 * and micbias2_lvl platform data members.
3483 int wm8994_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
3486 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3487 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3488 struct wm8994_micdet *micdet;
3489 struct wm8994 *control = wm8994->wm8994;
3492 if (control->type != WM8994) {
3493 dev_warn(component->dev, "Not a WM8994\n");
3499 micdet = &wm8994->micdet[0];
3501 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
3503 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
3506 micdet = &wm8994->micdet[1];
3508 ret = snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
3510 ret = snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
3513 dev_warn(component->dev, "Invalid MICBIAS %d\n", micbias);
3518 dev_warn(component->dev, "Failed to configure MICBIAS%d: %d\n",
3521 dev_dbg(component->dev, "Configuring microphone detection on %d %p\n",
3524 /* Store the configuration */
3525 micdet->jack = jack;
3526 micdet->detecting = true;
3528 /* If either of the jacks is set up then enable detection */
3529 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3530 reg = WM8994_MICD_ENA;
3534 snd_soc_component_update_bits(component, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3536 /* enable MICDET and MICSHRT deboune */
3537 snd_soc_component_update_bits(component, WM8994_IRQ_DEBOUNCE,
3538 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3539 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3540 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3542 snd_soc_dapm_sync(dapm);
3546 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3548 static void wm8994_mic_work(struct work_struct *work)
3550 struct wm8994_priv *priv = container_of(work,
3553 struct regmap *regmap = priv->wm8994->regmap;
3554 struct device *dev = priv->wm8994->dev;
3559 pm_runtime_get_sync(dev);
3561 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®);
3563 dev_err(dev, "Failed to read microphone status: %d\n",
3565 pm_runtime_put(dev);
3569 dev_dbg(dev, "Microphone status: %x\n", reg);
3572 if (reg & WM8994_MIC1_DET_STS) {
3573 if (priv->micdet[0].detecting)
3574 report = SND_JACK_HEADSET;
3576 if (reg & WM8994_MIC1_SHRT_STS) {
3577 if (priv->micdet[0].detecting)
3578 report = SND_JACK_HEADPHONE;
3580 report |= SND_JACK_BTN_0;
3583 priv->micdet[0].detecting = false;
3585 priv->micdet[0].detecting = true;
3587 snd_soc_jack_report(priv->micdet[0].jack, report,
3588 SND_JACK_HEADSET | SND_JACK_BTN_0);
3591 if (reg & WM8994_MIC2_DET_STS) {
3592 if (priv->micdet[1].detecting)
3593 report = SND_JACK_HEADSET;
3595 if (reg & WM8994_MIC2_SHRT_STS) {
3596 if (priv->micdet[1].detecting)
3597 report = SND_JACK_HEADPHONE;
3599 report |= SND_JACK_BTN_0;
3602 priv->micdet[1].detecting = false;
3604 priv->micdet[1].detecting = true;
3606 snd_soc_jack_report(priv->micdet[1].jack, report,
3607 SND_JACK_HEADSET | SND_JACK_BTN_0);
3609 pm_runtime_put(dev);
3612 static irqreturn_t wm8994_mic_irq(int irq, void *data)
3614 struct wm8994_priv *priv = data;
3615 struct snd_soc_component *component = priv->hubs.component;
3617 #ifndef CONFIG_SND_SOC_WM8994_MODULE
3618 trace_snd_soc_jack_irq(dev_name(component->dev));
3621 pm_wakeup_event(component->dev, 300);
3623 queue_delayed_work(system_power_efficient_wq,
3624 &priv->mic_work, msecs_to_jiffies(250));
3629 /* Should be called with accdet_lock held */
3630 static void wm1811_micd_stop(struct snd_soc_component *component)
3632 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3633 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3635 if (!wm8994->jackdet)
3638 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3640 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
3642 if (wm8994->wm8994->pdata.jd_ext_cap)
3643 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
3646 static void wm8958_button_det(struct snd_soc_component *component, u16 status)
3648 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3653 report |= SND_JACK_BTN_0;
3656 report |= SND_JACK_BTN_1;
3659 report |= SND_JACK_BTN_2;
3662 report |= SND_JACK_BTN_3;
3665 report |= SND_JACK_BTN_4;
3668 report |= SND_JACK_BTN_5;
3670 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3674 static void wm8958_open_circuit_work(struct work_struct *work)
3676 struct wm8994_priv *wm8994 = container_of(work,
3678 open_circuit_work.work);
3679 struct device *dev = wm8994->wm8994->dev;
3681 mutex_lock(&wm8994->accdet_lock);
3683 wm1811_micd_stop(wm8994->hubs.component);
3685 dev_dbg(dev, "Reporting open circuit\n");
3687 wm8994->jack_mic = false;
3688 wm8994->mic_detecting = true;
3690 wm8958_micd_set_rate(wm8994->hubs.component);
3692 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3696 mutex_unlock(&wm8994->accdet_lock);
3699 static void wm8958_mic_id(void *data, u16 status)
3701 struct snd_soc_component *component = data;
3702 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3704 /* Either nothing present or just starting detection */
3705 if (!(status & WM8958_MICD_STS)) {
3706 /* If nothing present then clear our statuses */
3707 dev_dbg(component->dev, "Detected open circuit\n");
3709 queue_delayed_work(system_power_efficient_wq,
3710 &wm8994->open_circuit_work,
3711 msecs_to_jiffies(2500));
3715 /* If the measurement is showing a high impedence we've got a
3718 if (status & 0x600) {
3719 dev_dbg(component->dev, "Detected microphone\n");
3721 wm8994->mic_detecting = false;
3722 wm8994->jack_mic = true;
3724 wm8958_micd_set_rate(component);
3726 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3731 if (status & 0xfc) {
3732 dev_dbg(component->dev, "Detected headphone\n");
3733 wm8994->mic_detecting = false;
3735 wm8958_micd_set_rate(component);
3737 /* If we have jackdet that will detect removal */
3738 wm1811_micd_stop(component);
3740 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3745 /* Deferred mic detection to allow for extra settling time */
3746 static void wm1811_mic_work(struct work_struct *work)
3748 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3750 struct wm8994 *control = wm8994->wm8994;
3751 struct snd_soc_component *component = wm8994->hubs.component;
3752 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3754 pm_runtime_get_sync(component->dev);
3756 /* If required for an external cap force MICBIAS on */
3757 if (control->pdata.jd_ext_cap) {
3758 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
3759 snd_soc_dapm_sync(dapm);
3762 mutex_lock(&wm8994->accdet_lock);
3764 dev_dbg(component->dev, "Starting mic detection\n");
3766 /* Use a user-supplied callback if we have one */
3767 if (wm8994->micd_cb) {
3768 wm8994->micd_cb(wm8994->micd_cb_data);
3771 * Start off measument of microphone impedence to find out
3772 * what's actually there.
3774 wm8994->mic_detecting = true;
3775 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_MIC);
3777 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3778 WM8958_MICD_ENA, WM8958_MICD_ENA);
3781 mutex_unlock(&wm8994->accdet_lock);
3783 pm_runtime_put(component->dev);
3786 static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3788 struct wm8994_priv *wm8994 = data;
3789 struct wm8994 *control = wm8994->wm8994;
3790 struct snd_soc_component *component = wm8994->hubs.component;
3791 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3795 pm_runtime_get_sync(component->dev);
3797 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3799 mutex_lock(&wm8994->accdet_lock);
3801 reg = snd_soc_component_read(component, WM1811_JACKDET_CTRL);
3803 dev_err(component->dev, "Failed to read jack status: %d\n", reg);
3804 mutex_unlock(&wm8994->accdet_lock);
3805 pm_runtime_put(component->dev);
3809 dev_dbg(component->dev, "JACKDET %x\n", reg);
3811 present = reg & WM1811_JACKDET_LVL;
3814 dev_dbg(component->dev, "Jack detected\n");
3816 wm8958_micd_set_rate(component);
3818 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3819 WM8958_MICB2_DISCH, 0);
3821 /* Disable debounce while inserted */
3822 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3823 WM1811_JACKDET_DB, 0);
3825 delay = control->pdata.micdet_delay;
3826 queue_delayed_work(system_power_efficient_wq,
3828 msecs_to_jiffies(delay));
3830 dev_dbg(component->dev, "Jack not detected\n");
3832 cancel_delayed_work_sync(&wm8994->mic_work);
3834 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3835 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3837 /* Enable debounce while removed */
3838 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3839 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3841 wm8994->mic_detecting = false;
3842 wm8994->jack_mic = false;
3843 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3844 WM8958_MICD_ENA, 0);
3845 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_JACK);
3848 mutex_unlock(&wm8994->accdet_lock);
3850 /* Turn off MICBIAS if it was on for an external cap */
3851 if (control->pdata.jd_ext_cap && !present)
3852 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
3855 snd_soc_jack_report(wm8994->micdet[0].jack,
3856 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3858 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3859 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3862 /* Since we only report deltas force an update, ensures we
3863 * avoid bootstrapping issues with the core. */
3864 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3866 pm_runtime_put(component->dev);
3870 static void wm1811_jackdet_bootstrap(struct work_struct *work)
3872 struct wm8994_priv *wm8994 = container_of(work,
3874 jackdet_bootstrap.work);
3875 wm1811_jackdet_irq(0, wm8994);
3879 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3881 * @component: WM8958 component
3882 * @jack: jack to report detection events on
3883 * @det_cb: detection callback
3884 * @det_cb_data: data for detection callback
3885 * @id_cb: mic id callback
3886 * @id_cb_data: data for mic id callback
3888 * Enable microphone detection functionality for the WM8958. By
3889 * default simple detection which supports the detection of up to 6
3890 * buttons plus video and microphone functionality is supported.
3892 * The WM8958 has an advanced jack detection facility which is able to
3893 * support complex accessory detection, especially when used in
3894 * conjunction with external circuitry. In order to provide maximum
3895 * flexiblity a callback is provided which allows a completely custom
3896 * detection algorithm.
3898 int wm8958_mic_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
3899 wm1811_micdet_cb det_cb, void *det_cb_data,
3900 wm1811_mic_id_cb id_cb, void *id_cb_data)
3902 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3903 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
3904 struct wm8994 *control = wm8994->wm8994;
3907 switch (control->type) {
3916 snd_soc_dapm_force_enable_pin(dapm, "CLK_SYS");
3917 snd_soc_dapm_sync(dapm);
3919 wm8994->micdet[0].jack = jack;
3922 wm8994->micd_cb = det_cb;
3923 wm8994->micd_cb_data = det_cb_data;
3925 wm8994->mic_detecting = true;
3926 wm8994->jack_mic = false;
3930 wm8994->mic_id_cb = id_cb;
3931 wm8994->mic_id_cb_data = id_cb_data;
3933 wm8994->mic_id_cb = wm8958_mic_id;
3934 wm8994->mic_id_cb_data = component;
3937 wm8958_micd_set_rate(component);
3939 /* Detect microphones and short circuits by default */
3940 if (control->pdata.micd_lvl_sel)
3941 micd_lvl_sel = control->pdata.micd_lvl_sel;
3943 micd_lvl_sel = 0x41;
3945 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3946 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3947 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3949 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_2,
3950 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3952 WARN_ON(snd_soc_component_get_bias_level(component) > SND_SOC_BIAS_STANDBY);
3955 * If we can use jack detection start off with that,
3956 * otherwise jump straight to microphone detection.
3958 if (wm8994->jackdet) {
3959 /* Disable debounce for the initial detect */
3960 snd_soc_component_update_bits(component, WM1811_JACKDET_CTRL,
3961 WM1811_JACKDET_DB, 0);
3963 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
3965 WM8958_MICB2_DISCH);
3966 snd_soc_component_update_bits(component, WM8994_LDO_1,
3967 WM8994_LDO1_DISCH, 0);
3968 wm1811_jackdet_set_mode(component,
3969 WM1811_JACKDET_MODE_JACK);
3971 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3972 WM8958_MICD_ENA, WM8958_MICD_ENA);
3976 snd_soc_component_update_bits(component, WM8958_MIC_DETECT_1,
3977 WM8958_MICD_ENA, 0);
3978 wm1811_jackdet_set_mode(component, WM1811_JACKDET_MODE_NONE);
3979 snd_soc_dapm_disable_pin(dapm, "CLK_SYS");
3980 snd_soc_dapm_sync(dapm);
3985 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3987 static void wm8958_mic_work(struct work_struct *work)
3989 struct wm8994_priv *wm8994 = container_of(work,
3991 mic_complete_work.work);
3992 struct snd_soc_component *component = wm8994->hubs.component;
3994 pm_runtime_get_sync(component->dev);
3996 mutex_lock(&wm8994->accdet_lock);
3998 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
4000 mutex_unlock(&wm8994->accdet_lock);
4002 pm_runtime_put(component->dev);
4005 static irqreturn_t wm8958_mic_irq(int irq, void *data)
4007 struct wm8994_priv *wm8994 = data;
4008 struct snd_soc_component *component = wm8994->hubs.component;
4009 int reg, count, ret, id_delay;
4012 * Jack detection may have detected a removal simulataneously
4013 * with an update of the MICDET status; if so it will have
4014 * stopped detection and we can ignore this interrupt.
4016 if (!(snd_soc_component_read(component, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
4019 cancel_delayed_work_sync(&wm8994->mic_complete_work);
4020 cancel_delayed_work_sync(&wm8994->open_circuit_work);
4022 pm_runtime_get_sync(component->dev);
4024 /* We may occasionally read a detection without an impedence
4025 * range being provided - if that happens loop again.
4029 reg = snd_soc_component_read(component, WM8958_MIC_DETECT_3);
4031 dev_err(component->dev,
4032 "Failed to read mic detect status: %d\n",
4034 pm_runtime_put(component->dev);
4038 if (!(reg & WM8958_MICD_VALID)) {
4039 dev_dbg(component->dev, "Mic detect data not valid\n");
4043 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
4050 dev_warn(component->dev, "No impedance range reported for jack\n");
4052 #ifndef CONFIG_SND_SOC_WM8994_MODULE
4053 trace_snd_soc_jack_irq(dev_name(component->dev));
4056 /* Avoid a transient report when the accessory is being removed */
4057 if (wm8994->jackdet) {
4058 ret = snd_soc_component_read(component, WM1811_JACKDET_CTRL);
4060 dev_err(component->dev, "Failed to read jack status: %d\n",
4062 } else if (!(ret & WM1811_JACKDET_LVL)) {
4063 dev_dbg(component->dev, "Ignoring removed jack\n");
4066 } else if (!(reg & WM8958_MICD_STS)) {
4067 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
4068 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
4070 wm8994->mic_detecting = true;
4074 wm8994->mic_status = reg;
4075 id_delay = wm8994->wm8994->pdata.mic_id_delay;
4077 if (wm8994->mic_detecting)
4078 queue_delayed_work(system_power_efficient_wq,
4079 &wm8994->mic_complete_work,
4080 msecs_to_jiffies(id_delay));
4082 wm8958_button_det(component, reg);
4085 pm_runtime_put(component->dev);
4089 static irqreturn_t wm8994_fifo_error(int irq, void *data)
4091 struct snd_soc_component *component = data;
4093 dev_err(component->dev, "FIFO error\n");
4098 static irqreturn_t wm8994_temp_warn(int irq, void *data)
4100 struct snd_soc_component *component = data;
4102 dev_err(component->dev, "Thermal warning\n");
4107 static irqreturn_t wm8994_temp_shut(int irq, void *data)
4109 struct snd_soc_component *component = data;
4111 dev_crit(component->dev, "Thermal shutdown\n");
4116 static int wm8994_component_probe(struct snd_soc_component *component)
4118 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
4119 struct wm8994 *control = dev_get_drvdata(component->dev->parent);
4120 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
4124 snd_soc_component_init_regmap(component, control->regmap);
4126 wm8994->hubs.component = component;
4128 mutex_init(&wm8994->accdet_lock);
4129 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
4130 wm1811_jackdet_bootstrap);
4131 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
4132 wm8958_open_circuit_work);
4134 switch (control->type) {
4136 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4139 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4145 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4147 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4148 init_completion(&wm8994->fll_locked[i]);
4150 wm8994->micdet_irq = control->pdata.micdet_irq;
4152 /* By default use idle_bias_off, will override for WM8994 */
4153 dapm->idle_bias_off = 1;
4155 /* Set revision-specific configuration */
4156 switch (control->type) {
4158 /* Single ended line outputs should have VMID on. */
4159 if (!control->pdata.lineout1_diff ||
4160 !control->pdata.lineout2_diff)
4161 dapm->idle_bias_off = 0;
4163 switch (control->revision) {
4166 wm8994->hubs.dcs_codes_l = -5;
4167 wm8994->hubs.dcs_codes_r = -5;
4168 wm8994->hubs.hp_startup_mode = 1;
4169 wm8994->hubs.dcs_readback_mode = 1;
4170 wm8994->hubs.series_startup = 1;
4173 wm8994->hubs.dcs_readback_mode = 2;
4179 wm8994->hubs.dcs_readback_mode = 1;
4180 wm8994->hubs.hp_startup_mode = 1;
4182 switch (control->revision) {
4186 wm8994->fll_byp = true;
4192 wm8994->hubs.dcs_readback_mode = 2;
4193 wm8994->hubs.no_series_update = 1;
4194 wm8994->hubs.hp_startup_mode = 1;
4195 wm8994->hubs.no_cache_dac_hp_direct = true;
4196 wm8994->fll_byp = true;
4198 wm8994->hubs.dcs_codes_l = -9;
4199 wm8994->hubs.dcs_codes_r = -7;
4201 snd_soc_component_update_bits(component, WM8994_ANALOGUE_HP_1,
4202 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4209 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4210 wm8994_fifo_error, "FIFO error", component);
4211 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4212 wm8994_temp_warn, "Thermal warning", component);
4213 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4214 wm8994_temp_shut, "Thermal shutdown", component);
4216 switch (control->type) {
4218 if (wm8994->micdet_irq)
4219 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4221 IRQF_TRIGGER_RISING |
4226 ret = wm8994_request_irq(wm8994->wm8994,
4227 WM8994_IRQ_MIC1_DET,
4228 wm8994_mic_irq, "Mic 1 detect",
4232 dev_warn(component->dev,
4233 "Failed to request Mic1 detect IRQ: %d\n",
4237 ret = wm8994_request_irq(wm8994->wm8994,
4238 WM8994_IRQ_MIC1_SHRT,
4239 wm8994_mic_irq, "Mic 1 short",
4242 dev_warn(component->dev,
4243 "Failed to request Mic1 short IRQ: %d\n",
4246 ret = wm8994_request_irq(wm8994->wm8994,
4247 WM8994_IRQ_MIC2_DET,
4248 wm8994_mic_irq, "Mic 2 detect",
4251 dev_warn(component->dev,
4252 "Failed to request Mic2 detect IRQ: %d\n",
4255 ret = wm8994_request_irq(wm8994->wm8994,
4256 WM8994_IRQ_MIC2_SHRT,
4257 wm8994_mic_irq, "Mic 2 short",
4260 dev_warn(component->dev,
4261 "Failed to request Mic2 short IRQ: %d\n",
4267 if (wm8994->micdet_irq) {
4268 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4270 IRQF_TRIGGER_RISING |
4275 dev_warn(component->dev,
4276 "Failed to request Mic detect IRQ: %d\n",
4279 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4280 wm8958_mic_irq, "Mic detect",
4285 switch (control->type) {
4287 if (control->cust_id > 1 || control->revision > 1) {
4288 ret = wm8994_request_irq(wm8994->wm8994,
4290 wm1811_jackdet_irq, "JACKDET",
4293 wm8994->jackdet = true;
4300 wm8994->fll_locked_irq = true;
4301 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4302 ret = wm8994_request_irq(wm8994->wm8994,
4303 WM8994_IRQ_FLL1_LOCK + i,
4304 wm8994_fll_locked_irq, "FLL lock",
4305 &wm8994->fll_locked[i]);
4307 wm8994->fll_locked_irq = false;
4310 /* Make sure we can read from the GPIOs if they're inputs */
4311 pm_runtime_get_sync(component->dev);
4313 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4314 * configured on init - if a system wants to do this dynamically
4315 * at runtime we can deal with that then.
4317 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®);
4319 dev_err(component->dev, "Failed to read GPIO1 state: %d\n", ret);
4322 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4323 wm8994->lrclk_shared[0] = 1;
4324 wm8994_dai[0].symmetric_rates = 1;
4326 wm8994->lrclk_shared[0] = 0;
4329 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®);
4331 dev_err(component->dev, "Failed to read GPIO6 state: %d\n", ret);
4334 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4335 wm8994->lrclk_shared[1] = 1;
4336 wm8994_dai[1].symmetric_rates = 1;
4338 wm8994->lrclk_shared[1] = 0;
4341 pm_runtime_put(component->dev);
4343 /* Latch volume update bits */
4344 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4345 snd_soc_component_update_bits(component, wm8994_vu_bits[i].reg,
4346 wm8994_vu_bits[i].mask,
4347 wm8994_vu_bits[i].mask);
4349 /* Set the low bit of the 3D stereo depth so TLV matches */
4350 snd_soc_component_update_bits(component, WM8994_AIF1_DAC1_FILTERS_2,
4351 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4352 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4353 snd_soc_component_update_bits(component, WM8994_AIF1_DAC2_FILTERS_2,
4354 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4355 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4356 snd_soc_component_update_bits(component, WM8994_AIF2_DAC_FILTERS_2,
4357 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4358 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4360 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4361 * use this; it only affects behaviour on idle TDM clock
4363 switch (control->type) {
4366 snd_soc_component_update_bits(component, WM8994_AIF1_CONTROL_1,
4367 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4373 /* Put MICBIAS into bypass mode by default on newer devices */
4374 switch (control->type) {
4377 snd_soc_component_update_bits(component, WM8958_MICBIAS1,
4378 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4379 snd_soc_component_update_bits(component, WM8958_MICBIAS2,
4380 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4386 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4387 wm_hubs_update_class_w(component);
4389 wm8994_handle_pdata(wm8994);
4391 wm_hubs_add_analogue_controls(component);
4392 snd_soc_add_component_controls(component, wm8994_common_snd_controls,
4393 ARRAY_SIZE(wm8994_common_snd_controls));
4394 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4395 ARRAY_SIZE(wm8994_dapm_widgets));
4397 switch (control->type) {
4399 snd_soc_add_component_controls(component, wm8994_snd_controls,
4400 ARRAY_SIZE(wm8994_snd_controls));
4401 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4402 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4403 if (control->revision < 4) {
4404 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4405 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4406 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4407 ARRAY_SIZE(wm8994_adc_revd_widgets));
4408 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4409 ARRAY_SIZE(wm8994_dac_revd_widgets));
4411 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4412 ARRAY_SIZE(wm8994_lateclk_widgets));
4413 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4414 ARRAY_SIZE(wm8994_adc_widgets));
4415 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4416 ARRAY_SIZE(wm8994_dac_widgets));
4420 snd_soc_add_component_controls(component, wm8994_snd_controls,
4421 ARRAY_SIZE(wm8994_snd_controls));
4422 snd_soc_add_component_controls(component, wm8958_snd_controls,
4423 ARRAY_SIZE(wm8958_snd_controls));
4424 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4425 ARRAY_SIZE(wm8958_dapm_widgets));
4426 if (control->revision < 1) {
4427 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4428 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4429 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4430 ARRAY_SIZE(wm8994_adc_revd_widgets));
4431 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4432 ARRAY_SIZE(wm8994_dac_revd_widgets));
4434 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4435 ARRAY_SIZE(wm8994_lateclk_widgets));
4436 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4437 ARRAY_SIZE(wm8994_adc_widgets));
4438 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4439 ARRAY_SIZE(wm8994_dac_widgets));
4444 snd_soc_add_component_controls(component, wm8958_snd_controls,
4445 ARRAY_SIZE(wm8958_snd_controls));
4446 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4447 ARRAY_SIZE(wm8958_dapm_widgets));
4448 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4449 ARRAY_SIZE(wm8994_lateclk_widgets));
4450 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4451 ARRAY_SIZE(wm8994_adc_widgets));
4452 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4453 ARRAY_SIZE(wm8994_dac_widgets));
4457 wm_hubs_add_analogue_routes(component, 0, 0);
4458 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4459 wm_hubs_dcs_done, "DC servo done",
4462 wm8994->hubs.dcs_done_irq = true;
4463 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4465 switch (control->type) {
4467 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4468 ARRAY_SIZE(wm8994_intercon));
4470 if (control->revision < 4) {
4471 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4472 ARRAY_SIZE(wm8994_revd_intercon));
4473 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4474 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4476 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4477 ARRAY_SIZE(wm8994_lateclk_intercon));
4481 if (control->revision < 1) {
4482 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4483 ARRAY_SIZE(wm8994_intercon));
4484 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4485 ARRAY_SIZE(wm8994_revd_intercon));
4486 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4487 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4489 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4490 ARRAY_SIZE(wm8994_lateclk_intercon));
4491 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4492 ARRAY_SIZE(wm8958_intercon));
4495 wm8958_dsp2_init(component);
4498 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4499 ARRAY_SIZE(wm8994_lateclk_intercon));
4500 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4501 ARRAY_SIZE(wm8958_intercon));
4508 if (wm8994->jackdet)
4509 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4510 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4511 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4512 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4513 if (wm8994->micdet_irq)
4514 free_irq(wm8994->micdet_irq, wm8994);
4515 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4516 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4517 &wm8994->fll_locked[i]);
4518 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4520 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
4521 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
4522 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
4527 static void wm8994_component_remove(struct snd_soc_component *component)
4529 struct wm8994_priv *wm8994 = snd_soc_component_get_drvdata(component);
4530 struct wm8994 *control = wm8994->wm8994;
4533 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4534 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4535 &wm8994->fll_locked[i]);
4537 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4539 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, component);
4540 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, component);
4541 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, component);
4543 if (wm8994->jackdet)
4544 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4546 switch (control->type) {
4548 if (wm8994->micdet_irq)
4549 free_irq(wm8994->micdet_irq, wm8994);
4550 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4552 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4554 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4560 if (wm8994->micdet_irq)
4561 free_irq(wm8994->micdet_irq, wm8994);
4564 release_firmware(wm8994->mbc);
4565 release_firmware(wm8994->mbc_vss);
4566 release_firmware(wm8994->enh_eq);
4567 kfree(wm8994->retune_mobile_texts);
4570 static const struct snd_soc_component_driver soc_component_dev_wm8994 = {
4571 .probe = wm8994_component_probe,
4572 .remove = wm8994_component_remove,
4573 .suspend = wm8994_component_suspend,
4574 .resume = wm8994_component_resume,
4575 .set_bias_level = wm8994_set_bias_level,
4577 .use_pmdown_time = 1,
4579 .non_legacy_dai_naming = 1,
4582 static int wm8994_probe(struct platform_device *pdev)
4584 struct wm8994_priv *wm8994;
4587 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4591 platform_set_drvdata(pdev, wm8994);
4593 mutex_init(&wm8994->fw_lock);
4595 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4597 wm8994->mclk[WM8994_MCLK1].id = "MCLK1";
4598 wm8994->mclk[WM8994_MCLK2].id = "MCLK2";
4600 ret = devm_clk_bulk_get_optional(pdev->dev.parent, ARRAY_SIZE(wm8994->mclk),
4603 dev_err(&pdev->dev, "Failed to get clocks: %d\n", ret);
4607 pm_runtime_enable(&pdev->dev);
4608 pm_runtime_idle(&pdev->dev);
4610 return devm_snd_soc_register_component(&pdev->dev, &soc_component_dev_wm8994,
4611 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4614 static int wm8994_remove(struct platform_device *pdev)
4616 pm_runtime_disable(&pdev->dev);
4621 #ifdef CONFIG_PM_SLEEP
4622 static int wm8994_suspend(struct device *dev)
4624 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4626 /* Drop down to power saving mode when system is suspended */
4627 if (wm8994->jackdet && !wm8994->active_refcount)
4628 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4629 WM1811_JACKDET_MODE_MASK,
4630 wm8994->jackdet_mode);
4635 static int wm8994_resume(struct device *dev)
4637 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4639 if (wm8994->jackdet && wm8994->jackdet_mode)
4640 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4641 WM1811_JACKDET_MODE_MASK,
4642 WM1811_JACKDET_MODE_AUDIO);
4648 static const struct dev_pm_ops wm8994_pm_ops = {
4649 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4652 static struct platform_driver wm8994_codec_driver = {
4654 .name = "wm8994-codec",
4655 .pm = &wm8994_pm_ops,
4657 .probe = wm8994_probe,
4658 .remove = wm8994_remove,
4661 module_platform_driver(wm8994_codec_driver);
4663 MODULE_DESCRIPTION("ASoC WM8994 driver");
4664 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4665 MODULE_LICENSE("GPL");
4666 MODULE_ALIAS("platform:wm8994-codec");