sound/soc/codecs/wcd938x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/module.h>
   5 #include <linux/slab.h>
   6 #include <linux/platform_device.h>
   7 #include <linux/device.h>
   8 #include <linux/delay.h>
   9 #include <linux/kernel.h>
  10 #include <linux/pm_runtime.h>
  11 #include <linux/component.h>
  12 #include <sound/tlv.h>
  13 #include <linux/of_gpio.h>
  14 #include <linux/of.h>
  15 #include <sound/jack.h>
  16 #include <sound/pcm.h>
  17 #include <sound/pcm_params.h>
  18 #include <linux/regmap.h>
  19 #include <sound/soc.h>
  20 #include <sound/soc-dapm.h>
  21 #include <linux/regulator/consumer.h>
  22
  23 #include "wcd-clsh-v2.h"
  24 #include "wcd-mbhc-v2.h"
  25 #include "wcd938x.h"
  26
  27 #define WCD938X_MAX_MICBIAS             (4)
  28 #define WCD938X_MAX_SUPPLY              (4)
  29 #define WCD938X_MBHC_MAX_BUTTONS        (8)
  30 #define TX_ADC_MAX                      (4)
  31 #define WCD938X_TX_MAX_SWR_PORTS        (5)
  32
  33 #define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  34                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  35                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  36 /* Fractional Rates */
  37 #define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  38                                  SNDRV_PCM_RATE_176400)
  39 #define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  40                                     SNDRV_PCM_FMTBIT_S24_LE)
  41 /* Convert from vout ctl to micbias voltage in mV */
  42 #define  WCD_VOUT_CTL_TO_MICB(v)        (1000 + v * 50)
  43 #define SWR_CLK_RATE_0P6MHZ             (600000)
  44 #define SWR_CLK_RATE_1P2MHZ             (1200000)
  45 #define SWR_CLK_RATE_2P4MHZ             (2400000)
  46 #define SWR_CLK_RATE_4P8MHZ             (4800000)
  47 #define SWR_CLK_RATE_9P6MHZ             (9600000)
  48 #define SWR_CLK_RATE_11P2896MHZ         (1128960)
  49
  50 #define WCD938X_DRV_NAME "wcd938x_codec"
  51 #define WCD938X_VERSION_1_0             (1)
  52 #define EAR_RX_PATH_AUX                 (1)
  53
  54 #define ADC_MODE_VAL_HIFI               0x01
  55 #define ADC_MODE_VAL_LO_HIF             0x02
  56 #define ADC_MODE_VAL_NORMAL             0x03
  57 #define ADC_MODE_VAL_LP                 0x05
  58 #define ADC_MODE_VAL_ULP1               0x09
  59 #define ADC_MODE_VAL_ULP2               0x0B
  60
  61 /* Z value defined in milliohm */
  62 #define WCD938X_ZDET_VAL_32             (32000)
  63 #define WCD938X_ZDET_VAL_400            (400000)
  64 #define WCD938X_ZDET_VAL_1200           (1200000)
  65 #define WCD938X_ZDET_VAL_100K           (100000000)
  66 /* Z floating defined in ohms */
  67 #define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
  68 #define WCD938X_ZDET_NUM_MEASUREMENTS   (900)
  69 #define WCD938X_MBHC_GET_C1(c)          ((c & 0xC000) >> 14)
  70 #define WCD938X_MBHC_GET_X1(x)          (x & 0x3FFF)
  71 /* Z value compared in milliOhm */
  72 #define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
  73 #define WCD938X_MBHC_ZDET_CONST         (86 * 16384)
  74 #define WCD938X_MBHC_MOISTURE_RREF      R_24_KOHM
  75 #define WCD_MBHC_HS_V_MAX           1600
  76
  77 #define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  78 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  79         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  80                  SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  81         .tlv.p = (tlv_array), \
  82         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  83         .put = wcd938x_ear_pa_put_gain, \
  84         .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  85
  86 enum {
  87         WCD9380 = 0,
  88         WCD9385 = 5,
  89 };
  90
  91 enum {
  92         TX_HDR12 = 0,
  93         TX_HDR34,
  94         TX_HDR_MAX,
  95 };
  96
  97 enum {
  98         WCD_RX1,
  99         WCD_RX2,
 100         WCD_RX3
 101 };
 102
 103 enum {
 104         /* INTR_CTRL_INT_MASK_0 */
 105         WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
 106         WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET,
 107         WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
 108         WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
 109         WCD938X_IRQ_MBHC_SW_DET,
 110         WCD938X_IRQ_HPHR_OCP_INT,
 111         WCD938X_IRQ_HPHR_CNP_INT,
 112         WCD938X_IRQ_HPHL_OCP_INT,
 113
 114         /* INTR_CTRL_INT_MASK_1 */
 115         WCD938X_IRQ_HPHL_CNP_INT,
 116         WCD938X_IRQ_EAR_CNP_INT,
 117         WCD938X_IRQ_EAR_SCD_INT,
 118         WCD938X_IRQ_AUX_CNP_INT,
 119         WCD938X_IRQ_AUX_SCD_INT,
 120         WCD938X_IRQ_HPHL_PDM_WD_INT,
 121         WCD938X_IRQ_HPHR_PDM_WD_INT,
 122         WCD938X_IRQ_AUX_PDM_WD_INT,
 123
 124         /* INTR_CTRL_INT_MASK_2 */
 125         WCD938X_IRQ_LDORT_SCD_INT,
 126         WCD938X_IRQ_MBHC_MOISTURE_INT,
 127         WCD938X_IRQ_HPHL_SURGE_DET_INT,
 128         WCD938X_IRQ_HPHR_SURGE_DET_INT,
 129         WCD938X_NUM_IRQS,
 130 };
 131
 132 enum {
 133         WCD_ADC1 = 0,
 134         WCD_ADC2,
 135         WCD_ADC3,
 136         WCD_ADC4,
 137         ALLOW_BUCK_DISABLE,
 138         HPH_COMP_DELAY,
 139         HPH_PA_DELAY,
 140         AMIC2_BCS_ENABLE,
 141         WCD_SUPPLIES_LPM_MODE,
 142 };
 143
 144 enum {
 145         ADC_MODE_INVALID = 0,
 146         ADC_MODE_HIFI,
 147         ADC_MODE_LO_HIF,
 148         ADC_MODE_NORMAL,
 149         ADC_MODE_LP,
 150         ADC_MODE_ULP1,
 151         ADC_MODE_ULP2,
 152 };
 153
 154 enum {
 155         AIF1_PB = 0,
 156         AIF1_CAP,
 157         NUM_CODEC_DAIS,
 158 };
 159
 160 static u8 tx_mode_bit[] = {
 161         [ADC_MODE_INVALID] = 0x00,
 162         [ADC_MODE_HIFI] = 0x01,
 163         [ADC_MODE_LO_HIF] = 0x02,
 164         [ADC_MODE_NORMAL] = 0x04,
 165         [ADC_MODE_LP] = 0x08,
 166         [ADC_MODE_ULP1] = 0x10,
 167         [ADC_MODE_ULP2] = 0x20,
 168 };
 169
 170 struct wcd938x_priv {
 171         struct sdw_slave *tx_sdw_dev;
 172         struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
 173         struct device *txdev;
 174         struct device *rxdev;
 175         struct device_node *rxnode, *txnode;
 176         struct regmap *regmap;
 177         struct mutex micb_lock;
 178         /* mbhc module */
 179         struct wcd_mbhc *wcd_mbhc;
 180         struct wcd_mbhc_config mbhc_cfg;
 181         struct wcd_mbhc_intr intr_ids;
 182         struct wcd_clsh_ctrl *clsh_info;
 183         struct irq_domain *virq;
 184         struct regmap_irq_chip *wcd_regmap_irq_chip;
 185         struct regmap_irq_chip_data *irq_chip;
 186         struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY];
 187         struct snd_soc_jack *jack;
 188         unsigned long status_mask;
 189         s32 micb_ref[WCD938X_MAX_MICBIAS];
 190         s32 pullup_ref[WCD938X_MAX_MICBIAS];
 191         u32 hph_mode;
 192         u32 tx_mode[TX_ADC_MAX];
 193         int flyback_cur_det_disable;
 194         int ear_rx_path;
 195         int variant;
 196         int reset_gpio;
 197         u32 micb1_mv;
 198         u32 micb2_mv;
 199         u32 micb3_mv;
 200         u32 micb4_mv;
 201         int hphr_pdm_wd_int;
 202         int hphl_pdm_wd_int;
 203         int aux_pdm_wd_int;
 204         bool comp1_enable;
 205         bool comp2_enable;
 206         bool ldoh;
 207         bool bcs_dis;
 208 };
 209
 210 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
 211 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000);
 212 static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
 213
 214 struct wcd938x_mbhc_zdet_param {
 215         u16 ldo_ctl;
 216         u16 noff;
 217         u16 nshift;
 218         u16 btn5;
 219         u16 btn6;
 220         u16 btn7;
 221 };
 222
 223 static struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
 224         WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD938X_ANA_MBHC_MECH, 0x80),
 225         WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD938X_ANA_MBHC_MECH, 0x40),
 226         WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD938X_ANA_MBHC_MECH, 0x20),
 227         WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
 228         WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD938X_ANA_MBHC_ELECT, 0x08),
 229         WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
 230         WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD938X_ANA_MBHC_MECH, 0x04),
 231         WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x10),
 232         WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD938X_ANA_MBHC_MECH, 0x08),
 233         WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD938X_ANA_MBHC_MECH, 0x01),
 234         WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD938X_ANA_MBHC_ELECT, 0x06),
 235         WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD938X_ANA_MBHC_ELECT, 0x80),
 236         WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD938X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
 237         WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD938X_MBHC_NEW_CTL_1, 0x03),
 238         WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD938X_MBHC_NEW_CTL_2, 0x03),
 239         WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x08),
 240         WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
 241         WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x20),
 242         WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x80),
 243         WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x40),
 244         WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD938X_HPH_OCP_CTL, 0x10),
 245         WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0x07),
 246         WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD938X_ANA_MBHC_ELECT, 0x70),
 247         WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD938X_ANA_MBHC_RESULT_3, 0xFF),
 248         WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD938X_ANA_MICB2, 0xC0),
 249         WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD938X_HPH_CNP_WG_TIME, 0xFF),
 250         WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD938X_ANA_HPH, 0x40),
 251         WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD938X_ANA_HPH, 0x80),
 252         WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD938X_ANA_HPH, 0xC0),
 253         WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD938X_ANA_MBHC_RESULT_3, 0x10),
 254         WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD938X_MBHC_CTL_BCS, 0x02),
 255         WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x01),
 256         WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD938X_MBHC_NEW_CTL_2, 0x70),
 257         WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD938X_MBHC_NEW_FSM_STATUS, 0x20),
 258         WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD938X_HPH_PA_CTL2, 0x40),
 259         WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD938X_HPH_PA_CTL2, 0x10),
 260         WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD938X_HPH_L_TEST, 0x01),
 261         WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD938X_HPH_R_TEST, 0x01),
 262         WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x80),
 263         WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD938X_DIGITAL_INTR_STATUS_0, 0x20),
 264         WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD938X_MBHC_NEW_CTL_1, 0x08),
 265         WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD938X_MBHC_NEW_FSM_STATUS, 0x40),
 266         WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD938X_MBHC_NEW_FSM_STATUS, 0x80),
 267         WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD938X_MBHC_NEW_ADC_RESULT, 0xFF),
 268         WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD938X_ANA_MICB2, 0x3F),
 269         WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD938X_MBHC_NEW_CTL_1, 0x10),
 270         WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD938X_MBHC_NEW_CTL_1, 0x04),
 271         WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD938X_ANA_MBHC_ZDET, 0x02),
 272 };
 273
 274 static const struct reg_default wcd938x_defaults[] = {
 275         {WCD938X_ANA_PAGE_REGISTER,                            0x00},
 276         {WCD938X_ANA_BIAS,                                     0x00},
 277         {WCD938X_ANA_RX_SUPPLIES,                              0x00},
 278         {WCD938X_ANA_HPH,                                      0x0C},
 279         {WCD938X_ANA_EAR,                                      0x00},
 280         {WCD938X_ANA_EAR_COMPANDER_CTL,                        0x02},
 281         {WCD938X_ANA_TX_CH1,                                   0x20},
 282         {WCD938X_ANA_TX_CH2,                                   0x00},
 283         {WCD938X_ANA_TX_CH3,                                   0x20},
 284         {WCD938X_ANA_TX_CH4,                                   0x00},
 285         {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC,                 0x00},
 286         {WCD938X_ANA_MICB3_DSP_EN_LOGIC,                       0x00},
 287         {WCD938X_ANA_MBHC_MECH,                                0x39},
 288         {WCD938X_ANA_MBHC_ELECT,                               0x08},
 289         {WCD938X_ANA_MBHC_ZDET,                                0x00},
 290         {WCD938X_ANA_MBHC_RESULT_1,                            0x00},
 291         {WCD938X_ANA_MBHC_RESULT_2,                            0x00},
 292         {WCD938X_ANA_MBHC_RESULT_3,                            0x00},
 293         {WCD938X_ANA_MBHC_BTN0,                                0x00},
 294         {WCD938X_ANA_MBHC_BTN1,                                0x10},
 295         {WCD938X_ANA_MBHC_BTN2,                                0x20},
 296         {WCD938X_ANA_MBHC_BTN3,                                0x30},
 297         {WCD938X_ANA_MBHC_BTN4,                                0x40},
 298         {WCD938X_ANA_MBHC_BTN5,                                0x50},
 299         {WCD938X_ANA_MBHC_BTN6,                                0x60},
 300         {WCD938X_ANA_MBHC_BTN7,                                0x70},
 301         {WCD938X_ANA_MICB1,                                    0x10},
 302         {WCD938X_ANA_MICB2,                                    0x10},
 303         {WCD938X_ANA_MICB2_RAMP,                               0x00},
 304         {WCD938X_ANA_MICB3,                                    0x10},
 305         {WCD938X_ANA_MICB4,                                    0x10},
 306         {WCD938X_BIAS_CTL,                                     0x2A},
 307         {WCD938X_BIAS_VBG_FINE_ADJ,                            0x55},
 308         {WCD938X_LDOL_VDDCX_ADJUST,                            0x01},
 309         {WCD938X_LDOL_DISABLE_LDOL,                            0x00},
 310         {WCD938X_MBHC_CTL_CLK,                                 0x00},
 311         {WCD938X_MBHC_CTL_ANA,                                 0x00},
 312         {WCD938X_MBHC_CTL_SPARE_1,                             0x00},
 313         {WCD938X_MBHC_CTL_SPARE_2,                             0x00},
 314         {WCD938X_MBHC_CTL_BCS,                                 0x00},
 315         {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS,                 0x00},
 316         {WCD938X_MBHC_TEST_CTL,                                0x00},
 317         {WCD938X_LDOH_MODE,                                    0x2B},
 318         {WCD938X_LDOH_BIAS,                                    0x68},
 319         {WCD938X_LDOH_STB_LOADS,                               0x00},
 320         {WCD938X_LDOH_SLOWRAMP,                                0x50},
 321         {WCD938X_MICB1_TEST_CTL_1,                             0x1A},
 322         {WCD938X_MICB1_TEST_CTL_2,                             0x00},
 323         {WCD938X_MICB1_TEST_CTL_3,                             0xA4},
 324         {WCD938X_MICB2_TEST_CTL_1,                             0x1A},
 325         {WCD938X_MICB2_TEST_CTL_2,                             0x00},
 326         {WCD938X_MICB2_TEST_CTL_3,                             0x24},
 327         {WCD938X_MICB3_TEST_CTL_1,                             0x1A},
 328         {WCD938X_MICB3_TEST_CTL_2,                             0x00},
 329         {WCD938X_MICB3_TEST_CTL_3,                             0xA4},
 330         {WCD938X_MICB4_TEST_CTL_1,                             0x1A},
 331         {WCD938X_MICB4_TEST_CTL_2,                             0x00},
 332         {WCD938X_MICB4_TEST_CTL_3,                             0xA4},
 333         {WCD938X_TX_COM_ADC_VCM,                               0x39},
 334         {WCD938X_TX_COM_BIAS_ATEST,                            0xE0},
 335         {WCD938X_TX_COM_SPARE1,                                0x00},
 336         {WCD938X_TX_COM_SPARE2,                                0x00},
 337         {WCD938X_TX_COM_TXFE_DIV_CTL,                          0x22},
 338         {WCD938X_TX_COM_TXFE_DIV_START,                        0x00},
 339         {WCD938X_TX_COM_SPARE3,                                0x00},
 340         {WCD938X_TX_COM_SPARE4,                                0x00},
 341         {WCD938X_TX_1_2_TEST_EN,                               0xCC},
 342         {WCD938X_TX_1_2_ADC_IB,                                0xE9},
 343         {WCD938X_TX_1_2_ATEST_REFCTL,                          0x0A},
 344         {WCD938X_TX_1_2_TEST_CTL,                              0x38},
 345         {WCD938X_TX_1_2_TEST_BLK_EN1,                          0xFF},
 346         {WCD938X_TX_1_2_TXFE1_CLKDIV,                          0x00},
 347         {WCD938X_TX_1_2_SAR2_ERR,                              0x00},
 348         {WCD938X_TX_1_2_SAR1_ERR,                              0x00},
 349         {WCD938X_TX_3_4_TEST_EN,                               0xCC},
 350         {WCD938X_TX_3_4_ADC_IB,                                0xE9},
 351         {WCD938X_TX_3_4_ATEST_REFCTL,                          0x0A},
 352         {WCD938X_TX_3_4_TEST_CTL,                              0x38},
 353         {WCD938X_TX_3_4_TEST_BLK_EN3,                          0xFF},
 354         {WCD938X_TX_3_4_TXFE3_CLKDIV,                          0x00},
 355         {WCD938X_TX_3_4_SAR4_ERR,                              0x00},
 356         {WCD938X_TX_3_4_SAR3_ERR,                              0x00},
 357         {WCD938X_TX_3_4_TEST_BLK_EN2,                          0xFB},
 358         {WCD938X_TX_3_4_TXFE2_CLKDIV,                          0x00},
 359         {WCD938X_TX_3_4_SPARE1,                                0x00},
 360         {WCD938X_TX_3_4_TEST_BLK_EN4,                          0xFB},
 361         {WCD938X_TX_3_4_TXFE4_CLKDIV,                          0x00},
 362         {WCD938X_TX_3_4_SPARE2,                                0x00},
 363         {WCD938X_CLASSH_MODE_1,                                0x40},
 364         {WCD938X_CLASSH_MODE_2,                                0x3A},
 365         {WCD938X_CLASSH_MODE_3,                                0x00},
 366         {WCD938X_CLASSH_CTRL_VCL_1,                            0x70},
 367         {WCD938X_CLASSH_CTRL_VCL_2,                            0x82},
 368         {WCD938X_CLASSH_CTRL_CCL_1,                            0x31},
 369         {WCD938X_CLASSH_CTRL_CCL_2,                            0x80},
 370         {WCD938X_CLASSH_CTRL_CCL_3,                            0x80},
 371         {WCD938X_CLASSH_CTRL_CCL_4,                            0x51},
 372         {WCD938X_CLASSH_CTRL_CCL_5,                            0x00},
 373         {WCD938X_CLASSH_BUCK_TMUX_A_D,                         0x00},
 374         {WCD938X_CLASSH_BUCK_SW_DRV_CNTL,                      0x77},
 375         {WCD938X_CLASSH_SPARE,                                 0x00},
 376         {WCD938X_FLYBACK_EN,                                   0x4E},
 377         {WCD938X_FLYBACK_VNEG_CTRL_1,                          0x0B},
 378         {WCD938X_FLYBACK_VNEG_CTRL_2,                          0x45},
 379         {WCD938X_FLYBACK_VNEG_CTRL_3,                          0x74},
 380         {WCD938X_FLYBACK_VNEG_CTRL_4,                          0x7F},
 381         {WCD938X_FLYBACK_VNEG_CTRL_5,                          0x83},
 382         {WCD938X_FLYBACK_VNEG_CTRL_6,                          0x98},
 383         {WCD938X_FLYBACK_VNEG_CTRL_7,                          0xA9},
 384         {WCD938X_FLYBACK_VNEG_CTRL_8,                          0x68},
 385         {WCD938X_FLYBACK_VNEG_CTRL_9,                          0x64},
 386         {WCD938X_FLYBACK_VNEGDAC_CTRL_1,                       0xED},
 387         {WCD938X_FLYBACK_VNEGDAC_CTRL_2,                       0xF0},
 388         {WCD938X_FLYBACK_VNEGDAC_CTRL_3,                       0xA6},
 389         {WCD938X_FLYBACK_CTRL_1,                               0x65},
 390         {WCD938X_FLYBACK_TEST_CTL,                             0x00},
 391         {WCD938X_RX_AUX_SW_CTL,                                0x00},
 392         {WCD938X_RX_PA_AUX_IN_CONN,                            0x01},
 393         {WCD938X_RX_TIMER_DIV,                                 0x32},
 394         {WCD938X_RX_OCP_CTL,                                   0x1F},
 395         {WCD938X_RX_OCP_COUNT,                                 0x77},
 396         {WCD938X_RX_BIAS_EAR_DAC,                              0xA0},
 397         {WCD938X_RX_BIAS_EAR_AMP,                              0xAA},
 398         {WCD938X_RX_BIAS_HPH_LDO,                              0xA9},
 399         {WCD938X_RX_BIAS_HPH_PA,                               0xAA},
 400         {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2,                    0x8A},
 401         {WCD938X_RX_BIAS_HPH_RDAC_LDO,                         0x88},
 402         {WCD938X_RX_BIAS_HPH_CNP1,                             0x82},
 403         {WCD938X_RX_BIAS_HPH_LOWPOWER,                         0x82},
 404         {WCD938X_RX_BIAS_AUX_DAC,                              0xA0},
 405         {WCD938X_RX_BIAS_AUX_AMP,                              0xAA},
 406         {WCD938X_RX_BIAS_VNEGDAC_BLEEDER,                      0x50},
 407         {WCD938X_RX_BIAS_MISC,                                 0x00},
 408         {WCD938X_RX_BIAS_BUCK_RST,                             0x08},
 409         {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP,                     0x44},
 410         {WCD938X_RX_BIAS_FLYB_ERRAMP,                          0x40},
 411         {WCD938X_RX_BIAS_FLYB_BUFF,                            0xAA},
 412         {WCD938X_RX_BIAS_FLYB_MID_RST,                         0x14},
 413         {WCD938X_HPH_L_STATUS,                                 0x04},
 414         {WCD938X_HPH_R_STATUS,                                 0x04},
 415         {WCD938X_HPH_CNP_EN,                                   0x80},
 416         {WCD938X_HPH_CNP_WG_CTL,                               0x9A},
 417         {WCD938X_HPH_CNP_WG_TIME,                              0x14},
 418         {WCD938X_HPH_OCP_CTL,                                  0x28},
 419         {WCD938X_HPH_AUTO_CHOP,                                0x16},
 420         {WCD938X_HPH_CHOP_CTL,                                 0x83},
 421         {WCD938X_HPH_PA_CTL1,                                  0x46},
 422         {WCD938X_HPH_PA_CTL2,                                  0x50},
 423         {WCD938X_HPH_L_EN,                                     0x80},
 424         {WCD938X_HPH_L_TEST,                                   0xE0},
 425         {WCD938X_HPH_L_ATEST,                                  0x50},
 426         {WCD938X_HPH_R_EN,                                     0x80},
 427         {WCD938X_HPH_R_TEST,                                   0xE0},
 428         {WCD938X_HPH_R_ATEST,                                  0x54},
 429         {WCD938X_HPH_RDAC_CLK_CTL1,                            0x99},
 430         {WCD938X_HPH_RDAC_CLK_CTL2,                            0x9B},
 431         {WCD938X_HPH_RDAC_LDO_CTL,                             0x33},
 432         {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL,                     0x00},
 433         {WCD938X_HPH_REFBUFF_UHQA_CTL,                         0x68},
 434         {WCD938X_HPH_REFBUFF_LP_CTL,                           0x0E},
 435         {WCD938X_HPH_L_DAC_CTL,                                0x20},
 436         {WCD938X_HPH_R_DAC_CTL,                                0x20},
 437         {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL,               0x55},
 438         {WCD938X_HPH_SURGE_HPHLR_SURGE_EN,                     0x19},
 439         {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1,                  0xA0},
 440         {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS,                 0x00},
 441         {WCD938X_EAR_EAR_EN_REG,                               0x22},
 442         {WCD938X_EAR_EAR_PA_CON,                               0x44},
 443         {WCD938X_EAR_EAR_SP_CON,                               0xDB},
 444         {WCD938X_EAR_EAR_DAC_CON,                              0x80},
 445         {WCD938X_EAR_EAR_CNP_FSM_CON,                          0xB2},
 446         {WCD938X_EAR_TEST_CTL,                                 0x00},
 447         {WCD938X_EAR_STATUS_REG_1,                             0x00},
 448         {WCD938X_EAR_STATUS_REG_2,                             0x08},
 449         {WCD938X_ANA_NEW_PAGE_REGISTER,                        0x00},
 450         {WCD938X_HPH_NEW_ANA_HPH2,                             0x00},
 451         {WCD938X_HPH_NEW_ANA_HPH3,                             0x00},
 452         {WCD938X_SLEEP_CTL,                                    0x16},
 453         {WCD938X_SLEEP_WATCHDOG_CTL,                           0x00},
 454         {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL,                 0x00},
 455         {WCD938X_MBHC_NEW_CTL_1,                               0x02},
 456         {WCD938X_MBHC_NEW_CTL_2,                               0x05},
 457         {WCD938X_MBHC_NEW_PLUG_DETECT_CTL,                     0xE9},
 458         {WCD938X_MBHC_NEW_ZDET_ANA_CTL,                        0x0F},
 459         {WCD938X_MBHC_NEW_ZDET_RAMP_CTL,                       0x00},
 460         {WCD938X_MBHC_NEW_FSM_STATUS,                          0x00},
 461         {WCD938X_MBHC_NEW_ADC_RESULT,                          0x00},
 462         {WCD938X_TX_NEW_AMIC_MUX_CFG,                          0x00},
 463         {WCD938X_AUX_AUXPA,                                    0x00},
 464         {WCD938X_LDORXTX_MODE,                                 0x0C},
 465         {WCD938X_LDORXTX_CONFIG,                               0x10},
 466         {WCD938X_DIE_CRACK_DIE_CRK_DET_EN,                     0x00},
 467         {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT,                    0x00},
 468         {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,                    0x40},
 469         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,                   0x81},
 470         {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL,                    0x10},
 471         {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL,                0x00},
 472         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,                   0x81},
 473         {WCD938X_HPH_NEW_INT_PA_MISC1,                         0x22},
 474         {WCD938X_HPH_NEW_INT_PA_MISC2,                         0x00},
 475         {WCD938X_HPH_NEW_INT_PA_RDAC_MISC,                     0x00},
 476         {WCD938X_HPH_NEW_INT_HPH_TIMER1,                       0xFE},
 477         {WCD938X_HPH_NEW_INT_HPH_TIMER2,                       0x02},
 478         {WCD938X_HPH_NEW_INT_HPH_TIMER3,                       0x4E},
 479         {WCD938X_HPH_NEW_INT_HPH_TIMER4,                       0x54},
 480         {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2,                    0x00},
 481         {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3,                    0x00},
 482         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,               0x90},
 483         {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,               0x90},
 484         {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI,              0x62},
 485         {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP,                 0x01},
 486         {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP,                   0x11},
 487         {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL,            0x57},
 488         {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,       0x01},
 489         {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT,                0x00},
 490         {WCD938X_MBHC_NEW_INT_SPARE_2,                         0x00},
 491         {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON,                  0xA8},
 492         {WCD938X_EAR_INT_NEW_CNP_VCM_CON1,                     0x42},
 493         {WCD938X_EAR_INT_NEW_CNP_VCM_CON2,                     0x22},
 494         {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS,                 0x00},
 495         {WCD938X_AUX_INT_EN_REG,                               0x00},
 496         {WCD938X_AUX_INT_PA_CTRL,                              0x06},
 497         {WCD938X_AUX_INT_SP_CTRL,                              0xD2},
 498         {WCD938X_AUX_INT_DAC_CTRL,                             0x80},
 499         {WCD938X_AUX_INT_CLK_CTRL,                             0x50},
 500         {WCD938X_AUX_INT_TEST_CTRL,                            0x00},
 501         {WCD938X_AUX_INT_STATUS_REG,                           0x00},
 502         {WCD938X_AUX_INT_MISC,                                 0x00},
 503         {WCD938X_LDORXTX_INT_BIAS,                             0x6E},
 504         {WCD938X_LDORXTX_INT_STB_LOADS_DTEST,                  0x50},
 505         {WCD938X_LDORXTX_INT_TEST0,                            0x1C},
 506         {WCD938X_LDORXTX_INT_STARTUP_TIMER,                    0xFF},
 507         {WCD938X_LDORXTX_INT_TEST1,                            0x1F},
 508         {WCD938X_LDORXTX_INT_STATUS,                           0x00},
 509         {WCD938X_SLEEP_INT_WATCHDOG_CTL_1,                     0x0A},
 510         {WCD938X_SLEEP_INT_WATCHDOG_CTL_2,                     0x0A},
 511         {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1,               0x02},
 512         {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2,               0x60},
 513         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2,               0xFF},
 514         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1,               0x7F},
 515         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0,               0x3F},
 516         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M,          0x1F},
 517         {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M,          0x0F},
 518         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1,          0xD7},
 519         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0,            0xC8},
 520         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP,           0xC6},
 521         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1,      0xD5},
 522         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0,        0xCA},
 523         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,       0x05},
 524         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0,    0xA5},
 525         {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,       0x13},
 526         {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1,             0x88},
 527         {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP,            0x42},
 528         {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2,                  0xFF},
 529         {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1,                  0x64},
 530         {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0,                  0x64},
 531         {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP,                 0x77},
 532         {WCD938X_DIGITAL_PAGE_REGISTER,                        0x00},
 533         {WCD938X_DIGITAL_CHIP_ID0,                             0x00},
 534         {WCD938X_DIGITAL_CHIP_ID1,                             0x00},
 535         {WCD938X_DIGITAL_CHIP_ID2,                             0x0D},
 536         {WCD938X_DIGITAL_CHIP_ID3,                             0x01},
 537         {WCD938X_DIGITAL_SWR_TX_CLK_RATE,                      0x00},
 538         {WCD938X_DIGITAL_CDC_RST_CTL,                          0x03},
 539         {WCD938X_DIGITAL_TOP_CLK_CFG,                          0x00},
 540         {WCD938X_DIGITAL_CDC_ANA_CLK_CTL,                      0x00},
 541         {WCD938X_DIGITAL_CDC_DIG_CLK_CTL,                      0xF0},
 542         {WCD938X_DIGITAL_SWR_RST_EN,                           0x00},
 543         {WCD938X_DIGITAL_CDC_PATH_MODE,                        0x55},
 544         {WCD938X_DIGITAL_CDC_RX_RST,                           0x00},
 545         {WCD938X_DIGITAL_CDC_RX0_CTL,                          0xFC},
 546         {WCD938X_DIGITAL_CDC_RX1_CTL,                          0xFC},
 547         {WCD938X_DIGITAL_CDC_RX2_CTL,                          0xFC},
 548         {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,                  0x00},
 549         {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,                  0x00},
 550         {WCD938X_DIGITAL_CDC_COMP_CTL_0,                       0x00},
 551         {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL,                   0x1E},
 552         {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0,                     0x00},
 553         {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1,                     0x01},
 554         {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0,                     0x63},
 555         {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1,                     0x04},
 556         {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0,                     0xAC},
 557         {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1,                     0x04},
 558         {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0,                     0x1A},
 559         {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1,                     0x03},
 560         {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0,                     0xBC},
 561         {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1,                     0x02},
 562         {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0,                     0xC7},
 563         {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0,                     0xF8},
 564         {WCD938X_DIGITAL_CDC_HPH_DSM_C_0,                      0x47},
 565         {WCD938X_DIGITAL_CDC_HPH_DSM_C_1,                      0x43},
 566         {WCD938X_DIGITAL_CDC_HPH_DSM_C_2,                      0xB1},
 567         {WCD938X_DIGITAL_CDC_HPH_DSM_C_3,                      0x17},
 568         {WCD938X_DIGITAL_CDC_HPH_DSM_R1,                       0x4D},
 569         {WCD938X_DIGITAL_CDC_HPH_DSM_R2,                       0x29},
 570         {WCD938X_DIGITAL_CDC_HPH_DSM_R3,                       0x34},
 571         {WCD938X_DIGITAL_CDC_HPH_DSM_R4,                       0x59},
 572         {WCD938X_DIGITAL_CDC_HPH_DSM_R5,                       0x66},
 573         {WCD938X_DIGITAL_CDC_HPH_DSM_R6,                       0x87},
 574         {WCD938X_DIGITAL_CDC_HPH_DSM_R7,                       0x64},
 575         {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0,                     0x00},
 576         {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1,                     0x01},
 577         {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0,                     0x96},
 578         {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1,                     0x09},
 579         {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0,                     0xAB},
 580         {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1,                     0x05},
 581         {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0,                     0x1C},
 582         {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1,                     0x02},
 583         {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0,                     0x17},
 584         {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1,                     0x02},
 585         {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0,                     0xAA},
 586         {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0,                     0xE3},
 587         {WCD938X_DIGITAL_CDC_AUX_DSM_C_0,                      0x69},
 588         {WCD938X_DIGITAL_CDC_AUX_DSM_C_1,                      0x54},
 589         {WCD938X_DIGITAL_CDC_AUX_DSM_C_2,                      0x02},
 590         {WCD938X_DIGITAL_CDC_AUX_DSM_C_3,                      0x15},
 591         {WCD938X_DIGITAL_CDC_AUX_DSM_R1,                       0xA4},
 592         {WCD938X_DIGITAL_CDC_AUX_DSM_R2,                       0xB5},
 593         {WCD938X_DIGITAL_CDC_AUX_DSM_R3,                       0x86},
 594         {WCD938X_DIGITAL_CDC_AUX_DSM_R4,                       0x85},
 595         {WCD938X_DIGITAL_CDC_AUX_DSM_R5,                       0xAA},
 596         {WCD938X_DIGITAL_CDC_AUX_DSM_R6,                       0xE2},
 597         {WCD938X_DIGITAL_CDC_AUX_DSM_R7,                       0x62},
 598         {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0,                    0x55},
 599         {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1,                    0xA9},
 600         {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0,                   0x3D},
 601         {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1,                   0x2E},
 602         {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2,                   0x01},
 603         {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0,                   0x00},
 604         {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1,                   0xFC},
 605         {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2,                   0x01},
 606         {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,                     0x00},
 607         {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,                     0x00},
 608         {WCD938X_DIGITAL_CDC_EAR_PATH_CTL,                     0x00},
 609         {WCD938X_DIGITAL_CDC_SWR_CLH,                          0x00},
 610         {WCD938X_DIGITAL_SWR_CLH_BYP,                          0x00},
 611         {WCD938X_DIGITAL_CDC_TX0_CTL,                          0x68},
 612         {WCD938X_DIGITAL_CDC_TX1_CTL,                          0x68},
 613         {WCD938X_DIGITAL_CDC_TX2_CTL,                          0x68},
 614         {WCD938X_DIGITAL_CDC_TX_RST,                           0x00},
 615         {WCD938X_DIGITAL_CDC_REQ_CTL,                          0x01},
 616         {WCD938X_DIGITAL_CDC_RST,                              0x00},
 617         {WCD938X_DIGITAL_CDC_AMIC_CTL,                         0x0F},
 618         {WCD938X_DIGITAL_CDC_DMIC_CTL,                         0x04},
 619         {WCD938X_DIGITAL_CDC_DMIC1_CTL,                        0x01},
 620         {WCD938X_DIGITAL_CDC_DMIC2_CTL,                        0x01},
 621         {WCD938X_DIGITAL_CDC_DMIC3_CTL,                        0x01},
 622         {WCD938X_DIGITAL_CDC_DMIC4_CTL,                        0x01},
 623         {WCD938X_DIGITAL_EFUSE_PRG_CTL,                        0x00},
 624         {WCD938X_DIGITAL_EFUSE_CTL,                            0x2B},
 625         {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2,                    0x11},
 626         {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4,                    0x11},
 627         {WCD938X_DIGITAL_PDM_WD_CTL0,                          0x00},
 628         {WCD938X_DIGITAL_PDM_WD_CTL1,                          0x00},
 629         {WCD938X_DIGITAL_PDM_WD_CTL2,                          0x00},
 630         {WCD938X_DIGITAL_INTR_MODE,                            0x00},
 631         {WCD938X_DIGITAL_INTR_MASK_0,                          0xFF},
 632         {WCD938X_DIGITAL_INTR_MASK_1,                          0xFF},
 633         {WCD938X_DIGITAL_INTR_MASK_2,                          0x3F},
 634         {WCD938X_DIGITAL_INTR_STATUS_0,                        0x00},
 635         {WCD938X_DIGITAL_INTR_STATUS_1,                        0x00},
 636         {WCD938X_DIGITAL_INTR_STATUS_2,                        0x00},
 637         {WCD938X_DIGITAL_INTR_CLEAR_0,                         0x00},
 638         {WCD938X_DIGITAL_INTR_CLEAR_1,                         0x00},
 639         {WCD938X_DIGITAL_INTR_CLEAR_2,                         0x00},
 640         {WCD938X_DIGITAL_INTR_LEVEL_0,                         0x00},
 641         {WCD938X_DIGITAL_INTR_LEVEL_1,                         0x00},
 642         {WCD938X_DIGITAL_INTR_LEVEL_2,                         0x00},
 643         {WCD938X_DIGITAL_INTR_SET_0,                           0x00},
 644         {WCD938X_DIGITAL_INTR_SET_1,                           0x00},
 645         {WCD938X_DIGITAL_INTR_SET_2,                           0x00},
 646         {WCD938X_DIGITAL_INTR_TEST_0,                          0x00},
 647         {WCD938X_DIGITAL_INTR_TEST_1,                          0x00},
 648         {WCD938X_DIGITAL_INTR_TEST_2,                          0x00},
 649         {WCD938X_DIGITAL_TX_MODE_DBG_EN,                       0x00},
 650         {WCD938X_DIGITAL_TX_MODE_DBG_0_1,                      0x00},
 651         {WCD938X_DIGITAL_TX_MODE_DBG_2_3,                      0x00},
 652         {WCD938X_DIGITAL_LB_IN_SEL_CTL,                        0x00},
 653         {WCD938X_DIGITAL_LOOP_BACK_MODE,                       0x00},
 654         {WCD938X_DIGITAL_SWR_DAC_TEST,                         0x00},
 655         {WCD938X_DIGITAL_SWR_HM_TEST_RX_0,                     0x40},
 656         {WCD938X_DIGITAL_SWR_HM_TEST_TX_0,                     0x40},
 657         {WCD938X_DIGITAL_SWR_HM_TEST_RX_1,                     0x00},
 658         {WCD938X_DIGITAL_SWR_HM_TEST_TX_1,                     0x00},
 659         {WCD938X_DIGITAL_SWR_HM_TEST_TX_2,                     0x00},
 660         {WCD938X_DIGITAL_SWR_HM_TEST_0,                        0x00},
 661         {WCD938X_DIGITAL_SWR_HM_TEST_1,                        0x00},
 662         {WCD938X_DIGITAL_PAD_CTL_SWR_0,                        0x8F},
 663         {WCD938X_DIGITAL_PAD_CTL_SWR_1,                        0x06},
 664         {WCD938X_DIGITAL_I2C_CTL,                              0x00},
 665         {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE,                0x00},
 666         {WCD938X_DIGITAL_EFUSE_TEST_CTL_0,                     0x00},
 667         {WCD938X_DIGITAL_EFUSE_TEST_CTL_1,                     0x00},
 668         {WCD938X_DIGITAL_EFUSE_T_DATA_0,                       0x00},
 669         {WCD938X_DIGITAL_EFUSE_T_DATA_1,                       0x00},
 670         {WCD938X_DIGITAL_PAD_CTL_PDM_RX0,                      0xF1},
 671         {WCD938X_DIGITAL_PAD_CTL_PDM_RX1,                      0xF1},
 672         {WCD938X_DIGITAL_PAD_CTL_PDM_TX0,                      0xF1},
 673         {WCD938X_DIGITAL_PAD_CTL_PDM_TX1,                      0xF1},
 674         {WCD938X_DIGITAL_PAD_CTL_PDM_TX2,                      0xF1},
 675         {WCD938X_DIGITAL_PAD_INP_DIS_0,                        0x00},
 676         {WCD938X_DIGITAL_PAD_INP_DIS_1,                        0x00},
 677         {WCD938X_DIGITAL_DRIVE_STRENGTH_0,                     0x00},
 678         {WCD938X_DIGITAL_DRIVE_STRENGTH_1,                     0x00},
 679         {WCD938X_DIGITAL_DRIVE_STRENGTH_2,                     0x00},
 680         {WCD938X_DIGITAL_RX_DATA_EDGE_CTL,                     0x1F},
 681         {WCD938X_DIGITAL_TX_DATA_EDGE_CTL,                     0x80},
 682         {WCD938X_DIGITAL_GPIO_MODE,                            0x00},
 683         {WCD938X_DIGITAL_PIN_CTL_OE,                           0x00},
 684         {WCD938X_DIGITAL_PIN_CTL_DATA_0,                       0x00},
 685         {WCD938X_DIGITAL_PIN_CTL_DATA_1,                       0x00},
 686         {WCD938X_DIGITAL_PIN_STATUS_0,                         0x00},
 687         {WCD938X_DIGITAL_PIN_STATUS_1,                         0x00},
 688         {WCD938X_DIGITAL_DIG_DEBUG_CTL,                        0x00},
 689         {WCD938X_DIGITAL_DIG_DEBUG_EN,                         0x00},
 690         {WCD938X_DIGITAL_ANA_CSR_DBG_ADD,                      0x00},
 691         {WCD938X_DIGITAL_ANA_CSR_DBG_CTL,                      0x48},
 692         {WCD938X_DIGITAL_SSP_DBG,                              0x00},
 693         {WCD938X_DIGITAL_MODE_STATUS_0,                        0x00},
 694         {WCD938X_DIGITAL_MODE_STATUS_1,                        0x00},
 695         {WCD938X_DIGITAL_SPARE_0,                              0x00},
 696         {WCD938X_DIGITAL_SPARE_1,                              0x00},
 697         {WCD938X_DIGITAL_SPARE_2,                              0x00},
 698         {WCD938X_DIGITAL_EFUSE_REG_0,                          0x00},
 699         {WCD938X_DIGITAL_EFUSE_REG_1,                          0xFF},
 700         {WCD938X_DIGITAL_EFUSE_REG_2,                          0xFF},
 701         {WCD938X_DIGITAL_EFUSE_REG_3,                          0xFF},
 702         {WCD938X_DIGITAL_EFUSE_REG_4,                          0xFF},
 703         {WCD938X_DIGITAL_EFUSE_REG_5,                          0xFF},
 704         {WCD938X_DIGITAL_EFUSE_REG_6,                          0xFF},
 705         {WCD938X_DIGITAL_EFUSE_REG_7,                          0xFF},
 706         {WCD938X_DIGITAL_EFUSE_REG_8,                          0xFF},
 707         {WCD938X_DIGITAL_EFUSE_REG_9,                          0xFF},
 708         {WCD938X_DIGITAL_EFUSE_REG_10,                         0xFF},
 709         {WCD938X_DIGITAL_EFUSE_REG_11,                         0xFF},
 710         {WCD938X_DIGITAL_EFUSE_REG_12,                         0xFF},
 711         {WCD938X_DIGITAL_EFUSE_REG_13,                         0xFF},
 712         {WCD938X_DIGITAL_EFUSE_REG_14,                         0xFF},
 713         {WCD938X_DIGITAL_EFUSE_REG_15,                         0xFF},
 714         {WCD938X_DIGITAL_EFUSE_REG_16,                         0xFF},
 715         {WCD938X_DIGITAL_EFUSE_REG_17,                         0xFF},
 716         {WCD938X_DIGITAL_EFUSE_REG_18,                         0xFF},
 717         {WCD938X_DIGITAL_EFUSE_REG_19,                         0xFF},
 718         {WCD938X_DIGITAL_EFUSE_REG_20,                         0x0E},
 719         {WCD938X_DIGITAL_EFUSE_REG_21,                         0x00},
 720         {WCD938X_DIGITAL_EFUSE_REG_22,                         0x00},
 721         {WCD938X_DIGITAL_EFUSE_REG_23,                         0xF8},
 722         {WCD938X_DIGITAL_EFUSE_REG_24,                         0x16},
 723         {WCD938X_DIGITAL_EFUSE_REG_25,                         0x00},
 724         {WCD938X_DIGITAL_EFUSE_REG_26,                         0x00},
 725         {WCD938X_DIGITAL_EFUSE_REG_27,                         0x00},
 726         {WCD938X_DIGITAL_EFUSE_REG_28,                         0x00},
 727         {WCD938X_DIGITAL_EFUSE_REG_29,                         0x00},
 728         {WCD938X_DIGITAL_EFUSE_REG_30,                         0x00},
 729         {WCD938X_DIGITAL_EFUSE_REG_31,                         0x00},
 730         {WCD938X_DIGITAL_TX_REQ_FB_CTL_0,                      0x88},
 731         {WCD938X_DIGITAL_TX_REQ_FB_CTL_1,                      0x88},
 732         {WCD938X_DIGITAL_TX_REQ_FB_CTL_2,                      0x88},
 733         {WCD938X_DIGITAL_TX_REQ_FB_CTL_3,                      0x88},
 734         {WCD938X_DIGITAL_TX_REQ_FB_CTL_4,                      0x88},
 735         {WCD938X_DIGITAL_DEM_BYPASS_DATA0,                     0x55},
 736         {WCD938X_DIGITAL_DEM_BYPASS_DATA1,                     0x55},
 737         {WCD938X_DIGITAL_DEM_BYPASS_DATA2,                     0x55},
 738         {WCD938X_DIGITAL_DEM_BYPASS_DATA3,                     0x01},
 739 };
 740
 741 static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg)
 742 {
 743         switch (reg) {
 744         case WCD938X_ANA_PAGE_REGISTER:
 745         case WCD938X_ANA_BIAS:
 746         case WCD938X_ANA_RX_SUPPLIES:
 747         case WCD938X_ANA_HPH:
 748         case WCD938X_ANA_EAR:
 749         case WCD938X_ANA_EAR_COMPANDER_CTL:
 750         case WCD938X_ANA_TX_CH1:
 751         case WCD938X_ANA_TX_CH2:
 752         case WCD938X_ANA_TX_CH3:
 753         case WCD938X_ANA_TX_CH4:
 754         case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC:
 755         case WCD938X_ANA_MICB3_DSP_EN_LOGIC:
 756         case WCD938X_ANA_MBHC_MECH:
 757         case WCD938X_ANA_MBHC_ELECT:
 758         case WCD938X_ANA_MBHC_ZDET:
 759         case WCD938X_ANA_MBHC_BTN0:
 760         case WCD938X_ANA_MBHC_BTN1:
 761         case WCD938X_ANA_MBHC_BTN2:
 762         case WCD938X_ANA_MBHC_BTN3:
 763         case WCD938X_ANA_MBHC_BTN4:
 764         case WCD938X_ANA_MBHC_BTN5:
 765         case WCD938X_ANA_MBHC_BTN6:
 766         case WCD938X_ANA_MBHC_BTN7:
 767         case WCD938X_ANA_MICB1:
 768         case WCD938X_ANA_MICB2:
 769         case WCD938X_ANA_MICB2_RAMP:
 770         case WCD938X_ANA_MICB3:
 771         case WCD938X_ANA_MICB4:
 772         case WCD938X_BIAS_CTL:
 773         case WCD938X_BIAS_VBG_FINE_ADJ:
 774         case WCD938X_LDOL_VDDCX_ADJUST:
 775         case WCD938X_LDOL_DISABLE_LDOL:
 776         case WCD938X_MBHC_CTL_CLK:
 777         case WCD938X_MBHC_CTL_ANA:
 778         case WCD938X_MBHC_CTL_SPARE_1:
 779         case WCD938X_MBHC_CTL_SPARE_2:
 780         case WCD938X_MBHC_CTL_BCS:
 781         case WCD938X_MBHC_TEST_CTL:
 782         case WCD938X_LDOH_MODE:
 783         case WCD938X_LDOH_BIAS:
 784         case WCD938X_LDOH_STB_LOADS:
 785         case WCD938X_LDOH_SLOWRAMP:
 786         case WCD938X_MICB1_TEST_CTL_1:
 787         case WCD938X_MICB1_TEST_CTL_2:
 788         case WCD938X_MICB1_TEST_CTL_3:
 789         case WCD938X_MICB2_TEST_CTL_1:
 790         case WCD938X_MICB2_TEST_CTL_2:
 791         case WCD938X_MICB2_TEST_CTL_3:
 792         case WCD938X_MICB3_TEST_CTL_1:
 793         case WCD938X_MICB3_TEST_CTL_2:
 794         case WCD938X_MICB3_TEST_CTL_3:
 795         case WCD938X_MICB4_TEST_CTL_1:
 796         case WCD938X_MICB4_TEST_CTL_2:
 797         case WCD938X_MICB4_TEST_CTL_3:
 798         case WCD938X_TX_COM_ADC_VCM:
 799         case WCD938X_TX_COM_BIAS_ATEST:
 800         case WCD938X_TX_COM_SPARE1:
 801         case WCD938X_TX_COM_SPARE2:
 802         case WCD938X_TX_COM_TXFE_DIV_CTL:
 803         case WCD938X_TX_COM_TXFE_DIV_START:
 804         case WCD938X_TX_COM_SPARE3:
 805         case WCD938X_TX_COM_SPARE4:
 806         case WCD938X_TX_1_2_TEST_EN:
 807         case WCD938X_TX_1_2_ADC_IB:
 808         case WCD938X_TX_1_2_ATEST_REFCTL:
 809         case WCD938X_TX_1_2_TEST_CTL:
 810         case WCD938X_TX_1_2_TEST_BLK_EN1:
 811         case WCD938X_TX_1_2_TXFE1_CLKDIV:
 812         case WCD938X_TX_3_4_TEST_EN:
 813         case WCD938X_TX_3_4_ADC_IB:
 814         case WCD938X_TX_3_4_ATEST_REFCTL:
 815         case WCD938X_TX_3_4_TEST_CTL:
 816         case WCD938X_TX_3_4_TEST_BLK_EN3:
 817         case WCD938X_TX_3_4_TXFE3_CLKDIV:
 818         case WCD938X_TX_3_4_TEST_BLK_EN2:
 819         case WCD938X_TX_3_4_TXFE2_CLKDIV:
 820         case WCD938X_TX_3_4_SPARE1:
 821         case WCD938X_TX_3_4_TEST_BLK_EN4:
 822         case WCD938X_TX_3_4_TXFE4_CLKDIV:
 823         case WCD938X_TX_3_4_SPARE2:
 824         case WCD938X_CLASSH_MODE_1:
 825         case WCD938X_CLASSH_MODE_2:
 826         case WCD938X_CLASSH_MODE_3:
 827         case WCD938X_CLASSH_CTRL_VCL_1:
 828         case WCD938X_CLASSH_CTRL_VCL_2:
 829         case WCD938X_CLASSH_CTRL_CCL_1:
 830         case WCD938X_CLASSH_CTRL_CCL_2:
 831         case WCD938X_CLASSH_CTRL_CCL_3:
 832         case WCD938X_CLASSH_CTRL_CCL_4:
 833         case WCD938X_CLASSH_CTRL_CCL_5:
 834         case WCD938X_CLASSH_BUCK_TMUX_A_D:
 835         case WCD938X_CLASSH_BUCK_SW_DRV_CNTL:
 836         case WCD938X_CLASSH_SPARE:
 837         case WCD938X_FLYBACK_EN:
 838         case WCD938X_FLYBACK_VNEG_CTRL_1:
 839         case WCD938X_FLYBACK_VNEG_CTRL_2:
 840         case WCD938X_FLYBACK_VNEG_CTRL_3:
 841         case WCD938X_FLYBACK_VNEG_CTRL_4:
 842         case WCD938X_FLYBACK_VNEG_CTRL_5:
 843         case WCD938X_FLYBACK_VNEG_CTRL_6:
 844         case WCD938X_FLYBACK_VNEG_CTRL_7:
 845         case WCD938X_FLYBACK_VNEG_CTRL_8:
 846         case WCD938X_FLYBACK_VNEG_CTRL_9:
 847         case WCD938X_FLYBACK_VNEGDAC_CTRL_1:
 848         case WCD938X_FLYBACK_VNEGDAC_CTRL_2:
 849         case WCD938X_FLYBACK_VNEGDAC_CTRL_3:
 850         case WCD938X_FLYBACK_CTRL_1:
 851         case WCD938X_FLYBACK_TEST_CTL:
 852         case WCD938X_RX_AUX_SW_CTL:
 853         case WCD938X_RX_PA_AUX_IN_CONN:
 854         case WCD938X_RX_TIMER_DIV:
 855         case WCD938X_RX_OCP_CTL:
 856         case WCD938X_RX_OCP_COUNT:
 857         case WCD938X_RX_BIAS_EAR_DAC:
 858         case WCD938X_RX_BIAS_EAR_AMP:
 859         case WCD938X_RX_BIAS_HPH_LDO:
 860         case WCD938X_RX_BIAS_HPH_PA:
 861         case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2:
 862         case WCD938X_RX_BIAS_HPH_RDAC_LDO:
 863         case WCD938X_RX_BIAS_HPH_CNP1:
 864         case WCD938X_RX_BIAS_HPH_LOWPOWER:
 865         case WCD938X_RX_BIAS_AUX_DAC:
 866         case WCD938X_RX_BIAS_AUX_AMP:
 867         case WCD938X_RX_BIAS_VNEGDAC_BLEEDER:
 868         case WCD938X_RX_BIAS_MISC:
 869         case WCD938X_RX_BIAS_BUCK_RST:
 870         case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP:
 871         case WCD938X_RX_BIAS_FLYB_ERRAMP:
 872         case WCD938X_RX_BIAS_FLYB_BUFF:
 873         case WCD938X_RX_BIAS_FLYB_MID_RST:
 874         case WCD938X_HPH_CNP_EN:
 875         case WCD938X_HPH_CNP_WG_CTL:
 876         case WCD938X_HPH_CNP_WG_TIME:
 877         case WCD938X_HPH_OCP_CTL:
 878         case WCD938X_HPH_AUTO_CHOP:
 879         case WCD938X_HPH_CHOP_CTL:
 880         case WCD938X_HPH_PA_CTL1:
 881         case WCD938X_HPH_PA_CTL2:
 882         case WCD938X_HPH_L_EN:
 883         case WCD938X_HPH_L_TEST:
 884         case WCD938X_HPH_L_ATEST:
 885         case WCD938X_HPH_R_EN:
 886         case WCD938X_HPH_R_TEST:
 887         case WCD938X_HPH_R_ATEST:
 888         case WCD938X_HPH_RDAC_CLK_CTL1:
 889         case WCD938X_HPH_RDAC_CLK_CTL2:
 890         case WCD938X_HPH_RDAC_LDO_CTL:
 891         case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL:
 892         case WCD938X_HPH_REFBUFF_UHQA_CTL:
 893         case WCD938X_HPH_REFBUFF_LP_CTL:
 894         case WCD938X_HPH_L_DAC_CTL:
 895         case WCD938X_HPH_R_DAC_CTL:
 896         case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL:
 897         case WCD938X_HPH_SURGE_HPHLR_SURGE_EN:
 898         case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1:
 899         case WCD938X_EAR_EAR_EN_REG:
 900         case WCD938X_EAR_EAR_PA_CON:
 901         case WCD938X_EAR_EAR_SP_CON:
 902         case WCD938X_EAR_EAR_DAC_CON:
 903         case WCD938X_EAR_EAR_CNP_FSM_CON:
 904         case WCD938X_EAR_TEST_CTL:
 905         case WCD938X_ANA_NEW_PAGE_REGISTER:
 906         case WCD938X_HPH_NEW_ANA_HPH2:
 907         case WCD938X_HPH_NEW_ANA_HPH3:
 908         case WCD938X_SLEEP_CTL:
 909         case WCD938X_SLEEP_WATCHDOG_CTL:
 910         case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL:
 911         case WCD938X_MBHC_NEW_CTL_1:
 912         case WCD938X_MBHC_NEW_CTL_2:
 913         case WCD938X_MBHC_NEW_PLUG_DETECT_CTL:
 914         case WCD938X_MBHC_NEW_ZDET_ANA_CTL:
 915         case WCD938X_MBHC_NEW_ZDET_RAMP_CTL:
 916         case WCD938X_TX_NEW_AMIC_MUX_CFG:
 917         case WCD938X_AUX_AUXPA:
 918         case WCD938X_LDORXTX_MODE:
 919         case WCD938X_LDORXTX_CONFIG:
 920         case WCD938X_DIE_CRACK_DIE_CRK_DET_EN:
 921         case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL:
 922         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L:
 923         case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL:
 924         case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL:
 925         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R:
 926         case WCD938X_HPH_NEW_INT_PA_MISC1:
 927         case WCD938X_HPH_NEW_INT_PA_MISC2:
 928         case WCD938X_HPH_NEW_INT_PA_RDAC_MISC:
 929         case WCD938X_HPH_NEW_INT_HPH_TIMER1:
 930         case WCD938X_HPH_NEW_INT_HPH_TIMER2:
 931         case WCD938X_HPH_NEW_INT_HPH_TIMER3:
 932         case WCD938X_HPH_NEW_INT_HPH_TIMER4:
 933         case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2:
 934         case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3:
 935         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW:
 936         case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW:
 937         case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI:
 938         case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP:
 939         case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP:
 940         case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL:
 941         case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL:
 942         case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT:
 943         case WCD938X_MBHC_NEW_INT_SPARE_2:
 944         case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON:
 945         case WCD938X_EAR_INT_NEW_CNP_VCM_CON1:
 946         case WCD938X_EAR_INT_NEW_CNP_VCM_CON2:
 947         case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS:
 948         case WCD938X_AUX_INT_EN_REG:
 949         case WCD938X_AUX_INT_PA_CTRL:
 950         case WCD938X_AUX_INT_SP_CTRL:
 951         case WCD938X_AUX_INT_DAC_CTRL:
 952         case WCD938X_AUX_INT_CLK_CTRL:
 953         case WCD938X_AUX_INT_TEST_CTRL:
 954         case WCD938X_AUX_INT_MISC:
 955         case WCD938X_LDORXTX_INT_BIAS:
 956         case WCD938X_LDORXTX_INT_STB_LOADS_DTEST:
 957         case WCD938X_LDORXTX_INT_TEST0:
 958         case WCD938X_LDORXTX_INT_STARTUP_TIMER:
 959         case WCD938X_LDORXTX_INT_TEST1:
 960         case WCD938X_SLEEP_INT_WATCHDOG_CTL_1:
 961         case WCD938X_SLEEP_INT_WATCHDOG_CTL_2:
 962         case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1:
 963         case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2:
 964         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2:
 965         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1:
 966         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0:
 967         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M:
 968         case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M:
 969         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1:
 970         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0:
 971         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP:
 972         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1:
 973         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0:
 974         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP:
 975         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0:
 976         case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP:
 977         case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1:
 978         case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP:
 979         case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2:
 980         case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1:
 981         case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0:
 982         case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP:
 983         case WCD938X_DIGITAL_PAGE_REGISTER:
 984         case WCD938X_DIGITAL_SWR_TX_CLK_RATE:
 985         case WCD938X_DIGITAL_CDC_RST_CTL:
 986         case WCD938X_DIGITAL_TOP_CLK_CFG:
 987         case WCD938X_DIGITAL_CDC_ANA_CLK_CTL:
 988         case WCD938X_DIGITAL_CDC_DIG_CLK_CTL:
 989         case WCD938X_DIGITAL_SWR_RST_EN:
 990         case WCD938X_DIGITAL_CDC_PATH_MODE:
 991         case WCD938X_DIGITAL_CDC_RX_RST:
 992         case WCD938X_DIGITAL_CDC_RX0_CTL:
 993         case WCD938X_DIGITAL_CDC_RX1_CTL:
 994         case WCD938X_DIGITAL_CDC_RX2_CTL:
 995         case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1:
 996         case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3:
 997         case WCD938X_DIGITAL_CDC_COMP_CTL_0:
 998         case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL:
 999         case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0:
1000         case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1:
1001         case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0:
1002         case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1:
1003         case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0:
1004         case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1:
1005         case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0:
1006         case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1:
1007         case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0:
1008         case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1:
1009         case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0:
1010         case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0:
1011         case WCD938X_DIGITAL_CDC_HPH_DSM_C_0:
1012         case WCD938X_DIGITAL_CDC_HPH_DSM_C_1:
1013         case WCD938X_DIGITAL_CDC_HPH_DSM_C_2:
1014         case WCD938X_DIGITAL_CDC_HPH_DSM_C_3:
1015         case WCD938X_DIGITAL_CDC_HPH_DSM_R1:
1016         case WCD938X_DIGITAL_CDC_HPH_DSM_R2:
1017         case WCD938X_DIGITAL_CDC_HPH_DSM_R3:
1018         case WCD938X_DIGITAL_CDC_HPH_DSM_R4:
1019         case WCD938X_DIGITAL_CDC_HPH_DSM_R5:
1020         case WCD938X_DIGITAL_CDC_HPH_DSM_R6:
1021         case WCD938X_DIGITAL_CDC_HPH_DSM_R7:
1022         case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0:
1023         case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1:
1024         case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0:
1025         case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1:
1026         case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0:
1027         case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1:
1028         case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0:
1029         case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1:
1030         case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0:
1031         case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1:
1032         case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0:
1033         case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0:
1034         case WCD938X_DIGITAL_CDC_AUX_DSM_C_0:
1035         case WCD938X_DIGITAL_CDC_AUX_DSM_C_1:
1036         case WCD938X_DIGITAL_CDC_AUX_DSM_C_2:
1037         case WCD938X_DIGITAL_CDC_AUX_DSM_C_3:
1038         case WCD938X_DIGITAL_CDC_AUX_DSM_R1:
1039         case WCD938X_DIGITAL_CDC_AUX_DSM_R2:
1040         case WCD938X_DIGITAL_CDC_AUX_DSM_R3:
1041         case WCD938X_DIGITAL_CDC_AUX_DSM_R4:
1042         case WCD938X_DIGITAL_CDC_AUX_DSM_R5:
1043         case WCD938X_DIGITAL_CDC_AUX_DSM_R6:
1044         case WCD938X_DIGITAL_CDC_AUX_DSM_R7:
1045         case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0:
1046         case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1:
1047         case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0:
1048         case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1:
1049         case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2:
1050         case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0:
1051         case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1:
1052         case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2:
1053         case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL:
1054         case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL:
1055         case WCD938X_DIGITAL_CDC_EAR_PATH_CTL:
1056         case WCD938X_DIGITAL_CDC_SWR_CLH:
1057         case WCD938X_DIGITAL_SWR_CLH_BYP:
1058         case WCD938X_DIGITAL_CDC_TX0_CTL:
1059         case WCD938X_DIGITAL_CDC_TX1_CTL:
1060         case WCD938X_DIGITAL_CDC_TX2_CTL:
1061         case WCD938X_DIGITAL_CDC_TX_RST:
1062         case WCD938X_DIGITAL_CDC_REQ_CTL:
1063         case WCD938X_DIGITAL_CDC_RST:
1064         case WCD938X_DIGITAL_CDC_AMIC_CTL:
1065         case WCD938X_DIGITAL_CDC_DMIC_CTL:
1066         case WCD938X_DIGITAL_CDC_DMIC1_CTL:
1067         case WCD938X_DIGITAL_CDC_DMIC2_CTL:
1068         case WCD938X_DIGITAL_CDC_DMIC3_CTL:
1069         case WCD938X_DIGITAL_CDC_DMIC4_CTL:
1070         case WCD938X_DIGITAL_EFUSE_PRG_CTL:
1071         case WCD938X_DIGITAL_EFUSE_CTL:
1072         case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2:
1073         case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4:
1074         case WCD938X_DIGITAL_PDM_WD_CTL0:
1075         case WCD938X_DIGITAL_PDM_WD_CTL1:
1076         case WCD938X_DIGITAL_PDM_WD_CTL2:
1077         case WCD938X_DIGITAL_INTR_MODE:
1078         case WCD938X_DIGITAL_INTR_MASK_0:
1079         case WCD938X_DIGITAL_INTR_MASK_1:
1080         case WCD938X_DIGITAL_INTR_MASK_2:
1081         case WCD938X_DIGITAL_INTR_CLEAR_0:
1082         case WCD938X_DIGITAL_INTR_CLEAR_1:
1083         case WCD938X_DIGITAL_INTR_CLEAR_2:
1084         case WCD938X_DIGITAL_INTR_LEVEL_0:
1085         case WCD938X_DIGITAL_INTR_LEVEL_1:
1086         case WCD938X_DIGITAL_INTR_LEVEL_2:
1087         case WCD938X_DIGITAL_INTR_SET_0:
1088         case WCD938X_DIGITAL_INTR_SET_1:
1089         case WCD938X_DIGITAL_INTR_SET_2:
1090         case WCD938X_DIGITAL_INTR_TEST_0:
1091         case WCD938X_DIGITAL_INTR_TEST_1:
1092         case WCD938X_DIGITAL_INTR_TEST_2:
1093         case WCD938X_DIGITAL_TX_MODE_DBG_EN:
1094         case WCD938X_DIGITAL_TX_MODE_DBG_0_1:
1095         case WCD938X_DIGITAL_TX_MODE_DBG_2_3:
1096         case WCD938X_DIGITAL_LB_IN_SEL_CTL:
1097         case WCD938X_DIGITAL_LOOP_BACK_MODE:
1098         case WCD938X_DIGITAL_SWR_DAC_TEST:
1099         case WCD938X_DIGITAL_SWR_HM_TEST_RX_0:
1100         case WCD938X_DIGITAL_SWR_HM_TEST_TX_0:
1101         case WCD938X_DIGITAL_SWR_HM_TEST_RX_1:
1102         case WCD938X_DIGITAL_SWR_HM_TEST_TX_1:
1103         case WCD938X_DIGITAL_SWR_HM_TEST_TX_2:
1104         case WCD938X_DIGITAL_PAD_CTL_SWR_0:
1105         case WCD938X_DIGITAL_PAD_CTL_SWR_1:
1106         case WCD938X_DIGITAL_I2C_CTL:
1107         case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE:
1108         case WCD938X_DIGITAL_EFUSE_TEST_CTL_0:
1109         case WCD938X_DIGITAL_EFUSE_TEST_CTL_1:
1110         case WCD938X_DIGITAL_PAD_CTL_PDM_RX0:
1111         case WCD938X_DIGITAL_PAD_CTL_PDM_RX1:
1112         case WCD938X_DIGITAL_PAD_CTL_PDM_TX0:
1113         case WCD938X_DIGITAL_PAD_CTL_PDM_TX1:
1114         case WCD938X_DIGITAL_PAD_CTL_PDM_TX2:
1115         case WCD938X_DIGITAL_PAD_INP_DIS_0:
1116         case WCD938X_DIGITAL_PAD_INP_DIS_1:
1117         case WCD938X_DIGITAL_DRIVE_STRENGTH_0:
1118         case WCD938X_DIGITAL_DRIVE_STRENGTH_1:
1119         case WCD938X_DIGITAL_DRIVE_STRENGTH_2:
1120         case WCD938X_DIGITAL_RX_DATA_EDGE_CTL:
1121         case WCD938X_DIGITAL_TX_DATA_EDGE_CTL:
1122         case WCD938X_DIGITAL_GPIO_MODE:
1123         case WCD938X_DIGITAL_PIN_CTL_OE:
1124         case WCD938X_DIGITAL_PIN_CTL_DATA_0:
1125         case WCD938X_DIGITAL_PIN_CTL_DATA_1:
1126         case WCD938X_DIGITAL_DIG_DEBUG_CTL:
1127         case WCD938X_DIGITAL_DIG_DEBUG_EN:
1128         case WCD938X_DIGITAL_ANA_CSR_DBG_ADD:
1129         case WCD938X_DIGITAL_ANA_CSR_DBG_CTL:
1130         case WCD938X_DIGITAL_SSP_DBG:
1131         case WCD938X_DIGITAL_SPARE_0:
1132         case WCD938X_DIGITAL_SPARE_1:
1133         case WCD938X_DIGITAL_SPARE_2:
1134         case WCD938X_DIGITAL_TX_REQ_FB_CTL_0:
1135         case WCD938X_DIGITAL_TX_REQ_FB_CTL_1:
1136         case WCD938X_DIGITAL_TX_REQ_FB_CTL_2:
1137         case WCD938X_DIGITAL_TX_REQ_FB_CTL_3:
1138         case WCD938X_DIGITAL_TX_REQ_FB_CTL_4:
1139         case WCD938X_DIGITAL_DEM_BYPASS_DATA0:
1140         case WCD938X_DIGITAL_DEM_BYPASS_DATA1:
1141         case WCD938X_DIGITAL_DEM_BYPASS_DATA2:
1142         case WCD938X_DIGITAL_DEM_BYPASS_DATA3:
1143                 return true;
1144         }
1145
1146         return false;
1147 }
1148
1149 static bool wcd938x_readonly_register(struct device *dev, unsigned int reg)
1150 {
1151         switch (reg) {
1152         case WCD938X_ANA_MBHC_RESULT_1:
1153         case WCD938X_ANA_MBHC_RESULT_2:
1154         case WCD938X_ANA_MBHC_RESULT_3:
1155         case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS:
1156         case WCD938X_TX_1_2_SAR2_ERR:
1157         case WCD938X_TX_1_2_SAR1_ERR:
1158         case WCD938X_TX_3_4_SAR4_ERR:
1159         case WCD938X_TX_3_4_SAR3_ERR:
1160         case WCD938X_HPH_L_STATUS:
1161         case WCD938X_HPH_R_STATUS:
1162         case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS:
1163         case WCD938X_EAR_STATUS_REG_1:
1164         case WCD938X_EAR_STATUS_REG_2:
1165         case WCD938X_MBHC_NEW_FSM_STATUS:
1166         case WCD938X_MBHC_NEW_ADC_RESULT:
1167         case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT:
1168         case WCD938X_AUX_INT_STATUS_REG:
1169         case WCD938X_LDORXTX_INT_STATUS:
1170         case WCD938X_DIGITAL_CHIP_ID0:
1171         case WCD938X_DIGITAL_CHIP_ID1:
1172         case WCD938X_DIGITAL_CHIP_ID2:
1173         case WCD938X_DIGITAL_CHIP_ID3:
1174         case WCD938X_DIGITAL_INTR_STATUS_0:
1175         case WCD938X_DIGITAL_INTR_STATUS_1:
1176         case WCD938X_DIGITAL_INTR_STATUS_2:
1177         case WCD938X_DIGITAL_INTR_CLEAR_0:
1178         case WCD938X_DIGITAL_INTR_CLEAR_1:
1179         case WCD938X_DIGITAL_INTR_CLEAR_2:
1180         case WCD938X_DIGITAL_SWR_HM_TEST_0:
1181         case WCD938X_DIGITAL_SWR_HM_TEST_1:
1182         case WCD938X_DIGITAL_EFUSE_T_DATA_0:
1183         case WCD938X_DIGITAL_EFUSE_T_DATA_1:
1184         case WCD938X_DIGITAL_PIN_STATUS_0:
1185         case WCD938X_DIGITAL_PIN_STATUS_1:
1186         case WCD938X_DIGITAL_MODE_STATUS_0:
1187         case WCD938X_DIGITAL_MODE_STATUS_1:
1188         case WCD938X_DIGITAL_EFUSE_REG_0:
1189         case WCD938X_DIGITAL_EFUSE_REG_1:
1190         case WCD938X_DIGITAL_EFUSE_REG_2:
1191         case WCD938X_DIGITAL_EFUSE_REG_3:
1192         case WCD938X_DIGITAL_EFUSE_REG_4:
1193         case WCD938X_DIGITAL_EFUSE_REG_5:
1194         case WCD938X_DIGITAL_EFUSE_REG_6:
1195         case WCD938X_DIGITAL_EFUSE_REG_7:
1196         case WCD938X_DIGITAL_EFUSE_REG_8:
1197         case WCD938X_DIGITAL_EFUSE_REG_9:
1198         case WCD938X_DIGITAL_EFUSE_REG_10:
1199         case WCD938X_DIGITAL_EFUSE_REG_11:
1200         case WCD938X_DIGITAL_EFUSE_REG_12:
1201         case WCD938X_DIGITAL_EFUSE_REG_13:
1202         case WCD938X_DIGITAL_EFUSE_REG_14:
1203         case WCD938X_DIGITAL_EFUSE_REG_15:
1204         case WCD938X_DIGITAL_EFUSE_REG_16:
1205         case WCD938X_DIGITAL_EFUSE_REG_17:
1206         case WCD938X_DIGITAL_EFUSE_REG_18:
1207         case WCD938X_DIGITAL_EFUSE_REG_19:
1208         case WCD938X_DIGITAL_EFUSE_REG_20:
1209         case WCD938X_DIGITAL_EFUSE_REG_21:
1210         case WCD938X_DIGITAL_EFUSE_REG_22:
1211         case WCD938X_DIGITAL_EFUSE_REG_23:
1212         case WCD938X_DIGITAL_EFUSE_REG_24:
1213         case WCD938X_DIGITAL_EFUSE_REG_25:
1214         case WCD938X_DIGITAL_EFUSE_REG_26:
1215         case WCD938X_DIGITAL_EFUSE_REG_27:
1216         case WCD938X_DIGITAL_EFUSE_REG_28:
1217         case WCD938X_DIGITAL_EFUSE_REG_29:
1218         case WCD938X_DIGITAL_EFUSE_REG_30:
1219         case WCD938X_DIGITAL_EFUSE_REG_31:
1220                 return true;
1221         }
1222         return false;
1223 }
1224
1225 static bool wcd938x_readable_register(struct device *dev, unsigned int reg)
1226 {
1227         bool ret;
1228
1229         ret = wcd938x_readonly_register(dev, reg);
1230         if (!ret)
1231                 return wcd938x_rdwr_register(dev, reg);
1232
1233         return ret;
1234 }
1235
1236 static bool wcd938x_writeable_register(struct device *dev, unsigned int reg)
1237 {
1238         return wcd938x_rdwr_register(dev, reg);
1239 }
1240
1241 static bool wcd938x_volatile_register(struct device *dev, unsigned int reg)
1242 {
1243         if (reg <= WCD938X_BASE_ADDRESS)
1244                 return false;
1245
1246         if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE)
1247                 return true;
1248
1249         if (wcd938x_readonly_register(dev, reg))
1250                 return true;
1251
1252         return false;
1253 }
1254
1255 static struct regmap_config wcd938x_regmap_config = {
1256         .name = "wcd938x_csr",
1257         .reg_bits = 32,
1258         .val_bits = 8,
1259         .cache_type = REGCACHE_RBTREE,
1260         .reg_defaults = wcd938x_defaults,
1261         .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults),
1262         .max_register = WCD938X_MAX_REGISTER,
1263         .readable_reg = wcd938x_readable_register,
1264         .writeable_reg = wcd938x_writeable_register,
1265         .volatile_reg = wcd938x_volatile_register,
1266         .can_multi_write = true,
1267 };
1268
1269 static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
1270         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
1271         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
1272         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
1273         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
1274         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
1275         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
1276         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
1277         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
1278         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
1279         REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
1280         REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
1281         REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
1282         REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
1283         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
1284         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
1285         REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
1286         REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
1287         REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
1288         REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
1289         REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
1290 };
1291
1292 static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
1293         .name = "wcd938x",
1294         .irqs = wcd938x_irqs,
1295         .num_irqs = ARRAY_SIZE(wcd938x_irqs),
1296         .num_regs = 3,
1297         .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
1298         .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
1299         .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
1300         .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
1301         .use_ack = 1,
1302         .runtime_pm = true,
1303         .irq_drv_data = NULL,
1304 };
1305
1306 static int wcd938x_get_clk_rate(int mode)
1307 {
1308         int rate;
1309
1310         switch (mode) {
1311         case ADC_MODE_ULP2:
1312                 rate = SWR_CLK_RATE_0P6MHZ;
1313                 break;
1314         case ADC_MODE_ULP1:
1315                 rate = SWR_CLK_RATE_1P2MHZ;
1316                 break;
1317         case ADC_MODE_LP:
1318                 rate = SWR_CLK_RATE_4P8MHZ;
1319                 break;
1320         case ADC_MODE_NORMAL:
1321         case ADC_MODE_LO_HIF:
1322         case ADC_MODE_HIFI:
1323         case ADC_MODE_INVALID:
1324         default:
1325                 rate = SWR_CLK_RATE_9P6MHZ;
1326                 break;
1327         }
1328
1329         return rate;
1330 }
1331
1332 static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)
1333 {
1334         u8 mask = (bank ? 0xF0 : 0x0F);
1335         u8 val = 0;
1336
1337         switch (rate) {
1338         case SWR_CLK_RATE_0P6MHZ:
1339                 val = (bank ? 0x60 : 0x06);
1340                 break;
1341         case SWR_CLK_RATE_1P2MHZ:
1342                 val = (bank ? 0x50 : 0x05);
1343                 break;
1344         case SWR_CLK_RATE_2P4MHZ:
1345                 val = (bank ? 0x30 : 0x03);
1346                 break;
1347         case SWR_CLK_RATE_4P8MHZ:
1348                 val = (bank ? 0x10 : 0x01);
1349                 break;
1350         case SWR_CLK_RATE_9P6MHZ:
1351         default:
1352                 val = 0x00;
1353                 break;
1354         }
1355         snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE,
1356                                       mask, val);
1357
1358         return 0;
1359 }
1360
1361 static int wcd938x_io_init(struct wcd938x_priv *wcd938x)
1362 {
1363         struct regmap *rm = wcd938x->regmap;
1364
1365         regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
1366         regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80);
1367         /* 1 msec delay as per HW requirement */
1368         usleep_range(1000, 1010);
1369         regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40);
1370         /* 1 msec delay as per HW requirement */
1371         usleep_range(1000, 1010);
1372         regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00);
1373         regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ,
1374                                                                 0xF0, 0x80);
1375         regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80);
1376         regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40);
1377         /* 10 msec delay as per HW requirement */
1378         usleep_range(10000, 10010);
1379
1380         regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00);
1381         regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
1382                                       0xF0, 0x00);
1383         regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
1384                                       0x1F, 0x15);
1385         regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
1386                                       0x1F, 0x15);
1387         regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL,
1388                                       0xC0, 0x80);
1389         regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL,
1390                                       0x02, 0x02);
1391
1392         regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
1393                            0xFF, 0x14);
1394         regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
1395                            0x1F, 0x08);
1396
1397         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
1398         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
1399         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
1400         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
1401         regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
1402
1403         /* Set Noise Filter Resistor value */
1404         regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
1405         regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
1406         regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
1407         regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
1408
1409         regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
1410         regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
1411
1412         return 0;
1413
1414 }
1415
1416 static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info,
1417                                     struct sdw_port_config *port_config,
1418                                     u8 enable)
1419 {
1420         u8 ch_mask, port_num;
1421
1422         port_num = ch_info->port_num;
1423         ch_mask = ch_info->ch_mask;
1424
1425         port_config->num = port_num;
1426
1427         if (enable)
1428                 port_config->ch_mask |= ch_mask;
1429         else
1430                 port_config->ch_mask &= ~ch_mask;
1431
1432         return 0;
1433 }
1434
1435 static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 ch_id, u8 enable)
1436 {
1437         u8 port_num;
1438
1439         port_num = wcd->ch_info[ch_id].port_num;
1440
1441         return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id],
1442                                         &wcd->port_config[port_num],
1443                                         enable);
1444 }
1445
1446 static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
1447                                       struct snd_kcontrol *kcontrol,
1448                                       int event)
1449 {
1450         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1451
1452         switch (event) {
1453         case SND_SOC_DAPM_PRE_PMU:
1454                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1455                                 WCD938X_ANA_RX_CLK_EN_MASK, 1);
1456                 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1457                                 WCD938X_RX_BIAS_EN_MASK, 1);
1458                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL,
1459                                 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1460                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL,
1461                                 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1462                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL,
1463                                 WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1464                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1465                                 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1);
1466                 snd_soc_component_write_field(component, WCD938X_AUX_AUXPA,
1467                                               WCD938X_AUXPA_CLK_EN_MASK, 1);
1468                 break;
1469         case SND_SOC_DAPM_POST_PMD:
1470                 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1471                                 WCD938X_VNEG_EN_MASK, 0);
1472                 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1473                                 WCD938X_VPOS_EN_MASK, 0);
1474                 snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1475                                 WCD938X_RX_BIAS_EN_MASK, 0);
1476                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1477                                 WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0);
1478                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1479                                 WCD938X_ANA_RX_CLK_EN_MASK, 0);
1480                 break;
1481         }
1482         return 0;
1483 }
1484
1485 static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
1486                                         struct snd_kcontrol *kcontrol,
1487                                         int event)
1488 {
1489         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1490         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1491
1492         switch (event) {
1493         case SND_SOC_DAPM_PRE_PMU:
1494                 snd_soc_component_write_field(component,
1495                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1496                                 WCD938X_RXD0_CLK_EN_MASK, 0x01);
1497                 snd_soc_component_write_field(component,
1498                                 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1499                                 WCD938X_HPHL_RX_EN_MASK, 1);
1500                 snd_soc_component_write_field(component,
1501                                 WCD938X_HPH_RDAC_CLK_CTL1,
1502                                 WCD938X_CHOP_CLK_EN_MASK, 0);
1503                 break;
1504         case SND_SOC_DAPM_POST_PMU:
1505                 snd_soc_component_write_field(component,
1506                                 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,
1507                                 WCD938X_HPH_RES_DIV_MASK, 0x02);
1508                 if (wcd938x->comp1_enable) {
1509                         snd_soc_component_write_field(component,
1510                                 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1511                                 WCD938X_HPHL_COMP_EN_MASK, 1);
1512                         /* 5msec compander delay as per HW requirement */
1513                         if (!wcd938x->comp2_enable || (snd_soc_component_read(component,
1514                                                          WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
1515                                 usleep_range(5000, 5010);
1516                         snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1517                                               WCD938X_AUTOCHOP_TIMER_EN, 0);
1518                 } else {
1519                         snd_soc_component_write_field(component,
1520                                         WCD938X_DIGITAL_CDC_COMP_CTL_0,
1521                                         WCD938X_HPHL_COMP_EN_MASK, 0);
1522                         snd_soc_component_write_field(component,
1523                                         WCD938X_HPH_L_EN,
1524                                         WCD938X_GAIN_SRC_SEL_MASK,
1525                                         WCD938X_GAIN_SRC_SEL_REGISTER);
1526
1527                 }
1528                 break;
1529         case SND_SOC_DAPM_POST_PMD:
1530                 snd_soc_component_write_field(component,
1531                         WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1532                         WCD938X_HPH_RES_DIV_MASK, 0x1);
1533                 break;
1534         }
1535
1536         return 0;
1537 }
1538
1539 static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
1540                                         struct snd_kcontrol *kcontrol,
1541                                         int event)
1542 {
1543         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1544         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1545
1546         switch (event) {
1547         case SND_SOC_DAPM_PRE_PMU:
1548                 snd_soc_component_write_field(component,
1549                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1550                                 WCD938X_RXD1_CLK_EN_MASK, 1);
1551                 snd_soc_component_write_field(component,
1552                                 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1553                                 WCD938X_HPHR_RX_EN_MASK, 1);
1554                 snd_soc_component_write_field(component,
1555                                 WCD938X_HPH_RDAC_CLK_CTL1,
1556                                 WCD938X_CHOP_CLK_EN_MASK, 0);
1557                 break;
1558         case SND_SOC_DAPM_POST_PMU:
1559                 snd_soc_component_write_field(component,
1560                                 WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1561                                 WCD938X_HPH_RES_DIV_MASK, 0x02);
1562                 if (wcd938x->comp2_enable) {
1563                         snd_soc_component_write_field(component,
1564                                 WCD938X_DIGITAL_CDC_COMP_CTL_0,
1565                                 WCD938X_HPHR_COMP_EN_MASK, 1);
1566                         /* 5msec compander delay as per HW requirement */
1567                         if (!wcd938x->comp1_enable ||
1568                                 (snd_soc_component_read(component,
1569                                         WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
1570                                 usleep_range(5000, 5010);
1571                         snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1572                                               WCD938X_AUTOCHOP_TIMER_EN, 0);
1573                 } else {
1574                         snd_soc_component_write_field(component,
1575                                         WCD938X_DIGITAL_CDC_COMP_CTL_0,
1576                                         WCD938X_HPHR_COMP_EN_MASK, 0);
1577                         snd_soc_component_write_field(component,
1578                                         WCD938X_HPH_R_EN,
1579                                         WCD938X_GAIN_SRC_SEL_MASK,
1580                                         WCD938X_GAIN_SRC_SEL_REGISTER);
1581                 }
1582                 break;
1583         case SND_SOC_DAPM_POST_PMD:
1584                 snd_soc_component_write_field(component,
1585                         WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1586                         WCD938X_HPH_RES_DIV_MASK, 0x01);
1587                 break;
1588         }
1589
1590         return 0;
1591 }
1592
1593 static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
1594                                        struct snd_kcontrol *kcontrol,
1595                                        int event)
1596 {
1597         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1598         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1599
1600         switch (event) {
1601         case SND_SOC_DAPM_PRE_PMU:
1602                 wcd938x->ear_rx_path =
1603                         snd_soc_component_read(
1604                                 component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1605                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1606                         snd_soc_component_write_field(component,
1607                                 WCD938X_EAR_EAR_DAC_CON,
1608                                 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0);
1609                         snd_soc_component_write_field(component,
1610                                 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1611                                 WCD938X_AUX_EN_MASK, 1);
1612                         snd_soc_component_write_field(component,
1613                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1614                                 WCD938X_RXD2_CLK_EN_MASK, 1);
1615                         snd_soc_component_write_field(component,
1616                                 WCD938X_ANA_EAR_COMPANDER_CTL,
1617                                 WCD938X_GAIN_OVRD_REG_MASK, 1);
1618                 } else {
1619                         snd_soc_component_write_field(component,
1620                                 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1621                                 WCD938X_HPHL_RX_EN_MASK, 1);
1622                         snd_soc_component_write_field(component,
1623                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1624                                 WCD938X_RXD0_CLK_EN_MASK, 1);
1625                         if (wcd938x->comp1_enable)
1626                                 snd_soc_component_write_field(component,
1627                                         WCD938X_DIGITAL_CDC_COMP_CTL_0,
1628                                         WCD938X_HPHL_COMP_EN_MASK, 1);
1629                 }
1630                 /* 5 msec delay as per HW requirement */
1631                 usleep_range(5000, 5010);
1632                 if (wcd938x->flyback_cur_det_disable == 0)
1633                         snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1634                                                       WCD938X_EN_CUR_DET_MASK, 0);
1635                 wcd938x->flyback_cur_det_disable++;
1636                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1637                              WCD_CLSH_EVENT_PRE_DAC,
1638                              WCD_CLSH_STATE_EAR,
1639                              wcd938x->hph_mode);
1640                 break;
1641         case SND_SOC_DAPM_POST_PMD:
1642                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1643                         snd_soc_component_write_field(component,
1644                                 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1645                                 WCD938X_AUX_EN_MASK, 0);
1646                         snd_soc_component_write_field(component,
1647                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1648                                 WCD938X_RXD2_CLK_EN_MASK, 0);
1649                 } else {
1650                         snd_soc_component_write_field(component,
1651                                 WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1652                                 WCD938X_HPHL_RX_EN_MASK, 0);
1653                         snd_soc_component_write_field(component,
1654                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1655                                 WCD938X_RXD0_CLK_EN_MASK, 0);
1656                         if (wcd938x->comp1_enable)
1657                                 snd_soc_component_write_field(component,
1658                                         WCD938X_DIGITAL_CDC_COMP_CTL_0,
1659                                         WCD938X_HPHL_COMP_EN_MASK, 0);
1660                 }
1661                 snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
1662                                               WCD938X_GAIN_OVRD_REG_MASK, 0);
1663                 snd_soc_component_write_field(component,
1664                                 WCD938X_EAR_EAR_DAC_CON,
1665                                 WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1);
1666                 break;
1667         }
1668         return 0;
1669
1670 }
1671
1672 static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
1673                                        struct snd_kcontrol *kcontrol,
1674                                        int event)
1675 {
1676         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1677         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1678
1679         switch (event) {
1680         case SND_SOC_DAPM_PRE_PMU:
1681                 snd_soc_component_write_field(component,
1682                                 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1683                                 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1);
1684                 snd_soc_component_write_field(component,
1685                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1686                                 WCD938X_RXD2_CLK_EN_MASK, 1);
1687                 snd_soc_component_write_field(component,
1688                                 WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1689                                 WCD938X_AUX_EN_MASK, 1);
1690                 if (wcd938x->flyback_cur_det_disable == 0)
1691                         snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1692                                                       WCD938X_EN_CUR_DET_MASK, 0);
1693                 wcd938x->flyback_cur_det_disable++;
1694                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1695                              WCD_CLSH_EVENT_PRE_DAC,
1696                              WCD_CLSH_STATE_AUX,
1697                              wcd938x->hph_mode);
1698                 break;
1699         case SND_SOC_DAPM_POST_PMD:
1700                 snd_soc_component_write_field(component,
1701                                 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1702                                 WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0);
1703                 break;
1704         }
1705         return 0;
1706
1707 }
1708
1709 static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
1710                                         struct snd_kcontrol *kcontrol, int event)
1711 {
1712         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1713         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1714         int hph_mode = wcd938x->hph_mode;
1715
1716         switch (event) {
1717         case SND_SOC_DAPM_PRE_PMU:
1718                 if (wcd938x->ldoh)
1719                         snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1720                                                       WCD938X_LDOH_EN_MASK, 1);
1721                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1722                                         WCD_CLSH_STATE_HPHR, hph_mode);
1723                 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1724
1725                 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1726                     hph_mode == CLS_H_ULP) {
1727                         snd_soc_component_write_field(component,
1728                                 WCD938X_HPH_REFBUFF_LP_CTL,
1729                                 WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1730                 }
1731                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1732                                               WCD938X_HPHR_REF_EN_MASK, 1);
1733                 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1734                 /* 100 usec delay as per HW requirement */
1735                 usleep_range(100, 110);
1736                 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1737                 snd_soc_component_write_field(component,
1738                                               WCD938X_DIGITAL_PDM_WD_CTL1,
1739                                               WCD938X_PDM_WD_EN_MASK, 0x3);
1740                 break;
1741         case SND_SOC_DAPM_POST_PMU:
1742                 /*
1743                  * 7ms sleep is required if compander is enabled as per
1744                  * HW requirement. If compander is disabled, then
1745                  * 20ms delay is required.
1746                  */
1747                 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1748                         if (!wcd938x->comp2_enable)
1749                                 usleep_range(20000, 20100);
1750                         else
1751                                 usleep_range(7000, 7100);
1752
1753                         if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1754                             hph_mode == CLS_H_ULP)
1755                                 snd_soc_component_write_field(component,
1756                                                 WCD938X_HPH_REFBUFF_LP_CTL,
1757                                                 WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1758                         clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1759                 }
1760                 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1761                                               WCD938X_AUTOCHOP_TIMER_EN, 1);
1762                 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1763                         hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1764                         snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1765                                         WCD938X_REGULATOR_MODE_MASK,
1766                                         WCD938X_REGULATOR_MODE_CLASS_AB);
1767                 enable_irq(wcd938x->hphr_pdm_wd_int);
1768                 break;
1769         case SND_SOC_DAPM_PRE_PMD:
1770                 disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
1771                 /*
1772                  * 7ms sleep is required if compander is enabled as per
1773                  * HW requirement. If compander is disabled, then
1774                  * 20ms delay is required.
1775                  */
1776                 if (!wcd938x->comp2_enable)
1777                         usleep_range(20000, 20100);
1778                 else
1779                         usleep_range(7000, 7100);
1780                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1781                                               WCD938X_HPHR_EN_MASK, 0);
1782                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1783                                              WCD_EVENT_PRE_HPHR_PA_OFF);
1784                 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1785                 break;
1786         case SND_SOC_DAPM_POST_PMD:
1787                 /*
1788                  * 7ms sleep is required if compander is enabled as per
1789                  * HW requirement. If compander is disabled, then
1790                  * 20ms delay is required.
1791                  */
1792                 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1793                         if (!wcd938x->comp2_enable)
1794                                 usleep_range(20000, 20100);
1795                         else
1796                                 usleep_range(7000, 7100);
1797                         clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1798                 }
1799                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1800                                              WCD_EVENT_POST_HPHR_PA_OFF);
1801                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1802                                               WCD938X_HPHR_REF_EN_MASK, 0);
1803                 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1,
1804                                               WCD938X_PDM_WD_EN_MASK, 0);
1805                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1806                                         WCD_CLSH_STATE_HPHR, hph_mode);
1807                 if (wcd938x->ldoh)
1808                         snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1809                                                       WCD938X_LDOH_EN_MASK, 0);
1810                 break;
1811         }
1812
1813         return 0;
1814 }
1815
1816 static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
1817                                         struct snd_kcontrol *kcontrol, int event)
1818 {
1819         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1820         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1821         int hph_mode = wcd938x->hph_mode;
1822
1823         switch (event) {
1824         case SND_SOC_DAPM_PRE_PMU:
1825                 if (wcd938x->ldoh)
1826                         snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1827                                                       WCD938X_LDOH_EN_MASK, 1);
1828                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1829                                         WCD_CLSH_STATE_HPHL, hph_mode);
1830                 wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1831                 if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1832                     hph_mode == CLS_H_ULP) {
1833                         snd_soc_component_write_field(component,
1834                                         WCD938X_HPH_REFBUFF_LP_CTL,
1835                                         WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1836                 }
1837                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1838                                               WCD938X_HPHL_REF_EN_MASK, 1);
1839                 wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1840                 /* 100 usec delay as per HW requirement */
1841                 usleep_range(100, 110);
1842                 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1843                 snd_soc_component_write_field(component,
1844                                         WCD938X_DIGITAL_PDM_WD_CTL0,
1845                                         WCD938X_PDM_WD_EN_MASK, 0x3);
1846                 break;
1847         case SND_SOC_DAPM_POST_PMU:
1848                 /*
1849                  * 7ms sleep is required if compander is enabled as per
1850                  * HW requirement. If compander is disabled, then
1851                  * 20ms delay is required.
1852                  */
1853                 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1854                         if (!wcd938x->comp1_enable)
1855                                 usleep_range(20000, 20100);
1856                         else
1857                                 usleep_range(7000, 7100);
1858                         if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1859                             hph_mode == CLS_H_ULP)
1860                                 snd_soc_component_write_field(component,
1861                                         WCD938X_HPH_REFBUFF_LP_CTL,
1862                                         WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1863                         clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1864                 }
1865
1866                 snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1867                                               WCD938X_AUTOCHOP_TIMER_EN, 1);
1868                 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1869                         hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1870                         snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1871                                         WCD938X_REGULATOR_MODE_MASK,
1872                                         WCD938X_REGULATOR_MODE_CLASS_AB);
1873                 enable_irq(wcd938x->hphl_pdm_wd_int);
1874                 break;
1875         case SND_SOC_DAPM_PRE_PMD:
1876                 disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
1877                 /*
1878                  * 7ms sleep is required if compander is enabled as per
1879                  * HW requirement. If compander is disabled, then
1880                  * 20ms delay is required.
1881                  */
1882                 if (!wcd938x->comp1_enable)
1883                         usleep_range(20000, 20100);
1884                 else
1885                         usleep_range(7000, 7100);
1886                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1887                                               WCD938X_HPHL_EN_MASK, 0);
1888                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
1889                 set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1890                 break;
1891         case SND_SOC_DAPM_POST_PMD:
1892                 /*
1893                  * 7ms sleep is required if compander is enabled as per
1894                  * HW requirement. If compander is disabled, then
1895                  * 20ms delay is required.
1896                  */
1897                 if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1898                         if (!wcd938x->comp1_enable)
1899                                 usleep_range(21000, 21100);
1900                         else
1901                                 usleep_range(7000, 7100);
1902                         clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1903                 }
1904                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
1905                                              WCD_EVENT_POST_HPHL_PA_OFF);
1906                 snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1907                                               WCD938X_HPHL_REF_EN_MASK, 0);
1908                 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
1909                                               WCD938X_PDM_WD_EN_MASK, 0);
1910                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1911                                         WCD_CLSH_STATE_HPHL, hph_mode);
1912                 if (wcd938x->ldoh)
1913                         snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1914                                                       WCD938X_LDOH_EN_MASK, 0);
1915                 break;
1916         }
1917
1918         return 0;
1919 }
1920
1921 static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
1922                                        struct snd_kcontrol *kcontrol, int event)
1923 {
1924         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1925         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1926         int hph_mode = wcd938x->hph_mode;
1927
1928         switch (event) {
1929         case SND_SOC_DAPM_PRE_PMU:
1930                 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1931                                               WCD938X_AUX_PDM_WD_EN_MASK, 1);
1932                 break;
1933         case SND_SOC_DAPM_POST_PMU:
1934                 /* 1 msec delay as per HW requirement */
1935                 usleep_range(1000, 1010);
1936                 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1937                         hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1938                         snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1939                                         WCD938X_REGULATOR_MODE_MASK,
1940                                         WCD938X_REGULATOR_MODE_CLASS_AB);
1941                 enable_irq(wcd938x->aux_pdm_wd_int);
1942                 break;
1943         case SND_SOC_DAPM_PRE_PMD:
1944                 disable_irq_nosync(wcd938x->aux_pdm_wd_int);
1945                 break;
1946         case SND_SOC_DAPM_POST_PMD:
1947                 /* 1 msec delay as per HW requirement */
1948                 usleep_range(1000, 1010);
1949                 snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1950                                               WCD938X_AUX_PDM_WD_EN_MASK, 0);
1951                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1952                              WCD_CLSH_EVENT_POST_PA,
1953                              WCD_CLSH_STATE_AUX,
1954                              hph_mode);
1955
1956                 wcd938x->flyback_cur_det_disable--;
1957                 if (wcd938x->flyback_cur_det_disable == 0)
1958                         snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1959                                                       WCD938X_EN_CUR_DET_MASK, 1);
1960                 break;
1961         }
1962         return 0;
1963 }
1964
1965 static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
1966                                        struct snd_kcontrol *kcontrol, int event)
1967 {
1968         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1969         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1970         int hph_mode = wcd938x->hph_mode;
1971
1972         switch (event) {
1973         case SND_SOC_DAPM_PRE_PMU:
1974                 /*
1975                  * Enable watchdog interrupt for HPHL or AUX
1976                  * depending on mux value
1977                  */
1978                 wcd938x->ear_rx_path = snd_soc_component_read(component,
1979                                                               WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1980                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1981                         snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1982                                               WCD938X_AUX_PDM_WD_EN_MASK, 1);
1983                 else
1984                         snd_soc_component_write_field(component,
1985                                                       WCD938X_DIGITAL_PDM_WD_CTL0,
1986                                                       WCD938X_PDM_WD_EN_MASK, 0x3);
1987                 if (!wcd938x->comp1_enable)
1988                         snd_soc_component_write_field(component,
1989                                                       WCD938X_ANA_EAR_COMPANDER_CTL,
1990                                                       WCD938X_GAIN_OVRD_REG_MASK, 1);
1991
1992                 break;
1993         case SND_SOC_DAPM_POST_PMU:
1994                 /* 6 msec delay as per HW requirement */
1995                 usleep_range(6000, 6010);
1996                 if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1997                         hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1998                         snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1999                                         WCD938X_REGULATOR_MODE_MASK,
2000                                         WCD938X_REGULATOR_MODE_CLASS_AB);
2001                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
2002                         enable_irq(wcd938x->aux_pdm_wd_int);
2003                 else
2004                         enable_irq(wcd938x->hphl_pdm_wd_int);
2005                 break;
2006         case SND_SOC_DAPM_PRE_PMD:
2007                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
2008                         disable_irq_nosync(wcd938x->aux_pdm_wd_int);
2009                 else
2010                         disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
2011                 break;
2012         case SND_SOC_DAPM_POST_PMD:
2013                 if (!wcd938x->comp1_enable)
2014                         snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
2015                                                       WCD938X_GAIN_OVRD_REG_MASK, 0);
2016                 /* 7 msec delay as per HW requirement */
2017                 usleep_range(7000, 7010);
2018                 if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
2019                         snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
2020                                               WCD938X_AUX_PDM_WD_EN_MASK, 0);
2021                 else
2022                         snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
2023                                         WCD938X_PDM_WD_EN_MASK, 0);
2024
2025                 wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
2026                                         WCD_CLSH_STATE_EAR, hph_mode);
2027
2028                 wcd938x->flyback_cur_det_disable--;
2029                 if (wcd938x->flyback_cur_det_disable == 0)
2030                         snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
2031                                                       WCD938X_EN_CUR_DET_MASK, 1);
2032                 break;
2033         }
2034
2035         return 0;
2036 }
2037
2038 static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2039                                      struct snd_kcontrol *kcontrol,
2040                                      int event)
2041 {
2042         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2043         u16 dmic_clk_reg, dmic_clk_en_reg;
2044         u8 dmic_sel_mask, dmic_clk_mask;
2045
2046         switch (w->shift) {
2047         case 0:
2048         case 1:
2049                 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
2050                 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
2051                 dmic_clk_mask = WCD938X_DMIC1_RATE_MASK;
2052                 dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK;
2053                 break;
2054         case 2:
2055         case 3:
2056                 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
2057                 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
2058                 dmic_clk_mask = WCD938X_DMIC2_RATE_MASK;
2059                 dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK;
2060                 break;
2061         case 4:
2062         case 5:
2063                 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
2064                 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
2065                 dmic_clk_mask = WCD938X_DMIC3_RATE_MASK;
2066                 dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK;
2067                 break;
2068         case 6:
2069         case 7:
2070                 dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
2071                 dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
2072                 dmic_clk_mask = WCD938X_DMIC4_RATE_MASK;
2073                 dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK;
2074                 break;
2075         default:
2076                 dev_err(component->dev, "%s: Invalid DMIC Selection\n",
2077                         __func__);
2078                 return -EINVAL;
2079         }
2080
2081         switch (event) {
2082         case SND_SOC_DAPM_PRE_PMU:
2083                 snd_soc_component_write_field(component,
2084                                 WCD938X_DIGITAL_CDC_AMIC_CTL,
2085                                 dmic_sel_mask,
2086                                 WCD938X_AMIC1_IN_SEL_DMIC);
2087                 /* 250us sleep as per HW requirement */
2088                 usleep_range(250, 260);
2089                 /* Setting DMIC clock rate to 2.4MHz */
2090                 snd_soc_component_write_field(component, dmic_clk_reg,
2091                                               dmic_clk_mask,
2092                                               WCD938X_DMIC4_RATE_2P4MHZ);
2093                 snd_soc_component_write_field(component, dmic_clk_en_reg,
2094                                               WCD938X_DMIC_CLK_EN_MASK, 1);
2095                 /* enable clock scaling */
2096                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
2097                                               WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3);
2098                 break;
2099         case SND_SOC_DAPM_POST_PMD:
2100                 snd_soc_component_write_field(component,
2101                                 WCD938X_DIGITAL_CDC_AMIC_CTL,
2102                                 dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC);
2103                 snd_soc_component_write_field(component, dmic_clk_en_reg,
2104                                               WCD938X_DMIC_CLK_EN_MASK, 0);
2105                 break;
2106         }
2107         return 0;
2108 }
2109
2110 static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
2111                                struct snd_kcontrol *kcontrol, int event)
2112 {
2113         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2114         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2115         int bank;
2116         int rate;
2117
2118         bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1;
2119         bank = bank ? 0 : 1;
2120
2121         switch (event) {
2122         case SND_SOC_DAPM_PRE_PMU:
2123                 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
2124                         int i = 0, mode = 0;
2125
2126                         if (test_bit(WCD_ADC1, &wcd938x->status_mask))
2127                                 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
2128                         if (test_bit(WCD_ADC2, &wcd938x->status_mask))
2129                                 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
2130                         if (test_bit(WCD_ADC3, &wcd938x->status_mask))
2131                                 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
2132                         if (test_bit(WCD_ADC4, &wcd938x->status_mask))
2133                                 mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
2134
2135                         if (mode != 0) {
2136                                 for (i = 0; i < ADC_MODE_ULP2; i++) {
2137                                         if (mode & (1 << i)) {
2138                                                 i++;
2139                                                 break;
2140                                         }
2141                                 }
2142                         }
2143                         rate = wcd938x_get_clk_rate(i);
2144                         wcd938x_set_swr_clk_rate(component, rate, bank);
2145                         /* Copy clk settings to active bank */
2146                         wcd938x_set_swr_clk_rate(component, rate, !bank);
2147                 }
2148                 break;
2149         case SND_SOC_DAPM_POST_PMD:
2150                 if (strnstr(w->name, "ADC", sizeof("ADC"))) {
2151                         rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
2152                         wcd938x_set_swr_clk_rate(component, rate, !bank);
2153                         wcd938x_set_swr_clk_rate(component, rate, bank);
2154                 }
2155                 break;
2156         }
2157
2158         return 0;
2159 }
2160
2161 static int wcd938x_get_adc_mode(int val)
2162 {
2163         int ret = 0;
2164
2165         switch (val) {
2166         case ADC_MODE_INVALID:
2167                 ret = ADC_MODE_VAL_NORMAL;
2168                 break;
2169         case ADC_MODE_HIFI:
2170                 ret = ADC_MODE_VAL_HIFI;
2171                 break;
2172         case ADC_MODE_LO_HIF:
2173                 ret = ADC_MODE_VAL_LO_HIF;
2174                 break;
2175         case ADC_MODE_NORMAL:
2176                 ret = ADC_MODE_VAL_NORMAL;
2177                 break;
2178         case ADC_MODE_LP:
2179                 ret = ADC_MODE_VAL_LP;
2180                 break;
2181         case ADC_MODE_ULP1:
2182                 ret = ADC_MODE_VAL_ULP1;
2183                 break;
2184         case ADC_MODE_ULP2:
2185                 ret = ADC_MODE_VAL_ULP2;
2186                 break;
2187         default:
2188                 ret = -EINVAL;
2189                 break;
2190         }
2191         return ret;
2192 }
2193
2194 static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
2195                                     struct snd_kcontrol *kcontrol, int event)
2196 {
2197         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2198         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2199
2200         switch (event) {
2201         case SND_SOC_DAPM_PRE_PMU:
2202                 snd_soc_component_write_field(component,
2203                                               WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2204                                               WCD938X_ANA_TX_CLK_EN_MASK, 1);
2205                 snd_soc_component_write_field(component,
2206                                               WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2207                                               WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
2208                 set_bit(w->shift, &wcd938x->status_mask);
2209                 break;
2210         case SND_SOC_DAPM_POST_PMD:
2211                 snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2212                                               WCD938X_ANA_TX_CLK_EN_MASK, 0);
2213                 clear_bit(w->shift, &wcd938x->status_mask);
2214                 break;
2215         }
2216
2217         return 0;
2218 }
2219
2220 static void wcd938x_tx_channel_config(struct snd_soc_component *component,
2221                                      int channel, int mode)
2222 {
2223         int reg, mask;
2224
2225         switch (channel) {
2226         case 0:
2227                 reg = WCD938X_ANA_TX_CH2;
2228                 mask = WCD938X_HPF1_INIT_MASK;
2229                 break;
2230         case 1:
2231                 reg = WCD938X_ANA_TX_CH2;
2232                 mask = WCD938X_HPF2_INIT_MASK;
2233                 break;
2234         case 2:
2235                 reg = WCD938X_ANA_TX_CH4;
2236                 mask = WCD938X_HPF3_INIT_MASK;
2237                 break;
2238         case 3:
2239                 reg = WCD938X_ANA_TX_CH4;
2240                 mask = WCD938X_HPF4_INIT_MASK;
2241                 break;
2242         default:
2243                 return;
2244         }
2245
2246         snd_soc_component_write_field(component, reg, mask, mode);
2247 }
2248
2249 static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w,
2250                                   struct snd_kcontrol *kcontrol, int event)
2251 {
2252         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2253         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2254         int mode;
2255
2256         switch (event) {
2257         case SND_SOC_DAPM_PRE_PMU:
2258                 snd_soc_component_write_field(component,
2259                                 WCD938X_DIGITAL_CDC_REQ_CTL,
2260                                 WCD938X_FS_RATE_4P8_MASK, 1);
2261                 snd_soc_component_write_field(component,
2262                                 WCD938X_DIGITAL_CDC_REQ_CTL,
2263                                 WCD938X_NO_NOTCH_MASK, 0);
2264                 wcd938x_tx_channel_config(component, w->shift, 1);
2265                 mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
2266                 if (mode < 0) {
2267                         dev_info(component->dev, "Invalid ADC mode\n");
2268                         return -EINVAL;
2269                 }
2270                 switch (w->shift) {
2271                 case 0:
2272                         snd_soc_component_write_field(component,
2273                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2274                                 WCD938X_TXD0_MODE_MASK, mode);
2275                         snd_soc_component_write_field(component,
2276                                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2277                                                 WCD938X_TXD0_CLK_EN_MASK, 1);
2278                         break;
2279                 case 1:
2280                         snd_soc_component_write_field(component,
2281                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2282                                 WCD938X_TXD1_MODE_MASK, mode);
2283                         snd_soc_component_write_field(component,
2284                                               WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2285                                               WCD938X_TXD1_CLK_EN_MASK, 1);
2286                         break;
2287                 case 2:
2288                         snd_soc_component_write_field(component,
2289                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2290                                 WCD938X_TXD2_MODE_MASK, mode);
2291                         snd_soc_component_write_field(component,
2292                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2293                                 WCD938X_TXD2_CLK_EN_MASK, 1);
2294                         break;
2295                 case 3:
2296                         snd_soc_component_write_field(component,
2297                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2298                                 WCD938X_TXD3_MODE_MASK, mode);
2299                         snd_soc_component_write_field(component,
2300                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2301                                 WCD938X_TXD3_CLK_EN_MASK, 1);
2302                         break;
2303                 default:
2304                         break;
2305                 }
2306
2307                 wcd938x_tx_channel_config(component, w->shift, 0);
2308                 break;
2309         case SND_SOC_DAPM_POST_PMD:
2310                 switch (w->shift) {
2311                 case 0:
2312                         snd_soc_component_write_field(component,
2313                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2314                                 WCD938X_TXD0_MODE_MASK, 0);
2315                         snd_soc_component_write_field(component,
2316                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2317                                 WCD938X_TXD0_CLK_EN_MASK, 0);
2318                         break;
2319                 case 1:
2320                         snd_soc_component_write_field(component,
2321                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2322                                 WCD938X_TXD1_MODE_MASK, 0);
2323                         snd_soc_component_write_field(component,
2324                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2325                                 WCD938X_TXD1_CLK_EN_MASK, 0);
2326                         break;
2327                 case 2:
2328                         snd_soc_component_write_field(component,
2329                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2330                                 WCD938X_TXD2_MODE_MASK, 0);
2331                         snd_soc_component_write_field(component,
2332                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2333                                 WCD938X_TXD2_CLK_EN_MASK, 0);
2334                         break;
2335                 case 3:
2336                         snd_soc_component_write_field(component,
2337                                 WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2338                                 WCD938X_TXD3_MODE_MASK, 0);
2339                         snd_soc_component_write_field(component,
2340                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2341                                 WCD938X_TXD3_CLK_EN_MASK, 0);
2342                         break;
2343                 default:
2344                         break;
2345                 }
2346                 snd_soc_component_write_field(component,
2347                                 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2348                                 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0);
2349                 break;
2350         }
2351
2352         return 0;
2353 }
2354
2355 static int wcd938x_micbias_control(struct snd_soc_component *component,
2356                                    int micb_num, int req, bool is_dapm)
2357 {
2358         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2359         int micb_index = micb_num - 1;
2360         u16 micb_reg;
2361
2362         switch (micb_num) {
2363         case MIC_BIAS_1:
2364                 micb_reg = WCD938X_ANA_MICB1;
2365                 break;
2366         case MIC_BIAS_2:
2367                 micb_reg = WCD938X_ANA_MICB2;
2368                 break;
2369         case MIC_BIAS_3:
2370                 micb_reg = WCD938X_ANA_MICB3;
2371                 break;
2372         case MIC_BIAS_4:
2373                 micb_reg = WCD938X_ANA_MICB4;
2374                 break;
2375         default:
2376                 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2377                         __func__, micb_num);
2378                 return -EINVAL;
2379         }
2380
2381         switch (req) {
2382         case MICB_PULLUP_ENABLE:
2383                 wcd938x->pullup_ref[micb_index]++;
2384                 if ((wcd938x->pullup_ref[micb_index] == 1) &&
2385                     (wcd938x->micb_ref[micb_index] == 0))
2386                         snd_soc_component_write_field(component, micb_reg,
2387                                                       WCD938X_MICB_EN_MASK,
2388                                                       WCD938X_MICB_PULL_UP);
2389                 break;
2390         case MICB_PULLUP_DISABLE:
2391                 if (wcd938x->pullup_ref[micb_index] > 0)
2392                         wcd938x->pullup_ref[micb_index]--;
2393
2394                 if ((wcd938x->pullup_ref[micb_index] == 0) &&
2395                     (wcd938x->micb_ref[micb_index] == 0))
2396                         snd_soc_component_write_field(component, micb_reg,
2397                                                       WCD938X_MICB_EN_MASK, 0);
2398                 break;
2399         case MICB_ENABLE:
2400                 wcd938x->micb_ref[micb_index]++;
2401                 if (wcd938x->micb_ref[micb_index] == 1) {
2402                         snd_soc_component_write_field(component,
2403                                 WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2404                                 WCD938X_TX_CLK_EN_MASK, 0xF);
2405                         snd_soc_component_write_field(component,
2406                                 WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2407                                 WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
2408                         snd_soc_component_write_field(component,
2409                                WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL,
2410                                WCD938X_TX_SC_CLK_EN_MASK, 1);
2411
2412                         snd_soc_component_write_field(component, micb_reg,
2413                                                       WCD938X_MICB_EN_MASK,
2414                                                       WCD938X_MICB_ENABLE);
2415                         if (micb_num  == MIC_BIAS_2)
2416                                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2417                                                       WCD_EVENT_POST_MICBIAS_2_ON);
2418                 }
2419                 if (micb_num  == MIC_BIAS_2 && is_dapm)
2420                         wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2421                                               WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
2422
2423
2424                 break;
2425         case MICB_DISABLE:
2426                 if (wcd938x->micb_ref[micb_index] > 0)
2427                         wcd938x->micb_ref[micb_index]--;
2428
2429                 if ((wcd938x->micb_ref[micb_index] == 0) &&
2430                     (wcd938x->pullup_ref[micb_index] > 0))
2431                         snd_soc_component_write_field(component, micb_reg,
2432                                                       WCD938X_MICB_EN_MASK,
2433                                                       WCD938X_MICB_PULL_UP);
2434                 else if ((wcd938x->micb_ref[micb_index] == 0) &&
2435                          (wcd938x->pullup_ref[micb_index] == 0)) {
2436                         if (micb_num  == MIC_BIAS_2)
2437                                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2438                                                       WCD_EVENT_PRE_MICBIAS_2_OFF);
2439
2440                         snd_soc_component_write_field(component, micb_reg,
2441                                                       WCD938X_MICB_EN_MASK, 0);
2442                         if (micb_num  == MIC_BIAS_2)
2443                                 wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2444                                                       WCD_EVENT_POST_MICBIAS_2_OFF);
2445                 }
2446                 if (is_dapm && micb_num  == MIC_BIAS_2)
2447                         wcd_mbhc_event_notify(wcd938x->wcd_mbhc,
2448                                               WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
2449                 break;
2450         }
2451
2452         return 0;
2453 }
2454
2455 static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2456                                         struct snd_kcontrol *kcontrol,
2457                                         int event)
2458 {
2459         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2460         int micb_num = w->shift;
2461
2462         switch (event) {
2463         case SND_SOC_DAPM_PRE_PMU:
2464                 wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true);
2465                 break;
2466         case SND_SOC_DAPM_POST_PMU:
2467                 /* 1 msec delay as per HW requirement */
2468                 usleep_range(1000, 1100);
2469                 break;
2470         case SND_SOC_DAPM_POST_PMD:
2471                 wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true);
2472                 break;
2473         }
2474
2475         return 0;
2476 }
2477
2478 static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
2479                                                struct snd_kcontrol *kcontrol,
2480                                                int event)
2481 {
2482         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2483         int micb_num = w->shift;
2484
2485         switch (event) {
2486         case SND_SOC_DAPM_PRE_PMU:
2487                 wcd938x_micbias_control(component, micb_num,
2488                                         MICB_PULLUP_ENABLE, true);
2489                 break;
2490         case SND_SOC_DAPM_POST_PMU:
2491                 /* 1 msec delay as per HW requirement */
2492                 usleep_range(1000, 1100);
2493                 break;
2494         case SND_SOC_DAPM_POST_PMD:
2495                 wcd938x_micbias_control(component, micb_num,
2496                                         MICB_PULLUP_DISABLE, true);
2497                 break;
2498         }
2499
2500         return 0;
2501 }
2502
2503 static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
2504                                struct snd_ctl_elem_value *ucontrol)
2505 {
2506         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2507         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2508         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2509         int path = e->shift_l;
2510
2511         ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
2512
2513         return 0;
2514 }
2515
2516 static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
2517                                struct snd_ctl_elem_value *ucontrol)
2518 {
2519         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2520         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2521         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2522         int path = e->shift_l;
2523
2524         wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0];
2525
2526         return 1;
2527 }
2528
2529 static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
2530                                  struct snd_ctl_elem_value *ucontrol)
2531 {
2532         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2533         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2534
2535         ucontrol->value.integer.value[0] = wcd938x->hph_mode;
2536
2537         return 0;
2538 }
2539
2540 static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
2541                                    struct snd_ctl_elem_value *ucontrol)
2542 {
2543         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2544         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2545
2546         wcd938x->hph_mode = ucontrol->value.enumerated.item[0];
2547
2548         return 1;
2549 }
2550
2551 static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
2552                                    struct snd_ctl_elem_value *ucontrol)
2553 {
2554         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2555         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2556
2557         if (wcd938x->comp1_enable) {
2558                 dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
2559                 return -EINVAL;
2560         }
2561
2562         snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
2563                                       WCD938X_EAR_GAIN_MASK,
2564                                       ucontrol->value.integer.value[0]);
2565
2566         return 0;
2567 }
2568
2569 static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
2570                                  struct snd_ctl_elem_value *ucontrol)
2571 {
2572
2573         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2574         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2575         struct soc_mixer_control *mc;
2576         bool hphr;
2577
2578         mc = (struct soc_mixer_control *)(kcontrol->private_value);
2579         hphr = mc->shift;
2580
2581         if (hphr)
2582                 ucontrol->value.integer.value[0] = wcd938x->comp2_enable;
2583         else
2584                 ucontrol->value.integer.value[0] = wcd938x->comp1_enable;
2585
2586         return 0;
2587 }
2588
2589 static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
2590                                  struct snd_ctl_elem_value *ucontrol)
2591 {
2592         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2593         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2594         struct wcd938x_sdw_priv *wcd;
2595         int value = ucontrol->value.integer.value[0];
2596         struct soc_mixer_control *mc;
2597         bool hphr;
2598
2599         mc = (struct soc_mixer_control *)(kcontrol->private_value);
2600         hphr = mc->shift;
2601
2602         wcd = wcd938x->sdw_priv[AIF1_PB];
2603
2604         if (hphr)
2605                 wcd938x->comp2_enable = value;
2606         else
2607                 wcd938x->comp1_enable = value;
2608
2609         if (value)
2610                 wcd938x_connect_port(wcd, mc->reg, true);
2611         else
2612                 wcd938x_connect_port(wcd, mc->reg, false);
2613
2614         return 0;
2615 }
2616
2617 static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
2618                             struct snd_ctl_elem_value *ucontrol)
2619 {
2620         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2621         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2622
2623         ucontrol->value.integer.value[0] = wcd938x->ldoh;
2624
2625         return 0;
2626 }
2627
2628 static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
2629                             struct snd_ctl_elem_value *ucontrol)
2630 {
2631         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2632         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2633
2634         wcd938x->ldoh = ucontrol->value.integer.value[0];
2635
2636         return 1;
2637 }
2638
2639 static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
2640                            struct snd_ctl_elem_value *ucontrol)
2641 {
2642         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2643         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2644
2645         ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
2646
2647         return 0;
2648 }
2649
2650 static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
2651                            struct snd_ctl_elem_value *ucontrol)
2652 {
2653         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2654         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2655
2656         wcd938x->bcs_dis = ucontrol->value.integer.value[0];
2657
2658         return 1;
2659 }
2660
2661 static const char * const tx_mode_mux_text_wcd9380[] = {
2662         "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2663 };
2664
2665 static const char * const tx_mode_mux_text[] = {
2666         "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2667         "ADC_ULP1", "ADC_ULP2",
2668 };
2669
2670 static const char * const rx_hph_mode_mux_text_wcd9380[] = {
2671         "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
2672         "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
2673         "CLS_AB_LOHIFI",
2674 };
2675
2676 static const char * const rx_hph_mode_mux_text[] = {
2677         "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
2678         "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
2679 };
2680
2681 static const char * const adc2_mux_text[] = {
2682         "INP2", "INP3"
2683 };
2684
2685 static const char * const adc3_mux_text[] = {
2686         "INP4", "INP6"
2687 };
2688
2689 static const char * const adc4_mux_text[] = {
2690         "INP5", "INP7"
2691 };
2692
2693 static const char * const rdac3_mux_text[] = {
2694         "RX1", "RX3"
2695 };
2696
2697 static const char * const hdr12_mux_text[] = {
2698         "NO_HDR12", "HDR12"
2699 };
2700
2701 static const char * const hdr34_mux_text[] = {
2702         "NO_HDR34", "HDR34"
2703 };
2704
2705 static const struct soc_enum tx0_mode_enum_wcd9380 =
2706         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2707                         tx_mode_mux_text_wcd9380);
2708
2709 static const struct soc_enum tx1_mode_enum_wcd9380 =
2710         SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2711                         tx_mode_mux_text_wcd9380);
2712
2713 static const struct soc_enum tx2_mode_enum_wcd9380 =
2714         SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2715                         tx_mode_mux_text_wcd9380);
2716
2717 static const struct soc_enum tx3_mode_enum_wcd9380 =
2718         SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2719                         tx_mode_mux_text_wcd9380);
2720
2721 static const struct soc_enum tx0_mode_enum_wcd9385 =
2722         SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
2723                         tx_mode_mux_text);
2724
2725 static const struct soc_enum tx1_mode_enum_wcd9385 =
2726         SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
2727                         tx_mode_mux_text);
2728
2729 static const struct soc_enum tx2_mode_enum_wcd9385 =
2730         SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
2731                         tx_mode_mux_text);
2732
2733 static const struct soc_enum tx3_mode_enum_wcd9385 =
2734         SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
2735                         tx_mode_mux_text);
2736
2737 static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
2738                 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
2739                                     rx_hph_mode_mux_text_wcd9380);
2740
2741 static const struct soc_enum rx_hph_mode_mux_enum =
2742                 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
2743                                     rx_hph_mode_mux_text);
2744
2745 static const struct soc_enum adc2_enum =
2746                 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
2747                                 ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
2748
2749 static const struct soc_enum adc3_enum =
2750                 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
2751                                 ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
2752
2753 static const struct soc_enum adc4_enum =
2754                 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
2755                                 ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
2756
2757 static const struct soc_enum hdr12_enum =
2758                 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
2759                                 ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
2760
2761 static const struct soc_enum hdr34_enum =
2762                 SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
2763                                 ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
2764
2765 static const struct soc_enum rdac3_enum =
2766                 SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
2767                                 ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
2768
2769 static const struct snd_kcontrol_new adc1_switch[] = {
2770         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2771 };
2772
2773 static const struct snd_kcontrol_new adc2_switch[] = {
2774         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2775 };
2776
2777 static const struct snd_kcontrol_new adc3_switch[] = {
2778         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2779 };
2780
2781 static const struct snd_kcontrol_new adc4_switch[] = {
2782         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2783 };
2784
2785 static const struct snd_kcontrol_new dmic1_switch[] = {
2786         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2787 };
2788
2789 static const struct snd_kcontrol_new dmic2_switch[] = {
2790         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2791 };
2792
2793 static const struct snd_kcontrol_new dmic3_switch[] = {
2794         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2795 };
2796
2797 static const struct snd_kcontrol_new dmic4_switch[] = {
2798         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2799 };
2800
2801 static const struct snd_kcontrol_new dmic5_switch[] = {
2802         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2803 };
2804
2805 static const struct snd_kcontrol_new dmic6_switch[] = {
2806         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2807 };
2808
2809 static const struct snd_kcontrol_new dmic7_switch[] = {
2810         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2811 };
2812
2813 static const struct snd_kcontrol_new dmic8_switch[] = {
2814         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2815 };
2816
2817 static const struct snd_kcontrol_new ear_rdac_switch[] = {
2818         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2819 };
2820
2821 static const struct snd_kcontrol_new aux_rdac_switch[] = {
2822         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2823 };
2824
2825 static const struct snd_kcontrol_new hphl_rdac_switch[] = {
2826         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2827 };
2828
2829 static const struct snd_kcontrol_new hphr_rdac_switch[] = {
2830         SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2831 };
2832
2833 static const struct snd_kcontrol_new tx_adc2_mux =
2834         SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
2835
2836 static const struct snd_kcontrol_new tx_adc3_mux =
2837         SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
2838
2839 static const struct snd_kcontrol_new tx_adc4_mux =
2840         SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
2841
2842 static const struct snd_kcontrol_new tx_hdr12_mux =
2843         SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
2844
2845 static const struct snd_kcontrol_new tx_hdr34_mux =
2846         SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
2847
2848 static const struct snd_kcontrol_new rx_rdac3_mux =
2849         SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
2850
2851 static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
2852         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
2853                      wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2854         SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380,
2855                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2856         SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380,
2857                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2858         SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380,
2859                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2860         SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380,
2861                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2862 };
2863
2864 static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
2865         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2866                      wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2867         SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385,
2868                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2869         SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385,
2870                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2871         SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385,
2872                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2873         SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385,
2874                      wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2875 };
2876
2877 static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol,
2878                             struct snd_ctl_elem_value *ucontrol)
2879 {
2880         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2881         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2882         struct wcd938x_sdw_priv *wcd;
2883         struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
2884         int dai_id = mixer->shift;
2885         int portidx = mixer->reg;
2886
2887         wcd = wcd938x->sdw_priv[dai_id];
2888
2889         ucontrol->value.integer.value[0] = wcd->port_enable[portidx];
2890
2891         return 0;
2892 }
2893
2894 static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol,
2895                             struct snd_ctl_elem_value *ucontrol)
2896 {
2897         struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2898         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2899         struct wcd938x_sdw_priv *wcd;
2900         struct soc_mixer_control *mixer =
2901                 (struct soc_mixer_control *)kcontrol->private_value;
2902         int portidx = mixer->reg;
2903         int dai_id = mixer->shift;
2904         bool enable;
2905
2906         wcd = wcd938x->sdw_priv[dai_id];
2907
2908         if (ucontrol->value.integer.value[0])
2909                 enable = true;
2910         else
2911                 enable = false;
2912
2913         wcd->port_enable[portidx] = enable;
2914
2915         wcd938x_connect_port(wcd, portidx, enable);
2916
2917         return 0;
2918
2919 }
2920
2921 /* MBHC related */
2922 static void wcd938x_mbhc_clk_setup(struct snd_soc_component *component,
2923                                    bool enable)
2924 {
2925         snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_1,
2926                                       WCD938X_MBHC_CTL_RCO_EN_MASK, enable);
2927 }
2928
2929 static void wcd938x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
2930                                            bool enable)
2931 {
2932         snd_soc_component_write_field(component, WCD938X_ANA_MBHC_ELECT,
2933                                       WCD938X_ANA_MBHC_BIAS_EN, enable);
2934 }
2935
2936 static void wcd938x_mbhc_program_btn_thr(struct snd_soc_component *component,
2937                                          int *btn_low, int *btn_high,
2938                                          int num_btn, bool is_micbias)
2939 {
2940         int i, vth;
2941
2942         if (num_btn > WCD_MBHC_DEF_BUTTONS) {
2943                 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
2944                         __func__, num_btn);
2945                 return;
2946         }
2947
2948         for (i = 0; i < num_btn; i++) {
2949                 vth = ((btn_high[i] * 2) / 25) & 0x3F;
2950                 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_BTN0 + i,
2951                                            WCD938X_MBHC_BTN_VTH_MASK, vth);
2952                 dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
2953                         __func__, i, btn_high[i], vth);
2954         }
2955 }
2956
2957 static bool wcd938x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
2958 {
2959         u8 val;
2960
2961         if (micb_num == MIC_BIAS_2) {
2962                 val = snd_soc_component_read_field(component,
2963                                                    WCD938X_ANA_MICB2,
2964                                                    WCD938X_ANA_MICB2_ENABLE_MASK);
2965                 if (val == WCD938X_MICB_ENABLE)
2966                         return true;
2967         }
2968         return false;
2969 }
2970
2971 static void wcd938x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
2972                                                         int pull_up_cur)
2973 {
2974         /* Default pull up current to 2uA */
2975         if (pull_up_cur > HS_PULLUP_I_OFF || pull_up_cur < HS_PULLUP_I_3P0_UA)
2976                 pull_up_cur = HS_PULLUP_I_2P0_UA;
2977
2978         snd_soc_component_write_field(component,
2979                                       WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT,
2980                                       WCD938X_HSDET_PULLUP_C_MASK, pull_up_cur);
2981 }
2982
2983 static int wcd938x_mbhc_request_micbias(struct snd_soc_component *component,
2984                                         int micb_num, int req)
2985 {
2986         return wcd938x_micbias_control(component, micb_num, req, false);
2987 }
2988
2989 static void wcd938x_mbhc_micb_ramp_control(struct snd_soc_component *component,
2990                                            bool enable)
2991 {
2992         if (enable) {
2993                 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
2994                                     WCD938X_RAMP_SHIFT_CTRL_MASK, 0x0C);
2995                 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
2996                                     WCD938X_RAMP_EN_MASK, 1);
2997         } else {
2998                 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
2999                                     WCD938X_RAMP_EN_MASK, 0);
3000                 snd_soc_component_write_field(component, WCD938X_ANA_MICB2_RAMP,
3001                                     WCD938X_RAMP_SHIFT_CTRL_MASK, 0);
3002         }
3003 }
3004
3005 static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
3006 {
3007         /* min micbias voltage is 1V and maximum is 2.85V */
3008         if (micb_mv < 1000 || micb_mv > 2850)
3009                 return -EINVAL;
3010
3011         return (micb_mv - 1000) / 50;
3012 }
3013
3014 static int wcd938x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
3015                                             int req_volt, int micb_num)
3016 {
3017         struct wcd938x_priv *wcd938x =  snd_soc_component_get_drvdata(component);
3018         int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
3019
3020         switch (micb_num) {
3021         case MIC_BIAS_1:
3022                 micb_reg = WCD938X_ANA_MICB1;
3023                 break;
3024         case MIC_BIAS_2:
3025                 micb_reg = WCD938X_ANA_MICB2;
3026                 break;
3027         case MIC_BIAS_3:
3028                 micb_reg = WCD938X_ANA_MICB3;
3029                 break;
3030         case MIC_BIAS_4:
3031                 micb_reg = WCD938X_ANA_MICB4;
3032                 break;
3033         default:
3034                 return -EINVAL;
3035         }
3036         mutex_lock(&wcd938x->micb_lock);
3037         /*
3038          * If requested micbias voltage is same as current micbias
3039          * voltage, then just return. Otherwise, adjust voltage as
3040          * per requested value. If micbias is already enabled, then
3041          * to avoid slow micbias ramp-up or down enable pull-up
3042          * momentarily, change the micbias value and then re-enable
3043          * micbias.
3044          */
3045         micb_en = snd_soc_component_read_field(component, micb_reg,
3046                                                 WCD938X_MICB_EN_MASK);
3047         cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
3048                                                     WCD938X_MICB_VOUT_MASK);
3049
3050         req_vout_ctl = wcd938x_get_micb_vout_ctl_val(req_volt);
3051         if (req_vout_ctl < 0) {
3052                 ret = -EINVAL;
3053                 goto exit;
3054         }
3055
3056         if (cur_vout_ctl == req_vout_ctl) {
3057                 ret = 0;
3058                 goto exit;
3059         }
3060
3061         if (micb_en == WCD938X_MICB_ENABLE)
3062                 snd_soc_component_write_field(component, micb_reg,
3063                                               WCD938X_MICB_EN_MASK,
3064                                               WCD938X_MICB_PULL_UP);
3065
3066         snd_soc_component_write_field(component, micb_reg,
3067                                       WCD938X_MICB_VOUT_MASK,
3068                                       req_vout_ctl);
3069
3070         if (micb_en == WCD938X_MICB_ENABLE) {
3071                 snd_soc_component_write_field(component, micb_reg,
3072                                               WCD938X_MICB_EN_MASK,
3073                                               WCD938X_MICB_ENABLE);
3074                 /*
3075                  * Add 2ms delay as per HW requirement after enabling
3076                  * micbias
3077                  */
3078                 usleep_range(2000, 2100);
3079         }
3080 exit:
3081         mutex_unlock(&wcd938x->micb_lock);
3082         return ret;
3083 }
3084
3085 static int wcd938x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
3086                                                 int micb_num, bool req_en)
3087 {
3088         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3089         int micb_mv;
3090
3091         if (micb_num != MIC_BIAS_2)
3092                 return -EINVAL;
3093         /*
3094          * If device tree micbias level is already above the minimum
3095          * voltage needed to detect threshold microphone, then do
3096          * not change the micbias, just return.
3097          */
3098         if (wcd938x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
3099                 return 0;
3100
3101         micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd938x->micb2_mv;
3102
3103         return wcd938x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
3104 }
3105
3106 static inline void wcd938x_mbhc_get_result_params(struct wcd938x_priv *wcd938x,
3107                                                 s16 *d1_a, u16 noff,
3108                                                 int32_t *zdet)
3109 {
3110         int i;
3111         int val, val1;
3112         s16 c1;
3113         s32 x1, d1;
3114         int32_t denom;
3115         int minCode_param[] = {
3116                         3277, 1639, 820, 410, 205, 103, 52, 26
3117         };
3118
3119         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x20);
3120         for (i = 0; i < WCD938X_ZDET_NUM_MEASUREMENTS; i++) {
3121                 regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_2, &val);
3122                 if (val & 0x80)
3123                         break;
3124         }
3125         val = val << 0x8;
3126         regmap_read(wcd938x->regmap, WCD938X_ANA_MBHC_RESULT_1, &val1);
3127         val |= val1;
3128         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MBHC_ZDET, 0x20, 0x00);
3129         x1 = WCD938X_MBHC_GET_X1(val);
3130         c1 = WCD938X_MBHC_GET_C1(val);
3131         /* If ramp is not complete, give additional 5ms */
3132         if ((c1 < 2) && x1)
3133                 usleep_range(5000, 5050);
3134
3135         if (!c1 || !x1) {
3136                 pr_err("%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
3137                         __func__, c1, x1);
3138                 goto ramp_down;
3139         }
3140         d1 = d1_a[c1];
3141         denom = (x1 * d1) - (1 << (14 - noff));
3142         if (denom > 0)
3143                 *zdet = (WCD938X_MBHC_ZDET_CONST * 1000) / denom;
3144         else if (x1 < minCode_param[noff])
3145                 *zdet = WCD938X_ZDET_FLOATING_IMPEDANCE;
3146
3147         pr_err("%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
3148                 __func__, d1, c1, x1, *zdet);
3149 ramp_down:
3150         i = 0;
3151         while (x1) {
3152                 regmap_read(wcd938x->regmap,
3153                                  WCD938X_ANA_MBHC_RESULT_1, &val);
3154                 regmap_read(wcd938x->regmap,
3155                                  WCD938X_ANA_MBHC_RESULT_2, &val1);
3156                 val = val << 0x08;
3157                 val |= val1;
3158                 x1 = WCD938X_MBHC_GET_X1(val);
3159                 i++;
3160                 if (i == WCD938X_ZDET_NUM_MEASUREMENTS)
3161                         break;
3162         }
3163 }
3164
3165 static void wcd938x_mbhc_zdet_ramp(struct snd_soc_component *component,
3166                                  struct wcd938x_mbhc_zdet_param *zdet_param,
3167                                  int32_t *zl, int32_t *zr, s16 *d1_a)
3168 {
3169         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3170         int32_t zdet = 0;
3171
3172         snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
3173                                 WCD938X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
3174         snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN5,
3175                                     WCD938X_VTH_MASK, zdet_param->btn5);
3176         snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN6,
3177                                       WCD938X_VTH_MASK, zdet_param->btn6);
3178         snd_soc_component_update_bits(component, WCD938X_ANA_MBHC_BTN7,
3179                                      WCD938X_VTH_MASK, zdet_param->btn7);
3180         snd_soc_component_write_field(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL,
3181                                 WCD938X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
3182         snd_soc_component_update_bits(component, WCD938X_MBHC_NEW_ZDET_RAMP_CTL,
3183                                 0x0F, zdet_param->nshift);
3184
3185         if (!zl)
3186                 goto z_right;
3187         /* Start impedance measurement for HPH_L */
3188         regmap_update_bits(wcd938x->regmap,
3189                            WCD938X_ANA_MBHC_ZDET, 0x80, 0x80);
3190         dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n",
3191                 __func__, zdet_param->noff);
3192         wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet);
3193         regmap_update_bits(wcd938x->regmap,
3194                            WCD938X_ANA_MBHC_ZDET, 0x80, 0x00);
3195
3196         *zl = zdet;
3197
3198 z_right:
3199         if (!zr)
3200                 return;
3201         /* Start impedance measurement for HPH_R */
3202         regmap_update_bits(wcd938x->regmap,
3203                            WCD938X_ANA_MBHC_ZDET, 0x40, 0x40);
3204         dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n",
3205                 __func__, zdet_param->noff);
3206         wcd938x_mbhc_get_result_params(wcd938x, d1_a, zdet_param->noff, &zdet);
3207         regmap_update_bits(wcd938x->regmap,
3208                            WCD938X_ANA_MBHC_ZDET, 0x40, 0x00);
3209
3210         *zr = zdet;
3211 }
3212
3213 static inline void wcd938x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
3214                                               int32_t *z_val, int flag_l_r)
3215 {
3216         s16 q1;
3217         int q1_cal;
3218
3219         if (*z_val < (WCD938X_ZDET_VAL_400/1000))
3220                 q1 = snd_soc_component_read(component,
3221                         WCD938X_DIGITAL_EFUSE_REG_23 + (2 * flag_l_r));
3222         else
3223                 q1 = snd_soc_component_read(component,
3224                         WCD938X_DIGITAL_EFUSE_REG_24 + (2 * flag_l_r));
3225         if (q1 & 0x80)
3226                 q1_cal = (10000 - ((q1 & 0x7F) * 25));
3227         else
3228                 q1_cal = (10000 + (q1 * 25));
3229         if (q1_cal > 0)
3230                 *z_val = ((*z_val) * 10000) / q1_cal;
3231 }
3232
3233 static void wcd938x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
3234                                             uint32_t *zl, uint32_t *zr)
3235 {
3236         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3237         s16 reg0, reg1, reg2, reg3, reg4;
3238         int32_t z1L, z1R, z1Ls;
3239         int zMono, z_diff1, z_diff2;
3240         bool is_fsm_disable = false;
3241         struct wcd938x_mbhc_zdet_param zdet_param[] = {
3242                 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
3243                 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
3244                 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
3245                 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
3246         };
3247         struct wcd938x_mbhc_zdet_param *zdet_param_ptr = NULL;
3248         s16 d1_a[][4] = {
3249                 {0, 30, 90, 30},
3250                 {0, 30, 30, 5},
3251                 {0, 30, 30, 5},
3252                 {0, 30, 30, 5},
3253         };
3254         s16 *d1 = NULL;
3255
3256         reg0 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN5);
3257         reg1 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN6);
3258         reg2 = snd_soc_component_read(component, WCD938X_ANA_MBHC_BTN7);
3259         reg3 = snd_soc_component_read(component, WCD938X_MBHC_CTL_CLK);
3260         reg4 = snd_soc_component_read(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL);
3261
3262         if (snd_soc_component_read(component, WCD938X_ANA_MBHC_ELECT) & 0x80) {
3263                 is_fsm_disable = true;
3264                 regmap_update_bits(wcd938x->regmap,
3265                                    WCD938X_ANA_MBHC_ELECT, 0x80, 0x00);
3266         }
3267
3268         /* For NO-jack, disable L_DET_EN before Z-det measurements */
3269         if (wcd938x->mbhc_cfg.hphl_swh)
3270                 regmap_update_bits(wcd938x->regmap,
3271                                    WCD938X_ANA_MBHC_MECH, 0x80, 0x00);
3272
3273         /* Turn off 100k pull down on HPHL */
3274         regmap_update_bits(wcd938x->regmap,
3275                            WCD938X_ANA_MBHC_MECH, 0x01, 0x00);
3276
3277         /* Disable surge protection before impedance detection.
3278          * This is done to give correct value for high impedance.
3279          */
3280         regmap_update_bits(wcd938x->regmap,
3281                            WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0x00);
3282         /* 1ms delay needed after disable surge protection */
3283         usleep_range(1000, 1010);
3284
3285         /* First get impedance on Left */
3286         d1 = d1_a[1];
3287         zdet_param_ptr = &zdet_param[1];
3288         wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
3289
3290         if (!WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
3291                 goto left_ch_impedance;
3292
3293         /* Second ramp for left ch */
3294         if (z1L < WCD938X_ZDET_VAL_32) {
3295                 zdet_param_ptr = &zdet_param[0];
3296                 d1 = d1_a[0];
3297         } else if ((z1L > WCD938X_ZDET_VAL_400) &&
3298                   (z1L <= WCD938X_ZDET_VAL_1200)) {
3299                 zdet_param_ptr = &zdet_param[2];
3300                 d1 = d1_a[2];
3301         } else if (z1L > WCD938X_ZDET_VAL_1200) {
3302                 zdet_param_ptr = &zdet_param[3];
3303                 d1 = d1_a[3];
3304         }
3305         wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
3306
3307 left_ch_impedance:
3308         if ((z1L == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3309                 (z1L > WCD938X_ZDET_VAL_100K)) {
3310                 *zl = WCD938X_ZDET_FLOATING_IMPEDANCE;
3311                 zdet_param_ptr = &zdet_param[1];
3312                 d1 = d1_a[1];
3313         } else {
3314                 *zl = z1L/1000;
3315                 wcd938x_wcd_mbhc_qfuse_cal(component, zl, 0);
3316         }
3317         dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
3318                 __func__, *zl);
3319
3320         /* Start of right impedance ramp and calculation */
3321         wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
3322         if (WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
3323                 if (((z1R > WCD938X_ZDET_VAL_1200) &&
3324                         (zdet_param_ptr->noff == 0x6)) ||
3325                         ((*zl) != WCD938X_ZDET_FLOATING_IMPEDANCE))
3326                         goto right_ch_impedance;
3327                 /* Second ramp for right ch */
3328                 if (z1R < WCD938X_ZDET_VAL_32) {
3329                         zdet_param_ptr = &zdet_param[0];
3330                         d1 = d1_a[0];
3331                 } else if ((z1R > WCD938X_ZDET_VAL_400) &&
3332                         (z1R <= WCD938X_ZDET_VAL_1200)) {
3333                         zdet_param_ptr = &zdet_param[2];
3334                         d1 = d1_a[2];
3335                 } else if (z1R > WCD938X_ZDET_VAL_1200) {
3336                         zdet_param_ptr = &zdet_param[3];
3337                         d1 = d1_a[3];
3338                 }
3339                 wcd938x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
3340         }
3341 right_ch_impedance:
3342         if ((z1R == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3343                 (z1R > WCD938X_ZDET_VAL_100K)) {
3344                 *zr = WCD938X_ZDET_FLOATING_IMPEDANCE;
3345         } else {
3346                 *zr = z1R/1000;
3347                 wcd938x_wcd_mbhc_qfuse_cal(component, zr, 1);
3348         }
3349         dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
3350                 __func__, *zr);
3351
3352         /* Mono/stereo detection */
3353         if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) &&
3354                 (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE)) {
3355                 dev_dbg(component->dev,
3356                         "%s: plug type is invalid or extension cable\n",
3357                         __func__);
3358                 goto zdet_complete;
3359         }
3360         if ((*zl == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3361             (*zr == WCD938X_ZDET_FLOATING_IMPEDANCE) ||
3362             ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
3363             ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
3364                 dev_dbg(component->dev,
3365                         "%s: Mono plug type with one ch floating or shorted to GND\n",
3366                         __func__);
3367                 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
3368                 goto zdet_complete;
3369         }
3370         snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
3371                                       WCD938X_HPHPA_GND_OVR_MASK, 1);
3372         snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3373                                       WCD938X_HPHPA_GND_R_MASK, 1);
3374         if (*zl < (WCD938X_ZDET_VAL_32/1000))
3375                 wcd938x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
3376         else
3377                 wcd938x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
3378         snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3379                                       WCD938X_HPHPA_GND_R_MASK, 0);
3380         snd_soc_component_write_field(component, WCD938X_HPH_R_ATEST,
3381                                       WCD938X_HPHPA_GND_OVR_MASK, 0);
3382         z1Ls /= 1000;
3383         wcd938x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
3384         /* Parallel of left Z and 9 ohm pull down resistor */
3385         zMono = ((*zl) * 9) / ((*zl) + 9);
3386         z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
3387         z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
3388         if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
3389                 dev_dbg(component->dev, "%s: stereo plug type detected\n",
3390                         __func__);
3391                 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
3392         } else {
3393                 dev_dbg(component->dev, "%s: MONO plug type detected\n",
3394                         __func__);
3395                 wcd_mbhc_set_hph_type(wcd938x->wcd_mbhc, WCD_MBHC_HPH_MONO);
3396         }
3397
3398         /* Enable surge protection again after impedance detection */
3399         regmap_update_bits(wcd938x->regmap,
3400                            WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
3401 zdet_complete:
3402         snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN5, reg0);
3403         snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN6, reg1);
3404         snd_soc_component_write(component, WCD938X_ANA_MBHC_BTN7, reg2);
3405         /* Turn on 100k pull down on HPHL */
3406         regmap_update_bits(wcd938x->regmap,
3407                            WCD938X_ANA_MBHC_MECH, 0x01, 0x01);
3408
3409         /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
3410         if (wcd938x->mbhc_cfg.hphl_swh)
3411                 regmap_update_bits(wcd938x->regmap,
3412                                    WCD938X_ANA_MBHC_MECH, 0x80, 0x80);
3413
3414         snd_soc_component_write(component, WCD938X_MBHC_NEW_ZDET_ANA_CTL, reg4);
3415         snd_soc_component_write(component, WCD938X_MBHC_CTL_CLK, reg3);
3416         if (is_fsm_disable)
3417                 regmap_update_bits(wcd938x->regmap,
3418                                    WCD938X_ANA_MBHC_ELECT, 0x80, 0x80);
3419 }
3420
3421 static void wcd938x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
3422                         bool enable)
3423 {
3424         if (enable) {
3425                 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3426                                               WCD938X_MBHC_HSG_PULLUP_COMP_EN, 1);
3427                 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3428                                               WCD938X_MBHC_GND_DET_EN_MASK, 1);
3429         } else {
3430                 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3431                                               WCD938X_MBHC_GND_DET_EN_MASK, 0);
3432                 snd_soc_component_write_field(component, WCD938X_ANA_MBHC_MECH,
3433                                               WCD938X_MBHC_HSG_PULLUP_COMP_EN, 0);
3434         }
3435 }
3436
3437 static void wcd938x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
3438                                           bool enable)
3439 {
3440         snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3441                                       WCD938X_HPHPA_GND_R_MASK, enable);
3442         snd_soc_component_write_field(component, WCD938X_HPH_PA_CTL2,
3443                                       WCD938X_HPHPA_GND_L_MASK, enable);
3444 }
3445
3446 static void wcd938x_mbhc_moisture_config(struct snd_soc_component *component)
3447 {
3448         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3449
3450         if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
3451                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3452                                     WCD938X_M_RTH_CTL_MASK, R_OFF);
3453                 return;
3454         }
3455
3456         /* Do not enable moisture detection if jack type is NC */
3457         if (!wcd938x->mbhc_cfg.hphl_swh) {
3458                 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
3459                         __func__);
3460                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3461                                     WCD938X_M_RTH_CTL_MASK, R_OFF);
3462                 return;
3463         }
3464
3465         snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3466                             WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
3467 }
3468
3469 static void wcd938x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
3470 {
3471         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3472
3473         if (enable)
3474                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3475                                         WCD938X_M_RTH_CTL_MASK, wcd938x->mbhc_cfg.moist_rref);
3476         else
3477                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3478                                     WCD938X_M_RTH_CTL_MASK, R_OFF);
3479 }
3480
3481 static bool wcd938x_mbhc_get_moisture_status(struct snd_soc_component *component)
3482 {
3483         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3484         bool ret = false;
3485
3486         if (wcd938x->mbhc_cfg.moist_rref == R_OFF) {
3487                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3488                                     WCD938X_M_RTH_CTL_MASK, R_OFF);
3489                 goto done;
3490         }
3491
3492         /* Do not enable moisture detection if jack type is NC */
3493         if (!wcd938x->mbhc_cfg.hphl_swh) {
3494                 dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
3495                         __func__);
3496                 snd_soc_component_write_field(component, WCD938X_MBHC_NEW_CTL_2,
3497                                     WCD938X_M_RTH_CTL_MASK, R_OFF);
3498                 goto done;
3499         }
3500
3501         /*
3502          * If moisture_en is already enabled, then skip to plug type
3503          * detection.
3504          */
3505         if (snd_soc_component_read_field(component, WCD938X_MBHC_NEW_CTL_2, WCD938X_M_RTH_CTL_MASK))
3506                 goto done;
3507
3508         wcd938x_mbhc_moisture_detect_en(component, true);
3509         /* Read moisture comparator status */
3510         ret = ((snd_soc_component_read(component, WCD938X_MBHC_NEW_FSM_STATUS)
3511                                 & 0x20) ? 0 : 1);
3512
3513 done:
3514         return ret;
3515
3516 }
3517
3518 static void wcd938x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
3519                                                 bool enable)
3520 {
3521         snd_soc_component_write_field(component,
3522                               WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
3523                               WCD938X_MOISTURE_EN_POLLING_MASK, enable);
3524 }
3525
3526 static const struct wcd_mbhc_cb mbhc_cb = {
3527         .clk_setup = wcd938x_mbhc_clk_setup,
3528         .mbhc_bias = wcd938x_mbhc_mbhc_bias_control,
3529         .set_btn_thr = wcd938x_mbhc_program_btn_thr,
3530         .micbias_enable_status = wcd938x_mbhc_micb_en_status,
3531         .hph_pull_up_control_v2 = wcd938x_mbhc_hph_l_pull_up_control,
3532         .mbhc_micbias_control = wcd938x_mbhc_request_micbias,
3533         .mbhc_micb_ramp_control = wcd938x_mbhc_micb_ramp_control,
3534         .mbhc_micb_ctrl_thr_mic = wcd938x_mbhc_micb_ctrl_threshold_mic,
3535         .compute_impedance = wcd938x_wcd_mbhc_calc_impedance,
3536         .mbhc_gnd_det_ctrl = wcd938x_mbhc_gnd_det_ctrl,
3537         .hph_pull_down_ctrl = wcd938x_mbhc_hph_pull_down_ctrl,
3538         .mbhc_moisture_config = wcd938x_mbhc_moisture_config,
3539         .mbhc_get_moisture_status = wcd938x_mbhc_get_moisture_status,
3540         .mbhc_moisture_polling_ctrl = wcd938x_mbhc_moisture_polling_ctrl,
3541         .mbhc_moisture_detect_en = wcd938x_mbhc_moisture_detect_en,
3542 };
3543
3544 static int wcd938x_get_hph_type(struct snd_kcontrol *kcontrol,
3545                               struct snd_ctl_elem_value *ucontrol)
3546 {
3547         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
3548         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3549
3550         ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd938x->wcd_mbhc);
3551
3552         return 0;
3553 }
3554
3555 static int wcd938x_hph_impedance_get(struct snd_kcontrol *kcontrol,
3556                                    struct snd_ctl_elem_value *ucontrol)
3557 {
3558         uint32_t zl, zr;
3559         bool hphr;
3560         struct soc_mixer_control *mc;
3561         struct snd_soc_component *component =
3562                                         snd_soc_kcontrol_component(kcontrol);
3563         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3564
3565         mc = (struct soc_mixer_control *)(kcontrol->private_value);
3566         hphr = mc->shift;
3567         wcd_mbhc_get_impedance(wcd938x->wcd_mbhc, &zl, &zr);
3568         dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
3569         ucontrol->value.integer.value[0] = hphr ? zr : zl;
3570
3571         return 0;
3572 }
3573
3574 static const struct snd_kcontrol_new hph_type_detect_controls[] = {
3575         SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0,
3576                        wcd938x_get_hph_type, NULL),
3577 };
3578
3579 static const struct snd_kcontrol_new impedance_detect_controls[] = {
3580         SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
3581                        wcd938x_hph_impedance_get, NULL),
3582         SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
3583                        wcd938x_hph_impedance_get, NULL),
3584 };
3585
3586 static int wcd938x_mbhc_init(struct snd_soc_component *component)
3587 {
3588         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3589         struct wcd_mbhc_intr *intr_ids = &wcd938x->intr_ids;
3590
3591         intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3592                                                     WCD938X_IRQ_MBHC_SW_DET);
3593         intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3594                                                            WCD938X_IRQ_MBHC_BUTTON_PRESS_DET);
3595         intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3596                                                              WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET);
3597         intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3598                                                         WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
3599         intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd938x->irq_chip,
3600                                                         WCD938X_IRQ_MBHC_ELECT_INS_REM_DET);
3601         intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
3602                                                     WCD938X_IRQ_HPHL_OCP_INT);
3603         intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd938x->irq_chip,
3604                                                      WCD938X_IRQ_HPHR_OCP_INT);
3605
3606         wcd938x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
3607
3608         snd_soc_add_component_controls(component, impedance_detect_controls,
3609                                        ARRAY_SIZE(impedance_detect_controls));
3610         snd_soc_add_component_controls(component, hph_type_detect_controls,
3611                                        ARRAY_SIZE(hph_type_detect_controls));
3612
3613         return 0;
3614 }
3615 /* END MBHC */
3616
3617 static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
3618         SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0,
3619                        wcd938x_get_compander, wcd938x_set_compander),
3620         SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0,
3621                        wcd938x_get_compander, wcd938x_set_compander),
3622         SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0,
3623                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3624         SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0,
3625                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3626         SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0,
3627                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3628         SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0,
3629                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3630         SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0,
3631                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3632         SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0,
3633                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3634         SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 0, line_gain),
3635         SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 0, line_gain),
3636         WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL,
3637                                 2, 0x10, 0, ear_pa_gain),
3638         SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0,
3639                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3640         SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0,
3641                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3642         SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0,
3643                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3644         SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0,
3645                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3646         SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0,
3647                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3648         SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0,
3649                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3650         SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0,
3651                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3652         SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0,
3653                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3654         SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0,
3655                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3656         SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0,
3657                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3658         SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0,
3659                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3660         SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0,
3661                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3662         SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0,
3663                        wcd938x_get_swr_port, wcd938x_set_swr_port),
3664         SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
3665                        wcd938x_ldoh_get, wcd938x_ldoh_put),
3666         SOC_SINGLE_EXT("ADC2_BCS Disable Switch", SND_SOC_NOPM, 0, 1, 0,
3667                        wcd938x_bcs_get, wcd938x_bcs_put),
3668
3669         SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain),
3670         SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain),
3671         SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain),
3672         SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain),
3673 };
3674
3675 static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
3676
3677         /*input widgets*/
3678         SND_SOC_DAPM_INPUT("AMIC1"),
3679         SND_SOC_DAPM_INPUT("AMIC2"),
3680         SND_SOC_DAPM_INPUT("AMIC3"),
3681         SND_SOC_DAPM_INPUT("AMIC4"),
3682         SND_SOC_DAPM_INPUT("AMIC5"),
3683         SND_SOC_DAPM_INPUT("AMIC6"),
3684         SND_SOC_DAPM_INPUT("AMIC7"),
3685         SND_SOC_DAPM_MIC("Analog Mic1", NULL),
3686         SND_SOC_DAPM_MIC("Analog Mic2", NULL),
3687         SND_SOC_DAPM_MIC("Analog Mic3", NULL),
3688         SND_SOC_DAPM_MIC("Analog Mic4", NULL),
3689         SND_SOC_DAPM_MIC("Analog Mic5", NULL),
3690
3691         /*tx widgets*/
3692         SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
3693                            wcd938x_codec_enable_adc,
3694                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3695         SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
3696                            wcd938x_codec_enable_adc,
3697                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3698         SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
3699                            wcd938x_codec_enable_adc,
3700                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3701         SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
3702                            wcd938x_codec_enable_adc,
3703                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3704         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
3705                            wcd938x_codec_enable_dmic,
3706                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3707         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
3708                            wcd938x_codec_enable_dmic,
3709                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3710         SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
3711                            wcd938x_codec_enable_dmic,
3712                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3713         SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
3714                            wcd938x_codec_enable_dmic,
3715                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3716         SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
3717                            wcd938x_codec_enable_dmic,
3718                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3719         SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
3720                            wcd938x_codec_enable_dmic,
3721                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3722         SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
3723                            wcd938x_codec_enable_dmic,
3724                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3725         SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
3726                            wcd938x_codec_enable_dmic,
3727                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3728
3729         SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
3730                              NULL, 0, wcd938x_adc_enable_req,
3731                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3732         SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
3733                              NULL, 0, wcd938x_adc_enable_req,
3734                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3735         SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
3736                              NULL, 0, wcd938x_adc_enable_req,
3737                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3738         SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0,
3739                              wcd938x_adc_enable_req,
3740                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3741
3742         SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
3743         SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux),
3744         SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux),
3745         SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux),
3746         SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux),
3747
3748         /*tx mixers*/
3749         SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch,
3750                              ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl,
3751                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3752         SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch,
3753                              ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl,
3754                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3755         SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
3756                              ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
3757                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3758         SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
3759                              ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
3760                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3761         SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch,
3762                              ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl,
3763                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3764         SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch,
3765                              ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl,
3766                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3767         SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch,
3768                              ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl,
3769                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3770         SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch,
3771                              ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl,
3772                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3773         SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch,
3774                              ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl,
3775                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3776         SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch,
3777                              ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl,
3778                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3779         SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch,
3780                              ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl,
3781                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3782         SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch,
3783                              ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl,
3784                              SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3785         /* micbias widgets*/
3786         SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
3787                             wcd938x_codec_enable_micbias,
3788                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3789                             SND_SOC_DAPM_POST_PMD),
3790         SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
3791                             wcd938x_codec_enable_micbias,
3792                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3793                             SND_SOC_DAPM_POST_PMD),
3794         SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
3795                             wcd938x_codec_enable_micbias,
3796                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3797                             SND_SOC_DAPM_POST_PMD),
3798         SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
3799                             wcd938x_codec_enable_micbias,
3800                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3801                             SND_SOC_DAPM_POST_PMD),
3802
3803         /* micbias pull up widgets*/
3804         SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
3805                                 wcd938x_codec_enable_micbias_pullup,
3806                                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3807                                 SND_SOC_DAPM_POST_PMD),
3808         SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
3809                                 wcd938x_codec_enable_micbias_pullup,
3810                                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3811                                 SND_SOC_DAPM_POST_PMD),
3812         SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
3813                                 wcd938x_codec_enable_micbias_pullup,
3814                                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3815                                 SND_SOC_DAPM_POST_PMD),
3816         SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
3817                                 wcd938x_codec_enable_micbias_pullup,
3818                                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3819                                 SND_SOC_DAPM_POST_PMD),
3820
3821         /*output widgets tx*/
3822         SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
3823         SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
3824         SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
3825         SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
3826         SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
3827         SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
3828         SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
3829         SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
3830         SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
3831         SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
3832         SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
3833         SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
3834
3835         SND_SOC_DAPM_INPUT("IN1_HPHL"),
3836         SND_SOC_DAPM_INPUT("IN2_HPHR"),
3837         SND_SOC_DAPM_INPUT("IN3_AUX"),
3838
3839         /*rx widgets*/
3840         SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
3841                            wcd938x_codec_enable_ear_pa,
3842                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3843                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3844         SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
3845                            wcd938x_codec_enable_aux_pa,
3846                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3847                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3848         SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
3849                            wcd938x_codec_enable_hphl_pa,
3850                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3851                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3852         SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
3853                            wcd938x_codec_enable_hphr_pa,
3854                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3855                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3856
3857         SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
3858                            wcd938x_codec_hphl_dac_event,
3859                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3860                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3861         SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
3862                            wcd938x_codec_hphr_dac_event,
3863                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3864                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3865         SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
3866                            wcd938x_codec_ear_dac_event,
3867                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3868                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3869         SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
3870                            wcd938x_codec_aux_dac_event,
3871                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3872                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3873
3874         SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
3875
3876         SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
3877         SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
3878                             wcd938x_codec_enable_rxclk,
3879                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3880                             SND_SOC_DAPM_POST_PMD),
3881
3882         SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
3883
3884         SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3885         SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3886         SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3887
3888         /* rx mixer widgets*/
3889         SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
3890                            ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
3891         SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
3892                            aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
3893         SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
3894                            hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
3895         SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
3896                            hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
3897
3898         /*output widgets rx*/
3899         SND_SOC_DAPM_OUTPUT("EAR"),
3900         SND_SOC_DAPM_OUTPUT("AUX"),
3901         SND_SOC_DAPM_OUTPUT("HPHL"),
3902         SND_SOC_DAPM_OUTPUT("HPHR"),
3903
3904 };
3905
3906 static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
3907         {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
3908         {"ADC1_MIXER", "Switch", "ADC1 REQ"},
3909         {"ADC1 REQ", NULL, "ADC1"},
3910         {"ADC1", NULL, "AMIC1"},
3911
3912         {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
3913         {"ADC2_MIXER", "Switch", "ADC2 REQ"},
3914         {"ADC2 REQ", NULL, "ADC2"},
3915         {"ADC2", NULL, "HDR12 MUX"},
3916         {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
3917         {"HDR12 MUX", "HDR12", "AMIC1"},
3918         {"ADC2 MUX", "INP3", "AMIC3"},
3919         {"ADC2 MUX", "INP2", "AMIC2"},
3920
3921         {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
3922         {"ADC3_MIXER", "Switch", "ADC3 REQ"},
3923         {"ADC3 REQ", NULL, "ADC3"},
3924         {"ADC3", NULL, "HDR34 MUX"},
3925         {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
3926         {"HDR34 MUX", "HDR34", "AMIC5"},
3927         {"ADC3 MUX", "INP4", "AMIC4"},
3928         {"ADC3 MUX", "INP6", "AMIC6"},
3929
3930         {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
3931         {"ADC4_MIXER", "Switch", "ADC4 REQ"},
3932         {"ADC4 REQ", NULL, "ADC4"},
3933         {"ADC4", NULL, "ADC4 MUX"},
3934         {"ADC4 MUX", "INP5", "AMIC5"},
3935         {"ADC4 MUX", "INP7", "AMIC7"},
3936
3937         {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
3938         {"DMIC1_MIXER", "Switch", "DMIC1"},
3939
3940         {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
3941         {"DMIC2_MIXER", "Switch", "DMIC2"},
3942
3943         {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
3944         {"DMIC3_MIXER", "Switch", "DMIC3"},
3945
3946         {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
3947         {"DMIC4_MIXER", "Switch", "DMIC4"},
3948
3949         {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
3950         {"DMIC5_MIXER", "Switch", "DMIC5"},
3951
3952         {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
3953         {"DMIC6_MIXER", "Switch", "DMIC6"},
3954
3955         {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
3956         {"DMIC7_MIXER", "Switch", "DMIC7"},
3957
3958         {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
3959         {"DMIC8_MIXER", "Switch", "DMIC8"},
3960
3961         {"IN1_HPHL", NULL, "VDD_BUCK"},
3962         {"IN1_HPHL", NULL, "CLS_H_PORT"},
3963
3964         {"RX1", NULL, "IN1_HPHL"},
3965         {"RX1", NULL, "RXCLK"},
3966         {"RDAC1", NULL, "RX1"},
3967         {"HPHL_RDAC", "Switch", "RDAC1"},
3968         {"HPHL PGA", NULL, "HPHL_RDAC"},
3969         {"HPHL", NULL, "HPHL PGA"},
3970
3971         {"IN2_HPHR", NULL, "VDD_BUCK"},
3972         {"IN2_HPHR", NULL, "CLS_H_PORT"},
3973         {"RX2", NULL, "IN2_HPHR"},
3974         {"RDAC2", NULL, "RX2"},
3975         {"RX2", NULL, "RXCLK"},
3976         {"HPHR_RDAC", "Switch", "RDAC2"},
3977         {"HPHR PGA", NULL, "HPHR_RDAC"},
3978         {"HPHR", NULL, "HPHR PGA"},
3979
3980         {"IN3_AUX", NULL, "VDD_BUCK"},
3981         {"IN3_AUX", NULL, "CLS_H_PORT"},
3982         {"RX3", NULL, "IN3_AUX"},
3983         {"RDAC4", NULL, "RX3"},
3984         {"RX3", NULL, "RXCLK"},
3985         {"AUX_RDAC", "Switch", "RDAC4"},
3986         {"AUX PGA", NULL, "AUX_RDAC"},
3987         {"AUX", NULL, "AUX PGA"},
3988
3989         {"RDAC3_MUX", "RX3", "RX3"},
3990         {"RDAC3_MUX", "RX1", "RX1"},
3991         {"RDAC3", NULL, "RDAC3_MUX"},
3992         {"EAR_RDAC", "Switch", "RDAC3"},
3993         {"EAR PGA", NULL, "EAR_RDAC"},
3994         {"EAR", NULL, "EAR PGA"},
3995 };
3996
3997 static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x)
3998 {
3999         int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
4000
4001         /* set micbias voltage */
4002         vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv);
4003         vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv);
4004         vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv);
4005         vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv);
4006         if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
4007                 return -EINVAL;
4008
4009         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1,
4010                            WCD938X_MICB_VOUT_MASK, vout_ctl_1);
4011         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2,
4012                            WCD938X_MICB_VOUT_MASK, vout_ctl_2);
4013         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3,
4014                            WCD938X_MICB_VOUT_MASK, vout_ctl_3);
4015         regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4,
4016                            WCD938X_MICB_VOUT_MASK, vout_ctl_4);
4017
4018         return 0;
4019 }
4020
4021 static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
4022 {
4023         return IRQ_HANDLED;
4024 }
4025
4026 static struct irq_chip wcd_irq_chip = {
4027         .name = "WCD938x",
4028 };
4029
4030 static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
4031                         irq_hw_number_t hw)
4032 {
4033         irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
4034         irq_set_nested_thread(virq, 1);
4035         irq_set_noprobe(virq);
4036
4037         return 0;
4038 }
4039
4040 static const struct irq_domain_ops wcd_domain_ops = {
4041         .map = wcd_irq_chip_map,
4042 };
4043
4044 static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev)
4045 {
4046
4047         wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
4048         if (!(wcd->virq)) {
4049                 dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
4050                 return -EINVAL;
4051         }
4052
4053         return devm_regmap_add_irq_chip(dev, wcd->regmap,
4054                                         irq_create_mapping(wcd->virq, 0),
4055                                         IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip,
4056                                         &wcd->irq_chip);
4057 }
4058
4059 static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
4060 {
4061         struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
4062         struct device *dev = component->dev;
4063         int ret, i;
4064
4065         snd_soc_component_init_regmap(component, wcd938x->regmap);
4066
4067         wcd938x->variant = snd_soc_component_read_field(component,
4068                                                  WCD938X_DIGITAL_EFUSE_REG_0,
4069                                                  WCD938X_ID_MASK);
4070
4071         wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X);
4072
4073         wcd938x_io_init(wcd938x);
4074         /* Set all interrupts as edge triggered */
4075         for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) {
4076                 regmap_write(wcd938x->regmap,
4077                              (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
4078         }
4079
4080         wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
4081                                                        WCD938X_IRQ_HPHR_PDM_WD_INT);
4082         wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
4083                                                        WCD938X_IRQ_HPHL_PDM_WD_INT);
4084         wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
4085                                                        WCD938X_IRQ_AUX_PDM_WD_INT);
4086
4087         /* Request for watchdog interrupt */
4088         ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
4089                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
4090                                    "HPHR PDM WD INT", wcd938x);
4091         if (ret)
4092                 dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
4093
4094         ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
4095                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
4096                                    "HPHL PDM WD INT", wcd938x);
4097         if (ret)
4098                 dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
4099
4100         ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
4101                                    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
4102                                    "AUX PDM WD INT", wcd938x);
4103         if (ret)
4104                 dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
4105
4106         /* Disable watchdog interrupt for HPH and AUX */
4107         disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
4108         disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
4109         disable_irq_nosync(wcd938x->aux_pdm_wd_int);
4110
4111         switch (wcd938x->variant) {
4112         case WCD9380:
4113                 ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
4114                                         ARRAY_SIZE(wcd9380_snd_controls));
4115                 if (ret < 0) {
4116                         dev_err(component->dev,
4117                                 "%s: Failed to add snd ctrls for variant: %d\n",
4118                                 __func__, wcd938x->variant);
4119                         goto err;
4120                 }
4121                 break;
4122         case WCD9385:
4123                 ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
4124                                         ARRAY_SIZE(wcd9385_snd_controls));
4125                 if (ret < 0) {
4126                         dev_err(component->dev,
4127                                 "%s: Failed to add snd ctrls for variant: %d\n",
4128                                 __func__, wcd938x->variant);
4129                         goto err;
4130                 }
4131                 break;
4132         default:
4133                 break;
4134         }
4135
4136         ret = wcd938x_mbhc_init(component);
4137         if (ret)
4138                 dev_err(component->dev,  "mbhc initialization failed\n");
4139 err:
4140         return ret;
4141 }
4142
4143 static int wcd938x_codec_set_jack(struct snd_soc_component *comp,
4144                                   struct snd_soc_jack *jack, void *data)
4145 {
4146         struct wcd938x_priv *wcd = dev_get_drvdata(comp->dev);
4147
4148         if (jack)
4149                 return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
4150         else
4151                 wcd_mbhc_stop(wcd->wcd_mbhc);
4152
4153         return 0;
4154 }
4155
4156 static const struct snd_soc_component_driver soc_codec_dev_wcd938x = {
4157         .name = "wcd938x_codec",
4158         .probe = wcd938x_soc_codec_probe,
4159         .controls = wcd938x_snd_controls,
4160         .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
4161         .dapm_widgets = wcd938x_dapm_widgets,
4162         .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
4163         .dapm_routes = wcd938x_audio_map,
4164         .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
4165         .set_jack = wcd938x_codec_set_jack,
4166 };
4167
4168 static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd)
4169 {
4170         struct device_node *np = dev->of_node;
4171         u32 prop_val = 0;
4172         int rc = 0;
4173
4174         rc = of_property_read_u32(np, "qcom,micbias1-microvolt",  &prop_val);
4175         if (!rc)
4176                 wcd->micb1_mv = prop_val/1000;
4177         else
4178                 dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
4179
4180         rc = of_property_read_u32(np, "qcom,micbias2-microvolt",  &prop_val);
4181         if (!rc)
4182                 wcd->micb2_mv = prop_val/1000;
4183         else
4184                 dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
4185
4186         rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
4187         if (!rc)
4188                 wcd->micb3_mv = prop_val/1000;
4189         else
4190                 dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
4191
4192         rc = of_property_read_u32(np, "qcom,micbias4-microvolt",  &prop_val);
4193         if (!rc)
4194                 wcd->micb4_mv = prop_val/1000;
4195         else
4196                 dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
4197 }
4198
4199 static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev)
4200 {
4201         struct wcd_mbhc_config *cfg = &wcd938x->mbhc_cfg;
4202         int ret;
4203
4204         wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);
4205         if (wcd938x->reset_gpio < 0) {
4206                 dev_err(dev, "Failed to get reset gpio: err = %d\n",
4207                         wcd938x->reset_gpio);
4208                 return wcd938x->reset_gpio;
4209         }
4210
4211         wcd938x->supplies[0].supply = "vdd-rxtx";
4212         wcd938x->supplies[1].supply = "vdd-io";
4213         wcd938x->supplies[2].supply = "vdd-buck";
4214         wcd938x->supplies[3].supply = "vdd-mic-bias";
4215
4216         ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies);
4217         if (ret) {
4218                 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
4219                 return ret;
4220         }
4221
4222         ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies);
4223         if (ret) {
4224                 dev_err(dev, "Failed to enable supplies: err = %d\n", ret);
4225                 return ret;
4226         }
4227
4228         wcd938x_dt_parse_micbias_info(dev, wcd938x);
4229
4230         cfg->mbhc_micbias = MIC_BIAS_2;
4231         cfg->anc_micbias = MIC_BIAS_2;
4232         cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
4233         cfg->num_btn = WCD938X_MBHC_MAX_BUTTONS;
4234         cfg->micb_mv = wcd938x->micb2_mv;
4235         cfg->linein_th = 5000;
4236         cfg->hs_thr = 1700;
4237         cfg->hph_thr = 50;
4238
4239         wcd_dt_parse_mbhc_data(dev, cfg);
4240
4241         return 0;
4242 }
4243
4244 static int wcd938x_reset(struct wcd938x_priv *wcd938x)
4245 {
4246         gpio_direction_output(wcd938x->reset_gpio, 0);
4247         /* 20us sleep required after pulling the reset gpio to LOW */
4248         usleep_range(20, 30);
4249         gpio_set_value(wcd938x->reset_gpio, 1);
4250         /* 20us sleep required after pulling the reset gpio to HIGH */
4251         usleep_range(20, 30);
4252
4253         return 0;
4254 }
4255
4256 static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream,
4257                                 struct snd_pcm_hw_params *params,
4258                                 struct snd_soc_dai *dai)
4259 {
4260         struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
4261         struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
4262
4263         return wcd938x_sdw_hw_params(wcd, substream, params, dai);
4264 }
4265
4266 static int wcd938x_codec_free(struct snd_pcm_substream *substream,
4267                               struct snd_soc_dai *dai)
4268 {
4269         struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
4270         struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
4271
4272         return wcd938x_sdw_free(wcd, substream, dai);
4273 }
4274
4275 static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai,
4276                                   void *stream, int direction)
4277 {
4278         struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
4279         struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
4280
4281         return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction);
4282
4283 }
4284
4285 static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = {
4286         .hw_params = wcd938x_codec_hw_params,
4287         .hw_free = wcd938x_codec_free,
4288         .set_stream = wcd938x_codec_set_sdw_stream,
4289 };
4290
4291 static struct snd_soc_dai_driver wcd938x_dais[] = {
4292         [0] = {
4293                 .name = "wcd938x-sdw-rx",
4294                 .playback = {
4295                         .stream_name = "WCD AIF1 Playback",
4296                         .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK,
4297                         .formats = WCD938X_FORMATS_S16_S24_LE,
4298                         .rate_max = 192000,
4299                         .rate_min = 8000,
4300                         .channels_min = 1,
4301                         .channels_max = 2,
4302                 },
4303                 .ops = &wcd938x_sdw_dai_ops,
4304         },
4305         [1] = {
4306                 .name = "wcd938x-sdw-tx",
4307                 .capture = {
4308                         .stream_name = "WCD AIF1 Capture",
4309                         .rates = WCD938X_RATES_MASK,
4310                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
4311                         .rate_min = 8000,
4312                         .rate_max = 192000,
4313                         .channels_min = 1,
4314                         .channels_max = 4,
4315                 },
4316                 .ops = &wcd938x_sdw_dai_ops,
4317         },
4318 };
4319
4320 static int wcd938x_bind(struct device *dev)
4321 {
4322         struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
4323         int ret;
4324
4325         ret = component_bind_all(dev, wcd938x);
4326         if (ret) {
4327                 dev_err(dev, "%s: Slave bind failed, ret = %d\n",
4328                         __func__, ret);
4329                 return ret;
4330         }
4331
4332         wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode);
4333         if (!wcd938x->rxdev) {
4334                 dev_err(dev, "could not find slave with matching of node\n");
4335                 return -EINVAL;
4336         }
4337         wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev);
4338         wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x;
4339
4340         wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode);
4341         if (!wcd938x->txdev) {
4342                 dev_err(dev, "could not find txslave with matching of node\n");
4343                 return -EINVAL;
4344         }
4345         wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev);
4346         wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x;
4347         wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev);
4348         if (!wcd938x->tx_sdw_dev) {
4349                 dev_err(dev, "could not get txslave with matching of dev\n");
4350                 return -EINVAL;
4351         }
4352
4353         /* As TX is main CSR reg interface, which should not be suspended first.
4354          * expicilty add the dependency link */
4355         if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS |
4356                             DL_FLAG_PM_RUNTIME)) {
4357                 dev_err(dev, "could not devlink tx and rx\n");
4358                 return -EINVAL;
4359         }
4360
4361         if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS |
4362                                         DL_FLAG_PM_RUNTIME)) {
4363                 dev_err(dev, "could not devlink wcd and tx\n");
4364                 return -EINVAL;
4365         }
4366
4367         if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS |
4368                                         DL_FLAG_PM_RUNTIME)) {
4369                 dev_err(dev, "could not devlink wcd and rx\n");
4370                 return -EINVAL;
4371         }
4372
4373         wcd938x->regmap = devm_regmap_init_sdw(wcd938x->tx_sdw_dev, &wcd938x_regmap_config);
4374         if (IS_ERR(wcd938x->regmap)) {
4375                 dev_err(dev, "%s: tx csr regmap not found\n", __func__);
4376                 return PTR_ERR(wcd938x->regmap);
4377         }
4378
4379         ret = wcd938x_irq_init(wcd938x, dev);
4380         if (ret) {
4381                 dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret);
4382                 return ret;
4383         }
4384
4385         wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq;
4386         wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq;
4387
4388         ret = wcd938x_set_micbias_data(wcd938x);
4389         if (ret < 0) {
4390                 dev_err(dev, "%s: bad micbias pdata\n", __func__);
4391                 return ret;
4392         }
4393
4394         ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
4395                                          wcd938x_dais, ARRAY_SIZE(wcd938x_dais));
4396         if (ret)
4397                 dev_err(dev, "%s: Codec registration failed\n",
4398                                 __func__);
4399
4400         return ret;
4401
4402 }
4403
4404 static void wcd938x_unbind(struct device *dev)
4405 {
4406         struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
4407
4408         device_link_remove(dev, wcd938x->txdev);
4409         device_link_remove(dev, wcd938x->rxdev);
4410         device_link_remove(wcd938x->rxdev, wcd938x->txdev);
4411         snd_soc_unregister_component(dev);
4412         component_unbind_all(dev, wcd938x);
4413 }
4414
4415 static const struct component_master_ops wcd938x_comp_ops = {
4416         .bind   = wcd938x_bind,
4417         .unbind = wcd938x_unbind,
4418 };
4419
4420 static int wcd938x_compare_of(struct device *dev, void *data)
4421 {
4422         return dev->of_node == data;
4423 }
4424
4425 static void wcd938x_release_of(struct device *dev, void *data)
4426 {
4427         of_node_put(data);
4428 }
4429
4430 static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x,
4431                                         struct device *dev,
4432                                         struct component_match **matchptr)
4433 {
4434         struct device_node *np;
4435
4436         np = dev->of_node;
4437
4438         wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
4439         if (!wcd938x->rxnode) {
4440                 dev_err(dev, "%s: Rx-device node not defined\n", __func__);
4441                 return -ENODEV;
4442         }
4443
4444         of_node_get(wcd938x->rxnode);
4445         component_match_add_release(dev, matchptr, wcd938x_release_of,
4446                                     wcd938x_compare_of, wcd938x->rxnode);
4447
4448         wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
4449         if (!wcd938x->txnode) {
4450                 dev_err(dev, "%s: Tx-device node not defined\n", __func__);
4451                 return -ENODEV;
4452         }
4453         of_node_get(wcd938x->txnode);
4454         component_match_add_release(dev, matchptr, wcd938x_release_of,
4455                                     wcd938x_compare_of, wcd938x->txnode);
4456         return 0;
4457 }
4458
4459 static int wcd938x_probe(struct platform_device *pdev)
4460 {
4461         struct component_match *match = NULL;
4462         struct wcd938x_priv *wcd938x = NULL;
4463         struct device *dev = &pdev->dev;
4464         int ret;
4465
4466         wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
4467                                 GFP_KERNEL);
4468         if (!wcd938x)
4469                 return -ENOMEM;
4470
4471         dev_set_drvdata(dev, wcd938x);
4472         mutex_init(&wcd938x->micb_lock);
4473
4474         ret = wcd938x_populate_dt_data(wcd938x, dev);
4475         if (ret) {
4476                 dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
4477                 return -EINVAL;
4478         }
4479
4480         ret = wcd938x_add_slave_components(wcd938x, dev, &match);
4481         if (ret)
4482                 return ret;
4483
4484         wcd938x_reset(wcd938x);
4485
4486         ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match);
4487         if (ret)
4488                 return ret;
4489
4490         pm_runtime_set_autosuspend_delay(dev, 1000);
4491         pm_runtime_use_autosuspend(dev);
4492         pm_runtime_mark_last_busy(dev);
4493         pm_runtime_set_active(dev);
4494         pm_runtime_enable(dev);
4495         pm_runtime_idle(dev);
4496
4497         return 0;
4498 }
4499
4500 static int wcd938x_remove(struct platform_device *pdev)
4501 {
4502         component_master_del(&pdev->dev, &wcd938x_comp_ops);
4503
4504         return 0;
4505 }
4506
4507 #if defined(CONFIG_OF)
4508 static const struct of_device_id wcd938x_dt_match[] = {
4509         { .compatible = "qcom,wcd9380-codec" },
4510         { .compatible = "qcom,wcd9385-codec" },
4511         {}
4512 };
4513 MODULE_DEVICE_TABLE(of, wcd938x_dt_match);
4514 #endif
4515
4516 static struct platform_driver wcd938x_codec_driver = {
4517         .probe = wcd938x_probe,
4518         .remove = wcd938x_remove,
4519         .driver = {
4520                 .name = "wcd938x_codec",
4521                 .of_match_table = of_match_ptr(wcd938x_dt_match),
4522                 .suppress_bind_attrs = true,
4523         },
4524 };
4525
4526 module_platform_driver(wcd938x_codec_driver);
4527 MODULE_DESCRIPTION("WCD938X Codec driver");
4528 MODULE_LICENSE("GPL");