sound/soc/codecs/wcd934x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/clk-provider.h>
   6 #include <linux/gpio.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/kernel.h>
   9 #include <linux/mfd/wcd934x/registers.h>
  10 #include <linux/mfd/wcd934x/wcd934x.h>
  11 #include <linux/module.h>
  12 #include <linux/mutex.h>
  13 #include <linux/of_clk.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_gpio.h>
  16 #include <linux/of.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regmap.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/slab.h>
  22 #include <linux/slimbus.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/soc.h>
  25 #include <sound/soc-dapm.h>
  26 #include <sound/tlv.h>
  27 #include "wcd-clsh-v2.h"
  28
  29 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  30                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  31                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  32 /* Fractional Rates */
  33 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  34                                  SNDRV_PCM_RATE_176400)
  35 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  36                                     SNDRV_PCM_FMTBIT_S24_LE)
  37
  38 /* slave port water mark level
  39  *   (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
  40  */
  41 #define SLAVE_PORT_WATER_MARK_6BYTES    0
  42 #define SLAVE_PORT_WATER_MARK_9BYTES    1
  43 #define SLAVE_PORT_WATER_MARK_12BYTES   2
  44 #define SLAVE_PORT_WATER_MARK_15BYTES   3
  45 #define SLAVE_PORT_WATER_MARK_SHIFT     1
  46 #define SLAVE_PORT_ENABLE               1
  47 #define SLAVE_PORT_DISABLE              0
  48 #define WCD934X_SLIM_WATER_MARK_VAL \
  49         ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
  50          (SLAVE_PORT_ENABLE))
  51
  52 #define WCD934X_SLIM_NUM_PORT_REG       3
  53 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
  54 #define WCD934X_SLIM_IRQ_OVERFLOW       BIT(0)
  55 #define WCD934X_SLIM_IRQ_UNDERFLOW      BIT(1)
  56 #define WCD934X_SLIM_IRQ_PORT_CLOSED    BIT(2)
  57
  58 #define WCD934X_MCLK_CLK_12P288MHZ      12288000
  59 #define WCD934X_MCLK_CLK_9P6MHZ         9600000
  60
  61 /* Only valid for 9.6 MHz mclk */
  62 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
  63 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
  64
  65 /* Only valid for 12.288 MHz mclk */
  66 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
  67
  68 #define WCD934X_DMIC_CLK_DIV_2          0x0
  69 #define WCD934X_DMIC_CLK_DIV_3          0x1
  70 #define WCD934X_DMIC_CLK_DIV_4          0x2
  71 #define WCD934X_DMIC_CLK_DIV_6          0x3
  72 #define WCD934X_DMIC_CLK_DIV_8          0x4
  73 #define WCD934X_DMIC_CLK_DIV_16         0x5
  74 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
  75
  76 #define TX_HPF_CUT_OFF_FREQ_MASK        0x60
  77 #define CF_MIN_3DB_4HZ                  0x0
  78 #define CF_MIN_3DB_75HZ                 0x1
  79 #define CF_MIN_3DB_150HZ                0x2
  80
  81 #define WCD934X_RX_START                16
  82 #define WCD934X_NUM_INTERPOLATORS       9
  83 #define WCD934X_RX_PATH_CTL_OFFSET      20
  84 #define WCD934X_MAX_VALID_ADC_MUX       13
  85 #define WCD934X_INVALID_ADC_MUX         9
  86
  87 #define WCD934X_SLIM_RX_CH(p) \
  88         {.port = p + WCD934X_RX_START, .shift = p,}
  89
  90 #define WCD934X_SLIM_TX_CH(p) \
  91         {.port = p, .shift = p,}
  92
  93 /* Feature masks to distinguish codec version */
  94 #define DSD_DISABLED_MASK   0
  95 #define SLNQ_DISABLED_MASK  1
  96
  97 #define DSD_DISABLED   BIT(DSD_DISABLED_MASK)
  98 #define SLNQ_DISABLED  BIT(SLNQ_DISABLED_MASK)
  99
 100 /* As fine version info cannot be retrieved before wcd probe.
 101  * Define three coarse versions for possible future use before wcd probe.
 102  */
 103 #define WCD_VERSION_WCD9340_1_0     0x400
 104 #define WCD_VERSION_WCD9341_1_0     0x410
 105 #define WCD_VERSION_WCD9340_1_1     0x401
 106 #define WCD_VERSION_WCD9341_1_1     0x411
 107 #define WCD934X_AMIC_PWR_LEVEL_LP       0
 108 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT  1
 109 #define WCD934X_AMIC_PWR_LEVEL_HP       2
 110 #define WCD934X_AMIC_PWR_LEVEL_HYBRID   3
 111 #define WCD934X_AMIC_PWR_LVL_MASK       0x60
 112 #define WCD934X_AMIC_PWR_LVL_SHIFT      0x5
 113
 114 #define WCD934X_DEC_PWR_LVL_MASK        0x06
 115 #define WCD934X_DEC_PWR_LVL_LP          0x02
 116 #define WCD934X_DEC_PWR_LVL_HP          0x04
 117 #define WCD934X_DEC_PWR_LVL_DF          0x00
 118 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
 119
 120 #define WCD934X_DEF_MICBIAS_MV  1800
 121 #define WCD934X_MAX_MICBIAS_MV  2850
 122
 123 enum {
 124         SIDO_SOURCE_INTERNAL,
 125         SIDO_SOURCE_RCO_BG,
 126 };
 127
 128 enum {
 129         INTERP_EAR = 0,
 130         INTERP_HPHL,
 131         INTERP_HPHR,
 132         INTERP_LO1,
 133         INTERP_LO2,
 134         INTERP_LO3_NA, /* LO3 not avalible in Tavil */
 135         INTERP_LO4_NA,
 136         INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
 137         INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
 138         INTERP_MAX,
 139 };
 140
 141 enum {
 142         WCD934X_RX0 = 0,
 143         WCD934X_RX1,
 144         WCD934X_RX2,
 145         WCD934X_RX3,
 146         WCD934X_RX4,
 147         WCD934X_RX5,
 148         WCD934X_RX6,
 149         WCD934X_RX7,
 150         WCD934X_RX8,
 151         WCD934X_RX9,
 152         WCD934X_RX10,
 153         WCD934X_RX11,
 154         WCD934X_RX12,
 155         WCD934X_RX_MAX,
 156 };
 157
 158 enum {
 159         WCD934X_TX0 = 0,
 160         WCD934X_TX1,
 161         WCD934X_TX2,
 162         WCD934X_TX3,
 163         WCD934X_TX4,
 164         WCD934X_TX5,
 165         WCD934X_TX6,
 166         WCD934X_TX7,
 167         WCD934X_TX8,
 168         WCD934X_TX9,
 169         WCD934X_TX10,
 170         WCD934X_TX11,
 171         WCD934X_TX12,
 172         WCD934X_TX13,
 173         WCD934X_TX14,
 174         WCD934X_TX15,
 175         WCD934X_TX_MAX,
 176 };
 177
 178 struct wcd934x_slim_ch {
 179         u32 ch_num;
 180         u16 port;
 181         u16 shift;
 182         struct list_head list;
 183 };
 184
 185 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
 186         WCD934X_SLIM_TX_CH(0),
 187         WCD934X_SLIM_TX_CH(1),
 188         WCD934X_SLIM_TX_CH(2),
 189         WCD934X_SLIM_TX_CH(3),
 190         WCD934X_SLIM_TX_CH(4),
 191         WCD934X_SLIM_TX_CH(5),
 192         WCD934X_SLIM_TX_CH(6),
 193         WCD934X_SLIM_TX_CH(7),
 194         WCD934X_SLIM_TX_CH(8),
 195         WCD934X_SLIM_TX_CH(9),
 196         WCD934X_SLIM_TX_CH(10),
 197         WCD934X_SLIM_TX_CH(11),
 198         WCD934X_SLIM_TX_CH(12),
 199         WCD934X_SLIM_TX_CH(13),
 200         WCD934X_SLIM_TX_CH(14),
 201         WCD934X_SLIM_TX_CH(15),
 202 };
 203
 204 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
 205         WCD934X_SLIM_RX_CH(0),   /* 16 */
 206         WCD934X_SLIM_RX_CH(1),   /* 17 */
 207         WCD934X_SLIM_RX_CH(2),
 208         WCD934X_SLIM_RX_CH(3),
 209         WCD934X_SLIM_RX_CH(4),
 210         WCD934X_SLIM_RX_CH(5),
 211         WCD934X_SLIM_RX_CH(6),
 212         WCD934X_SLIM_RX_CH(7),
 213         WCD934X_SLIM_RX_CH(8),
 214         WCD934X_SLIM_RX_CH(9),
 215         WCD934X_SLIM_RX_CH(10),
 216         WCD934X_SLIM_RX_CH(11),
 217         WCD934X_SLIM_RX_CH(12),
 218 };
 219
 220 enum {
 221         AIF1_PB = 0,
 222         AIF1_CAP,
 223         AIF2_PB,
 224         AIF2_CAP,
 225         AIF3_PB,
 226         AIF3_CAP,
 227         AIF4_PB,
 228         AIF4_VIFEED,
 229         AIF4_MAD_TX,
 230         NUM_CODEC_DAIS,
 231 };
 232
 233 enum {
 234         INTn_1_INP_SEL_ZERO = 0,
 235         INTn_1_INP_SEL_DEC0,
 236         INTn_1_INP_SEL_DEC1,
 237         INTn_1_INP_SEL_IIR0,
 238         INTn_1_INP_SEL_IIR1,
 239         INTn_1_INP_SEL_RX0,
 240         INTn_1_INP_SEL_RX1,
 241         INTn_1_INP_SEL_RX2,
 242         INTn_1_INP_SEL_RX3,
 243         INTn_1_INP_SEL_RX4,
 244         INTn_1_INP_SEL_RX5,
 245         INTn_1_INP_SEL_RX6,
 246         INTn_1_INP_SEL_RX7,
 247 };
 248
 249 enum {
 250         INTn_2_INP_SEL_ZERO = 0,
 251         INTn_2_INP_SEL_RX0,
 252         INTn_2_INP_SEL_RX1,
 253         INTn_2_INP_SEL_RX2,
 254         INTn_2_INP_SEL_RX3,
 255         INTn_2_INP_SEL_RX4,
 256         INTn_2_INP_SEL_RX5,
 257         INTn_2_INP_SEL_RX6,
 258         INTn_2_INP_SEL_RX7,
 259         INTn_2_INP_SEL_PROXIMITY,
 260 };
 261
 262 enum {
 263         INTERP_MAIN_PATH,
 264         INTERP_MIX_PATH,
 265 };
 266
 267 struct interp_sample_rate {
 268         int sample_rate;
 269         int rate_val;
 270 };
 271
 272 static struct interp_sample_rate sr_val_tbl[] = {
 273         {8000, 0x0},
 274         {16000, 0x1},
 275         {32000, 0x3},
 276         {48000, 0x4},
 277         {96000, 0x5},
 278         {192000, 0x6},
 279         {384000, 0x7},
 280         {44100, 0x9},
 281         {88200, 0xA},
 282         {176400, 0xB},
 283         {352800, 0xC},
 284 };
 285
 286 struct wcd_slim_codec_dai_data {
 287         struct list_head slim_ch_list;
 288         struct slim_stream_config sconfig;
 289         struct slim_stream_runtime *sruntime;
 290 };
 291
 292 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
 293         {
 294                 .name = "WCD9335-IFC-DEV",
 295                 .range_min =  0x0,
 296                 .range_max = 0xffff,
 297                 .selector_reg = 0x800,
 298                 .selector_mask = 0xfff,
 299                 .selector_shift = 0,
 300                 .window_start = 0x800,
 301                 .window_len = 0x400,
 302         },
 303 };
 304
 305 static struct regmap_config wcd934x_ifc_regmap_config = {
 306         .reg_bits = 16,
 307         .val_bits = 8,
 308         .max_register = 0xffff,
 309         .ranges = wcd934x_ifc_ranges,
 310         .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
 311 };
 312
 313 struct wcd934x_codec {
 314         struct device *dev;
 315         struct clk_hw hw;
 316         struct clk *extclk;
 317         struct regmap *regmap;
 318         struct regmap *if_regmap;
 319         struct slim_device *sdev;
 320         struct slim_device *sidev;
 321         struct wcd_clsh_ctrl *clsh_ctrl;
 322         struct snd_soc_component *component;
 323         struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
 324         struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
 325         struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
 326         int rate;
 327         u32 version;
 328         u32 hph_mode;
 329         int num_rx_port;
 330         int num_tx_port;
 331         u32 tx_port_value[WCD934X_TX_MAX];
 332         u32 rx_port_value[WCD934X_RX_MAX];
 333         int sido_input_src;
 334         int dmic_0_1_clk_cnt;
 335         int dmic_2_3_clk_cnt;
 336         int dmic_4_5_clk_cnt;
 337         int dmic_sample_rate;
 338         int sysclk_users;
 339         struct mutex sysclk_mutex;
 340 };
 341
 342 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
 343
 344 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd,
 345                                       int sido_src)
 346 {
 347         if (sido_src == wcd->sido_input_src)
 348                 return 0;
 349
 350         if (sido_src == SIDO_SOURCE_INTERNAL) {
 351                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
 352                                    WCD934X_ANA_BUCK_HI_ACCU_EN_MASK, 0);
 353                 usleep_range(100, 110);
 354                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
 355                                    WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK, 0x0);
 356                 usleep_range(100, 110);
 357                 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
 358                                    WCD934X_ANA_RCO_BG_EN_MASK, 0);
 359                 usleep_range(100, 110);
 360         } else if (sido_src == SIDO_SOURCE_RCO_BG) {
 361                 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
 362                                    WCD934X_ANA_RCO_BG_EN_MASK,
 363                                    WCD934X_ANA_RCO_BG_ENABLE);
 364                 usleep_range(100, 110);
 365                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
 366                                    WCD934X_ANA_BUCK_PRE_EN1_MASK,
 367                                    WCD934X_ANA_BUCK_PRE_EN1_ENABLE);
 368                 usleep_range(100, 110);
 369                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
 370                                    WCD934X_ANA_BUCK_PRE_EN2_MASK,
 371                                    WCD934X_ANA_BUCK_PRE_EN2_ENABLE);
 372                 usleep_range(100, 110);
 373                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
 374                                    WCD934X_ANA_BUCK_HI_ACCU_EN_MASK,
 375                                    WCD934X_ANA_BUCK_HI_ACCU_ENABLE);
 376                 usleep_range(100, 110);
 377         }
 378         wcd->sido_input_src = sido_src;
 379
 380         return 0;
 381 }
 382
 383 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
 384 {
 385         mutex_lock(&wcd->sysclk_mutex);
 386
 387         if (++wcd->sysclk_users != 1) {
 388                 mutex_unlock(&wcd->sysclk_mutex);
 389                 return 0;
 390         }
 391         mutex_unlock(&wcd->sysclk_mutex);
 392
 393         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 394                            WCD934X_ANA_BIAS_EN_MASK,
 395                            WCD934X_ANA_BIAS_EN);
 396         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 397                            WCD934X_ANA_PRECHRG_EN_MASK,
 398                            WCD934X_ANA_PRECHRG_EN);
 399         /*
 400          * 1ms delay is required after pre-charge is enabled
 401          * as per HW requirement
 402          */
 403         usleep_range(1000, 1100);
 404         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 405                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
 406         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 407                            WCD934X_ANA_PRECHRG_MODE_MASK, 0);
 408
 409         /*
 410          * In data clock contrl register is changed
 411          * to CLK_SYS_MCLK_PRG
 412          */
 413
 414         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
 415                            WCD934X_EXT_CLK_BUF_EN_MASK,
 416                            WCD934X_EXT_CLK_BUF_EN);
 417         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
 418                            WCD934X_EXT_CLK_DIV_RATIO_MASK,
 419                            WCD934X_EXT_CLK_DIV_BY_2);
 420         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
 421                            WCD934X_MCLK_SRC_MASK,
 422                            WCD934X_MCLK_SRC_EXT_CLK);
 423         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
 424                            WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
 425         regmap_update_bits(wcd->regmap,
 426                            WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
 427                            WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
 428                            WCD934X_CDC_FS_MCLK_CNT_ENABLE);
 429         regmap_update_bits(wcd->regmap,
 430                            WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
 431                            WCD934X_MCLK_EN_MASK,
 432                            WCD934X_MCLK_EN);
 433         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
 434                            WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
 435         /*
 436          * 10us sleep is required after clock is enabled
 437          * as per HW requirement
 438          */
 439         usleep_range(10, 15);
 440
 441         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
 442
 443         return 0;
 444 }
 445
 446 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
 447 {
 448         mutex_lock(&wcd->sysclk_mutex);
 449         if (--wcd->sysclk_users != 0) {
 450                 mutex_unlock(&wcd->sysclk_mutex);
 451                 return 0;
 452         }
 453         mutex_unlock(&wcd->sysclk_mutex);
 454
 455         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
 456                            WCD934X_EXT_CLK_BUF_EN_MASK |
 457                            WCD934X_MCLK_EN_MASK, 0x0);
 458         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_INTERNAL);
 459
 460         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 461                            WCD934X_ANA_BIAS_EN_MASK, 0);
 462         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 463                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
 464
 465         return 0;
 466 }
 467
 468 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
 469 {
 470         int ret = 0;
 471
 472         if (enable) {
 473                 ret = clk_prepare_enable(wcd->extclk);
 474
 475                 if (ret) {
 476                         dev_err(wcd->dev, "%s: ext clk enable failed\n",
 477                                 __func__);
 478                         return ret;
 479                 }
 480                 ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
 481         } else {
 482                 int val;
 483
 484                 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
 485                             &val);
 486
 487                 /* Don't disable clock if soundwire using it.*/
 488                 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
 489                         return 0;
 490
 491                 wcd934x_disable_ana_bias_and_syclk(wcd);
 492                 clk_disable_unprepare(wcd->extclk);
 493         }
 494
 495         return ret;
 496 }
 497
 498 static int wcd934x_get_version(struct wcd934x_codec *wcd)
 499 {
 500         int val1, val2, ver, ret;
 501         struct regmap *regmap;
 502         u16 id_minor;
 503         u32 version_mask = 0;
 504
 505         regmap = wcd->regmap;
 506         ver = 0;
 507
 508         ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
 509                                (u8 *)&id_minor, sizeof(u16));
 510
 511         if (ret)
 512                 return ret;
 513
 514         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
 515         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
 516
 517         version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
 518         version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
 519
 520         switch (version_mask) {
 521         case DSD_DISABLED | SLNQ_DISABLED:
 522                 if (id_minor == 0)
 523                         ver = WCD_VERSION_WCD9340_1_0;
 524                 else if (id_minor == 0x01)
 525                         ver = WCD_VERSION_WCD9340_1_1;
 526                 break;
 527         case SLNQ_DISABLED:
 528                 if (id_minor == 0)
 529                         ver = WCD_VERSION_WCD9341_1_0;
 530                 else if (id_minor == 0x01)
 531                         ver = WCD_VERSION_WCD9341_1_1;
 532                 break;
 533         }
 534
 535         wcd->version = ver;
 536         dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
 537
 538         return 0;
 539 }
 540
 541 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
 542 {
 543         int rc, val;
 544
 545         __wcd934x_cdc_mclk_enable(wcd, true);
 546
 547         regmap_update_bits(wcd->regmap,
 548                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
 549                            WCD934X_EFUSE_SENSE_STATE_MASK,
 550                            WCD934X_EFUSE_SENSE_STATE_DEF);
 551         regmap_update_bits(wcd->regmap,
 552                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
 553                            WCD934X_EFUSE_SENSE_EN_MASK,
 554                            WCD934X_EFUSE_SENSE_ENABLE);
 555         /*
 556          * 5ms sleep required after enabling efuse control
 557          * before checking the status.
 558          */
 559         usleep_range(5000, 5500);
 560         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
 561
 562         rc = regmap_read(wcd->regmap,
 563                          WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
 564         if (rc || (!(val & 0x01)))
 565                 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
 566                      __func__, val, rc);
 567
 568         __wcd934x_cdc_mclk_enable(wcd, false);
 569 }
 570
 571 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
 572 {
 573         if (enable) {
 574                 __wcd934x_cdc_mclk_enable(wcd, true);
 575                 regmap_update_bits(wcd->regmap,
 576                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
 577                                    WCD934X_CDC_SWR_CLK_EN_MASK,
 578                                    WCD934X_CDC_SWR_CLK_ENABLE);
 579         } else {
 580                 regmap_update_bits(wcd->regmap,
 581                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
 582                                    WCD934X_CDC_SWR_CLK_EN_MASK, 0);
 583                 __wcd934x_cdc_mclk_enable(wcd, false);
 584         }
 585
 586         return 0;
 587 }
 588
 589 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
 590                                               u8 rate_val, u32 rate)
 591 {
 592         struct snd_soc_component *comp = dai->component;
 593         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
 594         struct wcd934x_slim_ch *ch;
 595         u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
 596         int inp, j;
 597
 598         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
 599                 inp = ch->shift + INTn_1_INP_SEL_RX0;
 600                 /*
 601                  * Loop through all interpolator MUX inputs and find out
 602                  * to which interpolator input, the slim rx port
 603                  * is connected
 604                  */
 605                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
 606                         /* Interpolators 5 and 6 are not aviliable in Tavil */
 607                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
 608                                 continue;
 609
 610                         cfg0 = snd_soc_component_read32(comp,
 611                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
 612                         cfg1 = snd_soc_component_read32(comp,
 613                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
 614
 615                         inp0_sel = cfg0 &
 616                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
 617                         inp1_sel = (cfg0 >> 4) &
 618                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
 619                         inp2_sel = (cfg1 >> 4) &
 620                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
 621
 622                         if ((inp0_sel == inp) ||  (inp1_sel == inp) ||
 623                             (inp2_sel == inp)) {
 624                                 /* rate is in Hz */
 625                                 /*
 626                                  * Ear and speaker primary path does not support
 627                                  * native sample rates
 628                                  */
 629                                 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
 630                                      j == INTERP_SPKR2) && rate == 44100)
 631                                         dev_err(wcd->dev,
 632                                                 "Cannot set 44.1KHz on INT%d\n",
 633                                                 j);
 634                                 else
 635                                         snd_soc_component_update_bits(comp,
 636                                               WCD934X_CDC_RX_PATH_CTL(j),
 637                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
 638                                               rate_val);
 639                         }
 640                 }
 641         }
 642
 643         return 0;
 644 }
 645
 646 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
 647                                              int rate_val, u32 rate)
 648 {
 649         struct snd_soc_component *component = dai->component;
 650         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
 651         struct wcd934x_slim_ch *ch;
 652         int val, j;
 653
 654         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
 655                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
 656                         /* Interpolators 5 and 6 are not aviliable in Tavil */
 657                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
 658                                 continue;
 659                         val = snd_soc_component_read32(component,
 660                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
 661                                         WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
 662
 663                         if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
 664                                 /*
 665                                  * Ear mix path supports only 48, 96, 192,
 666                                  * 384KHz only
 667                                  */
 668                                 if ((j == INTERP_EAR) &&
 669                                     (rate_val < 0x4 ||
 670                                      rate_val > 0x7)) {
 671                                         dev_err(component->dev,
 672                                                 "Invalid rate for AIF_PB DAI(%d)\n",
 673                                                 dai->id);
 674                                         return -EINVAL;
 675                                 }
 676
 677                                 snd_soc_component_update_bits(component,
 678                                               WCD934X_CDC_RX_PATH_MIX_CTL(j),
 679                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
 680                                               rate_val);
 681                         }
 682                 }
 683         }
 684
 685         return 0;
 686 }
 687
 688 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
 689                                          u32 sample_rate)
 690 {
 691         int rate_val = 0;
 692         int i, ret;
 693
 694         for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
 695                 if (sample_rate == sr_val_tbl[i].sample_rate) {
 696                         rate_val = sr_val_tbl[i].rate_val;
 697                         break;
 698                 }
 699         }
 700         if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
 701                 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
 702                 return -EINVAL;
 703         }
 704
 705         ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
 706                                                  sample_rate);
 707         if (ret)
 708                 return ret;
 709         ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
 710                                                 sample_rate);
 711         if (ret)
 712                 return ret;
 713
 714         return ret;
 715 }
 716
 717 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
 718                                       u8 rate_val, u32 rate)
 719 {
 720         struct snd_soc_component *comp = dai->component;
 721         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
 722         u8 shift = 0, shift_val = 0, tx_mux_sel;
 723         struct wcd934x_slim_ch *ch;
 724         int tx_port, tx_port_reg;
 725         int decimator = -1;
 726
 727         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
 728                 tx_port = ch->port;
 729                 /* Find the SB TX MUX input - which decimator is connected */
 730                 switch (tx_port) {
 731                 case 0 ...  3:
 732                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
 733                         shift = (tx_port << 1);
 734                         shift_val = 0x03;
 735                         break;
 736                 case 4 ... 7:
 737                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
 738                         shift = ((tx_port - 4) << 1);
 739                         shift_val = 0x03;
 740                         break;
 741                 case 8 ... 10:
 742                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
 743                         shift = ((tx_port - 8) << 1);
 744                         shift_val = 0x03;
 745                         break;
 746                 case 11:
 747                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
 748                         shift = 0;
 749                         shift_val = 0x0F;
 750                         break;
 751                 case 13:
 752                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
 753                         shift = 4;
 754                         shift_val = 0x03;
 755                         break;
 756                 default:
 757                         dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
 758                                 tx_port, dai->id);
 759                         return -EINVAL;
 760                 }
 761
 762                 tx_mux_sel = snd_soc_component_read32(comp, tx_port_reg) &
 763                                                       (shift_val << shift);
 764
 765                 tx_mux_sel = tx_mux_sel >> shift;
 766                 switch (tx_port) {
 767                 case 0 ... 8:
 768                         if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
 769                                 decimator = tx_port;
 770                         break;
 771                 case 9 ... 10:
 772                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
 773                                 decimator = ((tx_port == 9) ? 7 : 6);
 774                         break;
 775                 case 11:
 776                         if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
 777                                 decimator = tx_mux_sel - 1;
 778                         break;
 779                 case 13:
 780                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
 781                                 decimator = 5;
 782                         break;
 783                 default:
 784                         dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
 785                                 tx_port);
 786                         return -EINVAL;
 787                 }
 788
 789                 snd_soc_component_update_bits(comp,
 790                                       WCD934X_CDC_TX_PATH_CTL(decimator),
 791                                       WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
 792                                       rate_val);
 793         }
 794
 795         return 0;
 796 }
 797
 798 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
 799                                       struct wcd_slim_codec_dai_data *dai_data,
 800                                       int direction)
 801 {
 802         struct list_head *slim_ch_list = &dai_data->slim_ch_list;
 803         struct slim_stream_config *cfg = &dai_data->sconfig;
 804         struct wcd934x_slim_ch *ch;
 805         u16 payload = 0;
 806         int ret, i;
 807
 808         cfg->ch_count = 0;
 809         cfg->direction = direction;
 810         cfg->port_mask = 0;
 811
 812         /* Configure slave interface device */
 813         list_for_each_entry(ch, slim_ch_list, list) {
 814                 cfg->ch_count++;
 815                 payload |= 1 << ch->shift;
 816                 cfg->port_mask |= BIT(ch->port);
 817         }
 818
 819         cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
 820         if (!cfg->chs)
 821                 return -ENOMEM;
 822
 823         i = 0;
 824         list_for_each_entry(ch, slim_ch_list, list) {
 825                 cfg->chs[i++] = ch->ch_num;
 826                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
 827                         /* write to interface device */
 828                         ret = regmap_write(wcd->if_regmap,
 829                            WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
 830                            payload);
 831
 832                         if (ret < 0)
 833                                 goto err;
 834
 835                         /* configure the slave port for water mark and enable*/
 836                         ret = regmap_write(wcd->if_regmap,
 837                                         WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
 838                                         WCD934X_SLIM_WATER_MARK_VAL);
 839                         if (ret < 0)
 840                                 goto err;
 841                 } else {
 842                         ret = regmap_write(wcd->if_regmap,
 843                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
 844                                 payload & 0x00FF);
 845                         if (ret < 0)
 846                                 goto err;
 847
 848                         /* ports 8,9 */
 849                         ret = regmap_write(wcd->if_regmap,
 850                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
 851                                 (payload & 0xFF00) >> 8);
 852                         if (ret < 0)
 853                                 goto err;
 854
 855                         /* configure the slave port for water mark and enable*/
 856                         ret = regmap_write(wcd->if_regmap,
 857                                         WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
 858                                         WCD934X_SLIM_WATER_MARK_VAL);
 859
 860                         if (ret < 0)
 861                                 goto err;
 862                 }
 863         }
 864
 865         dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
 866
 867         return 0;
 868
 869 err:
 870         dev_err(wcd->dev, "Error Setting slim hw params\n");
 871         kfree(cfg->chs);
 872         cfg->chs = NULL;
 873
 874         return ret;
 875 }
 876
 877 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
 878                              struct snd_pcm_hw_params *params,
 879                              struct snd_soc_dai *dai)
 880 {
 881         struct wcd934x_codec *wcd;
 882         int ret, tx_fs_rate = 0;
 883
 884         wcd = snd_soc_component_get_drvdata(dai->component);
 885
 886         switch (substream->stream) {
 887         case SNDRV_PCM_STREAM_PLAYBACK:
 888                 ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
 889                 if (ret) {
 890                         dev_err(wcd->dev, "cannot set sample rate: %u\n",
 891                                 params_rate(params));
 892                         return ret;
 893                 }
 894                 switch (params_width(params)) {
 895                 case 16 ... 24:
 896                         wcd->dai[dai->id].sconfig.bps = params_width(params);
 897                         break;
 898                 default:
 899                         dev_err(wcd->dev, "Invalid format 0x%x\n",
 900                                 params_width(params));
 901                         return -EINVAL;
 902                 }
 903                 break;
 904
 905         case SNDRV_PCM_STREAM_CAPTURE:
 906                 switch (params_rate(params)) {
 907                 case 8000:
 908                         tx_fs_rate = 0;
 909                         break;
 910                 case 16000:
 911                         tx_fs_rate = 1;
 912                         break;
 913                 case 32000:
 914                         tx_fs_rate = 3;
 915                         break;
 916                 case 48000:
 917                         tx_fs_rate = 4;
 918                         break;
 919                 case 96000:
 920                         tx_fs_rate = 5;
 921                         break;
 922                 case 192000:
 923                         tx_fs_rate = 6;
 924                         break;
 925                 case 384000:
 926                         tx_fs_rate = 7;
 927                         break;
 928                 default:
 929                         dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
 930                                 params_rate(params));
 931                         return -EINVAL;
 932
 933                 };
 934
 935                 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
 936                                                  params_rate(params));
 937                 if (ret < 0) {
 938                         dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
 939                         return ret;
 940                 }
 941                 switch (params_width(params)) {
 942                 case 16 ... 32:
 943                         wcd->dai[dai->id].sconfig.bps = params_width(params);
 944                         break;
 945                 default:
 946                         dev_err(wcd->dev, "Invalid format 0x%x\n",
 947                                 params_width(params));
 948                         return -EINVAL;
 949                 };
 950                 break;
 951         default:
 952                 dev_err(wcd->dev, "Invalid stream type %d\n",
 953                         substream->stream);
 954                 return -EINVAL;
 955         };
 956
 957         wcd->dai[dai->id].sconfig.rate = params_rate(params);
 958         wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
 959
 960         return 0;
 961 }
 962
 963 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
 964                            struct snd_soc_dai *dai)
 965 {
 966         struct wcd_slim_codec_dai_data *dai_data;
 967         struct wcd934x_codec *wcd;
 968
 969         wcd = snd_soc_component_get_drvdata(dai->component);
 970
 971         dai_data = &wcd->dai[dai->id];
 972
 973         kfree(dai_data->sconfig.chs);
 974
 975         return 0;
 976 }
 977
 978 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
 979                            struct snd_soc_dai *dai)
 980 {
 981         struct wcd_slim_codec_dai_data *dai_data;
 982         struct wcd934x_codec *wcd;
 983         struct slim_stream_config *cfg;
 984
 985         wcd = snd_soc_component_get_drvdata(dai->component);
 986
 987         dai_data = &wcd->dai[dai->id];
 988
 989         switch (cmd) {
 990         case SNDRV_PCM_TRIGGER_START:
 991         case SNDRV_PCM_TRIGGER_RESUME:
 992         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 993                 cfg = &dai_data->sconfig;
 994                 slim_stream_prepare(dai_data->sruntime, cfg);
 995                 slim_stream_enable(dai_data->sruntime);
 996                 break;
 997         case SNDRV_PCM_TRIGGER_STOP:
 998         case SNDRV_PCM_TRIGGER_SUSPEND:
 999         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1000                 slim_stream_unprepare(dai_data->sruntime);
1001                 slim_stream_disable(dai_data->sruntime);
1002                 break;
1003         default:
1004                 break;
1005         }
1006
1007         return 0;
1008 }
1009
1010 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1011                                    unsigned int tx_num, unsigned int *tx_slot,
1012                                    unsigned int rx_num, unsigned int *rx_slot)
1013 {
1014         struct wcd934x_codec *wcd;
1015         int i;
1016
1017         wcd = snd_soc_component_get_drvdata(dai->component);
1018
1019         if (!tx_slot || !rx_slot) {
1020                 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1021                         tx_slot, rx_slot);
1022                 return -EINVAL;
1023         }
1024
1025         if (wcd->rx_chs) {
1026                 wcd->num_rx_port = rx_num;
1027                 for (i = 0; i < rx_num; i++) {
1028                         wcd->rx_chs[i].ch_num = rx_slot[i];
1029                         INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1030                 }
1031         }
1032
1033         if (wcd->tx_chs) {
1034                 wcd->num_tx_port = tx_num;
1035                 for (i = 0; i < tx_num; i++) {
1036                         wcd->tx_chs[i].ch_num = tx_slot[i];
1037                         INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1038                 }
1039         }
1040
1041         return 0;
1042 }
1043
1044 static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
1045                                    unsigned int *tx_num, unsigned int *tx_slot,
1046                                    unsigned int *rx_num, unsigned int *rx_slot)
1047 {
1048         struct wcd934x_slim_ch *ch;
1049         struct wcd934x_codec *wcd;
1050         int i = 0;
1051
1052         wcd = snd_soc_component_get_drvdata(dai->component);
1053
1054         switch (dai->id) {
1055         case AIF1_PB:
1056         case AIF2_PB:
1057         case AIF3_PB:
1058         case AIF4_PB:
1059                 if (!rx_slot || !rx_num) {
1060                         dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1061                                 rx_slot, rx_num);
1062                         return -EINVAL;
1063                 }
1064
1065                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1066                         rx_slot[i++] = ch->ch_num;
1067
1068                 *rx_num = i;
1069                 break;
1070         case AIF1_CAP:
1071         case AIF2_CAP:
1072         case AIF3_CAP:
1073                 if (!tx_slot || !tx_num) {
1074                         dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1075                                 tx_slot, tx_num);
1076                         return -EINVAL;
1077                 }
1078
1079                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1080                         tx_slot[i++] = ch->ch_num;
1081
1082                 *tx_num = i;
1083                 break;
1084         default:
1085                 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
1086                 break;
1087         }
1088
1089         return 0;
1090 }
1091
1092 static struct snd_soc_dai_ops wcd934x_dai_ops = {
1093         .hw_params = wcd934x_hw_params,
1094         .hw_free = wcd934x_hw_free,
1095         .trigger = wcd934x_trigger,
1096         .set_channel_map = wcd934x_set_channel_map,
1097         .get_channel_map = wcd934x_get_channel_map,
1098 };
1099
1100 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
1101         [0] = {
1102                 .name = "wcd934x_rx1",
1103                 .id = AIF1_PB,
1104                 .playback = {
1105                         .stream_name = "AIF1 Playback",
1106                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1107                         .formats = WCD934X_FORMATS_S16_S24_LE,
1108                         .rate_max = 192000,
1109                         .rate_min = 8000,
1110                         .channels_min = 1,
1111                         .channels_max = 2,
1112                 },
1113                 .ops = &wcd934x_dai_ops,
1114         },
1115         [1] = {
1116                 .name = "wcd934x_tx1",
1117                 .id = AIF1_CAP,
1118                 .capture = {
1119                         .stream_name = "AIF1 Capture",
1120                         .rates = WCD934X_RATES_MASK,
1121                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1122                         .rate_min = 8000,
1123                         .rate_max = 192000,
1124                         .channels_min = 1,
1125                         .channels_max = 4,
1126                 },
1127                 .ops = &wcd934x_dai_ops,
1128         },
1129         [2] = {
1130                 .name = "wcd934x_rx2",
1131                 .id = AIF2_PB,
1132                 .playback = {
1133                         .stream_name = "AIF2 Playback",
1134                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1135                         .formats = WCD934X_FORMATS_S16_S24_LE,
1136                         .rate_min = 8000,
1137                         .rate_max = 192000,
1138                         .channels_min = 1,
1139                         .channels_max = 2,
1140                 },
1141                 .ops = &wcd934x_dai_ops,
1142         },
1143         [3] = {
1144                 .name = "wcd934x_tx2",
1145                 .id = AIF2_CAP,
1146                 .capture = {
1147                         .stream_name = "AIF2 Capture",
1148                         .rates = WCD934X_RATES_MASK,
1149                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1150                         .rate_min = 8000,
1151                         .rate_max = 192000,
1152                         .channels_min = 1,
1153                         .channels_max = 4,
1154                 },
1155                 .ops = &wcd934x_dai_ops,
1156         },
1157         [4] = {
1158                 .name = "wcd934x_rx3",
1159                 .id = AIF3_PB,
1160                 .playback = {
1161                         .stream_name = "AIF3 Playback",
1162                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1163                         .formats = WCD934X_FORMATS_S16_S24_LE,
1164                         .rate_min = 8000,
1165                         .rate_max = 192000,
1166                         .channels_min = 1,
1167                         .channels_max = 2,
1168                 },
1169                 .ops = &wcd934x_dai_ops,
1170         },
1171         [5] = {
1172                 .name = "wcd934x_tx3",
1173                 .id = AIF3_CAP,
1174                 .capture = {
1175                         .stream_name = "AIF3 Capture",
1176                         .rates = WCD934X_RATES_MASK,
1177                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1178                         .rate_min = 8000,
1179                         .rate_max = 192000,
1180                         .channels_min = 1,
1181                         .channels_max = 4,
1182                 },
1183                 .ops = &wcd934x_dai_ops,
1184         },
1185         [6] = {
1186                 .name = "wcd934x_rx4",
1187                 .id = AIF4_PB,
1188                 .playback = {
1189                         .stream_name = "AIF4 Playback",
1190                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1191                         .formats = WCD934X_FORMATS_S16_S24_LE,
1192                         .rate_min = 8000,
1193                         .rate_max = 192000,
1194                         .channels_min = 1,
1195                         .channels_max = 2,
1196                 },
1197                 .ops = &wcd934x_dai_ops,
1198         },
1199 };
1200
1201 static int swclk_gate_enable(struct clk_hw *hw)
1202 {
1203         return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
1204 }
1205
1206 static void swclk_gate_disable(struct clk_hw *hw)
1207 {
1208         wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
1209 }
1210
1211 static int swclk_gate_is_enabled(struct clk_hw *hw)
1212 {
1213         struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
1214         int ret, val;
1215
1216         regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
1217         ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
1218
1219         return ret;
1220 }
1221
1222 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
1223                                        unsigned long parent_rate)
1224 {
1225         return parent_rate / 2;
1226 }
1227
1228 static const struct clk_ops swclk_gate_ops = {
1229         .prepare = swclk_gate_enable,
1230         .unprepare = swclk_gate_disable,
1231         .is_enabled = swclk_gate_is_enabled,
1232         .recalc_rate = swclk_recalc_rate,
1233
1234 };
1235
1236 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
1237 {
1238         struct clk *parent = wcd->extclk;
1239         struct device *dev = wcd->dev;
1240         struct device_node *np = dev->parent->of_node;
1241         const char *parent_clk_name = NULL;
1242         const char *clk_name = "mclk";
1243         struct clk_hw *hw;
1244         struct clk_init_data init;
1245         int ret;
1246
1247         if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
1248                 return NULL;
1249
1250         parent_clk_name = __clk_get_name(parent);
1251
1252         of_property_read_string(np, "clock-output-names", &clk_name);
1253
1254         init.name = clk_name;
1255         init.ops = &swclk_gate_ops;
1256         init.flags = 0;
1257         init.parent_names = &parent_clk_name;
1258         init.num_parents = 1;
1259         wcd->hw.init = &init;
1260
1261         hw = &wcd->hw;
1262         ret = clk_hw_register(wcd->dev->parent, hw);
1263         if (ret)
1264                 return ERR_PTR(ret);
1265
1266         of_clk_add_provider(np, of_clk_src_simple_get, hw->clk);
1267
1268         return NULL;
1269 }
1270
1271 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias)
1272 {
1273         int mv;
1274
1275         if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
1276                 dev_err(dev, "%s value not found, using default\n", micbias);
1277                 mv = WCD934X_DEF_MICBIAS_MV;
1278         } else {
1279                 /* convert it to milli volts */
1280                 mv = mv/1000;
1281         }
1282
1283         if (mv < 1000 || mv > 2850) {
1284                 dev_err(dev, "%s value not in valid range, using default\n",
1285                         micbias);
1286                 mv = WCD934X_DEF_MICBIAS_MV;
1287         }
1288
1289         return (mv - 1000) / 50;
1290 }
1291
1292 static int wcd934x_init_dmic(struct snd_soc_component *comp)
1293 {
1294         int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
1295         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1296         u32 def_dmic_rate, dmic_clk_drv;
1297
1298         vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
1299                                              "qcom,micbias1-microvolt");
1300         vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
1301                                              "qcom,micbias2-microvolt");
1302         vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
1303                                              "qcom,micbias3-microvolt");
1304         vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
1305                                              "qcom,micbias4-microvolt");
1306
1307         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
1308                                       WCD934X_MICB_VAL_MASK, vout_ctl_1);
1309         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
1310                                       WCD934X_MICB_VAL_MASK, vout_ctl_2);
1311         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
1312                                       WCD934X_MICB_VAL_MASK, vout_ctl_3);
1313         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
1314                                       WCD934X_MICB_VAL_MASK, vout_ctl_4);
1315
1316         if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
1317                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
1318         else
1319                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
1320
1321         wcd->dmic_sample_rate = def_dmic_rate;
1322
1323         dmic_clk_drv = 0;
1324         snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
1325                                       0x0C, dmic_clk_drv << 2);
1326
1327         return 0;
1328 }
1329
1330 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
1331 {
1332         struct regmap *rm = wcd->regmap;
1333
1334         /* set SPKR rate to FS_2P4_3P072 */
1335         regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
1336         regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
1337
1338         /* Take DMICs out of reset */
1339         regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
1340 }
1341
1342 static int wcd934x_comp_init(struct snd_soc_component *component)
1343 {
1344         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1345
1346         wcd934x_hw_init(wcd);
1347         wcd934x_enable_efuse_sensing(wcd);
1348         wcd934x_get_version(wcd);
1349
1350         return 0;
1351 }
1352
1353 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
1354 {
1355         struct wcd934x_codec *wcd = data;
1356         unsigned long status = 0;
1357         int i, j, port_id;
1358         unsigned int val, int_val = 0;
1359         irqreturn_t ret = IRQ_NONE;
1360         bool tx;
1361         unsigned short reg = 0;
1362
1363         for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
1364              i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
1365                 regmap_read(wcd->if_regmap, i, &val);
1366                 status |= ((u32)val << (8 * j));
1367         }
1368
1369         for_each_set_bit(j, &status, 32) {
1370                 tx = false;
1371                 port_id = j;
1372
1373                 if (j >= 16) {
1374                         tx = true;
1375                         port_id = j - 16;
1376                 }
1377
1378                 regmap_read(wcd->if_regmap,
1379                             WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
1380                 if (val) {
1381                         if (!tx)
1382                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
1383                                         (port_id / 8);
1384                         else
1385                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
1386                                         (port_id / 8);
1387                         regmap_read(wcd->if_regmap, reg, &int_val);
1388                 }
1389
1390                 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
1391                         dev_err_ratelimited(wcd->dev,
1392                                             "overflow error on %s port %d, value %x\n",
1393                                             (tx ? "TX" : "RX"), port_id, val);
1394
1395                 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
1396                         dev_err_ratelimited(wcd->dev,
1397                                             "underflow error on %s port %d, value %x\n",
1398                                             (tx ? "TX" : "RX"), port_id, val);
1399
1400                 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
1401                     (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
1402                         if (!tx)
1403                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
1404                                         (port_id / 8);
1405                         else
1406                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
1407                                         (port_id / 8);
1408                         regmap_read(
1409                                 wcd->if_regmap, reg, &int_val);
1410                         if (int_val & (1 << (port_id % 8))) {
1411                                 int_val = int_val ^ (1 << (port_id % 8));
1412                                 regmap_write(wcd->if_regmap,
1413                                              reg, int_val);
1414                         }
1415                 }
1416
1417                 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
1418                         dev_err_ratelimited(wcd->dev,
1419                                             "Port Closed %s port %d, value %x\n",
1420                                             (tx ? "TX" : "RX"), port_id, val);
1421
1422                 regmap_write(wcd->if_regmap,
1423                              WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
1424                                 BIT(j % 8));
1425                 ret = IRQ_HANDLED;
1426         }
1427
1428         return ret;
1429 }
1430
1431 static int wcd934x_comp_probe(struct snd_soc_component *component)
1432 {
1433         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1434         int i;
1435
1436         snd_soc_component_init_regmap(component, wcd->regmap);
1437         wcd->component = component;
1438
1439         /* Class-H Init*/
1440         wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
1441         if (IS_ERR(wcd->clsh_ctrl))
1442                 return PTR_ERR(wcd->clsh_ctrl);
1443
1444         /* Default HPH Mode to Class-H Low HiFi */
1445         wcd->hph_mode = CLS_H_LOHIFI;
1446
1447         wcd934x_comp_init(component);
1448
1449         for (i = 0; i < NUM_CODEC_DAIS; i++)
1450                 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
1451
1452         wcd934x_init_dmic(component);
1453         return 0;
1454 }
1455
1456 static void wcd934x_comp_remove(struct snd_soc_component *comp)
1457 {
1458         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1459
1460         wcd_clsh_ctrl_free(wcd->clsh_ctrl);
1461 }
1462
1463 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
1464                                    int clk_id, int source,
1465                                    unsigned int freq, int dir)
1466 {
1467         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1468         int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
1469
1470         wcd->rate = freq;
1471
1472         if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
1473                 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
1474
1475         snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
1476                                       WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
1477                                       val);
1478
1479         return clk_set_rate(wcd->extclk, freq);
1480 }
1481
1482 static const struct snd_soc_component_driver wcd934x_component_drv = {
1483         .probe = wcd934x_comp_probe,
1484         .remove = wcd934x_comp_remove,
1485         .set_sysclk = wcd934x_comp_set_sysclk,
1486 };
1487
1488 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
1489 {
1490         struct device *dev = &wcd->sdev->dev;
1491         struct device_node *ifc_dev_np;
1492
1493         ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
1494         if (!ifc_dev_np) {
1495                 dev_err(dev, "No Interface device found\n");
1496                 return -EINVAL;
1497         }
1498
1499         wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
1500         if (!wcd->sidev) {
1501                 dev_err(dev, "Unable to get SLIM Interface device\n");
1502                 return -EINVAL;
1503         }
1504
1505         slim_get_logical_addr(wcd->sidev);
1506         wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
1507                                   &wcd934x_ifc_regmap_config);
1508         if (IS_ERR(wcd->if_regmap)) {
1509                 dev_err(dev, "Failed to allocate ifc register map\n");
1510                 return PTR_ERR(wcd->if_regmap);
1511         }
1512
1513         of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
1514                              &wcd->dmic_sample_rate);
1515
1516         return 0;
1517 }
1518
1519 static int wcd934x_codec_probe(struct platform_device *pdev)
1520 {
1521         struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent);
1522         struct wcd934x_codec *wcd;
1523         struct device *dev = &pdev->dev;
1524         int ret, irq;
1525
1526         wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL);
1527         if (!wcd)
1528                 return -ENOMEM;
1529
1530         wcd->dev = dev;
1531         wcd->regmap = data->regmap;
1532         wcd->extclk = data->extclk;
1533         wcd->sdev = to_slim_device(data->dev);
1534         mutex_init(&wcd->sysclk_mutex);
1535
1536         ret = wcd934x_codec_parse_data(wcd);
1537         if (ret) {
1538                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
1539                 return ret;
1540         }
1541
1542         /* set default rate 9P6MHz */
1543         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
1544                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
1545                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
1546         memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
1547         memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
1548
1549         irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
1550         if (irq < 0) {
1551                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
1552                 return irq;
1553         }
1554
1555         ret = devm_request_threaded_irq(dev, irq, NULL,
1556                                         wcd934x_slim_irq_handler,
1557                                         IRQF_TRIGGER_RISING,
1558                                         "slim", wcd);
1559         if (ret) {
1560                 dev_err(dev, "Failed to request slimbus irq\n");
1561                 return ret;
1562         }
1563
1564         wcd934x_register_mclk_output(wcd);
1565         platform_set_drvdata(pdev, wcd);
1566
1567         return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
1568                                                wcd934x_slim_dais,
1569                                                ARRAY_SIZE(wcd934x_slim_dais));
1570 }
1571
1572 static const struct platform_device_id wcd934x_driver_id[] = {
1573         {
1574                 .name = "wcd934x-codec",
1575         },
1576         {},
1577 };
1578 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
1579
1580 static struct platform_driver wcd934x_codec_driver = {
1581         .probe  = &wcd934x_codec_probe,
1582         .id_table = wcd934x_driver_id,
1583         .driver = {
1584                 .name   = "wcd934x-codec",
1585         }
1586 };
1587
1588 MODULE_ALIAS("platform:wcd934x-codec");
1589 module_platform_driver(wcd934x_codec_driver);
1590 MODULE_DESCRIPTION("WCD934x codec driver");
1591 MODULE_LICENSE("GPL v2");