sound/soc/codecs/wcd934x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/clk-provider.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/kernel.h>
   8 #include <linux/mfd/wcd934x/registers.h>
   9 #include <linux/mfd/wcd934x/wcd934x.h>
  10 #include <linux/module.h>
  11 #include <linux/mutex.h>
  12 #include <linux/of_clk.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/regmap.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <linux/slab.h>
  18 #include <linux/slimbus.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/soc.h>
  21 #include <sound/soc-dapm.h>
  22 #include <sound/tlv.h>
  23 #include "wcd-clsh-v2.h"
  24
  25 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  26                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  27                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  28 /* Fractional Rates */
  29 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  30                                  SNDRV_PCM_RATE_176400)
  31 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  32                                     SNDRV_PCM_FMTBIT_S24_LE)
  33
  34 /* slave port water mark level
  35  *   (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
  36  */
  37 #define SLAVE_PORT_WATER_MARK_6BYTES    0
  38 #define SLAVE_PORT_WATER_MARK_9BYTES    1
  39 #define SLAVE_PORT_WATER_MARK_12BYTES   2
  40 #define SLAVE_PORT_WATER_MARK_15BYTES   3
  41 #define SLAVE_PORT_WATER_MARK_SHIFT     1
  42 #define SLAVE_PORT_ENABLE               1
  43 #define SLAVE_PORT_DISABLE              0
  44 #define WCD934X_SLIM_WATER_MARK_VAL \
  45         ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
  46          (SLAVE_PORT_ENABLE))
  47
  48 #define WCD934X_SLIM_NUM_PORT_REG       3
  49 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
  50 #define WCD934X_SLIM_IRQ_OVERFLOW       BIT(0)
  51 #define WCD934X_SLIM_IRQ_UNDERFLOW      BIT(1)
  52 #define WCD934X_SLIM_IRQ_PORT_CLOSED    BIT(2)
  53
  54 #define WCD934X_MCLK_CLK_12P288MHZ      12288000
  55 #define WCD934X_MCLK_CLK_9P6MHZ         9600000
  56
  57 /* Only valid for 9.6 MHz mclk */
  58 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
  59 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
  60
  61 /* Only valid for 12.288 MHz mclk */
  62 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
  63
  64 #define WCD934X_DMIC_CLK_DIV_2          0x0
  65 #define WCD934X_DMIC_CLK_DIV_3          0x1
  66 #define WCD934X_DMIC_CLK_DIV_4          0x2
  67 #define WCD934X_DMIC_CLK_DIV_6          0x3
  68 #define WCD934X_DMIC_CLK_DIV_8          0x4
  69 #define WCD934X_DMIC_CLK_DIV_16         0x5
  70 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
  71
  72 #define TX_HPF_CUT_OFF_FREQ_MASK        0x60
  73 #define CF_MIN_3DB_4HZ                  0x0
  74 #define CF_MIN_3DB_75HZ                 0x1
  75 #define CF_MIN_3DB_150HZ                0x2
  76
  77 #define WCD934X_RX_START                16
  78 #define WCD934X_NUM_INTERPOLATORS       9
  79 #define WCD934X_RX_PATH_CTL_OFFSET      20
  80 #define WCD934X_MAX_VALID_ADC_MUX       13
  81 #define WCD934X_INVALID_ADC_MUX         9
  82
  83 #define WCD934X_SLIM_RX_CH(p) \
  84         {.port = p + WCD934X_RX_START, .shift = p,}
  85
  86 #define WCD934X_SLIM_TX_CH(p) \
  87         {.port = p, .shift = p,}
  88
  89 /* Feature masks to distinguish codec version */
  90 #define DSD_DISABLED_MASK   0
  91 #define SLNQ_DISABLED_MASK  1
  92
  93 #define DSD_DISABLED   BIT(DSD_DISABLED_MASK)
  94 #define SLNQ_DISABLED  BIT(SLNQ_DISABLED_MASK)
  95
  96 /* As fine version info cannot be retrieved before wcd probe.
  97  * Define three coarse versions for possible future use before wcd probe.
  98  */
  99 #define WCD_VERSION_WCD9340_1_0     0x400
 100 #define WCD_VERSION_WCD9341_1_0     0x410
 101 #define WCD_VERSION_WCD9340_1_1     0x401
 102 #define WCD_VERSION_WCD9341_1_1     0x411
 103 #define WCD934X_AMIC_PWR_LEVEL_LP       0
 104 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT  1
 105 #define WCD934X_AMIC_PWR_LEVEL_HP       2
 106 #define WCD934X_AMIC_PWR_LEVEL_HYBRID   3
 107 #define WCD934X_AMIC_PWR_LVL_MASK       0x60
 108 #define WCD934X_AMIC_PWR_LVL_SHIFT      0x5
 109
 110 #define WCD934X_DEC_PWR_LVL_MASK        0x06
 111 #define WCD934X_DEC_PWR_LVL_LP          0x02
 112 #define WCD934X_DEC_PWR_LVL_HP          0x04
 113 #define WCD934X_DEC_PWR_LVL_DF          0x00
 114 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
 115
 116 #define WCD934X_DEF_MICBIAS_MV  1800
 117 #define WCD934X_MAX_MICBIAS_MV  2850
 118
 119 #define WCD_IIR_FILTER_SIZE     (sizeof(u32) * BAND_MAX)
 120
 121 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
 122 { \
 123         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 124         .info = wcd934x_iir_filter_info, \
 125         .get = wcd934x_get_iir_band_audio_mixer, \
 126         .put = wcd934x_put_iir_band_audio_mixer, \
 127         .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
 128                 .iir_idx = iidx, \
 129                 .band_idx = bidx, \
 130                 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
 131         } \
 132 }
 133
 134 #define WCD934X_INTERPOLATOR_PATH(id)                   \
 135         {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"},       \
 136         {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"},       \
 137         {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"},       \
 138         {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"},       \
 139         {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"},       \
 140         {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"},       \
 141         {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"},       \
 142         {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"},       \
 143         {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"},  \
 144         {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"},  \
 145         {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"},       \
 146         {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"},       \
 147         {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"},       \
 148         {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"},       \
 149         {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"},       \
 150         {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"},       \
 151         {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"},       \
 152         {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"},       \
 153         {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"},  \
 154         {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"},  \
 155         {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"},       \
 156         {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"},       \
 157         {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"},       \
 158         {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"},       \
 159         {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"},       \
 160         {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"},       \
 161         {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"},       \
 162         {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"},       \
 163         {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"},          \
 164         {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"},          \
 165         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
 166         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
 167         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
 168         {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"},     \
 169         {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"},     \
 170         {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"},     \
 171         {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"},     \
 172         {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"},     \
 173         {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"},     \
 174         {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"},     \
 175         {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"},     \
 176         {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
 177         {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
 178         {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"},        \
 179         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"},      \
 180         {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"},       \
 181         {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"},     \
 182         {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"},  \
 183         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
 184
 185 #define WCD934X_INTERPOLATOR_MIX2(id)                   \
 186         {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
 187         {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
 188
 189 #define WCD934X_SLIM_RX_AIF_PATH(id)    \
 190         {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"},     \
 191         {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"},     \
 192         {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"},     \
 193         {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"},   \
 194         {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
 195
 196 #define WCD934X_ADC_MUX(id) \
 197         {"ADC MUX" #id, "DMIC", "DMIC MUX" #id },       \
 198         {"ADC MUX" #id, "AMIC", "AMIC MUX" #id },       \
 199         {"DMIC MUX" #id, "DMIC0", "DMIC0"},             \
 200         {"DMIC MUX" #id, "DMIC1", "DMIC1"},             \
 201         {"DMIC MUX" #id, "DMIC2", "DMIC2"},             \
 202         {"DMIC MUX" #id, "DMIC3", "DMIC3"},             \
 203         {"DMIC MUX" #id, "DMIC4", "DMIC4"},             \
 204         {"DMIC MUX" #id, "DMIC5", "DMIC5"},             \
 205         {"AMIC MUX" #id, "ADC1", "ADC1"},               \
 206         {"AMIC MUX" #id, "ADC2", "ADC2"},               \
 207         {"AMIC MUX" #id, "ADC3", "ADC3"},               \
 208         {"AMIC MUX" #id, "ADC4", "ADC4"}
 209
 210 #define WCD934X_IIR_INP_MUX(id) \
 211         {"IIR" #id, NULL, "IIR" #id " INP0 MUX"},       \
 212         {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"},    \
 213         {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"},    \
 214         {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"},    \
 215         {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"},    \
 216         {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"},    \
 217         {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"},    \
 218         {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"},    \
 219         {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"},    \
 220         {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"},    \
 221         {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"},     \
 222         {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"},     \
 223         {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"},     \
 224         {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"},     \
 225         {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"},     \
 226         {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"},     \
 227         {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"},     \
 228         {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"},     \
 229         {"IIR" #id, NULL, "IIR" #id " INP1 MUX"},       \
 230         {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"},    \
 231         {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"},    \
 232         {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"},    \
 233         {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"},    \
 234         {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"},    \
 235         {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"},    \
 236         {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"},    \
 237         {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"},    \
 238         {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"},    \
 239         {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"},     \
 240         {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"},     \
 241         {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"},     \
 242         {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"},     \
 243         {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"},     \
 244         {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"},     \
 245         {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"},     \
 246         {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"},     \
 247         {"IIR" #id, NULL, "IIR" #id " INP2 MUX"},       \
 248         {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"},    \
 249         {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"},    \
 250         {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"},    \
 251         {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"},    \
 252         {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"},    \
 253         {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"},    \
 254         {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"},    \
 255         {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"},    \
 256         {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"},    \
 257         {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"},     \
 258         {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"},     \
 259         {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"},     \
 260         {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"},     \
 261         {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"},     \
 262         {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"},     \
 263         {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"},     \
 264         {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"},     \
 265         {"IIR" #id, NULL, "IIR" #id " INP3 MUX"},       \
 266         {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"},    \
 267         {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"},    \
 268         {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"},    \
 269         {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"},    \
 270         {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"},    \
 271         {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"},    \
 272         {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"},    \
 273         {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"},    \
 274         {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"},    \
 275         {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"},     \
 276         {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"},     \
 277         {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"},     \
 278         {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"},     \
 279         {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"},     \
 280         {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"},     \
 281         {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"},     \
 282         {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
 283
 284 #define WCD934X_SLIM_TX_AIF_PATH(id)    \
 285         {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 286         {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 287         {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id },      \
 288         {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
 289
 290 enum {
 291         MIC_BIAS_1 = 1,
 292         MIC_BIAS_2,
 293         MIC_BIAS_3,
 294         MIC_BIAS_4
 295 };
 296
 297 enum {
 298         SIDO_SOURCE_INTERNAL,
 299         SIDO_SOURCE_RCO_BG,
 300 };
 301
 302 enum {
 303         INTERP_EAR = 0,
 304         INTERP_HPHL,
 305         INTERP_HPHR,
 306         INTERP_LO1,
 307         INTERP_LO2,
 308         INTERP_LO3_NA, /* LO3 not avalible in Tavil */
 309         INTERP_LO4_NA,
 310         INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
 311         INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
 312         INTERP_MAX,
 313 };
 314
 315 enum {
 316         WCD934X_RX0 = 0,
 317         WCD934X_RX1,
 318         WCD934X_RX2,
 319         WCD934X_RX3,
 320         WCD934X_RX4,
 321         WCD934X_RX5,
 322         WCD934X_RX6,
 323         WCD934X_RX7,
 324         WCD934X_RX8,
 325         WCD934X_RX9,
 326         WCD934X_RX10,
 327         WCD934X_RX11,
 328         WCD934X_RX12,
 329         WCD934X_RX_MAX,
 330 };
 331
 332 enum {
 333         WCD934X_TX0 = 0,
 334         WCD934X_TX1,
 335         WCD934X_TX2,
 336         WCD934X_TX3,
 337         WCD934X_TX4,
 338         WCD934X_TX5,
 339         WCD934X_TX6,
 340         WCD934X_TX7,
 341         WCD934X_TX8,
 342         WCD934X_TX9,
 343         WCD934X_TX10,
 344         WCD934X_TX11,
 345         WCD934X_TX12,
 346         WCD934X_TX13,
 347         WCD934X_TX14,
 348         WCD934X_TX15,
 349         WCD934X_TX_MAX,
 350 };
 351
 352 struct wcd934x_slim_ch {
 353         u32 ch_num;
 354         u16 port;
 355         u16 shift;
 356         struct list_head list;
 357 };
 358
 359 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
 360         WCD934X_SLIM_TX_CH(0),
 361         WCD934X_SLIM_TX_CH(1),
 362         WCD934X_SLIM_TX_CH(2),
 363         WCD934X_SLIM_TX_CH(3),
 364         WCD934X_SLIM_TX_CH(4),
 365         WCD934X_SLIM_TX_CH(5),
 366         WCD934X_SLIM_TX_CH(6),
 367         WCD934X_SLIM_TX_CH(7),
 368         WCD934X_SLIM_TX_CH(8),
 369         WCD934X_SLIM_TX_CH(9),
 370         WCD934X_SLIM_TX_CH(10),
 371         WCD934X_SLIM_TX_CH(11),
 372         WCD934X_SLIM_TX_CH(12),
 373         WCD934X_SLIM_TX_CH(13),
 374         WCD934X_SLIM_TX_CH(14),
 375         WCD934X_SLIM_TX_CH(15),
 376 };
 377
 378 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
 379         WCD934X_SLIM_RX_CH(0),   /* 16 */
 380         WCD934X_SLIM_RX_CH(1),   /* 17 */
 381         WCD934X_SLIM_RX_CH(2),
 382         WCD934X_SLIM_RX_CH(3),
 383         WCD934X_SLIM_RX_CH(4),
 384         WCD934X_SLIM_RX_CH(5),
 385         WCD934X_SLIM_RX_CH(6),
 386         WCD934X_SLIM_RX_CH(7),
 387         WCD934X_SLIM_RX_CH(8),
 388         WCD934X_SLIM_RX_CH(9),
 389         WCD934X_SLIM_RX_CH(10),
 390         WCD934X_SLIM_RX_CH(11),
 391         WCD934X_SLIM_RX_CH(12),
 392 };
 393
 394 /* Codec supports 2 IIR filters */
 395 enum {
 396         IIR0 = 0,
 397         IIR1,
 398         IIR_MAX,
 399 };
 400
 401 /* Each IIR has 5 Filter Stages */
 402 enum {
 403         BAND1 = 0,
 404         BAND2,
 405         BAND3,
 406         BAND4,
 407         BAND5,
 408         BAND_MAX,
 409 };
 410
 411 enum {
 412         COMPANDER_1, /* HPH_L */
 413         COMPANDER_2, /* HPH_R */
 414         COMPANDER_3, /* LO1_DIFF */
 415         COMPANDER_4, /* LO2_DIFF */
 416         COMPANDER_5, /* LO3_SE - not used in Tavil */
 417         COMPANDER_6, /* LO4_SE - not used in Tavil */
 418         COMPANDER_7, /* SWR SPK CH1 */
 419         COMPANDER_8, /* SWR SPK CH2 */
 420         COMPANDER_MAX,
 421 };
 422
 423 enum {
 424         AIF1_PB = 0,
 425         AIF1_CAP,
 426         AIF2_PB,
 427         AIF2_CAP,
 428         AIF3_PB,
 429         AIF3_CAP,
 430         AIF4_PB,
 431         AIF4_VIFEED,
 432         AIF4_MAD_TX,
 433         NUM_CODEC_DAIS,
 434 };
 435
 436 enum {
 437         INTn_1_INP_SEL_ZERO = 0,
 438         INTn_1_INP_SEL_DEC0,
 439         INTn_1_INP_SEL_DEC1,
 440         INTn_1_INP_SEL_IIR0,
 441         INTn_1_INP_SEL_IIR1,
 442         INTn_1_INP_SEL_RX0,
 443         INTn_1_INP_SEL_RX1,
 444         INTn_1_INP_SEL_RX2,
 445         INTn_1_INP_SEL_RX3,
 446         INTn_1_INP_SEL_RX4,
 447         INTn_1_INP_SEL_RX5,
 448         INTn_1_INP_SEL_RX6,
 449         INTn_1_INP_SEL_RX7,
 450 };
 451
 452 enum {
 453         INTn_2_INP_SEL_ZERO = 0,
 454         INTn_2_INP_SEL_RX0,
 455         INTn_2_INP_SEL_RX1,
 456         INTn_2_INP_SEL_RX2,
 457         INTn_2_INP_SEL_RX3,
 458         INTn_2_INP_SEL_RX4,
 459         INTn_2_INP_SEL_RX5,
 460         INTn_2_INP_SEL_RX6,
 461         INTn_2_INP_SEL_RX7,
 462         INTn_2_INP_SEL_PROXIMITY,
 463 };
 464
 465 enum {
 466         INTERP_MAIN_PATH,
 467         INTERP_MIX_PATH,
 468 };
 469
 470 struct interp_sample_rate {
 471         int sample_rate;
 472         int rate_val;
 473 };
 474
 475 static struct interp_sample_rate sr_val_tbl[] = {
 476         {8000, 0x0},
 477         {16000, 0x1},
 478         {32000, 0x3},
 479         {48000, 0x4},
 480         {96000, 0x5},
 481         {192000, 0x6},
 482         {384000, 0x7},
 483         {44100, 0x9},
 484         {88200, 0xA},
 485         {176400, 0xB},
 486         {352800, 0xC},
 487 };
 488
 489 struct wcd_slim_codec_dai_data {
 490         struct list_head slim_ch_list;
 491         struct slim_stream_config sconfig;
 492         struct slim_stream_runtime *sruntime;
 493 };
 494
 495 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
 496         {
 497                 .name = "WCD9335-IFC-DEV",
 498                 .range_min =  0x0,
 499                 .range_max = 0xffff,
 500                 .selector_reg = 0x800,
 501                 .selector_mask = 0xfff,
 502                 .selector_shift = 0,
 503                 .window_start = 0x800,
 504                 .window_len = 0x400,
 505         },
 506 };
 507
 508 static struct regmap_config wcd934x_ifc_regmap_config = {
 509         .reg_bits = 16,
 510         .val_bits = 8,
 511         .max_register = 0xffff,
 512         .ranges = wcd934x_ifc_ranges,
 513         .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
 514 };
 515
 516 struct wcd934x_codec {
 517         struct device *dev;
 518         struct clk_hw hw;
 519         struct clk *extclk;
 520         struct regmap *regmap;
 521         struct regmap *if_regmap;
 522         struct slim_device *sdev;
 523         struct slim_device *sidev;
 524         struct wcd_clsh_ctrl *clsh_ctrl;
 525         struct snd_soc_component *component;
 526         struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
 527         struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
 528         struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
 529         int rate;
 530         u32 version;
 531         u32 hph_mode;
 532         int num_rx_port;
 533         int num_tx_port;
 534         u32 tx_port_value[WCD934X_TX_MAX];
 535         u32 rx_port_value[WCD934X_RX_MAX];
 536         int sido_input_src;
 537         int dmic_0_1_clk_cnt;
 538         int dmic_2_3_clk_cnt;
 539         int dmic_4_5_clk_cnt;
 540         int dmic_sample_rate;
 541         int comp_enabled[COMPANDER_MAX];
 542         int sysclk_users;
 543         struct mutex sysclk_mutex;
 544 };
 545
 546 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
 547
 548 struct wcd_iir_filter_ctl {
 549         unsigned int iir_idx;
 550         unsigned int band_idx;
 551         struct soc_bytes_ext bytes_ext;
 552 };
 553
 554 static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
 555 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 556 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 557 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
 558
 559 /* Cutoff frequency for high pass filter */
 560 static const char * const cf_text[] = {
 561         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
 562 };
 563
 564 static const char * const rx_cf_text[] = {
 565         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
 566         "CF_NEG_3DB_0P48HZ"
 567 };
 568
 569 static const char * const rx_hph_mode_mux_text[] = {
 570         "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
 571         "Class-H Hi-Fi Low Power"
 572 };
 573
 574 static const char *const slim_rx_mux_text[] = {
 575         "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
 576 };
 577
 578 static const char * const rx_int0_7_mix_mux_text[] = {
 579         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 580         "RX6", "RX7", "PROXIMITY"
 581 };
 582
 583 static const char * const rx_int_mix_mux_text[] = {
 584         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 585         "RX6", "RX7"
 586 };
 587
 588 static const char * const rx_prim_mix_text[] = {
 589         "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
 590         "RX3", "RX4", "RX5", "RX6", "RX7"
 591 };
 592
 593 static const char * const rx_sidetone_mix_text[] = {
 594         "ZERO", "SRC0", "SRC1", "SRC_SUM"
 595 };
 596
 597 static const char * const iir_inp_mux_text[] = {
 598         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
 599         "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
 600 };
 601
 602 static const char * const rx_int_dem_inp_mux_text[] = {
 603         "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
 604 };
 605
 606 static const char * const rx_int0_1_interp_mux_text[] = {
 607         "ZERO", "RX INT0_1 MIX1",
 608 };
 609
 610 static const char * const rx_int1_1_interp_mux_text[] = {
 611         "ZERO", "RX INT1_1 MIX1",
 612 };
 613
 614 static const char * const rx_int2_1_interp_mux_text[] = {
 615         "ZERO", "RX INT2_1 MIX1",
 616 };
 617
 618 static const char * const rx_int3_1_interp_mux_text[] = {
 619         "ZERO", "RX INT3_1 MIX1",
 620 };
 621
 622 static const char * const rx_int4_1_interp_mux_text[] = {
 623         "ZERO", "RX INT4_1 MIX1",
 624 };
 625
 626 static const char * const rx_int7_1_interp_mux_text[] = {
 627         "ZERO", "RX INT7_1 MIX1",
 628 };
 629
 630 static const char * const rx_int8_1_interp_mux_text[] = {
 631         "ZERO", "RX INT8_1 MIX1",
 632 };
 633
 634 static const char * const rx_int0_2_interp_mux_text[] = {
 635         "ZERO", "RX INT0_2 MUX",
 636 };
 637
 638 static const char * const rx_int1_2_interp_mux_text[] = {
 639         "ZERO", "RX INT1_2 MUX",
 640 };
 641
 642 static const char * const rx_int2_2_interp_mux_text[] = {
 643         "ZERO", "RX INT2_2 MUX",
 644 };
 645
 646 static const char * const rx_int3_2_interp_mux_text[] = {
 647         "ZERO", "RX INT3_2 MUX",
 648 };
 649
 650 static const char * const rx_int4_2_interp_mux_text[] = {
 651         "ZERO", "RX INT4_2 MUX",
 652 };
 653
 654 static const char * const rx_int7_2_interp_mux_text[] = {
 655         "ZERO", "RX INT7_2 MUX",
 656 };
 657
 658 static const char * const rx_int8_2_interp_mux_text[] = {
 659         "ZERO", "RX INT8_2 MUX",
 660 };
 661
 662 static const char * const dmic_mux_text[] = {
 663         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
 664 };
 665
 666 static const char * const amic_mux_text[] = {
 667         "ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
 668 };
 669
 670 static const char * const amic4_5_sel_text[] = {
 671         "AMIC4", "AMIC5"
 672 };
 673
 674 static const char * const adc_mux_text[] = {
 675         "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
 676 };
 677
 678 static const char * const cdc_if_tx0_mux_text[] = {
 679         "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
 680 };
 681
 682 static const char * const cdc_if_tx1_mux_text[] = {
 683         "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
 684 };
 685
 686 static const char * const cdc_if_tx2_mux_text[] = {
 687         "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
 688 };
 689
 690 static const char * const cdc_if_tx3_mux_text[] = {
 691         "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
 692 };
 693
 694 static const char * const cdc_if_tx4_mux_text[] = {
 695         "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
 696 };
 697
 698 static const char * const cdc_if_tx5_mux_text[] = {
 699         "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
 700 };
 701
 702 static const char * const cdc_if_tx6_mux_text[] = {
 703         "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
 704 };
 705
 706 static const char * const cdc_if_tx7_mux_text[] = {
 707         "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
 708 };
 709
 710 static const char * const cdc_if_tx8_mux_text[] = {
 711         "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
 712 };
 713
 714 static const char * const cdc_if_tx9_mux_text[] = {
 715         "ZERO", "DEC7", "DEC7_192"
 716 };
 717
 718 static const char * const cdc_if_tx10_mux_text[] = {
 719         "ZERO", "DEC6", "DEC6_192"
 720 };
 721
 722 static const char * const cdc_if_tx11_mux_text[] = {
 723         "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
 724 };
 725
 726 static const char * const cdc_if_tx11_inp1_mux_text[] = {
 727         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
 728         "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
 729 };
 730
 731 static const char * const cdc_if_tx13_mux_text[] = {
 732         "CDC_DEC_5", "MAD_BRDCST"
 733 };
 734
 735 static const char * const cdc_if_tx13_inp1_mux_text[] = {
 736         "ZERO", "DEC5", "DEC5_192"
 737 };
 738
 739 static const struct soc_enum cf_dec0_enum =
 740         SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
 741
 742 static const struct soc_enum cf_dec1_enum =
 743         SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
 744
 745 static const struct soc_enum cf_dec2_enum =
 746         SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
 747
 748 static const struct soc_enum cf_dec3_enum =
 749         SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
 750
 751 static const struct soc_enum cf_dec4_enum =
 752         SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
 753
 754 static const struct soc_enum cf_dec5_enum =
 755         SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
 756
 757 static const struct soc_enum cf_dec6_enum =
 758         SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
 759
 760 static const struct soc_enum cf_dec7_enum =
 761         SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
 762
 763 static const struct soc_enum cf_dec8_enum =
 764         SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
 765
 766 static const struct soc_enum cf_int0_1_enum =
 767         SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
 768
 769 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
 770                      rx_cf_text);
 771
 772 static const struct soc_enum cf_int1_1_enum =
 773         SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
 774
 775 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
 776                      rx_cf_text);
 777
 778 static const struct soc_enum cf_int2_1_enum =
 779         SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
 780
 781 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
 782                      rx_cf_text);
 783
 784 static const struct soc_enum cf_int3_1_enum =
 785         SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
 786
 787 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
 788                             rx_cf_text);
 789
 790 static const struct soc_enum cf_int4_1_enum =
 791         SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
 792
 793 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
 794                             rx_cf_text);
 795
 796 static const struct soc_enum cf_int7_1_enum =
 797         SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
 798
 799 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
 800                             rx_cf_text);
 801
 802 static const struct soc_enum cf_int8_1_enum =
 803         SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
 804
 805 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
 806                             rx_cf_text);
 807
 808 static const struct soc_enum rx_hph_mode_mux_enum =
 809         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
 810                             rx_hph_mode_mux_text);
 811
 812 static const struct soc_enum slim_rx_mux_enum =
 813         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
 814
 815 static const struct soc_enum rx_int0_2_mux_chain_enum =
 816         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
 817                         rx_int0_7_mix_mux_text);
 818
 819 static const struct soc_enum rx_int1_2_mux_chain_enum =
 820         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
 821                         rx_int_mix_mux_text);
 822
 823 static const struct soc_enum rx_int2_2_mux_chain_enum =
 824         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
 825                         rx_int_mix_mux_text);
 826
 827 static const struct soc_enum rx_int3_2_mux_chain_enum =
 828         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
 829                         rx_int_mix_mux_text);
 830
 831 static const struct soc_enum rx_int4_2_mux_chain_enum =
 832         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
 833                         rx_int_mix_mux_text);
 834
 835 static const struct soc_enum rx_int7_2_mux_chain_enum =
 836         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
 837                         rx_int0_7_mix_mux_text);
 838
 839 static const struct soc_enum rx_int8_2_mux_chain_enum =
 840         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
 841                         rx_int_mix_mux_text);
 842
 843 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
 844         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
 845                         rx_prim_mix_text);
 846
 847 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
 848         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
 849                         rx_prim_mix_text);
 850
 851 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
 852         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
 853                         rx_prim_mix_text);
 854
 855 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
 856         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
 857                         rx_prim_mix_text);
 858
 859 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
 860         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
 861                         rx_prim_mix_text);
 862
 863 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
 864         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
 865                         rx_prim_mix_text);
 866
 867 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
 868         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
 869                         rx_prim_mix_text);
 870
 871 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
 872         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
 873                         rx_prim_mix_text);
 874
 875 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
 876         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
 877                         rx_prim_mix_text);
 878
 879 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
 880         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
 881                         rx_prim_mix_text);
 882
 883 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
 884         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
 885                         rx_prim_mix_text);
 886
 887 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
 888         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
 889                         rx_prim_mix_text);
 890
 891 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
 892         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
 893                         rx_prim_mix_text);
 894
 895 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
 896         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
 897                         rx_prim_mix_text);
 898
 899 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
 900         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
 901                         rx_prim_mix_text);
 902
 903 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
 904         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
 905                         rx_prim_mix_text);
 906
 907 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
 908         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
 909                         rx_prim_mix_text);
 910
 911 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
 912         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
 913                         rx_prim_mix_text);
 914
 915 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
 916         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
 917                         rx_prim_mix_text);
 918
 919 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
 920         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
 921                         rx_prim_mix_text);
 922
 923 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
 924         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
 925                         rx_prim_mix_text);
 926
 927 static const struct soc_enum rx_int0_mix2_inp_mux_enum =
 928         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
 929                         rx_sidetone_mix_text);
 930
 931 static const struct soc_enum rx_int1_mix2_inp_mux_enum =
 932         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
 933                         rx_sidetone_mix_text);
 934
 935 static const struct soc_enum rx_int2_mix2_inp_mux_enum =
 936         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
 937                         rx_sidetone_mix_text);
 938
 939 static const struct soc_enum rx_int3_mix2_inp_mux_enum =
 940         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
 941                         rx_sidetone_mix_text);
 942
 943 static const struct soc_enum rx_int4_mix2_inp_mux_enum =
 944         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
 945                         rx_sidetone_mix_text);
 946
 947 static const struct soc_enum rx_int7_mix2_inp_mux_enum =
 948         SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
 949                         rx_sidetone_mix_text);
 950
 951 static const struct soc_enum iir0_inp0_mux_enum =
 952         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
 953                         0, 18, iir_inp_mux_text);
 954
 955 static const struct soc_enum iir0_inp1_mux_enum =
 956         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
 957                         0, 18, iir_inp_mux_text);
 958
 959 static const struct soc_enum iir0_inp2_mux_enum =
 960         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
 961                         0, 18, iir_inp_mux_text);
 962
 963 static const struct soc_enum iir0_inp3_mux_enum =
 964         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
 965                         0, 18, iir_inp_mux_text);
 966
 967 static const struct soc_enum iir1_inp0_mux_enum =
 968         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
 969                         0, 18, iir_inp_mux_text);
 970
 971 static const struct soc_enum iir1_inp1_mux_enum =
 972         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
 973                         0, 18, iir_inp_mux_text);
 974
 975 static const struct soc_enum iir1_inp2_mux_enum =
 976         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
 977                         0, 18, iir_inp_mux_text);
 978
 979 static const struct soc_enum iir1_inp3_mux_enum =
 980         SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
 981                         0, 18, iir_inp_mux_text);
 982
 983 static const struct soc_enum rx_int0_dem_inp_mux_enum =
 984         SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
 985                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 986                         rx_int_dem_inp_mux_text);
 987
 988 static const struct soc_enum rx_int1_dem_inp_mux_enum =
 989         SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
 990                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 991                         rx_int_dem_inp_mux_text);
 992
 993 static const struct soc_enum rx_int2_dem_inp_mux_enum =
 994         SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
 995                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 996                         rx_int_dem_inp_mux_text);
 997
 998 static const struct soc_enum tx_adc_mux0_enum =
 999         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
1000                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1001 static const struct soc_enum tx_adc_mux1_enum =
1002         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
1003                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1004 static const struct soc_enum tx_adc_mux2_enum =
1005         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
1006                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1007 static const struct soc_enum tx_adc_mux3_enum =
1008         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
1009                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1010 static const struct soc_enum tx_adc_mux4_enum =
1011         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
1012                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1013 static const struct soc_enum tx_adc_mux5_enum =
1014         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
1015                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1016 static const struct soc_enum tx_adc_mux6_enum =
1017         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
1018                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1019 static const struct soc_enum tx_adc_mux7_enum =
1020         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
1021                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1022 static const struct soc_enum tx_adc_mux8_enum =
1023         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
1024                         ARRAY_SIZE(adc_mux_text), adc_mux_text);
1025
1026 static const struct soc_enum rx_int0_1_interp_mux_enum =
1027         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1028                         rx_int0_1_interp_mux_text);
1029
1030 static const struct soc_enum rx_int1_1_interp_mux_enum =
1031         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1032                         rx_int1_1_interp_mux_text);
1033
1034 static const struct soc_enum rx_int2_1_interp_mux_enum =
1035         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2,
1036                         rx_int2_1_interp_mux_text);
1037
1038 static const struct soc_enum rx_int3_1_interp_mux_enum =
1039         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int3_1_interp_mux_text);
1040
1041 static const struct soc_enum rx_int4_1_interp_mux_enum =
1042         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int4_1_interp_mux_text);
1043
1044 static const struct soc_enum rx_int7_1_interp_mux_enum =
1045         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int7_1_interp_mux_text);
1046
1047 static const struct soc_enum rx_int8_1_interp_mux_enum =
1048         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int8_1_interp_mux_text);
1049
1050 static const struct soc_enum rx_int0_2_interp_mux_enum =
1051         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int0_2_interp_mux_text);
1052
1053 static const struct soc_enum rx_int1_2_interp_mux_enum =
1054         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int1_2_interp_mux_text);
1055
1056 static const struct soc_enum rx_int2_2_interp_mux_enum =
1057         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int2_2_interp_mux_text);
1058
1059 static const struct soc_enum rx_int3_2_interp_mux_enum =
1060         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int3_2_interp_mux_text);
1061
1062 static const struct soc_enum rx_int4_2_interp_mux_enum =
1063         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int4_2_interp_mux_text);
1064
1065 static const struct soc_enum rx_int7_2_interp_mux_enum =
1066         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int7_2_interp_mux_text);
1067
1068 static const struct soc_enum rx_int8_2_interp_mux_enum =
1069         SOC_ENUM_SINGLE(SND_SOC_NOPM,   0, 2, rx_int8_2_interp_mux_text);
1070
1071 static const struct soc_enum tx_dmic_mux0_enum =
1072         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
1073                         dmic_mux_text);
1074
1075 static const struct soc_enum tx_dmic_mux1_enum =
1076         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
1077                         dmic_mux_text);
1078
1079 static const struct soc_enum tx_dmic_mux2_enum =
1080         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
1081                         dmic_mux_text);
1082
1083 static const struct soc_enum tx_dmic_mux3_enum =
1084         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
1085                         dmic_mux_text);
1086
1087 static const struct soc_enum tx_dmic_mux4_enum =
1088         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
1089                         dmic_mux_text);
1090
1091 static const struct soc_enum tx_dmic_mux5_enum =
1092         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
1093                         dmic_mux_text);
1094
1095 static const struct soc_enum tx_dmic_mux6_enum =
1096         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
1097                         dmic_mux_text);
1098
1099 static const struct soc_enum tx_dmic_mux7_enum =
1100         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
1101                         dmic_mux_text);
1102
1103 static const struct soc_enum tx_dmic_mux8_enum =
1104         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
1105                         dmic_mux_text);
1106
1107 static const struct soc_enum tx_amic_mux0_enum =
1108         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
1109                         amic_mux_text);
1110 static const struct soc_enum tx_amic_mux1_enum =
1111         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
1112                         amic_mux_text);
1113 static const struct soc_enum tx_amic_mux2_enum =
1114         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
1115                         amic_mux_text);
1116 static const struct soc_enum tx_amic_mux3_enum =
1117         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
1118                         amic_mux_text);
1119 static const struct soc_enum tx_amic_mux4_enum =
1120         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
1121                         amic_mux_text);
1122 static const struct soc_enum tx_amic_mux5_enum =
1123         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
1124                         amic_mux_text);
1125 static const struct soc_enum tx_amic_mux6_enum =
1126         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
1127                         amic_mux_text);
1128 static const struct soc_enum tx_amic_mux7_enum =
1129         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
1130                         amic_mux_text);
1131 static const struct soc_enum tx_amic_mux8_enum =
1132         SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
1133                         amic_mux_text);
1134
1135 static const struct soc_enum tx_amic4_5_enum =
1136         SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
1137
1138 static const struct soc_enum cdc_if_tx0_mux_enum =
1139         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
1140                         ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
1141 static const struct soc_enum cdc_if_tx1_mux_enum =
1142         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
1143                         ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
1144 static const struct soc_enum cdc_if_tx2_mux_enum =
1145         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
1146                         ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
1147 static const struct soc_enum cdc_if_tx3_mux_enum =
1148         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
1149                         ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
1150 static const struct soc_enum cdc_if_tx4_mux_enum =
1151         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
1152                         ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
1153 static const struct soc_enum cdc_if_tx5_mux_enum =
1154         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
1155                         ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
1156 static const struct soc_enum cdc_if_tx6_mux_enum =
1157         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
1158                         ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
1159 static const struct soc_enum cdc_if_tx7_mux_enum =
1160         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
1161                         ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
1162 static const struct soc_enum cdc_if_tx8_mux_enum =
1163         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
1164                         ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
1165 static const struct soc_enum cdc_if_tx9_mux_enum =
1166         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
1167                         ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
1168 static const struct soc_enum cdc_if_tx10_mux_enum =
1169         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
1170                         ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
1171 static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
1172         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
1173                         ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
1174                         cdc_if_tx11_inp1_mux_text);
1175 static const struct soc_enum cdc_if_tx11_mux_enum =
1176         SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
1177                         ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
1178 static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
1179         SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
1180                         ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
1181                         cdc_if_tx13_inp1_mux_text);
1182 static const struct soc_enum cdc_if_tx13_mux_enum =
1183         SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
1184                         ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
1185
1186 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
1187 {
1188         if (sido_src == wcd->sido_input_src)
1189                 return 0;
1190
1191         if (sido_src == SIDO_SOURCE_INTERNAL) {
1192                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1193                                    WCD934X_ANA_BUCK_HI_ACCU_EN_MASK, 0);
1194                 usleep_range(100, 110);
1195                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1196                                    WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK, 0x0);
1197                 usleep_range(100, 110);
1198                 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1199                                    WCD934X_ANA_RCO_BG_EN_MASK, 0);
1200                 usleep_range(100, 110);
1201                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1202                                    WCD934X_ANA_BUCK_PRE_EN1_MASK,
1203                                    WCD934X_ANA_BUCK_PRE_EN1_ENABLE);
1204                 usleep_range(100, 110);
1205                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1206                                    WCD934X_ANA_BUCK_PRE_EN2_MASK,
1207                                    WCD934X_ANA_BUCK_PRE_EN2_ENABLE);
1208                 usleep_range(100, 110);
1209                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
1210                                    WCD934X_ANA_BUCK_HI_ACCU_EN_MASK,
1211                                    WCD934X_ANA_BUCK_HI_ACCU_ENABLE);
1212                 usleep_range(100, 110);
1213         } else if (sido_src == SIDO_SOURCE_RCO_BG) {
1214                 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1215                                    WCD934X_ANA_RCO_BG_EN_MASK,
1216                                    WCD934X_ANA_RCO_BG_ENABLE);
1217                 usleep_range(100, 110);
1218         }
1219         wcd->sido_input_src = sido_src;
1220
1221         return 0;
1222 }
1223
1224 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
1225 {
1226         mutex_lock(&wcd->sysclk_mutex);
1227
1228         if (++wcd->sysclk_users != 1) {
1229                 mutex_unlock(&wcd->sysclk_mutex);
1230                 return 0;
1231         }
1232         mutex_unlock(&wcd->sysclk_mutex);
1233
1234         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1235                            WCD934X_ANA_BIAS_EN_MASK,
1236                            WCD934X_ANA_BIAS_EN);
1237         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1238                            WCD934X_ANA_PRECHRG_EN_MASK,
1239                            WCD934X_ANA_PRECHRG_EN);
1240         /*
1241          * 1ms delay is required after pre-charge is enabled
1242          * as per HW requirement
1243          */
1244         usleep_range(1000, 1100);
1245         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1246                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
1247         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1248                            WCD934X_ANA_PRECHRG_MODE_MASK, 0);
1249
1250         /*
1251          * In data clock contrl register is changed
1252          * to CLK_SYS_MCLK_PRG
1253          */
1254
1255         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1256                            WCD934X_EXT_CLK_BUF_EN_MASK,
1257                            WCD934X_EXT_CLK_BUF_EN);
1258         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1259                            WCD934X_EXT_CLK_DIV_RATIO_MASK,
1260                            WCD934X_EXT_CLK_DIV_BY_2);
1261         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1262                            WCD934X_MCLK_SRC_MASK,
1263                            WCD934X_MCLK_SRC_EXT_CLK);
1264         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1265                            WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
1266         regmap_update_bits(wcd->regmap,
1267                            WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
1268                            WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
1269                            WCD934X_CDC_FS_MCLK_CNT_ENABLE);
1270         regmap_update_bits(wcd->regmap,
1271                            WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
1272                            WCD934X_MCLK_EN_MASK,
1273                            WCD934X_MCLK_EN);
1274         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
1275                            WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
1276         /*
1277          * 10us sleep is required after clock is enabled
1278          * as per HW requirement
1279          */
1280         usleep_range(10, 15);
1281
1282         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1283
1284         return 0;
1285 }
1286
1287 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
1288 {
1289         mutex_lock(&wcd->sysclk_mutex);
1290         if (--wcd->sysclk_users != 0) {
1291                 mutex_unlock(&wcd->sysclk_mutex);
1292                 return 0;
1293         }
1294         mutex_unlock(&wcd->sysclk_mutex);
1295
1296         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1297                            WCD934X_EXT_CLK_BUF_EN_MASK |
1298                            WCD934X_MCLK_EN_MASK, 0x0);
1299         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_INTERNAL);
1300
1301         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1302                            WCD934X_ANA_BIAS_EN_MASK, 0);
1303         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1304                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
1305
1306         return 0;
1307 }
1308
1309 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
1310 {
1311         int ret = 0;
1312
1313         if (enable) {
1314                 ret = clk_prepare_enable(wcd->extclk);
1315
1316                 if (ret) {
1317                         dev_err(wcd->dev, "%s: ext clk enable failed\n",
1318                                 __func__);
1319                         return ret;
1320                 }
1321                 ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
1322         } else {
1323                 int val;
1324
1325                 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1326                             &val);
1327
1328                 /* Don't disable clock if soundwire using it.*/
1329                 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1330                         return 0;
1331
1332                 wcd934x_disable_ana_bias_and_syclk(wcd);
1333                 clk_disable_unprepare(wcd->extclk);
1334         }
1335
1336         return ret;
1337 }
1338
1339 static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
1340                                      struct snd_kcontrol *kc, int event)
1341 {
1342         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
1343         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1344
1345         switch (event) {
1346         case SND_SOC_DAPM_PRE_PMU:
1347                 return __wcd934x_cdc_mclk_enable(wcd, true);
1348         case SND_SOC_DAPM_POST_PMD:
1349                 return __wcd934x_cdc_mclk_enable(wcd, false);
1350         }
1351
1352         return 0;
1353 }
1354
1355 static int wcd934x_get_version(struct wcd934x_codec *wcd)
1356 {
1357         int val1, val2, ver, ret;
1358         struct regmap *regmap;
1359         u16 id_minor;
1360         u32 version_mask = 0;
1361
1362         regmap = wcd->regmap;
1363         ver = 0;
1364
1365         ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
1366                                (u8 *)&id_minor, sizeof(u16));
1367
1368         if (ret)
1369                 return ret;
1370
1371         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
1372         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
1373
1374         version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
1375         version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
1376
1377         switch (version_mask) {
1378         case DSD_DISABLED | SLNQ_DISABLED:
1379                 if (id_minor == 0)
1380                         ver = WCD_VERSION_WCD9340_1_0;
1381                 else if (id_minor == 0x01)
1382                         ver = WCD_VERSION_WCD9340_1_1;
1383                 break;
1384         case SLNQ_DISABLED:
1385                 if (id_minor == 0)
1386                         ver = WCD_VERSION_WCD9341_1_0;
1387                 else if (id_minor == 0x01)
1388                         ver = WCD_VERSION_WCD9341_1_1;
1389                 break;
1390         }
1391
1392         wcd->version = ver;
1393         dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
1394
1395         return 0;
1396 }
1397
1398 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
1399 {
1400         int rc, val;
1401
1402         __wcd934x_cdc_mclk_enable(wcd, true);
1403
1404         regmap_update_bits(wcd->regmap,
1405                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1406                            WCD934X_EFUSE_SENSE_STATE_MASK,
1407                            WCD934X_EFUSE_SENSE_STATE_DEF);
1408         regmap_update_bits(wcd->regmap,
1409                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1410                            WCD934X_EFUSE_SENSE_EN_MASK,
1411                            WCD934X_EFUSE_SENSE_ENABLE);
1412         /*
1413          * 5ms sleep required after enabling efuse control
1414          * before checking the status.
1415          */
1416         usleep_range(5000, 5500);
1417         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1418
1419         rc = regmap_read(wcd->regmap,
1420                          WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1421         if (rc || (!(val & 0x01)))
1422                 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1423                      __func__, val, rc);
1424
1425         __wcd934x_cdc_mclk_enable(wcd, false);
1426 }
1427
1428 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
1429 {
1430         if (enable) {
1431                 __wcd934x_cdc_mclk_enable(wcd, true);
1432                 regmap_update_bits(wcd->regmap,
1433                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1434                                    WCD934X_CDC_SWR_CLK_EN_MASK,
1435                                    WCD934X_CDC_SWR_CLK_ENABLE);
1436         } else {
1437                 regmap_update_bits(wcd->regmap,
1438                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1439                                    WCD934X_CDC_SWR_CLK_EN_MASK, 0);
1440                 __wcd934x_cdc_mclk_enable(wcd, false);
1441         }
1442
1443         return 0;
1444 }
1445
1446 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1447                                               u8 rate_val, u32 rate)
1448 {
1449         struct snd_soc_component *comp = dai->component;
1450         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1451         struct wcd934x_slim_ch *ch;
1452         u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1453         int inp, j;
1454
1455         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1456                 inp = ch->shift + INTn_1_INP_SEL_RX0;
1457                 /*
1458                  * Loop through all interpolator MUX inputs and find out
1459                  * to which interpolator input, the slim rx port
1460                  * is connected
1461                  */
1462                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1463                         /* Interpolators 5 and 6 are not aviliable in Tavil */
1464                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1465                                 continue;
1466
1467                         cfg0 = snd_soc_component_read32(comp,
1468                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1469                         cfg1 = snd_soc_component_read32(comp,
1470                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1471
1472                         inp0_sel = cfg0 &
1473                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1474                         inp1_sel = (cfg0 >> 4) &
1475                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1476                         inp2_sel = (cfg1 >> 4) &
1477                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1478
1479                         if ((inp0_sel == inp) ||  (inp1_sel == inp) ||
1480                             (inp2_sel == inp)) {
1481                                 /* rate is in Hz */
1482                                 /*
1483                                  * Ear and speaker primary path does not support
1484                                  * native sample rates
1485                                  */
1486                                 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
1487                                      j == INTERP_SPKR2) && rate == 44100)
1488                                         dev_err(wcd->dev,
1489                                                 "Cannot set 44.1KHz on INT%d\n",
1490                                                 j);
1491                                 else
1492                                         snd_soc_component_update_bits(comp,
1493                                               WCD934X_CDC_RX_PATH_CTL(j),
1494                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
1495                                               rate_val);
1496                         }
1497                 }
1498         }
1499
1500         return 0;
1501 }
1502
1503 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1504                                              int rate_val, u32 rate)
1505 {
1506         struct snd_soc_component *component = dai->component;
1507         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1508         struct wcd934x_slim_ch *ch;
1509         int val, j;
1510
1511         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1512                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1513                         /* Interpolators 5 and 6 are not aviliable in Tavil */
1514                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1515                                 continue;
1516                         val = snd_soc_component_read32(component,
1517                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1518                                         WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1519
1520                         if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
1521                                 /*
1522                                  * Ear mix path supports only 48, 96, 192,
1523                                  * 384KHz only
1524                                  */
1525                                 if ((j == INTERP_EAR) &&
1526                                     (rate_val < 0x4 ||
1527                                      rate_val > 0x7)) {
1528                                         dev_err(component->dev,
1529                                                 "Invalid rate for AIF_PB DAI(%d)\n",
1530                                                 dai->id);
1531                                         return -EINVAL;
1532                                 }
1533
1534                                 snd_soc_component_update_bits(component,
1535                                               WCD934X_CDC_RX_PATH_MIX_CTL(j),
1536                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
1537                                               rate_val);
1538                         }
1539                 }
1540         }
1541
1542         return 0;
1543 }
1544
1545 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
1546                                          u32 sample_rate)
1547 {
1548         int rate_val = 0;
1549         int i, ret;
1550
1551         for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
1552                 if (sample_rate == sr_val_tbl[i].sample_rate) {
1553                         rate_val = sr_val_tbl[i].rate_val;
1554                         break;
1555                 }
1556         }
1557         if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
1558                 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
1559                 return -EINVAL;
1560         }
1561
1562         ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
1563                                                  sample_rate);
1564         if (ret)
1565                 return ret;
1566         ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
1567                                                 sample_rate);
1568         if (ret)
1569                 return ret;
1570
1571         return ret;
1572 }
1573
1574 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
1575                                       u8 rate_val, u32 rate)
1576 {
1577         struct snd_soc_component *comp = dai->component;
1578         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
1579         u8 shift = 0, shift_val = 0, tx_mux_sel;
1580         struct wcd934x_slim_ch *ch;
1581         int tx_port, tx_port_reg;
1582         int decimator = -1;
1583
1584         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1585                 tx_port = ch->port;
1586                 /* Find the SB TX MUX input - which decimator is connected */
1587                 switch (tx_port) {
1588                 case 0 ...  3:
1589                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
1590                         shift = (tx_port << 1);
1591                         shift_val = 0x03;
1592                         break;
1593                 case 4 ... 7:
1594                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
1595                         shift = ((tx_port - 4) << 1);
1596                         shift_val = 0x03;
1597                         break;
1598                 case 8 ... 10:
1599                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
1600                         shift = ((tx_port - 8) << 1);
1601                         shift_val = 0x03;
1602                         break;
1603                 case 11:
1604                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1605                         shift = 0;
1606                         shift_val = 0x0F;
1607                         break;
1608                 case 13:
1609                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1610                         shift = 4;
1611                         shift_val = 0x03;
1612                         break;
1613                 default:
1614                         dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1615                                 tx_port, dai->id);
1616                         return -EINVAL;
1617                 }
1618
1619                 tx_mux_sel = snd_soc_component_read32(comp, tx_port_reg) &
1620                                                       (shift_val << shift);
1621
1622                 tx_mux_sel = tx_mux_sel >> shift;
1623                 switch (tx_port) {
1624                 case 0 ... 8:
1625                         if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1626                                 decimator = tx_port;
1627                         break;
1628                 case 9 ... 10:
1629                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1630                                 decimator = ((tx_port == 9) ? 7 : 6);
1631                         break;
1632                 case 11:
1633                         if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1634                                 decimator = tx_mux_sel - 1;
1635                         break;
1636                 case 13:
1637                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1638                                 decimator = 5;
1639                         break;
1640                 default:
1641                         dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
1642                                 tx_port);
1643                         return -EINVAL;
1644                 }
1645
1646                 snd_soc_component_update_bits(comp,
1647                                       WCD934X_CDC_TX_PATH_CTL(decimator),
1648                                       WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1649                                       rate_val);
1650         }
1651
1652         return 0;
1653 }
1654
1655 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
1656                                       struct wcd_slim_codec_dai_data *dai_data,
1657                                       int direction)
1658 {
1659         struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1660         struct slim_stream_config *cfg = &dai_data->sconfig;
1661         struct wcd934x_slim_ch *ch;
1662         u16 payload = 0;
1663         int ret, i;
1664
1665         cfg->ch_count = 0;
1666         cfg->direction = direction;
1667         cfg->port_mask = 0;
1668
1669         /* Configure slave interface device */
1670         list_for_each_entry(ch, slim_ch_list, list) {
1671                 cfg->ch_count++;
1672                 payload |= 1 << ch->shift;
1673                 cfg->port_mask |= BIT(ch->port);
1674         }
1675
1676         cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1677         if (!cfg->chs)
1678                 return -ENOMEM;
1679
1680         i = 0;
1681         list_for_each_entry(ch, slim_ch_list, list) {
1682                 cfg->chs[i++] = ch->ch_num;
1683                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1684                         /* write to interface device */
1685                         ret = regmap_write(wcd->if_regmap,
1686                            WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1687                            payload);
1688
1689                         if (ret < 0)
1690                                 goto err;
1691
1692                         /* configure the slave port for water mark and enable*/
1693                         ret = regmap_write(wcd->if_regmap,
1694                                         WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
1695                                         WCD934X_SLIM_WATER_MARK_VAL);
1696                         if (ret < 0)
1697                                 goto err;
1698                 } else {
1699                         ret = regmap_write(wcd->if_regmap,
1700                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1701                                 payload & 0x00FF);
1702                         if (ret < 0)
1703                                 goto err;
1704
1705                         /* ports 8,9 */
1706                         ret = regmap_write(wcd->if_regmap,
1707                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1708                                 (payload & 0xFF00) >> 8);
1709                         if (ret < 0)
1710                                 goto err;
1711
1712                         /* configure the slave port for water mark and enable*/
1713                         ret = regmap_write(wcd->if_regmap,
1714                                         WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1715                                         WCD934X_SLIM_WATER_MARK_VAL);
1716
1717                         if (ret < 0)
1718                                 goto err;
1719                 }
1720         }
1721
1722         dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1723
1724         return 0;
1725
1726 err:
1727         dev_err(wcd->dev, "Error Setting slim hw params\n");
1728         kfree(cfg->chs);
1729         cfg->chs = NULL;
1730
1731         return ret;
1732 }
1733
1734 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1735                              struct snd_pcm_hw_params *params,
1736                              struct snd_soc_dai *dai)
1737 {
1738         struct wcd934x_codec *wcd;
1739         int ret, tx_fs_rate = 0;
1740
1741         wcd = snd_soc_component_get_drvdata(dai->component);
1742
1743         switch (substream->stream) {
1744         case SNDRV_PCM_STREAM_PLAYBACK:
1745                 ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1746                 if (ret) {
1747                         dev_err(wcd->dev, "cannot set sample rate: %u\n",
1748                                 params_rate(params));
1749                         return ret;
1750                 }
1751                 switch (params_width(params)) {
1752                 case 16 ... 24:
1753                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1754                         break;
1755                 default:
1756                         dev_err(wcd->dev, "Invalid format 0x%x\n",
1757                                 params_width(params));
1758                         return -EINVAL;
1759                 }
1760                 break;
1761
1762         case SNDRV_PCM_STREAM_CAPTURE:
1763                 switch (params_rate(params)) {
1764                 case 8000:
1765                         tx_fs_rate = 0;
1766                         break;
1767                 case 16000:
1768                         tx_fs_rate = 1;
1769                         break;
1770                 case 32000:
1771                         tx_fs_rate = 3;
1772                         break;
1773                 case 48000:
1774                         tx_fs_rate = 4;
1775                         break;
1776                 case 96000:
1777                         tx_fs_rate = 5;
1778                         break;
1779                 case 192000:
1780                         tx_fs_rate = 6;
1781                         break;
1782                 case 384000:
1783                         tx_fs_rate = 7;
1784                         break;
1785                 default:
1786                         dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1787                                 params_rate(params));
1788                         return -EINVAL;
1789
1790                 };
1791
1792                 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1793                                                  params_rate(params));
1794                 if (ret < 0) {
1795                         dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1796                         return ret;
1797                 }
1798                 switch (params_width(params)) {
1799                 case 16 ... 32:
1800                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1801                         break;
1802                 default:
1803                         dev_err(wcd->dev, "Invalid format 0x%x\n",
1804                                 params_width(params));
1805                         return -EINVAL;
1806                 };
1807                 break;
1808         default:
1809                 dev_err(wcd->dev, "Invalid stream type %d\n",
1810                         substream->stream);
1811                 return -EINVAL;
1812         };
1813
1814         wcd->dai[dai->id].sconfig.rate = params_rate(params);
1815         wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1816
1817         return 0;
1818 }
1819
1820 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1821                            struct snd_soc_dai *dai)
1822 {
1823         struct wcd_slim_codec_dai_data *dai_data;
1824         struct wcd934x_codec *wcd;
1825
1826         wcd = snd_soc_component_get_drvdata(dai->component);
1827
1828         dai_data = &wcd->dai[dai->id];
1829
1830         kfree(dai_data->sconfig.chs);
1831
1832         return 0;
1833 }
1834
1835 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1836                            struct snd_soc_dai *dai)
1837 {
1838         struct wcd_slim_codec_dai_data *dai_data;
1839         struct wcd934x_codec *wcd;
1840         struct slim_stream_config *cfg;
1841
1842         wcd = snd_soc_component_get_drvdata(dai->component);
1843
1844         dai_data = &wcd->dai[dai->id];
1845
1846         switch (cmd) {
1847         case SNDRV_PCM_TRIGGER_START:
1848         case SNDRV_PCM_TRIGGER_RESUME:
1849         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1850                 cfg = &dai_data->sconfig;
1851                 slim_stream_prepare(dai_data->sruntime, cfg);
1852                 slim_stream_enable(dai_data->sruntime);
1853                 break;
1854         case SNDRV_PCM_TRIGGER_STOP:
1855         case SNDRV_PCM_TRIGGER_SUSPEND:
1856         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1857                 slim_stream_unprepare(dai_data->sruntime);
1858                 slim_stream_disable(dai_data->sruntime);
1859                 break;
1860         default:
1861                 break;
1862         }
1863
1864         return 0;
1865 }
1866
1867 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1868                                    unsigned int tx_num, unsigned int *tx_slot,
1869                                    unsigned int rx_num, unsigned int *rx_slot)
1870 {
1871         struct wcd934x_codec *wcd;
1872         int i;
1873
1874         wcd = snd_soc_component_get_drvdata(dai->component);
1875
1876         if (!tx_slot || !rx_slot) {
1877                 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1878                         tx_slot, rx_slot);
1879                 return -EINVAL;
1880         }
1881
1882         wcd->num_rx_port = rx_num;
1883         for (i = 0; i < rx_num; i++) {
1884                 wcd->rx_chs[i].ch_num = rx_slot[i];
1885                 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1886         }
1887
1888         wcd->num_tx_port = tx_num;
1889         for (i = 0; i < tx_num; i++) {
1890                 wcd->tx_chs[i].ch_num = tx_slot[i];
1891                 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1892         }
1893
1894         return 0;
1895 }
1896
1897 static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
1898                                    unsigned int *tx_num, unsigned int *tx_slot,
1899                                    unsigned int *rx_num, unsigned int *rx_slot)
1900 {
1901         struct wcd934x_slim_ch *ch;
1902         struct wcd934x_codec *wcd;
1903         int i = 0;
1904
1905         wcd = snd_soc_component_get_drvdata(dai->component);
1906
1907         switch (dai->id) {
1908         case AIF1_PB:
1909         case AIF2_PB:
1910         case AIF3_PB:
1911         case AIF4_PB:
1912                 if (!rx_slot || !rx_num) {
1913                         dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1914                                 rx_slot, rx_num);
1915                         return -EINVAL;
1916                 }
1917
1918                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1919                         rx_slot[i++] = ch->ch_num;
1920
1921                 *rx_num = i;
1922                 break;
1923         case AIF1_CAP:
1924         case AIF2_CAP:
1925         case AIF3_CAP:
1926                 if (!tx_slot || !tx_num) {
1927                         dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1928                                 tx_slot, tx_num);
1929                         return -EINVAL;
1930                 }
1931
1932                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1933                         tx_slot[i++] = ch->ch_num;
1934
1935                 *tx_num = i;
1936                 break;
1937         default:
1938                 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
1939                 break;
1940         }
1941
1942         return 0;
1943 }
1944
1945 static struct snd_soc_dai_ops wcd934x_dai_ops = {
1946         .hw_params = wcd934x_hw_params,
1947         .hw_free = wcd934x_hw_free,
1948         .trigger = wcd934x_trigger,
1949         .set_channel_map = wcd934x_set_channel_map,
1950         .get_channel_map = wcd934x_get_channel_map,
1951 };
1952
1953 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
1954         [0] = {
1955                 .name = "wcd934x_rx1",
1956                 .id = AIF1_PB,
1957                 .playback = {
1958                         .stream_name = "AIF1 Playback",
1959                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1960                         .formats = WCD934X_FORMATS_S16_S24_LE,
1961                         .rate_max = 192000,
1962                         .rate_min = 8000,
1963                         .channels_min = 1,
1964                         .channels_max = 2,
1965                 },
1966                 .ops = &wcd934x_dai_ops,
1967         },
1968         [1] = {
1969                 .name = "wcd934x_tx1",
1970                 .id = AIF1_CAP,
1971                 .capture = {
1972                         .stream_name = "AIF1 Capture",
1973                         .rates = WCD934X_RATES_MASK,
1974                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1975                         .rate_min = 8000,
1976                         .rate_max = 192000,
1977                         .channels_min = 1,
1978                         .channels_max = 4,
1979                 },
1980                 .ops = &wcd934x_dai_ops,
1981         },
1982         [2] = {
1983                 .name = "wcd934x_rx2",
1984                 .id = AIF2_PB,
1985                 .playback = {
1986                         .stream_name = "AIF2 Playback",
1987                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1988                         .formats = WCD934X_FORMATS_S16_S24_LE,
1989                         .rate_min = 8000,
1990                         .rate_max = 192000,
1991                         .channels_min = 1,
1992                         .channels_max = 2,
1993                 },
1994                 .ops = &wcd934x_dai_ops,
1995         },
1996         [3] = {
1997                 .name = "wcd934x_tx2",
1998                 .id = AIF2_CAP,
1999                 .capture = {
2000                         .stream_name = "AIF2 Capture",
2001                         .rates = WCD934X_RATES_MASK,
2002                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2003                         .rate_min = 8000,
2004                         .rate_max = 192000,
2005                         .channels_min = 1,
2006                         .channels_max = 4,
2007                 },
2008                 .ops = &wcd934x_dai_ops,
2009         },
2010         [4] = {
2011                 .name = "wcd934x_rx3",
2012                 .id = AIF3_PB,
2013                 .playback = {
2014                         .stream_name = "AIF3 Playback",
2015                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2016                         .formats = WCD934X_FORMATS_S16_S24_LE,
2017                         .rate_min = 8000,
2018                         .rate_max = 192000,
2019                         .channels_min = 1,
2020                         .channels_max = 2,
2021                 },
2022                 .ops = &wcd934x_dai_ops,
2023         },
2024         [5] = {
2025                 .name = "wcd934x_tx3",
2026                 .id = AIF3_CAP,
2027                 .capture = {
2028                         .stream_name = "AIF3 Capture",
2029                         .rates = WCD934X_RATES_MASK,
2030                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2031                         .rate_min = 8000,
2032                         .rate_max = 192000,
2033                         .channels_min = 1,
2034                         .channels_max = 4,
2035                 },
2036                 .ops = &wcd934x_dai_ops,
2037         },
2038         [6] = {
2039                 .name = "wcd934x_rx4",
2040                 .id = AIF4_PB,
2041                 .playback = {
2042                         .stream_name = "AIF4 Playback",
2043                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2044                         .formats = WCD934X_FORMATS_S16_S24_LE,
2045                         .rate_min = 8000,
2046                         .rate_max = 192000,
2047                         .channels_min = 1,
2048                         .channels_max = 2,
2049                 },
2050                 .ops = &wcd934x_dai_ops,
2051         },
2052 };
2053
2054 static int swclk_gate_enable(struct clk_hw *hw)
2055 {
2056         return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
2057 }
2058
2059 static void swclk_gate_disable(struct clk_hw *hw)
2060 {
2061         wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
2062 }
2063
2064 static int swclk_gate_is_enabled(struct clk_hw *hw)
2065 {
2066         struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
2067         int ret, val;
2068
2069         regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2070         ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2071
2072         return ret;
2073 }
2074
2075 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2076                                        unsigned long parent_rate)
2077 {
2078         return parent_rate / 2;
2079 }
2080
2081 static const struct clk_ops swclk_gate_ops = {
2082         .prepare = swclk_gate_enable,
2083         .unprepare = swclk_gate_disable,
2084         .is_enabled = swclk_gate_is_enabled,
2085         .recalc_rate = swclk_recalc_rate,
2086
2087 };
2088
2089 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
2090 {
2091         struct clk *parent = wcd->extclk;
2092         struct device *dev = wcd->dev;
2093         struct device_node *np = dev->parent->of_node;
2094         const char *parent_clk_name = NULL;
2095         const char *clk_name = "mclk";
2096         struct clk_hw *hw;
2097         struct clk_init_data init;
2098         int ret;
2099
2100         if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
2101                 return NULL;
2102
2103         parent_clk_name = __clk_get_name(parent);
2104
2105         of_property_read_string(np, "clock-output-names", &clk_name);
2106
2107         init.name = clk_name;
2108         init.ops = &swclk_gate_ops;
2109         init.flags = 0;
2110         init.parent_names = &parent_clk_name;
2111         init.num_parents = 1;
2112         wcd->hw.init = &init;
2113
2114         hw = &wcd->hw;
2115         ret = clk_hw_register(wcd->dev->parent, hw);
2116         if (ret)
2117                 return ERR_PTR(ret);
2118
2119         of_clk_add_provider(np, of_clk_src_simple_get, hw->clk);
2120
2121         return NULL;
2122 }
2123
2124 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias)
2125 {
2126         int mv;
2127
2128         if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
2129                 dev_err(dev, "%s value not found, using default\n", micbias);
2130                 mv = WCD934X_DEF_MICBIAS_MV;
2131         } else {
2132                 /* convert it to milli volts */
2133                 mv = mv/1000;
2134         }
2135
2136         if (mv < 1000 || mv > 2850) {
2137                 dev_err(dev, "%s value not in valid range, using default\n",
2138                         micbias);
2139                 mv = WCD934X_DEF_MICBIAS_MV;
2140         }
2141
2142         return (mv - 1000) / 50;
2143 }
2144
2145 static int wcd934x_init_dmic(struct snd_soc_component *comp)
2146 {
2147         int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2148         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2149         u32 def_dmic_rate, dmic_clk_drv;
2150
2151         vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
2152                                              "qcom,micbias1-microvolt");
2153         vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
2154                                              "qcom,micbias2-microvolt");
2155         vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
2156                                              "qcom,micbias3-microvolt");
2157         vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
2158                                              "qcom,micbias4-microvolt");
2159
2160         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
2161                                       WCD934X_MICB_VAL_MASK, vout_ctl_1);
2162         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
2163                                       WCD934X_MICB_VAL_MASK, vout_ctl_2);
2164         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
2165                                       WCD934X_MICB_VAL_MASK, vout_ctl_3);
2166         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
2167                                       WCD934X_MICB_VAL_MASK, vout_ctl_4);
2168
2169         if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
2170                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
2171         else
2172                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
2173
2174         wcd->dmic_sample_rate = def_dmic_rate;
2175
2176         dmic_clk_drv = 0;
2177         snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
2178                                       0x0C, dmic_clk_drv << 2);
2179
2180         return 0;
2181 }
2182
2183 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
2184 {
2185         struct regmap *rm = wcd->regmap;
2186
2187         /* set SPKR rate to FS_2P4_3P072 */
2188         regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
2189         regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
2190
2191         /* Take DMICs out of reset */
2192         regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
2193 }
2194
2195 static int wcd934x_comp_init(struct snd_soc_component *component)
2196 {
2197         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2198
2199         wcd934x_hw_init(wcd);
2200         wcd934x_enable_efuse_sensing(wcd);
2201         wcd934x_get_version(wcd);
2202
2203         return 0;
2204 }
2205
2206 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
2207 {
2208         struct wcd934x_codec *wcd = data;
2209         unsigned long status = 0;
2210         int i, j, port_id;
2211         unsigned int val, int_val = 0;
2212         irqreturn_t ret = IRQ_NONE;
2213         bool tx;
2214         unsigned short reg = 0;
2215
2216         for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
2217              i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
2218                 regmap_read(wcd->if_regmap, i, &val);
2219                 status |= ((u32)val << (8 * j));
2220         }
2221
2222         for_each_set_bit(j, &status, 32) {
2223                 tx = false;
2224                 port_id = j;
2225
2226                 if (j >= 16) {
2227                         tx = true;
2228                         port_id = j - 16;
2229                 }
2230
2231                 regmap_read(wcd->if_regmap,
2232                             WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2233                 if (val) {
2234                         if (!tx)
2235                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2236                                         (port_id / 8);
2237                         else
2238                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2239                                         (port_id / 8);
2240                         regmap_read(wcd->if_regmap, reg, &int_val);
2241                 }
2242
2243                 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2244                         dev_err_ratelimited(wcd->dev,
2245                                             "overflow error on %s port %d, value %x\n",
2246                                             (tx ? "TX" : "RX"), port_id, val);
2247
2248                 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2249                         dev_err_ratelimited(wcd->dev,
2250                                             "underflow error on %s port %d, value %x\n",
2251                                             (tx ? "TX" : "RX"), port_id, val);
2252
2253                 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2254                     (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2255                         if (!tx)
2256                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2257                                         (port_id / 8);
2258                         else
2259                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2260                                         (port_id / 8);
2261                         regmap_read(
2262                                 wcd->if_regmap, reg, &int_val);
2263                         if (int_val & (1 << (port_id % 8))) {
2264                                 int_val = int_val ^ (1 << (port_id % 8));
2265                                 regmap_write(wcd->if_regmap,
2266                                              reg, int_val);
2267                         }
2268                 }
2269
2270                 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2271                         dev_err_ratelimited(wcd->dev,
2272                                             "Port Closed %s port %d, value %x\n",
2273                                             (tx ? "TX" : "RX"), port_id, val);
2274
2275                 regmap_write(wcd->if_regmap,
2276                              WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
2277                                 BIT(j % 8));
2278                 ret = IRQ_HANDLED;
2279         }
2280
2281         return ret;
2282 }
2283
2284 static int wcd934x_comp_probe(struct snd_soc_component *component)
2285 {
2286         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2287         int i;
2288
2289         snd_soc_component_init_regmap(component, wcd->regmap);
2290         wcd->component = component;
2291
2292         /* Class-H Init*/
2293         wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
2294         if (IS_ERR(wcd->clsh_ctrl))
2295                 return PTR_ERR(wcd->clsh_ctrl);
2296
2297         /* Default HPH Mode to Class-H Low HiFi */
2298         wcd->hph_mode = CLS_H_LOHIFI;
2299
2300         wcd934x_comp_init(component);
2301
2302         for (i = 0; i < NUM_CODEC_DAIS; i++)
2303                 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
2304
2305         wcd934x_init_dmic(component);
2306         return 0;
2307 }
2308
2309 static void wcd934x_comp_remove(struct snd_soc_component *comp)
2310 {
2311         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2312
2313         wcd_clsh_ctrl_free(wcd->clsh_ctrl);
2314 }
2315
2316 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
2317                                    int clk_id, int source,
2318                                    unsigned int freq, int dir)
2319 {
2320         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2321         int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
2322
2323         wcd->rate = freq;
2324
2325         if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
2326                 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
2327
2328         snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
2329                                       WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
2330                                       val);
2331
2332         return clk_set_rate(wcd->extclk, freq);
2333 }
2334
2335 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
2336                                    int iir_idx, int band_idx, int coeff_idx)
2337 {
2338         u32 value = 0;
2339         int reg, b2_reg;
2340
2341         /* Address does not automatically update if reading */
2342         reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2343         b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2344
2345         snd_soc_component_write(component, reg,
2346                                 ((band_idx * BAND_MAX + coeff_idx) *
2347                                  sizeof(uint32_t)) & 0x7F);
2348
2349         value |= snd_soc_component_read32(component, b2_reg);
2350         snd_soc_component_write(component, reg,
2351                                 ((band_idx * BAND_MAX + coeff_idx)
2352                                  * sizeof(uint32_t) + 1) & 0x7F);
2353
2354         value |= (snd_soc_component_read32(component, b2_reg) << 8);
2355         snd_soc_component_write(component, reg,
2356                                 ((band_idx * BAND_MAX + coeff_idx)
2357                                  * sizeof(uint32_t) + 2) & 0x7F);
2358
2359         value |= (snd_soc_component_read32(component, b2_reg) << 16);
2360         snd_soc_component_write(component, reg,
2361                 ((band_idx * BAND_MAX + coeff_idx)
2362                 * sizeof(uint32_t) + 3) & 0x7F);
2363
2364         /* Mask bits top 2 bits since they are reserved */
2365         value |= (snd_soc_component_read32(component, b2_reg) << 24);
2366         return value;
2367 }
2368
2369 static void set_iir_band_coeff(struct snd_soc_component *component,
2370                                int iir_idx, int band_idx, uint32_t value)
2371 {
2372         int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2373
2374         snd_soc_component_write(component, reg, (value & 0xFF));
2375         snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
2376         snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
2377         /* Mask top 2 bits, 7-8 are reserved */
2378         snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
2379 }
2380
2381 static int wcd934x_put_iir_band_audio_mixer(
2382                                         struct snd_kcontrol *kcontrol,
2383                                         struct snd_ctl_elem_value *ucontrol)
2384 {
2385         struct snd_soc_component *component =
2386                         snd_soc_kcontrol_component(kcontrol);
2387         struct wcd_iir_filter_ctl *ctl =
2388                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2389         struct soc_bytes_ext *params = &ctl->bytes_ext;
2390         int iir_idx = ctl->iir_idx;
2391         int band_idx = ctl->band_idx;
2392         u32 coeff[BAND_MAX];
2393         int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2394
2395         memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
2396
2397         /* Mask top bit it is reserved */
2398         /* Updates addr automatically for each B2 write */
2399         snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
2400                                                  sizeof(uint32_t)) & 0x7F);
2401
2402         set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
2403         set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
2404         set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
2405         set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
2406         set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
2407
2408         return 0;
2409 }
2410
2411 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
2412                                     struct snd_ctl_elem_value *ucontrol)
2413 {
2414         struct snd_soc_component *component =
2415                         snd_soc_kcontrol_component(kcontrol);
2416         struct wcd_iir_filter_ctl *ctl =
2417                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2418         struct soc_bytes_ext *params = &ctl->bytes_ext;
2419         int iir_idx = ctl->iir_idx;
2420         int band_idx = ctl->band_idx;
2421         u32 coeff[BAND_MAX];
2422
2423         coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
2424         coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
2425         coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
2426         coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
2427         coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
2428
2429         memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
2430
2431         return 0;
2432 }
2433
2434 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
2435                                    struct snd_ctl_elem_info *ucontrol)
2436 {
2437         struct wcd_iir_filter_ctl *ctl =
2438                 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2439         struct soc_bytes_ext *params = &ctl->bytes_ext;
2440
2441         ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
2442         ucontrol->count = params->max;
2443
2444         return 0;
2445 }
2446
2447 static int wcd934x_compander_get(struct snd_kcontrol *kc,
2448                                  struct snd_ctl_elem_value *ucontrol)
2449 {
2450         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2451         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2452         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2453
2454         ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2455
2456         return 0;
2457 }
2458
2459 static int wcd934x_compander_set(struct snd_kcontrol *kc,
2460                                  struct snd_ctl_elem_value *ucontrol)
2461 {
2462         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2463         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2464         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2465         int value = ucontrol->value.integer.value[0];
2466         int sel;
2467
2468         wcd->comp_enabled[comp] = value;
2469         sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
2470                 WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
2471
2472         /* Any specific register configuration for compander */
2473         switch (comp) {
2474         case COMPANDER_1:
2475                 /* Set Gain Source Select based on compander enable/disable */
2476                 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
2477                                               WCD934X_HPH_GAIN_SRC_SEL_MASK,
2478                                               sel);
2479                 break;
2480         case COMPANDER_2:
2481                 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
2482                                               WCD934X_HPH_GAIN_SRC_SEL_MASK,
2483                                               sel);
2484                 break;
2485         case COMPANDER_3:
2486         case COMPANDER_4:
2487         case COMPANDER_7:
2488         case COMPANDER_8:
2489                 break;
2490         default:
2491                 break;
2492         };
2493
2494         return 0;
2495 }
2496
2497 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
2498                                    struct snd_ctl_elem_value *ucontrol)
2499 {
2500         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2501         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2502
2503         ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2504
2505         return 0;
2506 }
2507
2508 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
2509                                    struct snd_ctl_elem_value *ucontrol)
2510 {
2511         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2512         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2513         u32 mode_val;
2514
2515         mode_val = ucontrol->value.enumerated.item[0];
2516
2517         if (mode_val == 0) {
2518                 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2519                 mode_val = CLS_H_LOHIFI;
2520         }
2521         wcd->hph_mode = mode_val;
2522
2523         return 0;
2524 }
2525
2526 static int slim_rx_mux_get(struct snd_kcontrol *kc,
2527                            struct snd_ctl_elem_value *ucontrol)
2528 {
2529         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
2530         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
2531         struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
2532
2533         ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
2534
2535         return 0;
2536 }
2537
2538 static int slim_rx_mux_put(struct snd_kcontrol *kc,
2539                            struct snd_ctl_elem_value *ucontrol)
2540 {
2541         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
2542         struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
2543         struct soc_enum *e = (struct soc_enum *)kc->private_value;
2544         struct snd_soc_dapm_update *update = NULL;
2545         u32 port_id = w->shift;
2546
2547         if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
2548                 return 0;
2549
2550         wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
2551
2552         switch (wcd->rx_port_value[port_id]) {
2553         case 0:
2554                 list_del_init(&wcd->rx_chs[port_id].list);
2555                 break;
2556         case 1:
2557                 list_add_tail(&wcd->rx_chs[port_id].list,
2558                               &wcd->dai[AIF1_PB].slim_ch_list);
2559                 break;
2560         case 2:
2561                 list_add_tail(&wcd->rx_chs[port_id].list,
2562                               &wcd->dai[AIF2_PB].slim_ch_list);
2563                 break;
2564         case 3:
2565                 list_add_tail(&wcd->rx_chs[port_id].list,
2566                               &wcd->dai[AIF3_PB].slim_ch_list);
2567                 break;
2568         case 4:
2569                 list_add_tail(&wcd->rx_chs[port_id].list,
2570                               &wcd->dai[AIF4_PB].slim_ch_list);
2571                 break;
2572         default:
2573                 dev_err(wcd->dev, "Unknown AIF %d\n",
2574                         wcd->rx_port_value[port_id]);
2575                 goto err;
2576         }
2577
2578         snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
2579                                       e, update);
2580
2581         return 0;
2582 err:
2583         return -EINVAL;
2584 }
2585
2586 static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
2587                                        struct snd_ctl_elem_value *ucontrol)
2588 {
2589         struct soc_enum *e = (struct soc_enum *)kc->private_value;
2590         struct snd_soc_component *component;
2591         int reg, val, ret;
2592
2593         component = snd_soc_dapm_kcontrol_component(kc);
2594         val = ucontrol->value.enumerated.item[0];
2595         if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
2596                 reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
2597         else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
2598                 reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
2599         else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
2600                 reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
2601         else
2602                 return -EINVAL;
2603
2604         /* Set Look Ahead Delay */
2605         if (val)
2606                 snd_soc_component_update_bits(component, reg,
2607                                               WCD934X_RX_DLY_ZN_EN_MASK,
2608                                               WCD934X_RX_DLY_ZN_ENABLE);
2609         else
2610                 snd_soc_component_update_bits(component, reg,
2611                                               WCD934X_RX_DLY_ZN_EN_MASK,
2612                                               WCD934X_RX_DLY_ZN_DISABLE);
2613
2614         ret = snd_soc_dapm_put_enum_double(kc, ucontrol);
2615
2616         return ret;
2617 }
2618
2619 static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
2620                                 struct snd_ctl_elem_value *ucontrol)
2621 {
2622         struct snd_soc_component *comp;
2623         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2624         unsigned int val;
2625         u16 mic_sel_reg = 0;
2626         u8 mic_sel;
2627
2628         comp = snd_soc_dapm_kcontrol_component(kcontrol);
2629
2630         val = ucontrol->value.enumerated.item[0];
2631         if (val > e->items - 1)
2632                 return -EINVAL;
2633
2634         switch (e->reg) {
2635         case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
2636                 if (e->shift_l == 0)
2637                         mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
2638                 else if (e->shift_l == 2)
2639                         mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
2640                 else if (e->shift_l == 4)
2641                         mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
2642                 break;
2643         case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
2644                 if (e->shift_l == 0)
2645                         mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
2646                 else if (e->shift_l == 2)
2647                         mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
2648                 break;
2649         case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
2650                 if (e->shift_l == 0)
2651                         mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
2652                 else if (e->shift_l == 2)
2653                         mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
2654                 break;
2655         case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
2656                 if (e->shift_l == 0)
2657                         mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
2658                 else if (e->shift_l == 2)
2659                         mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
2660                 break;
2661         default:
2662                 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
2663                         __func__, e->reg);
2664                 return -EINVAL;
2665         }
2666
2667         /* ADC: 0, DMIC: 1 */
2668         mic_sel = val ? 0x0 : 0x1;
2669         if (mic_sel_reg)
2670                 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
2671                                               mic_sel << 7);
2672
2673         return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
2674 }
2675
2676 static const struct snd_kcontrol_new rx_int0_2_mux =
2677         SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
2678
2679 static const struct snd_kcontrol_new rx_int1_2_mux =
2680         SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
2681
2682 static const struct snd_kcontrol_new rx_int2_2_mux =
2683         SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
2684
2685 static const struct snd_kcontrol_new rx_int3_2_mux =
2686         SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
2687
2688 static const struct snd_kcontrol_new rx_int4_2_mux =
2689         SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
2690
2691 static const struct snd_kcontrol_new rx_int7_2_mux =
2692         SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
2693
2694 static const struct snd_kcontrol_new rx_int8_2_mux =
2695         SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
2696
2697 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
2698         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
2699
2700 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
2701         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
2702
2703 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
2704         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
2705
2706 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
2707         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
2708
2709 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
2710         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
2711
2712 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
2713         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
2714
2715 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
2716         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
2717
2718 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
2719         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
2720
2721 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
2722         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
2723
2724 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
2725         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
2726
2727 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
2728         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
2729
2730 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
2731         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
2732
2733 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
2734         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
2735
2736 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
2737         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
2738
2739 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
2740         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
2741
2742 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
2743         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
2744
2745 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
2746         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
2747
2748 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
2749         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
2750
2751 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
2752         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
2753
2754 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
2755         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
2756
2757 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
2758         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
2759
2760 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
2761         SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
2762
2763 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
2764         SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
2765
2766 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
2767         SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
2768
2769 static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
2770         SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
2771
2772 static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
2773         SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
2774
2775 static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
2776         SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
2777
2778 static const struct snd_kcontrol_new iir0_inp0_mux =
2779         SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
2780 static const struct snd_kcontrol_new iir0_inp1_mux =
2781         SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
2782 static const struct snd_kcontrol_new iir0_inp2_mux =
2783         SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
2784 static const struct snd_kcontrol_new iir0_inp3_mux =
2785         SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
2786
2787 static const struct snd_kcontrol_new iir1_inp0_mux =
2788         SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
2789 static const struct snd_kcontrol_new iir1_inp1_mux =
2790         SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
2791 static const struct snd_kcontrol_new iir1_inp2_mux =
2792         SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
2793 static const struct snd_kcontrol_new iir1_inp3_mux =
2794         SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
2795
2796 static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
2797         SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
2798                           slim_rx_mux_get, slim_rx_mux_put),
2799         SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
2800                           slim_rx_mux_get, slim_rx_mux_put),
2801         SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
2802                           slim_rx_mux_get, slim_rx_mux_put),
2803         SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
2804                           slim_rx_mux_get, slim_rx_mux_put),
2805         SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
2806                           slim_rx_mux_get, slim_rx_mux_put),
2807         SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
2808                           slim_rx_mux_get, slim_rx_mux_put),
2809         SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
2810                           slim_rx_mux_get, slim_rx_mux_put),
2811         SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
2812                           slim_rx_mux_get, slim_rx_mux_put),
2813 };
2814
2815 static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
2816         SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
2817 };
2818
2819 static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
2820         SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
2821 };
2822
2823 static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
2824         SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
2825 };
2826
2827 static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
2828         SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
2829 };
2830
2831 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
2832         SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
2833                           snd_soc_dapm_get_enum_double,
2834                           wcd934x_int_dem_inp_mux_put);
2835
2836 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
2837         SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
2838                           snd_soc_dapm_get_enum_double,
2839                           wcd934x_int_dem_inp_mux_put);
2840
2841 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
2842         SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
2843                           snd_soc_dapm_get_enum_double,
2844                           wcd934x_int_dem_inp_mux_put);
2845
2846 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
2847         SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
2848
2849 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
2850         SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
2851
2852 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
2853         SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
2854
2855 static const struct snd_kcontrol_new rx_int3_1_interp_mux =
2856         SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
2857
2858 static const struct snd_kcontrol_new rx_int4_1_interp_mux =
2859         SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
2860
2861 static const struct snd_kcontrol_new rx_int7_1_interp_mux =
2862         SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
2863
2864 static const struct snd_kcontrol_new rx_int8_1_interp_mux =
2865         SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
2866
2867 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
2868         SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
2869
2870 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
2871         SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
2872
2873 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
2874         SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
2875
2876 static const struct snd_kcontrol_new rx_int3_2_interp_mux =
2877         SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
2878
2879 static const struct snd_kcontrol_new rx_int4_2_interp_mux =
2880         SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
2881
2882 static const struct snd_kcontrol_new rx_int7_2_interp_mux =
2883         SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
2884
2885 static const struct snd_kcontrol_new rx_int8_2_interp_mux =
2886         SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
2887
2888 static const struct snd_kcontrol_new tx_dmic_mux0 =
2889         SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
2890
2891 static const struct snd_kcontrol_new tx_dmic_mux1 =
2892         SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
2893
2894 static const struct snd_kcontrol_new tx_dmic_mux2 =
2895         SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
2896
2897 static const struct snd_kcontrol_new tx_dmic_mux3 =
2898         SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
2899
2900 static const struct snd_kcontrol_new tx_dmic_mux4 =
2901         SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
2902
2903 static const struct snd_kcontrol_new tx_dmic_mux5 =
2904         SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
2905
2906 static const struct snd_kcontrol_new tx_dmic_mux6 =
2907         SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
2908
2909 static const struct snd_kcontrol_new tx_dmic_mux7 =
2910         SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
2911
2912 static const struct snd_kcontrol_new tx_dmic_mux8 =
2913         SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
2914
2915 static const struct snd_kcontrol_new tx_amic_mux0 =
2916         SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
2917
2918 static const struct snd_kcontrol_new tx_amic_mux1 =
2919         SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
2920
2921 static const struct snd_kcontrol_new tx_amic_mux2 =
2922         SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
2923
2924 static const struct snd_kcontrol_new tx_amic_mux3 =
2925         SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
2926
2927 static const struct snd_kcontrol_new tx_amic_mux4 =
2928         SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
2929
2930 static const struct snd_kcontrol_new tx_amic_mux5 =
2931         SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
2932
2933 static const struct snd_kcontrol_new tx_amic_mux6 =
2934         SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
2935
2936 static const struct snd_kcontrol_new tx_amic_mux7 =
2937         SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
2938
2939 static const struct snd_kcontrol_new tx_amic_mux8 =
2940         SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
2941
2942 static const struct snd_kcontrol_new tx_amic4_5 =
2943         SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
2944
2945 static const struct snd_kcontrol_new tx_adc_mux0_mux =
2946         SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
2947                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2948 static const struct snd_kcontrol_new tx_adc_mux1_mux =
2949         SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
2950                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2951 static const struct snd_kcontrol_new tx_adc_mux2_mux =
2952         SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
2953                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2954 static const struct snd_kcontrol_new tx_adc_mux3_mux =
2955         SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
2956                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2957 static const struct snd_kcontrol_new tx_adc_mux4_mux =
2958         SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
2959                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2960 static const struct snd_kcontrol_new tx_adc_mux5_mux =
2961         SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
2962                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2963 static const struct snd_kcontrol_new tx_adc_mux6_mux =
2964         SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
2965                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2966 static const struct snd_kcontrol_new tx_adc_mux7_mux =
2967         SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
2968                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2969 static const struct snd_kcontrol_new tx_adc_mux8_mux =
2970         SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
2971                           snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
2972
2973 static const struct snd_kcontrol_new cdc_if_tx0_mux =
2974         SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
2975 static const struct snd_kcontrol_new cdc_if_tx1_mux =
2976         SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
2977 static const struct snd_kcontrol_new cdc_if_tx2_mux =
2978         SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
2979 static const struct snd_kcontrol_new cdc_if_tx3_mux =
2980         SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
2981 static const struct snd_kcontrol_new cdc_if_tx4_mux =
2982         SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
2983 static const struct snd_kcontrol_new cdc_if_tx5_mux =
2984         SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
2985 static const struct snd_kcontrol_new cdc_if_tx6_mux =
2986         SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
2987 static const struct snd_kcontrol_new cdc_if_tx7_mux =
2988         SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
2989 static const struct snd_kcontrol_new cdc_if_tx8_mux =
2990         SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
2991 static const struct snd_kcontrol_new cdc_if_tx9_mux =
2992         SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
2993 static const struct snd_kcontrol_new cdc_if_tx10_mux =
2994         SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
2995 static const struct snd_kcontrol_new cdc_if_tx11_mux =
2996         SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
2997 static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
2998         SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
2999 static const struct snd_kcontrol_new cdc_if_tx13_mux =
3000         SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
3001 static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
3002         SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
3003
3004 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
3005                              struct snd_ctl_elem_value *ucontrol)
3006 {
3007         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3008         struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3009         struct soc_mixer_control *mixer =
3010                         (struct soc_mixer_control *)kc->private_value;
3011         int port_id = mixer->shift;
3012
3013         ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
3014
3015         return 0;
3016 }
3017
3018 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
3019                              struct snd_ctl_elem_value *ucontrol)
3020 {
3021         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
3022         struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
3023         struct snd_soc_dapm_update *update = NULL;
3024         struct soc_mixer_control *mixer =
3025                         (struct soc_mixer_control *)kc->private_value;
3026         int enable = ucontrol->value.integer.value[0];
3027         int dai_id = widget->shift;
3028         int port_id = mixer->shift;
3029
3030         /* only add to the list if value not set */
3031         if (enable == wcd->tx_port_value[port_id])
3032                 return 0;
3033
3034         wcd->tx_port_value[port_id] = enable;
3035
3036         if (enable)
3037                 list_add_tail(&wcd->tx_chs[port_id].list,
3038                               &wcd->dai[dai_id].slim_ch_list);
3039         else
3040                 list_del_init(&wcd->tx_chs[port_id].list);
3041
3042         snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
3043
3044         return 0;
3045 }
3046
3047 static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
3048         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3049                        slim_tx_mixer_get, slim_tx_mixer_put),
3050         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3051                        slim_tx_mixer_get, slim_tx_mixer_put),
3052         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3053                        slim_tx_mixer_get, slim_tx_mixer_put),
3054         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3055                        slim_tx_mixer_get, slim_tx_mixer_put),
3056         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3057                        slim_tx_mixer_get, slim_tx_mixer_put),
3058         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3059                        slim_tx_mixer_get, slim_tx_mixer_put),
3060         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3061                        slim_tx_mixer_get, slim_tx_mixer_put),
3062         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3063                        slim_tx_mixer_get, slim_tx_mixer_put),
3064         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3065                        slim_tx_mixer_get, slim_tx_mixer_put),
3066         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3067                        slim_tx_mixer_get, slim_tx_mixer_put),
3068         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3069                        slim_tx_mixer_get, slim_tx_mixer_put),
3070         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3071                        slim_tx_mixer_get, slim_tx_mixer_put),
3072         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3073                        slim_tx_mixer_get, slim_tx_mixer_put),
3074 };
3075
3076 static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
3077         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3078                        slim_tx_mixer_get, slim_tx_mixer_put),
3079         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3080                        slim_tx_mixer_get, slim_tx_mixer_put),
3081         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3082                        slim_tx_mixer_get, slim_tx_mixer_put),
3083         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3084                        slim_tx_mixer_get, slim_tx_mixer_put),
3085         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3086                        slim_tx_mixer_get, slim_tx_mixer_put),
3087         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3088                        slim_tx_mixer_get, slim_tx_mixer_put),
3089         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3090                        slim_tx_mixer_get, slim_tx_mixer_put),
3091         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3092                        slim_tx_mixer_get, slim_tx_mixer_put),
3093         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3094                        slim_tx_mixer_get, slim_tx_mixer_put),
3095         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3096                        slim_tx_mixer_get, slim_tx_mixer_put),
3097         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3098                        slim_tx_mixer_get, slim_tx_mixer_put),
3099         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3100                        slim_tx_mixer_get, slim_tx_mixer_put),
3101         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3102                        slim_tx_mixer_get, slim_tx_mixer_put),
3103 };
3104
3105 static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
3106         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3107                        slim_tx_mixer_get, slim_tx_mixer_put),
3108         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3109                        slim_tx_mixer_get, slim_tx_mixer_put),
3110         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3111                        slim_tx_mixer_get, slim_tx_mixer_put),
3112         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3113                        slim_tx_mixer_get, slim_tx_mixer_put),
3114         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3115                        slim_tx_mixer_get, slim_tx_mixer_put),
3116         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3117                        slim_tx_mixer_get, slim_tx_mixer_put),
3118         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3119                        slim_tx_mixer_get, slim_tx_mixer_put),
3120         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3121                        slim_tx_mixer_get, slim_tx_mixer_put),
3122         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3123                        slim_tx_mixer_get, slim_tx_mixer_put),
3124         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3125                        slim_tx_mixer_get, slim_tx_mixer_put),
3126         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3127                        slim_tx_mixer_get, slim_tx_mixer_put),
3128         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3129                        slim_tx_mixer_get, slim_tx_mixer_put),
3130         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3131                        slim_tx_mixer_get, slim_tx_mixer_put),
3132 };
3133
3134 static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
3135         /* Gain Controls */
3136         SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
3137         SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
3138         SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
3139         SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3140                        3, 16, 1, line_gain),
3141         SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3142                        3, 16, 1, line_gain),
3143
3144         SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
3145         SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
3146         SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
3147         SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
3148
3149         SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
3150                           -84, 40, digital_gain), /* -84dB min - 40dB max */
3151         SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
3152                           -84, 40, digital_gain),
3153         SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
3154                           -84, 40, digital_gain),
3155         SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
3156                           -84, 40, digital_gain),
3157         SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
3158                           -84, 40, digital_gain),
3159         SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
3160                           -84, 40, digital_gain),
3161         SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
3162                           -84, 40, digital_gain),
3163         SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
3164                           WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
3165                           -84, 40, digital_gain),
3166         SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
3167                           WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
3168                           -84, 40, digital_gain),
3169         SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
3170                           WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
3171                           -84, 40, digital_gain),
3172         SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
3173                           WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
3174                           -84, 40, digital_gain),
3175         SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
3176                           WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
3177                           -84, 40, digital_gain),
3178         SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
3179                           WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
3180                           -84, 40, digital_gain),
3181         SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
3182                           WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
3183                           -84, 40, digital_gain),
3184
3185         SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
3186                           -84, 40, digital_gain),
3187         SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
3188                           -84, 40, digital_gain),
3189         SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
3190                           -84, 40, digital_gain),
3191         SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
3192                           -84, 40, digital_gain),
3193         SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
3194                           -84, 40, digital_gain),
3195         SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
3196                           -84, 40, digital_gain),
3197         SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
3198                           -84, 40, digital_gain),
3199         SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
3200                           -84, 40, digital_gain),
3201         SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
3202                           -84, 40, digital_gain),
3203
3204         SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
3205                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
3206                           digital_gain),
3207         SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
3208                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
3209                           digital_gain),
3210         SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
3211                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
3212                           digital_gain),
3213         SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
3214                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
3215                           digital_gain),
3216         SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
3217                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
3218                           digital_gain),
3219         SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
3220                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
3221                           digital_gain),
3222         SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
3223                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
3224                           digital_gain),
3225         SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
3226                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
3227                           digital_gain),
3228
3229         SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
3230         SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
3231         SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
3232         SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
3233         SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
3234         SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
3235         SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
3236         SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
3237         SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
3238
3239         SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
3240         SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
3241         SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
3242         SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
3243         SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
3244         SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
3245         SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
3246         SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
3247         SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
3248         SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
3249         SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
3250         SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
3251         SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
3252         SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
3253
3254         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
3255                      wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
3256
3257         SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3258                    0, 1, 0),
3259         SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3260                    1, 1, 0),
3261         SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3262                    2, 1, 0),
3263         SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3264                    3, 1, 0),
3265         SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
3266                    4, 1, 0),
3267         SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3268                    0, 1, 0),
3269         SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3270                    1, 1, 0),
3271         SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3272                    2, 1, 0),
3273         SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3274                    3, 1, 0),
3275         SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
3276                    4, 1, 0),
3277         WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
3278         WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
3279         WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
3280         WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
3281         WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
3282
3283         WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
3284         WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
3285         WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
3286         WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
3287         WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
3288
3289         SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
3290                        wcd934x_compander_get, wcd934x_compander_set),
3291         SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
3292                        wcd934x_compander_get, wcd934x_compander_set),
3293         SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
3294                        wcd934x_compander_get, wcd934x_compander_set),
3295         SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
3296                        wcd934x_compander_get, wcd934x_compander_set),
3297         SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
3298                        wcd934x_compander_get, wcd934x_compander_set),
3299         SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
3300                        wcd934x_compander_get, wcd934x_compander_set),
3301 };
3302
3303 static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
3304                                           struct snd_soc_component *component)
3305 {
3306         int port_num = 0;
3307         unsigned short reg = 0;
3308         unsigned int val = 0;
3309         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3310         struct wcd934x_slim_ch *ch;
3311
3312         list_for_each_entry(ch, &dai->slim_ch_list, list) {
3313                 if (ch->port >= WCD934X_RX_START) {
3314                         port_num = ch->port - WCD934X_RX_START;
3315                         reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
3316                 } else {
3317                         port_num = ch->port;
3318                         reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
3319                 }
3320
3321                 regmap_read(wcd->if_regmap, reg, &val);
3322                 if (!(val & BIT(port_num % 8)))
3323                         regmap_write(wcd->if_regmap, reg,
3324                                      val | BIT(port_num % 8));
3325         }
3326 }
3327
3328 static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
3329                                      struct snd_kcontrol *kc, int event)
3330 {
3331         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3332         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
3333         struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
3334
3335         switch (event) {
3336         case SND_SOC_DAPM_POST_PMU:
3337                 wcd934x_codec_enable_int_port(dai, comp);
3338                 break;
3339         }
3340
3341         return 0;
3342 }
3343
3344 static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
3345                                       u16 interp_idx, int event)
3346 {
3347         u16 hd2_scale_reg;
3348         u16 hd2_enable_reg = 0;
3349
3350         switch (interp_idx) {
3351         case INTERP_HPHL:
3352                 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
3353                 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
3354                 break;
3355         case INTERP_HPHR:
3356                 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
3357                 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
3358                 break;
3359         default:
3360                 return;
3361         }
3362
3363         if (SND_SOC_DAPM_EVENT_ON(event)) {
3364                 snd_soc_component_update_bits(component, hd2_scale_reg,
3365                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3366                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
3367                 snd_soc_component_update_bits(component, hd2_enable_reg,
3368                                       WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
3369                                       WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
3370         }
3371
3372         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3373                 snd_soc_component_update_bits(component, hd2_enable_reg,
3374                                       WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
3375                                       WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
3376                 snd_soc_component_update_bits(component, hd2_scale_reg,
3377                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3378                                       WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3379         }
3380 }
3381
3382 static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
3383                                              u16 interp_idx, int event)
3384 {
3385         u8 hph_dly_mask;
3386         u16 hph_lut_bypass_reg = 0;
3387
3388         switch (interp_idx) {
3389         case INTERP_HPHL:
3390                 hph_dly_mask = 1;
3391                 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
3392                 break;
3393         case INTERP_HPHR:
3394                 hph_dly_mask = 2;
3395                 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
3396                 break;
3397         default:
3398                 return;
3399         }
3400
3401         if (SND_SOC_DAPM_EVENT_ON(event)) {
3402                 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
3403                                               hph_dly_mask, 0x0);
3404                 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
3405                                               WCD934X_HPH_LUT_BYPASS_MASK,
3406                                               WCD934X_HPH_LUT_BYPASS_ENABLE);
3407         }
3408
3409         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3410                 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
3411                                               hph_dly_mask, hph_dly_mask);
3412                 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
3413                                               WCD934X_HPH_LUT_BYPASS_MASK,
3414                                               WCD934X_HPH_LUT_BYPASS_DISABLE);
3415         }
3416 }
3417
3418 static int wcd934x_config_compander(struct snd_soc_component *comp,
3419                                     int interp_n, int event)
3420 {
3421         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3422         int compander;
3423         u16 comp_ctl0_reg, rx_path_cfg0_reg;
3424
3425         /* EAR does not have compander */
3426         if (!interp_n)
3427                 return 0;
3428
3429         compander = interp_n - 1;
3430         if (!wcd->comp_enabled[compander])
3431                 return 0;
3432
3433         comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
3434         rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
3435
3436         switch (event) {
3437         case SND_SOC_DAPM_PRE_PMU:
3438                 /* Enable Compander Clock */
3439                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3440                                               WCD934X_COMP_CLK_EN_MASK,
3441                                               WCD934X_COMP_CLK_ENABLE);
3442                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3443                                               WCD934X_COMP_SOFT_RST_MASK,
3444                                               WCD934X_COMP_SOFT_RST_ENABLE);
3445                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3446                                               WCD934X_COMP_SOFT_RST_MASK,
3447                                               WCD934X_COMP_SOFT_RST_DISABLE);
3448                 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
3449                                               WCD934X_HPH_CMP_EN_MASK,
3450                                               WCD934X_HPH_CMP_ENABLE);
3451                 break;
3452         case SND_SOC_DAPM_POST_PMD:
3453                 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
3454                                               WCD934X_HPH_CMP_EN_MASK,
3455                                               WCD934X_HPH_CMP_DISABLE);
3456                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3457                                               WCD934X_COMP_HALT_MASK,
3458                                               WCD934X_COMP_HALT);
3459                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3460                                               WCD934X_COMP_SOFT_RST_MASK,
3461                                               WCD934X_COMP_SOFT_RST_ENABLE);
3462                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3463                                               WCD934X_COMP_SOFT_RST_MASK,
3464                                               WCD934X_COMP_SOFT_RST_DISABLE);
3465                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3466                                               WCD934X_COMP_CLK_EN_MASK, 0x0);
3467                 snd_soc_component_update_bits(comp, comp_ctl0_reg,
3468                                               WCD934X_COMP_SOFT_RST_MASK, 0x0);
3469                 break;
3470         }
3471
3472         return 0;
3473 }
3474
3475 static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
3476                                          struct snd_kcontrol *kc, int event)
3477 {
3478         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3479         int interp_idx = w->shift;
3480         u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
3481
3482         switch (event) {
3483         case SND_SOC_DAPM_PRE_PMU:
3484                 /* Clk enable */
3485                 snd_soc_component_update_bits(comp, main_reg,
3486                                              WCD934X_RX_CLK_EN_MASK,
3487                                              WCD934X_RX_CLK_ENABLE);
3488                 wcd934x_codec_hd2_control(comp, interp_idx, event);
3489                 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
3490                 wcd934x_config_compander(comp, interp_idx, event);
3491                 break;
3492         case SND_SOC_DAPM_POST_PMD:
3493                 wcd934x_config_compander(comp, interp_idx, event);
3494                 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
3495                 wcd934x_codec_hd2_control(comp, interp_idx, event);
3496                 /* Clk Disable */
3497                 snd_soc_component_update_bits(comp, main_reg,
3498                                              WCD934X_RX_CLK_EN_MASK, 0);
3499                 /* Reset enable and disable */
3500                 snd_soc_component_update_bits(comp, main_reg,
3501                                               WCD934X_RX_RESET_MASK,
3502                                               WCD934X_RX_RESET_ENABLE);
3503                 snd_soc_component_update_bits(comp, main_reg,
3504                                               WCD934X_RX_RESET_MASK,
3505                                               WCD934X_RX_RESET_DISABLE);
3506                 /* Reset rate to 48K*/
3507                 snd_soc_component_update_bits(comp, main_reg,
3508                                               WCD934X_RX_PCM_RATE_MASK,
3509                                               WCD934X_RX_PCM_RATE_F_48K);
3510                 break;
3511         }
3512
3513         return 0;
3514 }
3515
3516 static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
3517                                          struct snd_kcontrol *kc, int event)
3518 {
3519         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3520         int offset_val = 0;
3521         u16 gain_reg, mix_reg;
3522         int val = 0;
3523
3524         gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
3525                                         (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
3526         mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
3527                                         (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
3528
3529         switch (event) {
3530         case SND_SOC_DAPM_PRE_PMU:
3531                 /* Clk enable */
3532                 snd_soc_component_update_bits(comp, mix_reg,
3533                                               WCD934X_CDC_RX_MIX_CLK_EN_MASK,
3534                                               WCD934X_CDC_RX_MIX_CLK_ENABLE);
3535                 break;
3536
3537         case SND_SOC_DAPM_POST_PMU:
3538                 val = snd_soc_component_read32(comp, gain_reg);
3539                 val += offset_val;
3540                 snd_soc_component_write(comp, gain_reg, val);
3541                 break;
3542         };
3543
3544         return 0;
3545 }
3546
3547 static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
3548                                       struct snd_kcontrol *kcontrol, int event)
3549 {
3550         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3551         int reg = w->reg;
3552
3553         switch (event) {
3554         case SND_SOC_DAPM_POST_PMU:
3555                 /* B1 GAIN */
3556                 snd_soc_component_write(comp, reg,
3557                                         snd_soc_component_read32(comp, reg));
3558                 /* B2 GAIN */
3559                 reg++;
3560                 snd_soc_component_write(comp, reg,
3561                                         snd_soc_component_read32(comp, reg));
3562                 /* B3 GAIN */
3563                 reg++;
3564                 snd_soc_component_write(comp, reg,
3565                                         snd_soc_component_read32(comp, reg));
3566                 /* B4 GAIN */
3567                 reg++;
3568                 snd_soc_component_write(comp, reg,
3569                                         snd_soc_component_read32(comp, reg));
3570                 /* B5 GAIN */
3571                 reg++;
3572                 snd_soc_component_write(comp, reg,
3573                                         snd_soc_component_read32(comp, reg));
3574                 break;
3575         default:
3576                 break;
3577         }
3578         return 0;
3579 }
3580
3581 static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
3582                                           struct snd_kcontrol *kcontrol,
3583                                           int event)
3584 {
3585         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3586         u16 gain_reg;
3587
3588         gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
3589                                                  WCD934X_RX_PATH_CTL_OFFSET);
3590
3591         switch (event) {
3592         case SND_SOC_DAPM_POST_PMU:
3593                 snd_soc_component_write(comp, gain_reg,
3594                                 snd_soc_component_read32(comp, gain_reg));
3595                 break;
3596         };
3597
3598         return 0;
3599 }
3600
3601 static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3602                                        struct snd_kcontrol *kc, int event)
3603 {
3604         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3605         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3606
3607         switch (event) {
3608         case SND_SOC_DAPM_PRE_PMU:
3609                 /* Disable AutoChop timer during power up */
3610                 snd_soc_component_update_bits(comp,
3611                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
3612                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3613                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3614                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3615
3616                 break;
3617         case SND_SOC_DAPM_POST_PMD:
3618                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3619                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3620                 break;
3621         };
3622
3623         return 0;
3624 }
3625
3626 static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3627                                         struct snd_kcontrol *kcontrol,
3628                                         int event)
3629 {
3630         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3631         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3632         int hph_mode = wcd->hph_mode;
3633         u8 dem_inp;
3634
3635         switch (event) {
3636         case SND_SOC_DAPM_PRE_PMU:
3637                 /* Read DEM INP Select */
3638                 dem_inp = snd_soc_component_read32(comp,
3639                                    WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
3640
3641                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3642                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3643                         return -EINVAL;
3644                 }
3645                 if (hph_mode != CLS_H_LP)
3646                         /* Ripple freq control enable */
3647                         snd_soc_component_update_bits(comp,
3648                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3649                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
3650                                         WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
3651                 /* Disable AutoChop timer during power up */
3652                 snd_soc_component_update_bits(comp,
3653                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
3654                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3655                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3656                                         WCD_CLSH_STATE_HPHL, hph_mode);
3657
3658                 break;
3659         case SND_SOC_DAPM_POST_PMD:
3660                 /* 1000us required as per HW requirement */
3661                 usleep_range(1000, 1100);
3662                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3663                                         WCD_CLSH_STATE_HPHL, hph_mode);
3664                 if (hph_mode != CLS_H_LP)
3665                         /* Ripple freq control disable */
3666                         snd_soc_component_update_bits(comp,
3667                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3668                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
3669
3670                 break;
3671         default:
3672                 break;
3673         };
3674
3675         return 0;
3676 }
3677
3678 static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3679                                         struct snd_kcontrol *kcontrol,
3680                                         int event)
3681 {
3682         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3683         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3684         int hph_mode = wcd->hph_mode;
3685         u8 dem_inp;
3686
3687         switch (event) {
3688         case SND_SOC_DAPM_PRE_PMU:
3689                 dem_inp = snd_soc_component_read32(comp,
3690                                         WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
3691                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3692                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3693                         return -EINVAL;
3694                 }
3695                 if (hph_mode != CLS_H_LP)
3696                         /* Ripple freq control enable */
3697                         snd_soc_component_update_bits(comp,
3698                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3699                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
3700                                         WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
3701                 /* Disable AutoChop timer during power up */
3702                 snd_soc_component_update_bits(comp,
3703                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
3704                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
3705                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3706                                         WCD_CLSH_STATE_HPHR,
3707                              hph_mode);
3708                 break;
3709         case SND_SOC_DAPM_POST_PMD:
3710                 /* 1000us required as per HW requirement */
3711                 usleep_range(1000, 1100);
3712
3713                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3714                                         WCD_CLSH_STATE_HPHR, hph_mode);
3715                 if (hph_mode != CLS_H_LP)
3716                         /* Ripple freq control disable */
3717                         snd_soc_component_update_bits(comp,
3718                                         WCD934X_SIDO_NEW_VOUT_D_FREQ2,
3719                                         WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
3720                 break;
3721         default:
3722                 break;
3723         };
3724
3725         return 0;
3726 }
3727
3728 static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3729                                            struct snd_kcontrol *kc, int event)
3730 {
3731         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3732         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3733
3734         switch (event) {
3735         case SND_SOC_DAPM_PRE_PMU:
3736                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3737                                         WCD_CLSH_STATE_LO, CLS_AB);
3738                 break;
3739         case SND_SOC_DAPM_POST_PMD:
3740                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3741                                         WCD_CLSH_STATE_LO, CLS_AB);
3742                 break;
3743         }
3744
3745         return 0;
3746 }
3747
3748 static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3749                                         struct snd_kcontrol *kcontrol,
3750                                         int event)
3751 {
3752         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3753
3754         switch (event) {
3755         case SND_SOC_DAPM_POST_PMU:
3756                 /*
3757                  * 7ms sleep is required after PA is enabled as per
3758                  * HW requirement. If compander is disabled, then
3759                  * 20ms delay is needed.
3760                  */
3761                 usleep_range(20000, 20100);
3762
3763                 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
3764                                               WCD934X_HPH_OCP_DET_MASK,
3765                                               WCD934X_HPH_OCP_DET_ENABLE);
3766                 /* Remove Mute on primary path */
3767                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
3768                                       WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3769                                       0);
3770                 /* Enable GM3 boost */
3771                 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
3772                                               WCD934X_HPH_GM3_BOOST_EN_MASK,
3773                                               WCD934X_HPH_GM3_BOOST_ENABLE);
3774                 /* Enable AutoChop timer at the end of power up */
3775                 snd_soc_component_update_bits(comp,
3776                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
3777                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
3778                                       WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
3779                 /* Remove mix path mute */
3780                 snd_soc_component_update_bits(comp,
3781                                 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
3782                                 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
3783                 break;
3784         case SND_SOC_DAPM_PRE_PMD:
3785                 /* Enable DSD Mute before PA disable */
3786                 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
3787                                               WCD934X_HPH_OCP_DET_MASK,
3788                                               WCD934X_HPH_OCP_DET_DISABLE);
3789                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
3790                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3791                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3792                 snd_soc_component_update_bits(comp,
3793                                               WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
3794                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3795                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3796                 break;
3797         case SND_SOC_DAPM_POST_PMD:
3798                 /*
3799                  * 5ms sleep is required after PA disable. If compander is
3800                  * disabled, then 20ms delay is needed after PA disable.
3801                  */
3802                 usleep_range(20000, 20100);
3803                 break;
3804         };
3805
3806         return 0;
3807 }
3808
3809 static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3810                                         struct snd_kcontrol *kcontrol,
3811                                         int event)
3812 {
3813         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3814
3815         switch (event) {
3816         case SND_SOC_DAPM_POST_PMU:
3817                 /*
3818                  * 7ms sleep is required after PA is enabled as per
3819                  * HW requirement. If compander is disabled, then
3820                  * 20ms delay is needed.
3821                  */
3822                 usleep_range(20000, 20100);
3823                 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
3824                                               WCD934X_HPH_OCP_DET_MASK,
3825                                               WCD934X_HPH_OCP_DET_ENABLE);
3826                 /* Remove mute */
3827                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
3828                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3829                                               0);
3830                 /* Enable GM3 boost */
3831                 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
3832                                               WCD934X_HPH_GM3_BOOST_EN_MASK,
3833                                               WCD934X_HPH_GM3_BOOST_ENABLE);
3834                 /* Enable AutoChop timer at the end of power up */
3835                 snd_soc_component_update_bits(comp,
3836                                       WCD934X_HPH_NEW_INT_HPH_TIMER1,
3837                                       WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
3838                                       WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
3839                 /* Remove mix path mute if it is enabled */
3840                 if ((snd_soc_component_read32(comp,
3841                                       WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
3842                         snd_soc_component_update_bits(comp,
3843                                               WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
3844                                               WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
3845                                               WCD934X_CDC_RX_PGA_MUTE_DISABLE);
3846                 break;
3847         case SND_SOC_DAPM_PRE_PMD:
3848                 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
3849                                               WCD934X_HPH_OCP_DET_MASK,
3850                                               WCD934X_HPH_OCP_DET_DISABLE);
3851                 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
3852                                               WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
3853                                               WCD934X_RX_PATH_PGA_MUTE_ENABLE);
3854                 snd_soc_component_update_bits(comp,
3855                                               WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
3856                                               WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
3857                                               WCD934X_CDC_RX_PGA_MUTE_ENABLE);
3858                 break;
3859         case SND_SOC_DAPM_POST_PMD:
3860                 /*
3861                  * 5ms sleep is required after PA disable. If compander is
3862                  * disabled, then 20ms delay is needed after PA disable.
3863                  */
3864                 usleep_range(20000, 20100);
3865                 break;
3866         };
3867
3868         return 0;
3869 }
3870
3871 static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
3872                                         unsigned int dmic,
3873                                       struct wcd934x_codec *wcd)
3874 {
3875         u8 tx_stream_fs;
3876         u8 adc_mux_index = 0, adc_mux_sel = 0;
3877         bool dec_found = false;
3878         u16 adc_mux_ctl_reg, tx_fs_reg;
3879         u32 dmic_fs;
3880
3881         while (dec_found == 0 && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
3882                 if (adc_mux_index < 4) {
3883                         adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
3884                                                 (adc_mux_index * 2);
3885                 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
3886                         adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
3887                                                 adc_mux_index - 4;
3888                 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
3889                         ++adc_mux_index;
3890                         continue;
3891                 }
3892                 adc_mux_sel = ((snd_soc_component_read32(comp, adc_mux_ctl_reg)
3893                                & 0xF8) >> 3) - 1;
3894
3895                 if (adc_mux_sel == dmic) {
3896                         dec_found = true;
3897                         break;
3898                 }
3899
3900                 ++adc_mux_index;
3901         }
3902
3903         if (dec_found && adc_mux_index <= 8) {
3904                 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
3905                 tx_stream_fs = snd_soc_component_read32(comp, tx_fs_reg) & 0x0F;
3906                 if (tx_stream_fs <= 4)  {
3907                         if (wcd->dmic_sample_rate <=
3908                                         WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ)
3909                                 dmic_fs = wcd->dmic_sample_rate;
3910                         else
3911                                 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ;
3912                 } else
3913                         dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
3914         } else {
3915                 dmic_fs = wcd->dmic_sample_rate;
3916         }
3917
3918         return dmic_fs;
3919 }
3920
3921 static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
3922                                    u32 mclk_rate, u32 dmic_clk_rate)
3923 {
3924         u32 div_factor;
3925         u8 dmic_ctl_val;
3926
3927         /* Default value to return in case of error */
3928         if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
3929                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
3930         else
3931                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
3932
3933         if (dmic_clk_rate == 0) {
3934                 dev_err(comp->dev,
3935                         "%s: dmic_sample_rate cannot be 0\n",
3936                         __func__);
3937                 goto done;
3938         }
3939
3940         div_factor = mclk_rate / dmic_clk_rate;
3941         switch (div_factor) {
3942         case 2:
3943                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
3944                 break;
3945         case 3:
3946                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
3947                 break;
3948         case 4:
3949                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
3950                 break;
3951         case 6:
3952                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
3953                 break;
3954         case 8:
3955                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
3956                 break;
3957         case 16:
3958                 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
3959                 break;
3960         default:
3961                 dev_err(comp->dev,
3962                         "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
3963                         __func__, div_factor, mclk_rate, dmic_clk_rate);
3964                 break;
3965         }
3966
3967 done:
3968         return dmic_ctl_val;
3969 }
3970
3971 static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
3972                                      struct snd_kcontrol *kcontrol, int event)
3973 {
3974         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3975         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3976         u8  dmic_clk_en = 0x01;
3977         u16 dmic_clk_reg;
3978         s32 *dmic_clk_cnt;
3979         u8 dmic_rate_val, dmic_rate_shift = 1;
3980         unsigned int dmic;
3981         u32 dmic_sample_rate;
3982         int ret;
3983         char *wname;
3984
3985         wname = strpbrk(w->name, "012345");
3986         if (!wname) {
3987                 dev_err(comp->dev, "%s: widget not found\n", __func__);
3988                 return -EINVAL;
3989         }
3990
3991         ret = kstrtouint(wname, 10, &dmic);
3992         if (ret < 0) {
3993                 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
3994                         __func__);
3995                 return -EINVAL;
3996         }
3997
3998         switch (dmic) {
3999         case 0:
4000         case 1:
4001                 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
4002                 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
4003                 break;
4004         case 2:
4005         case 3:
4006                 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
4007                 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
4008                 break;
4009         case 4:
4010         case 5:
4011                 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
4012                 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
4013                 break;
4014         default:
4015                 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
4016                         __func__);
4017                 return -EINVAL;
4018         };
4019
4020         switch (event) {
4021         case SND_SOC_DAPM_PRE_PMU:
4022                 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
4023                                                                 wcd);
4024                 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
4025                                                          dmic_sample_rate);
4026                 (*dmic_clk_cnt)++;
4027                 if (*dmic_clk_cnt == 1) {
4028                         dmic_rate_val = dmic_rate_val << dmic_rate_shift;
4029                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4030                                                       WCD934X_DMIC_RATE_MASK,
4031                                                       dmic_rate_val);
4032                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4033                                                       dmic_clk_en, dmic_clk_en);
4034                 }
4035
4036                 break;
4037         case SND_SOC_DAPM_POST_PMD:
4038                 (*dmic_clk_cnt)--;
4039                 if (*dmic_clk_cnt == 0)
4040                         snd_soc_component_update_bits(comp, dmic_clk_reg,
4041                                                       dmic_clk_en, 0);
4042                 break;
4043         };
4044
4045         return 0;
4046 }
4047
4048 static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
4049                                          int adc_mux_n)
4050 {
4051         u16 mask, shift, adc_mux_in_reg;
4052         u16 amic_mux_sel_reg;
4053         bool is_amic;
4054
4055         if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
4056             adc_mux_n == WCD934X_INVALID_ADC_MUX)
4057                 return 0;
4058
4059         if (adc_mux_n < 3) {
4060                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4061                                  adc_mux_n;
4062                 mask = 0x03;
4063                 shift = 0;
4064                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4065                                    2 * adc_mux_n;
4066         } else if (adc_mux_n < 4) {
4067                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4068                 mask = 0x03;
4069                 shift = 0;
4070                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4071                                    2 * adc_mux_n;
4072         } else if (adc_mux_n < 7) {
4073                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4074                                  (adc_mux_n - 4);
4075                 mask = 0x0C;
4076                 shift = 2;
4077                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4078                                    adc_mux_n - 4;
4079         } else if (adc_mux_n < 8) {
4080                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4081                 mask = 0x0C;
4082                 shift = 2;
4083                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4084                                    adc_mux_n - 4;
4085         } else if (adc_mux_n < 12) {
4086                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4087                                  ((adc_mux_n == 8) ? (adc_mux_n - 8) :
4088                                   (adc_mux_n - 9));
4089                 mask = 0x30;
4090                 shift = 4;
4091                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4092                                    adc_mux_n - 4;
4093         } else if (adc_mux_n < 13) {
4094                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4095                 mask = 0x30;
4096                 shift = 4;
4097                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4098                                    adc_mux_n - 4;
4099         } else {
4100                 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
4101                 mask = 0xC0;
4102                 shift = 6;
4103                 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4104                                    adc_mux_n - 4;
4105         }
4106
4107         is_amic = (((snd_soc_component_read32(comp, adc_mux_in_reg)
4108                      & mask) >> shift) == 1);
4109         if (!is_amic)
4110                 return 0;
4111
4112         return snd_soc_component_read32(comp, amic_mux_sel_reg) & 0x07;
4113 }
4114
4115 static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
4116                                             int amic)
4117 {
4118         u16 pwr_level_reg = 0;
4119
4120         switch (amic) {
4121         case 1:
4122         case 2:
4123                 pwr_level_reg = WCD934X_ANA_AMIC1;
4124                 break;
4125
4126         case 3:
4127         case 4:
4128                 pwr_level_reg = WCD934X_ANA_AMIC3;
4129                 break;
4130         default:
4131                 break;
4132         }
4133
4134         return pwr_level_reg;
4135 }
4136
4137 static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
4138                                     struct snd_kcontrol *kcontrol, int event)
4139 {
4140         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4141         unsigned int decimator;
4142         char *dec_adc_mux_name = NULL;
4143         char *widget_name = NULL;
4144         char *wname;
4145         int ret = 0, amic_n;
4146         u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
4147         u16 tx_gain_ctl_reg;
4148         char *dec;
4149         u8 hpf_coff_freq;
4150
4151         widget_name = kstrndup(w->name, 15, GFP_KERNEL);
4152         if (!widget_name)
4153                 return -ENOMEM;
4154
4155         wname = widget_name;
4156         dec_adc_mux_name = strsep(&widget_name, " ");
4157         if (!dec_adc_mux_name) {
4158                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4159                         __func__, w->name);
4160                 ret =  -EINVAL;
4161                 goto out;
4162         }
4163         dec_adc_mux_name = widget_name;
4164
4165         dec = strpbrk(dec_adc_mux_name, "012345678");
4166         if (!dec) {
4167                 dev_err(comp->dev, "%s: decimator index not found\n",
4168                         __func__);
4169                 ret =  -EINVAL;
4170                 goto out;
4171         }
4172
4173         ret = kstrtouint(dec, 10, &decimator);
4174         if (ret < 0) {
4175                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4176                         __func__, wname);
4177                 ret =  -EINVAL;
4178                 goto out;
4179         }
4180
4181         tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
4182         hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
4183         dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
4184         tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
4185
4186         switch (event) {
4187         case SND_SOC_DAPM_PRE_PMU:
4188                 amic_n = wcd934x_codec_find_amic_input(comp, decimator);
4189                 if (amic_n)
4190                         pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
4191                                                                  amic_n);
4192
4193                 if (!pwr_level_reg)
4194                         break;
4195
4196                 switch ((snd_soc_component_read32(comp, pwr_level_reg) &
4197                                       WCD934X_AMIC_PWR_LVL_MASK) >>
4198                                       WCD934X_AMIC_PWR_LVL_SHIFT) {
4199                 case WCD934X_AMIC_PWR_LEVEL_LP:
4200                         snd_soc_component_update_bits(comp, dec_cfg_reg,
4201                                         WCD934X_DEC_PWR_LVL_MASK,
4202                                         WCD934X_DEC_PWR_LVL_LP);
4203                         break;
4204                 case WCD934X_AMIC_PWR_LEVEL_HP:
4205                         snd_soc_component_update_bits(comp, dec_cfg_reg,
4206                                         WCD934X_DEC_PWR_LVL_MASK,
4207                                         WCD934X_DEC_PWR_LVL_HP);
4208                         break;
4209                 case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
4210                 case WCD934X_AMIC_PWR_LEVEL_HYBRID:
4211                 default:
4212                         snd_soc_component_update_bits(comp, dec_cfg_reg,
4213                                         WCD934X_DEC_PWR_LVL_MASK,
4214                                         WCD934X_DEC_PWR_LVL_DF);
4215                         break;
4216                 }
4217                 break;
4218         case SND_SOC_DAPM_POST_PMU:
4219                 hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) &
4220                                  TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
4221                 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
4222                         snd_soc_component_update_bits(comp, dec_cfg_reg,
4223                                                       TX_HPF_CUT_OFF_FREQ_MASK,
4224                                                       CF_MIN_3DB_150HZ << 5);
4225                         snd_soc_component_update_bits(comp, hpf_gate_reg,
4226                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4227                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
4228                         /*
4229                          * Minimum 1 clk cycle delay is required as per
4230                          * HW spec.
4231                          */
4232                         usleep_range(1000, 1010);
4233                         snd_soc_component_update_bits(comp, hpf_gate_reg,
4234                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4235                                       0);
4236                 }
4237                 /* apply gain after decimator is enabled */
4238                 snd_soc_component_write(comp, tx_gain_ctl_reg,
4239                                         snd_soc_component_read32(comp,
4240                                                          tx_gain_ctl_reg));
4241                 break;
4242         case SND_SOC_DAPM_PRE_PMD:
4243                 hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) &
4244                                  TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
4245
4246                 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
4247                         snd_soc_component_update_bits(comp, dec_cfg_reg,
4248                                                       TX_HPF_CUT_OFF_FREQ_MASK,
4249                                                       hpf_coff_freq << 5);
4250                         snd_soc_component_update_bits(comp, hpf_gate_reg,
4251                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4252                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
4253                                 /*
4254                                  * Minimum 1 clk cycle delay is required as per
4255                                  * HW spec.
4256                                  */
4257                         usleep_range(1000, 1010);
4258                         snd_soc_component_update_bits(comp, hpf_gate_reg,
4259                                       WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
4260                                       0);
4261                 }
4262                 break;
4263         case SND_SOC_DAPM_POST_PMD:
4264                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
4265                                               0x10, 0x00);
4266                 snd_soc_component_update_bits(comp, dec_cfg_reg,
4267                                               WCD934X_DEC_PWR_LVL_MASK,
4268                                               WCD934X_DEC_PWR_LVL_DF);
4269                 break;
4270         };
4271 out:
4272         kfree(wname);
4273         return ret;
4274 }
4275
4276 static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
4277                                       u16 amic_reg, bool set)
4278 {
4279         u8 mask = 0x20;
4280         u8 val;
4281
4282         if (amic_reg == WCD934X_ANA_AMIC1 ||
4283             amic_reg == WCD934X_ANA_AMIC3)
4284                 mask = 0x40;
4285
4286         val = set ? mask : 0x00;
4287
4288         switch (amic_reg) {
4289         case WCD934X_ANA_AMIC1:
4290         case WCD934X_ANA_AMIC2:
4291                 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
4292                                               mask, val);
4293                 break;
4294         case WCD934X_ANA_AMIC3:
4295         case WCD934X_ANA_AMIC4:
4296                 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
4297                                               mask, val);
4298                 break;
4299         default:
4300                 break;
4301         }
4302 }
4303
4304 static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
4305                                     struct snd_kcontrol *kcontrol, int event)
4306 {
4307         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4308
4309         switch (event) {
4310         case SND_SOC_DAPM_PRE_PMU:
4311                 wcd934x_codec_set_tx_hold(comp, w->reg, true);
4312                 break;
4313         default:
4314                 break;
4315         }
4316
4317         return 0;
4318 }
4319
4320 static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
4321         /* Analog Outputs */
4322         SND_SOC_DAPM_OUTPUT("EAR"),
4323         SND_SOC_DAPM_OUTPUT("HPHL"),
4324         SND_SOC_DAPM_OUTPUT("HPHR"),
4325         SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4326         SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4327         SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
4328         SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
4329         SND_SOC_DAPM_OUTPUT("ANC EAR"),
4330         SND_SOC_DAPM_OUTPUT("ANC HPHL"),
4331         SND_SOC_DAPM_OUTPUT("ANC HPHR"),
4332         SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
4333         SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
4334         SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
4335         SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4336                               AIF1_PB, 0, wcd934x_codec_enable_slim,
4337                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4338         SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4339                               AIF2_PB, 0, wcd934x_codec_enable_slim,
4340                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4341         SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4342                               AIF3_PB, 0, wcd934x_codec_enable_slim,
4343                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4344         SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4345                               AIF4_PB, 0, wcd934x_codec_enable_slim,
4346                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4347
4348         SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
4349                          &slim_rx_mux[WCD934X_RX0]),
4350         SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
4351                          &slim_rx_mux[WCD934X_RX1]),
4352         SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
4353                          &slim_rx_mux[WCD934X_RX2]),
4354         SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
4355                          &slim_rx_mux[WCD934X_RX3]),
4356         SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
4357                          &slim_rx_mux[WCD934X_RX4]),
4358         SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
4359                          &slim_rx_mux[WCD934X_RX5]),
4360         SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
4361                          &slim_rx_mux[WCD934X_RX6]),
4362         SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
4363                          &slim_rx_mux[WCD934X_RX7]),
4364
4365         SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4366         SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4367         SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4368         SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4369         SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4370         SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4371         SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4372         SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4373
4374         SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
4375                            &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
4376                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4377                            SND_SOC_DAPM_POST_PMD),
4378         SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
4379                            &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
4380                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4381                            SND_SOC_DAPM_POST_PMD),
4382         SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
4383                            &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
4384                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4385                            SND_SOC_DAPM_POST_PMD),
4386         SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
4387                            &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
4388                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4389                            SND_SOC_DAPM_POST_PMD),
4390         SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
4391                            &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
4392                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4393                            SND_SOC_DAPM_POST_PMD),
4394         SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
4395                            &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
4396                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4397                            SND_SOC_DAPM_POST_PMD),
4398         SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
4399                            &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
4400                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4401                            SND_SOC_DAPM_POST_PMD),
4402
4403         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4404                          &rx_int0_1_mix_inp0_mux),
4405         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4406                          &rx_int0_1_mix_inp1_mux),
4407         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4408                          &rx_int0_1_mix_inp2_mux),
4409         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4410                          &rx_int1_1_mix_inp0_mux),
4411         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4412                          &rx_int1_1_mix_inp1_mux),
4413         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4414                          &rx_int1_1_mix_inp2_mux),
4415         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4416                          &rx_int2_1_mix_inp0_mux),
4417         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4418                          &rx_int2_1_mix_inp1_mux),
4419         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4420                          &rx_int2_1_mix_inp2_mux),
4421         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4422                          &rx_int3_1_mix_inp0_mux),
4423         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4424                          &rx_int3_1_mix_inp1_mux),
4425         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4426                          &rx_int3_1_mix_inp2_mux),
4427         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4428                          &rx_int4_1_mix_inp0_mux),
4429         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4430                          &rx_int4_1_mix_inp1_mux),
4431         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4432                          &rx_int4_1_mix_inp2_mux),
4433         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4434                            &rx_int7_1_mix_inp0_mux),
4435         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4436                            &rx_int7_1_mix_inp1_mux),
4437         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4438                            &rx_int7_1_mix_inp2_mux),
4439         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4440                            &rx_int8_1_mix_inp0_mux),
4441         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4442                            &rx_int8_1_mix_inp1_mux),
4443         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4444                            &rx_int8_1_mix_inp2_mux),
4445         SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4446         SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4447         SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4448         SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
4449                            rx_int1_asrc_switch,
4450                            ARRAY_SIZE(rx_int1_asrc_switch)),
4451         SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4452         SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
4453                            rx_int2_asrc_switch,
4454                            ARRAY_SIZE(rx_int2_asrc_switch)),
4455         SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4456         SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
4457                            rx_int3_asrc_switch,
4458                            ARRAY_SIZE(rx_int3_asrc_switch)),
4459         SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4460         SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
4461                            rx_int4_asrc_switch,
4462                            ARRAY_SIZE(rx_int4_asrc_switch)),
4463         SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4464         SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4465         SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4466         SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4467         SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4468         SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4469         SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4470         SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4471         SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4472         SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4473         SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4474         SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4475         SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4476
4477         SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4478         SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
4479                              NULL, 0, NULL, 0),
4480         SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
4481                              NULL, 0, NULL, 0),
4482         SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
4483                            0,  &rx_int0_mix2_inp_mux, NULL,
4484                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4485         SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
4486                            0, &rx_int1_mix2_inp_mux,  NULL,
4487                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4488         SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
4489                            0, &rx_int2_mix2_inp_mux, NULL,
4490                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4491         SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
4492                            0, &rx_int3_mix2_inp_mux, NULL,
4493                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4494         SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
4495                            0, &rx_int4_mix2_inp_mux, NULL,
4496                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4497         SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
4498                            0, &rx_int7_mix2_inp_mux, NULL,
4499                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4500
4501         SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
4502         SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
4503         SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
4504         SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
4505         SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
4506         SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
4507         SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
4508         SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
4509
4510         SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
4511                            0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
4512                            SND_SOC_DAPM_POST_PMU),
4513         SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
4514                            1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
4515                            SND_SOC_DAPM_POST_PMU),
4516         SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
4517                            4, 0, NULL, 0),
4518         SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
4519                            4, 0, NULL, 0),
4520         SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4521                          &rx_int0_dem_inp_mux),
4522         SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4523                          &rx_int1_dem_inp_mux),
4524         SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4525                          &rx_int2_dem_inp_mux),
4526
4527         SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
4528                            &rx_int0_1_interp_mux,
4529                            wcd934x_codec_enable_main_path,
4530                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4531                            SND_SOC_DAPM_POST_PMD),
4532         SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
4533                            &rx_int1_1_interp_mux,
4534                            wcd934x_codec_enable_main_path,
4535                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4536                            SND_SOC_DAPM_POST_PMD),
4537         SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
4538                            &rx_int2_1_interp_mux,
4539                            wcd934x_codec_enable_main_path,
4540                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4541                            SND_SOC_DAPM_POST_PMD),
4542         SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
4543                            &rx_int3_1_interp_mux,
4544                            wcd934x_codec_enable_main_path,
4545                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4546                            SND_SOC_DAPM_POST_PMD),
4547         SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
4548                            &rx_int4_1_interp_mux,
4549                            wcd934x_codec_enable_main_path,
4550                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4551                            SND_SOC_DAPM_POST_PMD),
4552         SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
4553                            &rx_int7_1_interp_mux,
4554                            wcd934x_codec_enable_main_path,
4555                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4556                            SND_SOC_DAPM_POST_PMD),
4557         SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
4558                            &rx_int8_1_interp_mux,
4559                            wcd934x_codec_enable_main_path,
4560                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4561                            SND_SOC_DAPM_POST_PMD),
4562
4563         SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
4564                          &rx_int0_2_interp_mux),
4565         SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
4566                          &rx_int1_2_interp_mux),
4567         SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
4568                          &rx_int2_2_interp_mux),
4569         SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
4570                          &rx_int3_2_interp_mux),
4571         SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
4572                          &rx_int4_2_interp_mux),
4573         SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
4574                          &rx_int7_2_interp_mux),
4575         SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
4576                          &rx_int8_2_interp_mux),
4577         SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4578                            0, 0, wcd934x_codec_ear_dac_event,
4579                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4580                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4581         SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
4582                            5, 0, wcd934x_codec_hphl_dac_event,
4583                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4584                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4585         SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
4586                            4, 0, wcd934x_codec_hphr_dac_event,
4587                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4588                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4589         SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4590                            0, 0, wcd934x_codec_lineout_dac_event,
4591                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4592         SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4593                            0, 0, wcd934x_codec_lineout_dac_event,
4594                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4595         SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
4596         SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
4597                            wcd934x_codec_enable_hphl_pa,
4598                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4599                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4600         SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
4601                            wcd934x_codec_enable_hphr_pa,
4602                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4603                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4604         SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
4605                            NULL, 0),
4606         SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
4607                            NULL, 0),
4608         SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
4609                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4610         SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
4611                          0, 0, NULL, 0),
4612         SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
4613                             0, 0, NULL, 0),
4614         SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
4615                          0, 0, NULL, 0),
4616         SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
4617                             0, 0, NULL, 0),
4618         SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
4619                             wcd934x_codec_enable_interp_clk,
4620                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4621         SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
4622                             wcd934x_codec_enable_interp_clk,
4623                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4624         SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
4625                             wcd934x_codec_enable_interp_clk,
4626                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4627         SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
4628                             wcd934x_codec_enable_interp_clk,
4629                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4630         SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
4631                             wcd934x_codec_enable_interp_clk,
4632                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4633         SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
4634                             wcd934x_codec_enable_interp_clk,
4635                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4636         SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
4637                             wcd934x_codec_enable_interp_clk,
4638                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4639         SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
4640                             0, 0, NULL, 0),
4641         SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
4642                             0, 0, NULL, 0),
4643         SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
4644                             0, 0, NULL, 0),
4645         SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
4646                             0, 0, NULL, 0),
4647         SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
4648                             0, 0, NULL, 0),
4649         SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
4650                             0, 0, NULL, 0),
4651         SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
4652                             0, 0, NULL, 0),
4653         SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
4654                             wcd934x_codec_enable_mclk,
4655                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4656
4657         /* TX */
4658         SND_SOC_DAPM_INPUT("AMIC1"),
4659         SND_SOC_DAPM_INPUT("AMIC2"),
4660         SND_SOC_DAPM_INPUT("AMIC3"),
4661         SND_SOC_DAPM_INPUT("AMIC4"),
4662         SND_SOC_DAPM_INPUT("AMIC5"),
4663         SND_SOC_DAPM_INPUT("DMIC0 Pin"),
4664         SND_SOC_DAPM_INPUT("DMIC1 Pin"),
4665         SND_SOC_DAPM_INPUT("DMIC2 Pin"),
4666         SND_SOC_DAPM_INPUT("DMIC3 Pin"),
4667         SND_SOC_DAPM_INPUT("DMIC4 Pin"),
4668         SND_SOC_DAPM_INPUT("DMIC5 Pin"),
4669
4670         SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4671                                AIF1_CAP, 0, wcd934x_codec_enable_slim,
4672                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4673         SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4674                                AIF2_CAP, 0, wcd934x_codec_enable_slim,
4675                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4676         SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4677                                AIF3_CAP, 0, wcd934x_codec_enable_slim,
4678                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4679
4680         SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4681         SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4682         SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4683         SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4684         SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4685         SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4686         SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4687         SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4688         SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
4689         SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
4690         SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
4691         SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
4692         SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
4693
4694         /* Digital Mic Inputs */
4695         SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4696                            wcd934x_codec_enable_dmic,
4697                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4698         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4699                            wcd934x_codec_enable_dmic,
4700                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4701         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4702                            wcd934x_codec_enable_dmic,
4703                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4704         SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4705                            wcd934x_codec_enable_dmic,
4706                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4707         SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4708                            wcd934x_codec_enable_dmic,
4709                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4710         SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4711                            wcd934x_codec_enable_dmic,
4712                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4713         SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
4714         SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
4715         SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
4716         SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
4717         SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
4718         SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
4719         SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
4720         SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
4721         SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
4722         SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
4723         SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
4724         SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
4725         SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
4726         SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
4727         SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
4728         SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
4729         SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
4730         SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
4731         SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
4732                            &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
4733                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4734                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4735         SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
4736                            &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
4737                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4738                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4739         SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
4740                            &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
4741                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4742                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4743         SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
4744                            &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
4745                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4746                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4747         SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
4748                            &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
4749                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4750                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4751         SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
4752                            &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
4753                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4754                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4755         SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
4756                            &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
4757                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4758                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4759         SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
4760                            &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
4761                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4762                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4763         SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
4764                            &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
4765                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4766                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4767         SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
4768                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4769         SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
4770                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4771         SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
4772                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4773         SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
4774                            wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4775         SND_SOC_DAPM_SUPPLY("MIC BIAS1", WCD934X_ANA_MICB1, 6, 0, NULL,
4776                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4777         SND_SOC_DAPM_SUPPLY("MIC BIAS2", WCD934X_ANA_MICB2, 6, 0, NULL,
4778                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4779         SND_SOC_DAPM_SUPPLY("MIC BIAS3", WCD934X_ANA_MICB3, 6, 0, NULL,
4780                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4781         SND_SOC_DAPM_SUPPLY("MIC BIAS4", WCD934X_ANA_MICB4, 6, 0, NULL,
4782                             SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4783
4784         SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
4785         SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
4786                          &cdc_if_tx0_mux),
4787         SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
4788                          &cdc_if_tx1_mux),
4789         SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
4790                          &cdc_if_tx2_mux),
4791         SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
4792                          &cdc_if_tx3_mux),
4793         SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
4794                          &cdc_if_tx4_mux),
4795         SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
4796                          &cdc_if_tx5_mux),
4797         SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
4798                          &cdc_if_tx6_mux),
4799         SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
4800                          &cdc_if_tx7_mux),
4801         SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
4802                          &cdc_if_tx8_mux),
4803         SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
4804                          &cdc_if_tx9_mux),
4805         SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
4806                          &cdc_if_tx10_mux),
4807         SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
4808                          &cdc_if_tx11_mux),
4809         SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
4810                          &cdc_if_tx11_inp1_mux),
4811         SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
4812                          &cdc_if_tx13_mux),
4813         SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
4814                          &cdc_if_tx13_inp1_mux),
4815         SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4816                            aif1_slim_cap_mixer,
4817                            ARRAY_SIZE(aif1_slim_cap_mixer)),
4818         SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4819                            aif2_slim_cap_mixer,
4820                            ARRAY_SIZE(aif2_slim_cap_mixer)),
4821         SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4822                            aif3_slim_cap_mixer,
4823                            ARRAY_SIZE(aif3_slim_cap_mixer)),
4824 };
4825
4826 static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
4827         /* RX0-RX7 */
4828         WCD934X_SLIM_RX_AIF_PATH(0),
4829         WCD934X_SLIM_RX_AIF_PATH(1),
4830         WCD934X_SLIM_RX_AIF_PATH(2),
4831         WCD934X_SLIM_RX_AIF_PATH(3),
4832         WCD934X_SLIM_RX_AIF_PATH(4),
4833         WCD934X_SLIM_RX_AIF_PATH(5),
4834         WCD934X_SLIM_RX_AIF_PATH(6),
4835         WCD934X_SLIM_RX_AIF_PATH(7),
4836
4837         /* RX0 Ear out */
4838         WCD934X_INTERPOLATOR_PATH(0),
4839         WCD934X_INTERPOLATOR_MIX2(0),
4840         {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
4841         {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
4842         {"RX INT0 DAC", NULL, "RX_BIAS"},
4843         {"EAR PA", NULL, "RX INT0 DAC"},
4844         {"EAR", NULL, "EAR PA"},
4845
4846         /* RX1 Headphone left */
4847         WCD934X_INTERPOLATOR_PATH(1),
4848         WCD934X_INTERPOLATOR_MIX2(1),
4849         {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
4850         {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
4851         {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
4852         {"RX INT1 DAC", NULL, "RX_BIAS"},
4853         {"HPHL PA", NULL, "RX INT1 DAC"},
4854         {"HPHL", NULL, "HPHL PA"},
4855
4856         /* RX2 Headphone right */
4857         WCD934X_INTERPOLATOR_PATH(2),
4858         WCD934X_INTERPOLATOR_MIX2(2),
4859         {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
4860         {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
4861         {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
4862         {"RX INT2 DAC", NULL, "RX_BIAS"},
4863         {"HPHR PA", NULL, "RX INT2 DAC"},
4864         {"HPHR", NULL, "HPHR PA"},
4865
4866         /* RX3 HIFi LineOut1 */
4867         WCD934X_INTERPOLATOR_PATH(3),
4868         WCD934X_INTERPOLATOR_MIX2(3),
4869         {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
4870         {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
4871         {"RX INT3 DAC", NULL, "RX_BIAS"},
4872         {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
4873         {"LINEOUT1", NULL, "LINEOUT1 PA"},
4874
4875         /* RX4 HIFi LineOut2 */
4876         WCD934X_INTERPOLATOR_PATH(4),
4877         WCD934X_INTERPOLATOR_MIX2(4),
4878         {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
4879         {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
4880         {"RX INT4 DAC", NULL, "RX_BIAS"},
4881         {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
4882         {"LINEOUT2", NULL, "LINEOUT2 PA"},
4883
4884         /* RX7 Speaker Left Out PA */
4885         WCD934X_INTERPOLATOR_PATH(7),
4886         WCD934X_INTERPOLATOR_MIX2(7),
4887         {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
4888         {"RX INT7 CHAIN", NULL, "RX_BIAS"},
4889         {"RX INT7 CHAIN", NULL, "SBOOST0"},
4890         {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
4891         {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
4892
4893         /* RX8 Speaker Right Out PA */
4894         WCD934X_INTERPOLATOR_PATH(8),
4895         {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
4896         {"RX INT8 CHAIN", NULL, "RX_BIAS"},
4897         {"RX INT8 CHAIN", NULL, "SBOOST1"},
4898         {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
4899         {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
4900
4901         /* Tx */
4902         {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
4903         {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
4904         {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
4905
4906         WCD934X_SLIM_TX_AIF_PATH(0),
4907         WCD934X_SLIM_TX_AIF_PATH(1),
4908         WCD934X_SLIM_TX_AIF_PATH(2),
4909         WCD934X_SLIM_TX_AIF_PATH(3),
4910         WCD934X_SLIM_TX_AIF_PATH(4),
4911         WCD934X_SLIM_TX_AIF_PATH(5),
4912         WCD934X_SLIM_TX_AIF_PATH(6),
4913         WCD934X_SLIM_TX_AIF_PATH(7),
4914         WCD934X_SLIM_TX_AIF_PATH(8),
4915
4916         WCD934X_ADC_MUX(0),
4917         WCD934X_ADC_MUX(1),
4918         WCD934X_ADC_MUX(2),
4919         WCD934X_ADC_MUX(3),
4920         WCD934X_ADC_MUX(4),
4921         WCD934X_ADC_MUX(5),
4922         WCD934X_ADC_MUX(6),
4923         WCD934X_ADC_MUX(7),
4924         WCD934X_ADC_MUX(8),
4925
4926         {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
4927         {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
4928         {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
4929         {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
4930         {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
4931         {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
4932         {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
4933         {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
4934         {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
4935
4936         {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
4937         {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
4938
4939         { "DMIC0", NULL, "DMIC0 Pin" },
4940         { "DMIC1", NULL, "DMIC1 Pin" },
4941         { "DMIC2", NULL, "DMIC2 Pin" },
4942         { "DMIC3", NULL, "DMIC3 Pin" },
4943         { "DMIC4", NULL, "DMIC4 Pin" },
4944         { "DMIC5", NULL, "DMIC5 Pin" },
4945
4946         {"ADC1", NULL, "AMIC1"},
4947         {"ADC2", NULL, "AMIC2"},
4948         {"ADC3", NULL, "AMIC3"},
4949         {"ADC4", NULL, "AMIC4_5 SEL"},
4950
4951         WCD934X_IIR_INP_MUX(0),
4952         WCD934X_IIR_INP_MUX(1),
4953
4954         {"SRC0", NULL, "IIR0"},
4955         {"SRC1", NULL, "IIR1"},
4956 };
4957
4958 static const struct snd_soc_component_driver wcd934x_component_drv = {
4959         .probe = wcd934x_comp_probe,
4960         .remove = wcd934x_comp_remove,
4961         .set_sysclk = wcd934x_comp_set_sysclk,
4962         .controls = wcd934x_snd_controls,
4963         .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
4964         .dapm_widgets = wcd934x_dapm_widgets,
4965         .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
4966         .dapm_routes = wcd934x_audio_map,
4967         .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
4968 };
4969
4970 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
4971 {
4972         struct device *dev = &wcd->sdev->dev;
4973         struct device_node *ifc_dev_np;
4974
4975         ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
4976         if (!ifc_dev_np) {
4977                 dev_err(dev, "No Interface device found\n");
4978                 return -EINVAL;
4979         }
4980
4981         wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
4982         if (!wcd->sidev) {
4983                 dev_err(dev, "Unable to get SLIM Interface device\n");
4984                 return -EINVAL;
4985         }
4986
4987         slim_get_logical_addr(wcd->sidev);
4988         wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
4989                                   &wcd934x_ifc_regmap_config);
4990         if (IS_ERR(wcd->if_regmap)) {
4991                 dev_err(dev, "Failed to allocate ifc register map\n");
4992                 return PTR_ERR(wcd->if_regmap);
4993         }
4994
4995         of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
4996                              &wcd->dmic_sample_rate);
4997
4998         return 0;
4999 }
5000
5001 static int wcd934x_codec_probe(struct platform_device *pdev)
5002 {
5003         struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent);
5004         struct wcd934x_codec *wcd;
5005         struct device *dev = &pdev->dev;
5006         int ret, irq;
5007
5008         wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL);
5009         if (!wcd)
5010                 return -ENOMEM;
5011
5012         wcd->dev = dev;
5013         wcd->regmap = data->regmap;
5014         wcd->extclk = data->extclk;
5015         wcd->sdev = to_slim_device(data->dev);
5016         mutex_init(&wcd->sysclk_mutex);
5017
5018         ret = wcd934x_codec_parse_data(wcd);
5019         if (ret) {
5020                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5021                 return ret;
5022         }
5023
5024         /* set default rate 9P6MHz */
5025         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
5026                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
5027                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
5028         memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
5029         memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
5030
5031         irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
5032         if (irq < 0) {
5033                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
5034                 return irq;
5035         }
5036
5037         ret = devm_request_threaded_irq(dev, irq, NULL,
5038                                         wcd934x_slim_irq_handler,
5039                                         IRQF_TRIGGER_RISING,
5040                                         "slim", wcd);
5041         if (ret) {
5042                 dev_err(dev, "Failed to request slimbus irq\n");
5043                 return ret;
5044         }
5045
5046         wcd934x_register_mclk_output(wcd);
5047         platform_set_drvdata(pdev, wcd);
5048
5049         return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
5050                                                wcd934x_slim_dais,
5051                                                ARRAY_SIZE(wcd934x_slim_dais));
5052 }
5053
5054 static const struct platform_device_id wcd934x_driver_id[] = {
5055         {
5056                 .name = "wcd934x-codec",
5057         },
5058         {},
5059 };
5060 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
5061
5062 static struct platform_driver wcd934x_codec_driver = {
5063         .probe  = &wcd934x_codec_probe,
5064         .id_table = wcd934x_driver_id,
5065         .driver = {
5066                 .name   = "wcd934x-codec",
5067         }
5068 };
5069
5070 MODULE_ALIAS("platform:wcd934x-codec");
5071 module_platform_driver(wcd934x_codec_driver);
5072 MODULE_DESCRIPTION("WCD934x codec driver");
5073 MODULE_LICENSE("GPL v2");