sound/soc/codecs/wcd934x.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2019, Linaro Limited
   3
   4 #include <linux/clk.h>
   5 #include <linux/clk-provider.h>
   6 #include <linux/gpio.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/kernel.h>
   9 #include <linux/mfd/wcd934x/registers.h>
  10 #include <linux/mfd/wcd934x/wcd934x.h>
  11 #include <linux/module.h>
  12 #include <linux/mutex.h>
  13 #include <linux/of_clk.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_gpio.h>
  16 #include <linux/of.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regmap.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/slab.h>
  22 #include <linux/slimbus.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/soc.h>
  25 #include <sound/soc-dapm.h>
  26 #include <sound/tlv.h>
  27 #include "wcd-clsh-v2.h"
  28
  29 #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  30                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  31                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  32 /* Fractional Rates */
  33 #define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  34                                  SNDRV_PCM_RATE_176400)
  35 #define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  36                                     SNDRV_PCM_FMTBIT_S24_LE)
  37
  38 /* slave port water mark level
  39  *   (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
  40  */
  41 #define SLAVE_PORT_WATER_MARK_6BYTES    0
  42 #define SLAVE_PORT_WATER_MARK_9BYTES    1
  43 #define SLAVE_PORT_WATER_MARK_12BYTES   2
  44 #define SLAVE_PORT_WATER_MARK_15BYTES   3
  45 #define SLAVE_PORT_WATER_MARK_SHIFT     1
  46 #define SLAVE_PORT_ENABLE               1
  47 #define SLAVE_PORT_DISABLE              0
  48 #define WCD934X_SLIM_WATER_MARK_VAL \
  49         ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
  50          (SLAVE_PORT_ENABLE))
  51
  52 #define WCD934X_SLIM_NUM_PORT_REG       3
  53 #define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
  54 #define WCD934X_SLIM_IRQ_OVERFLOW       BIT(0)
  55 #define WCD934X_SLIM_IRQ_UNDERFLOW      BIT(1)
  56 #define WCD934X_SLIM_IRQ_PORT_CLOSED    BIT(2)
  57
  58 #define WCD934X_MCLK_CLK_12P288MHZ      12288000
  59 #define WCD934X_MCLK_CLK_9P6MHZ         9600000
  60
  61 /* Only valid for 9.6 MHz mclk */
  62 #define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
  63 #define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
  64
  65 /* Only valid for 12.288 MHz mclk */
  66 #define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
  67
  68 #define WCD934X_DMIC_CLK_DIV_2          0x0
  69 #define WCD934X_DMIC_CLK_DIV_3          0x1
  70 #define WCD934X_DMIC_CLK_DIV_4          0x2
  71 #define WCD934X_DMIC_CLK_DIV_6          0x3
  72 #define WCD934X_DMIC_CLK_DIV_8          0x4
  73 #define WCD934X_DMIC_CLK_DIV_16         0x5
  74 #define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
  75
  76 #define TX_HPF_CUT_OFF_FREQ_MASK        0x60
  77 #define CF_MIN_3DB_4HZ                  0x0
  78 #define CF_MIN_3DB_75HZ                 0x1
  79 #define CF_MIN_3DB_150HZ                0x2
  80
  81 #define WCD934X_RX_START                16
  82 #define WCD934X_NUM_INTERPOLATORS       9
  83 #define WCD934X_RX_PATH_CTL_OFFSET      20
  84 #define WCD934X_MAX_VALID_ADC_MUX       13
  85 #define WCD934X_INVALID_ADC_MUX         9
  86
  87 #define WCD934X_SLIM_RX_CH(p) \
  88         {.port = p + WCD934X_RX_START, .shift = p,}
  89
  90 #define WCD934X_SLIM_TX_CH(p) \
  91         {.port = p, .shift = p,}
  92
  93 /* Feature masks to distinguish codec version */
  94 #define DSD_DISABLED_MASK   0
  95 #define SLNQ_DISABLED_MASK  1
  96
  97 #define DSD_DISABLED   BIT(DSD_DISABLED_MASK)
  98 #define SLNQ_DISABLED  BIT(SLNQ_DISABLED_MASK)
  99
 100 /* As fine version info cannot be retrieved before wcd probe.
 101  * Define three coarse versions for possible future use before wcd probe.
 102  */
 103 #define WCD_VERSION_WCD9340_1_0     0x400
 104 #define WCD_VERSION_WCD9341_1_0     0x410
 105 #define WCD_VERSION_WCD9340_1_1     0x401
 106 #define WCD_VERSION_WCD9341_1_1     0x411
 107 #define WCD934X_AMIC_PWR_LEVEL_LP       0
 108 #define WCD934X_AMIC_PWR_LEVEL_DEFAULT  1
 109 #define WCD934X_AMIC_PWR_LEVEL_HP       2
 110 #define WCD934X_AMIC_PWR_LEVEL_HYBRID   3
 111 #define WCD934X_AMIC_PWR_LVL_MASK       0x60
 112 #define WCD934X_AMIC_PWR_LVL_SHIFT      0x5
 113
 114 #define WCD934X_DEC_PWR_LVL_MASK        0x06
 115 #define WCD934X_DEC_PWR_LVL_LP          0x02
 116 #define WCD934X_DEC_PWR_LVL_HP          0x04
 117 #define WCD934X_DEC_PWR_LVL_DF          0x00
 118 #define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
 119
 120 #define WCD934X_DEF_MICBIAS_MV  1800
 121 #define WCD934X_MAX_MICBIAS_MV  2850
 122
 123 #define WCD_IIR_FILTER_SIZE     (sizeof(u32) * BAND_MAX)
 124
 125 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
 126 { \
 127         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 128         .info = wcd934x_iir_filter_info, \
 129         .get = wcd934x_get_iir_band_audio_mixer, \
 130         .put = wcd934x_put_iir_band_audio_mixer, \
 131         .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
 132                 .iir_idx = iidx, \
 133                 .band_idx = bidx, \
 134                 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
 135         } \
 136 }
 137
 138 enum {
 139         SIDO_SOURCE_INTERNAL,
 140         SIDO_SOURCE_RCO_BG,
 141 };
 142
 143 enum {
 144         INTERP_EAR = 0,
 145         INTERP_HPHL,
 146         INTERP_HPHR,
 147         INTERP_LO1,
 148         INTERP_LO2,
 149         INTERP_LO3_NA, /* LO3 not avalible in Tavil */
 150         INTERP_LO4_NA,
 151         INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
 152         INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
 153         INTERP_MAX,
 154 };
 155
 156 enum {
 157         WCD934X_RX0 = 0,
 158         WCD934X_RX1,
 159         WCD934X_RX2,
 160         WCD934X_RX3,
 161         WCD934X_RX4,
 162         WCD934X_RX5,
 163         WCD934X_RX6,
 164         WCD934X_RX7,
 165         WCD934X_RX8,
 166         WCD934X_RX9,
 167         WCD934X_RX10,
 168         WCD934X_RX11,
 169         WCD934X_RX12,
 170         WCD934X_RX_MAX,
 171 };
 172
 173 enum {
 174         WCD934X_TX0 = 0,
 175         WCD934X_TX1,
 176         WCD934X_TX2,
 177         WCD934X_TX3,
 178         WCD934X_TX4,
 179         WCD934X_TX5,
 180         WCD934X_TX6,
 181         WCD934X_TX7,
 182         WCD934X_TX8,
 183         WCD934X_TX9,
 184         WCD934X_TX10,
 185         WCD934X_TX11,
 186         WCD934X_TX12,
 187         WCD934X_TX13,
 188         WCD934X_TX14,
 189         WCD934X_TX15,
 190         WCD934X_TX_MAX,
 191 };
 192
 193 struct wcd934x_slim_ch {
 194         u32 ch_num;
 195         u16 port;
 196         u16 shift;
 197         struct list_head list;
 198 };
 199
 200 static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
 201         WCD934X_SLIM_TX_CH(0),
 202         WCD934X_SLIM_TX_CH(1),
 203         WCD934X_SLIM_TX_CH(2),
 204         WCD934X_SLIM_TX_CH(3),
 205         WCD934X_SLIM_TX_CH(4),
 206         WCD934X_SLIM_TX_CH(5),
 207         WCD934X_SLIM_TX_CH(6),
 208         WCD934X_SLIM_TX_CH(7),
 209         WCD934X_SLIM_TX_CH(8),
 210         WCD934X_SLIM_TX_CH(9),
 211         WCD934X_SLIM_TX_CH(10),
 212         WCD934X_SLIM_TX_CH(11),
 213         WCD934X_SLIM_TX_CH(12),
 214         WCD934X_SLIM_TX_CH(13),
 215         WCD934X_SLIM_TX_CH(14),
 216         WCD934X_SLIM_TX_CH(15),
 217 };
 218
 219 static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
 220         WCD934X_SLIM_RX_CH(0),   /* 16 */
 221         WCD934X_SLIM_RX_CH(1),   /* 17 */
 222         WCD934X_SLIM_RX_CH(2),
 223         WCD934X_SLIM_RX_CH(3),
 224         WCD934X_SLIM_RX_CH(4),
 225         WCD934X_SLIM_RX_CH(5),
 226         WCD934X_SLIM_RX_CH(6),
 227         WCD934X_SLIM_RX_CH(7),
 228         WCD934X_SLIM_RX_CH(8),
 229         WCD934X_SLIM_RX_CH(9),
 230         WCD934X_SLIM_RX_CH(10),
 231         WCD934X_SLIM_RX_CH(11),
 232         WCD934X_SLIM_RX_CH(12),
 233 };
 234
 235 /* Codec supports 2 IIR filters */
 236 enum {
 237         IIR0 = 0,
 238         IIR1,
 239         IIR_MAX,
 240 };
 241
 242 /* Each IIR has 5 Filter Stages */
 243 enum {
 244         BAND1 = 0,
 245         BAND2,
 246         BAND3,
 247         BAND4,
 248         BAND5,
 249         BAND_MAX,
 250 };
 251
 252 enum {
 253         COMPANDER_1, /* HPH_L */
 254         COMPANDER_2, /* HPH_R */
 255         COMPANDER_3, /* LO1_DIFF */
 256         COMPANDER_4, /* LO2_DIFF */
 257         COMPANDER_5, /* LO3_SE - not used in Tavil */
 258         COMPANDER_6, /* LO4_SE - not used in Tavil */
 259         COMPANDER_7, /* SWR SPK CH1 */
 260         COMPANDER_8, /* SWR SPK CH2 */
 261         COMPANDER_MAX,
 262 };
 263
 264 enum {
 265         AIF1_PB = 0,
 266         AIF1_CAP,
 267         AIF2_PB,
 268         AIF2_CAP,
 269         AIF3_PB,
 270         AIF3_CAP,
 271         AIF4_PB,
 272         AIF4_VIFEED,
 273         AIF4_MAD_TX,
 274         NUM_CODEC_DAIS,
 275 };
 276
 277 enum {
 278         INTn_1_INP_SEL_ZERO = 0,
 279         INTn_1_INP_SEL_DEC0,
 280         INTn_1_INP_SEL_DEC1,
 281         INTn_1_INP_SEL_IIR0,
 282         INTn_1_INP_SEL_IIR1,
 283         INTn_1_INP_SEL_RX0,
 284         INTn_1_INP_SEL_RX1,
 285         INTn_1_INP_SEL_RX2,
 286         INTn_1_INP_SEL_RX3,
 287         INTn_1_INP_SEL_RX4,
 288         INTn_1_INP_SEL_RX5,
 289         INTn_1_INP_SEL_RX6,
 290         INTn_1_INP_SEL_RX7,
 291 };
 292
 293 enum {
 294         INTn_2_INP_SEL_ZERO = 0,
 295         INTn_2_INP_SEL_RX0,
 296         INTn_2_INP_SEL_RX1,
 297         INTn_2_INP_SEL_RX2,
 298         INTn_2_INP_SEL_RX3,
 299         INTn_2_INP_SEL_RX4,
 300         INTn_2_INP_SEL_RX5,
 301         INTn_2_INP_SEL_RX6,
 302         INTn_2_INP_SEL_RX7,
 303         INTn_2_INP_SEL_PROXIMITY,
 304 };
 305
 306 enum {
 307         INTERP_MAIN_PATH,
 308         INTERP_MIX_PATH,
 309 };
 310
 311 struct interp_sample_rate {
 312         int sample_rate;
 313         int rate_val;
 314 };
 315
 316 static struct interp_sample_rate sr_val_tbl[] = {
 317         {8000, 0x0},
 318         {16000, 0x1},
 319         {32000, 0x3},
 320         {48000, 0x4},
 321         {96000, 0x5},
 322         {192000, 0x6},
 323         {384000, 0x7},
 324         {44100, 0x9},
 325         {88200, 0xA},
 326         {176400, 0xB},
 327         {352800, 0xC},
 328 };
 329
 330 struct wcd_slim_codec_dai_data {
 331         struct list_head slim_ch_list;
 332         struct slim_stream_config sconfig;
 333         struct slim_stream_runtime *sruntime;
 334 };
 335
 336 static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
 337         {
 338                 .name = "WCD9335-IFC-DEV",
 339                 .range_min =  0x0,
 340                 .range_max = 0xffff,
 341                 .selector_reg = 0x800,
 342                 .selector_mask = 0xfff,
 343                 .selector_shift = 0,
 344                 .window_start = 0x800,
 345                 .window_len = 0x400,
 346         },
 347 };
 348
 349 static struct regmap_config wcd934x_ifc_regmap_config = {
 350         .reg_bits = 16,
 351         .val_bits = 8,
 352         .max_register = 0xffff,
 353         .ranges = wcd934x_ifc_ranges,
 354         .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
 355 };
 356
 357 struct wcd934x_codec {
 358         struct device *dev;
 359         struct clk_hw hw;
 360         struct clk *extclk;
 361         struct regmap *regmap;
 362         struct regmap *if_regmap;
 363         struct slim_device *sdev;
 364         struct slim_device *sidev;
 365         struct wcd_clsh_ctrl *clsh_ctrl;
 366         struct snd_soc_component *component;
 367         struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
 368         struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
 369         struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
 370         int rate;
 371         u32 version;
 372         u32 hph_mode;
 373         int num_rx_port;
 374         int num_tx_port;
 375         u32 tx_port_value[WCD934X_TX_MAX];
 376         u32 rx_port_value[WCD934X_RX_MAX];
 377         int sido_input_src;
 378         int dmic_0_1_clk_cnt;
 379         int dmic_2_3_clk_cnt;
 380         int dmic_4_5_clk_cnt;
 381         int dmic_sample_rate;
 382         int comp_enabled[COMPANDER_MAX];
 383         int sysclk_users;
 384         struct mutex sysclk_mutex;
 385 };
 386
 387 #define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
 388
 389 struct wcd_iir_filter_ctl {
 390         unsigned int iir_idx;
 391         unsigned int band_idx;
 392         struct soc_bytes_ext bytes_ext;
 393 };
 394
 395 static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
 396 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 397 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 398 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
 399
 400 /* Cutoff frequency for high pass filter */
 401 static const char * const cf_text[] = {
 402         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
 403 };
 404
 405 static const char * const rx_cf_text[] = {
 406         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
 407         "CF_NEG_3DB_0P48HZ"
 408 };
 409
 410 static const char * const rx_hph_mode_mux_text[] = {
 411         "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
 412         "Class-H Hi-Fi Low Power"
 413 };
 414
 415 static const struct soc_enum cf_dec0_enum =
 416         SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
 417
 418 static const struct soc_enum cf_dec1_enum =
 419         SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
 420
 421 static const struct soc_enum cf_dec2_enum =
 422         SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
 423
 424 static const struct soc_enum cf_dec3_enum =
 425         SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
 426
 427 static const struct soc_enum cf_dec4_enum =
 428         SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
 429
 430 static const struct soc_enum cf_dec5_enum =
 431         SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
 432
 433 static const struct soc_enum cf_dec6_enum =
 434         SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
 435
 436 static const struct soc_enum cf_dec7_enum =
 437         SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
 438
 439 static const struct soc_enum cf_dec8_enum =
 440         SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
 441
 442 static const struct soc_enum cf_int0_1_enum =
 443         SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
 444
 445 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
 446                      rx_cf_text);
 447
 448 static const struct soc_enum cf_int1_1_enum =
 449         SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
 450
 451 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
 452                      rx_cf_text);
 453
 454 static const struct soc_enum cf_int2_1_enum =
 455         SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
 456
 457 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
 458                      rx_cf_text);
 459
 460 static const struct soc_enum cf_int3_1_enum =
 461         SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
 462
 463 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
 464                             rx_cf_text);
 465
 466 static const struct soc_enum cf_int4_1_enum =
 467         SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
 468
 469 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
 470                             rx_cf_text);
 471
 472 static const struct soc_enum cf_int7_1_enum =
 473         SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
 474
 475 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
 476                             rx_cf_text);
 477
 478 static const struct soc_enum cf_int8_1_enum =
 479         SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
 480
 481 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
 482                             rx_cf_text);
 483
 484 static const struct soc_enum rx_hph_mode_mux_enum =
 485         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
 486                             rx_hph_mode_mux_text);
 487
 488 static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd,
 489                                       int sido_src)
 490 {
 491         if (sido_src == wcd->sido_input_src)
 492                 return 0;
 493
 494         if (sido_src == SIDO_SOURCE_INTERNAL) {
 495                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
 496                                    WCD934X_ANA_BUCK_HI_ACCU_EN_MASK, 0);
 497                 usleep_range(100, 110);
 498                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
 499                                    WCD934X_ANA_BUCK_HI_ACCU_PRE_ENX_MASK, 0x0);
 500                 usleep_range(100, 110);
 501                 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
 502                                    WCD934X_ANA_RCO_BG_EN_MASK, 0);
 503                 usleep_range(100, 110);
 504         } else if (sido_src == SIDO_SOURCE_RCO_BG) {
 505                 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
 506                                    WCD934X_ANA_RCO_BG_EN_MASK,
 507                                    WCD934X_ANA_RCO_BG_ENABLE);
 508                 usleep_range(100, 110);
 509                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
 510                                    WCD934X_ANA_BUCK_PRE_EN1_MASK,
 511                                    WCD934X_ANA_BUCK_PRE_EN1_ENABLE);
 512                 usleep_range(100, 110);
 513                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
 514                                    WCD934X_ANA_BUCK_PRE_EN2_MASK,
 515                                    WCD934X_ANA_BUCK_PRE_EN2_ENABLE);
 516                 usleep_range(100, 110);
 517                 regmap_update_bits(wcd->regmap, WCD934X_ANA_BUCK_CTL,
 518                                    WCD934X_ANA_BUCK_HI_ACCU_EN_MASK,
 519                                    WCD934X_ANA_BUCK_HI_ACCU_ENABLE);
 520                 usleep_range(100, 110);
 521         }
 522         wcd->sido_input_src = sido_src;
 523
 524         return 0;
 525 }
 526
 527 static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
 528 {
 529         mutex_lock(&wcd->sysclk_mutex);
 530
 531         if (++wcd->sysclk_users != 1) {
 532                 mutex_unlock(&wcd->sysclk_mutex);
 533                 return 0;
 534         }
 535         mutex_unlock(&wcd->sysclk_mutex);
 536
 537         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 538                            WCD934X_ANA_BIAS_EN_MASK,
 539                            WCD934X_ANA_BIAS_EN);
 540         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 541                            WCD934X_ANA_PRECHRG_EN_MASK,
 542                            WCD934X_ANA_PRECHRG_EN);
 543         /*
 544          * 1ms delay is required after pre-charge is enabled
 545          * as per HW requirement
 546          */
 547         usleep_range(1000, 1100);
 548         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 549                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
 550         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 551                            WCD934X_ANA_PRECHRG_MODE_MASK, 0);
 552
 553         /*
 554          * In data clock contrl register is changed
 555          * to CLK_SYS_MCLK_PRG
 556          */
 557
 558         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
 559                            WCD934X_EXT_CLK_BUF_EN_MASK,
 560                            WCD934X_EXT_CLK_BUF_EN);
 561         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
 562                            WCD934X_EXT_CLK_DIV_RATIO_MASK,
 563                            WCD934X_EXT_CLK_DIV_BY_2);
 564         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
 565                            WCD934X_MCLK_SRC_MASK,
 566                            WCD934X_MCLK_SRC_EXT_CLK);
 567         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
 568                            WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
 569         regmap_update_bits(wcd->regmap,
 570                            WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
 571                            WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
 572                            WCD934X_CDC_FS_MCLK_CNT_ENABLE);
 573         regmap_update_bits(wcd->regmap,
 574                            WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
 575                            WCD934X_MCLK_EN_MASK,
 576                            WCD934X_MCLK_EN);
 577         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
 578                            WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
 579         /*
 580          * 10us sleep is required after clock is enabled
 581          * as per HW requirement
 582          */
 583         usleep_range(10, 15);
 584
 585         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
 586
 587         return 0;
 588 }
 589
 590 static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
 591 {
 592         mutex_lock(&wcd->sysclk_mutex);
 593         if (--wcd->sysclk_users != 0) {
 594                 mutex_unlock(&wcd->sysclk_mutex);
 595                 return 0;
 596         }
 597         mutex_unlock(&wcd->sysclk_mutex);
 598
 599         regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
 600                            WCD934X_EXT_CLK_BUF_EN_MASK |
 601                            WCD934X_MCLK_EN_MASK, 0x0);
 602         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_INTERNAL);
 603
 604         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 605                            WCD934X_ANA_BIAS_EN_MASK, 0);
 606         regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
 607                            WCD934X_ANA_PRECHRG_EN_MASK, 0);
 608
 609         return 0;
 610 }
 611
 612 static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
 613 {
 614         int ret = 0;
 615
 616         if (enable) {
 617                 ret = clk_prepare_enable(wcd->extclk);
 618
 619                 if (ret) {
 620                         dev_err(wcd->dev, "%s: ext clk enable failed\n",
 621                                 __func__);
 622                         return ret;
 623                 }
 624                 ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
 625         } else {
 626                 int val;
 627
 628                 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
 629                             &val);
 630
 631                 /* Don't disable clock if soundwire using it.*/
 632                 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
 633                         return 0;
 634
 635                 wcd934x_disable_ana_bias_and_syclk(wcd);
 636                 clk_disable_unprepare(wcd->extclk);
 637         }
 638
 639         return ret;
 640 }
 641
 642 static int wcd934x_get_version(struct wcd934x_codec *wcd)
 643 {
 644         int val1, val2, ver, ret;
 645         struct regmap *regmap;
 646         u16 id_minor;
 647         u32 version_mask = 0;
 648
 649         regmap = wcd->regmap;
 650         ver = 0;
 651
 652         ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
 653                                (u8 *)&id_minor, sizeof(u16));
 654
 655         if (ret)
 656                 return ret;
 657
 658         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
 659         regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
 660
 661         version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
 662         version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
 663
 664         switch (version_mask) {
 665         case DSD_DISABLED | SLNQ_DISABLED:
 666                 if (id_minor == 0)
 667                         ver = WCD_VERSION_WCD9340_1_0;
 668                 else if (id_minor == 0x01)
 669                         ver = WCD_VERSION_WCD9340_1_1;
 670                 break;
 671         case SLNQ_DISABLED:
 672                 if (id_minor == 0)
 673                         ver = WCD_VERSION_WCD9341_1_0;
 674                 else if (id_minor == 0x01)
 675                         ver = WCD_VERSION_WCD9341_1_1;
 676                 break;
 677         }
 678
 679         wcd->version = ver;
 680         dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
 681
 682         return 0;
 683 }
 684
 685 static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
 686 {
 687         int rc, val;
 688
 689         __wcd934x_cdc_mclk_enable(wcd, true);
 690
 691         regmap_update_bits(wcd->regmap,
 692                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
 693                            WCD934X_EFUSE_SENSE_STATE_MASK,
 694                            WCD934X_EFUSE_SENSE_STATE_DEF);
 695         regmap_update_bits(wcd->regmap,
 696                            WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
 697                            WCD934X_EFUSE_SENSE_EN_MASK,
 698                            WCD934X_EFUSE_SENSE_ENABLE);
 699         /*
 700          * 5ms sleep required after enabling efuse control
 701          * before checking the status.
 702          */
 703         usleep_range(5000, 5500);
 704         wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
 705
 706         rc = regmap_read(wcd->regmap,
 707                          WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
 708         if (rc || (!(val & 0x01)))
 709                 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
 710                      __func__, val, rc);
 711
 712         __wcd934x_cdc_mclk_enable(wcd, false);
 713 }
 714
 715 static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
 716 {
 717         if (enable) {
 718                 __wcd934x_cdc_mclk_enable(wcd, true);
 719                 regmap_update_bits(wcd->regmap,
 720                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
 721                                    WCD934X_CDC_SWR_CLK_EN_MASK,
 722                                    WCD934X_CDC_SWR_CLK_ENABLE);
 723         } else {
 724                 regmap_update_bits(wcd->regmap,
 725                                    WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
 726                                    WCD934X_CDC_SWR_CLK_EN_MASK, 0);
 727                 __wcd934x_cdc_mclk_enable(wcd, false);
 728         }
 729
 730         return 0;
 731 }
 732
 733 static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
 734                                               u8 rate_val, u32 rate)
 735 {
 736         struct snd_soc_component *comp = dai->component;
 737         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
 738         struct wcd934x_slim_ch *ch;
 739         u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
 740         int inp, j;
 741
 742         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
 743                 inp = ch->shift + INTn_1_INP_SEL_RX0;
 744                 /*
 745                  * Loop through all interpolator MUX inputs and find out
 746                  * to which interpolator input, the slim rx port
 747                  * is connected
 748                  */
 749                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
 750                         /* Interpolators 5 and 6 are not aviliable in Tavil */
 751                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
 752                                 continue;
 753
 754                         cfg0 = snd_soc_component_read32(comp,
 755                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
 756                         cfg1 = snd_soc_component_read32(comp,
 757                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
 758
 759                         inp0_sel = cfg0 &
 760                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
 761                         inp1_sel = (cfg0 >> 4) &
 762                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
 763                         inp2_sel = (cfg1 >> 4) &
 764                                  WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
 765
 766                         if ((inp0_sel == inp) ||  (inp1_sel == inp) ||
 767                             (inp2_sel == inp)) {
 768                                 /* rate is in Hz */
 769                                 /*
 770                                  * Ear and speaker primary path does not support
 771                                  * native sample rates
 772                                  */
 773                                 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
 774                                      j == INTERP_SPKR2) && rate == 44100)
 775                                         dev_err(wcd->dev,
 776                                                 "Cannot set 44.1KHz on INT%d\n",
 777                                                 j);
 778                                 else
 779                                         snd_soc_component_update_bits(comp,
 780                                               WCD934X_CDC_RX_PATH_CTL(j),
 781                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
 782                                               rate_val);
 783                         }
 784                 }
 785         }
 786
 787         return 0;
 788 }
 789
 790 static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
 791                                              int rate_val, u32 rate)
 792 {
 793         struct snd_soc_component *component = dai->component;
 794         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
 795         struct wcd934x_slim_ch *ch;
 796         int val, j;
 797
 798         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
 799                 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
 800                         /* Interpolators 5 and 6 are not aviliable in Tavil */
 801                         if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
 802                                 continue;
 803                         val = snd_soc_component_read32(component,
 804                                         WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
 805                                         WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
 806
 807                         if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
 808                                 /*
 809                                  * Ear mix path supports only 48, 96, 192,
 810                                  * 384KHz only
 811                                  */
 812                                 if ((j == INTERP_EAR) &&
 813                                     (rate_val < 0x4 ||
 814                                      rate_val > 0x7)) {
 815                                         dev_err(component->dev,
 816                                                 "Invalid rate for AIF_PB DAI(%d)\n",
 817                                                 dai->id);
 818                                         return -EINVAL;
 819                                 }
 820
 821                                 snd_soc_component_update_bits(component,
 822                                               WCD934X_CDC_RX_PATH_MIX_CTL(j),
 823                                               WCD934X_CDC_MIX_PCM_RATE_MASK,
 824                                               rate_val);
 825                         }
 826                 }
 827         }
 828
 829         return 0;
 830 }
 831
 832 static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
 833                                          u32 sample_rate)
 834 {
 835         int rate_val = 0;
 836         int i, ret;
 837
 838         for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
 839                 if (sample_rate == sr_val_tbl[i].sample_rate) {
 840                         rate_val = sr_val_tbl[i].rate_val;
 841                         break;
 842                 }
 843         }
 844         if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
 845                 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
 846                 return -EINVAL;
 847         }
 848
 849         ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
 850                                                  sample_rate);
 851         if (ret)
 852                 return ret;
 853         ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
 854                                                 sample_rate);
 855         if (ret)
 856                 return ret;
 857
 858         return ret;
 859 }
 860
 861 static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
 862                                       u8 rate_val, u32 rate)
 863 {
 864         struct snd_soc_component *comp = dai->component;
 865         struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
 866         u8 shift = 0, shift_val = 0, tx_mux_sel;
 867         struct wcd934x_slim_ch *ch;
 868         int tx_port, tx_port_reg;
 869         int decimator = -1;
 870
 871         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
 872                 tx_port = ch->port;
 873                 /* Find the SB TX MUX input - which decimator is connected */
 874                 switch (tx_port) {
 875                 case 0 ...  3:
 876                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
 877                         shift = (tx_port << 1);
 878                         shift_val = 0x03;
 879                         break;
 880                 case 4 ... 7:
 881                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
 882                         shift = ((tx_port - 4) << 1);
 883                         shift_val = 0x03;
 884                         break;
 885                 case 8 ... 10:
 886                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
 887                         shift = ((tx_port - 8) << 1);
 888                         shift_val = 0x03;
 889                         break;
 890                 case 11:
 891                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
 892                         shift = 0;
 893                         shift_val = 0x0F;
 894                         break;
 895                 case 13:
 896                         tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
 897                         shift = 4;
 898                         shift_val = 0x03;
 899                         break;
 900                 default:
 901                         dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
 902                                 tx_port, dai->id);
 903                         return -EINVAL;
 904                 }
 905
 906                 tx_mux_sel = snd_soc_component_read32(comp, tx_port_reg) &
 907                                                       (shift_val << shift);
 908
 909                 tx_mux_sel = tx_mux_sel >> shift;
 910                 switch (tx_port) {
 911                 case 0 ... 8:
 912                         if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
 913                                 decimator = tx_port;
 914                         break;
 915                 case 9 ... 10:
 916                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
 917                                 decimator = ((tx_port == 9) ? 7 : 6);
 918                         break;
 919                 case 11:
 920                         if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
 921                                 decimator = tx_mux_sel - 1;
 922                         break;
 923                 case 13:
 924                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
 925                                 decimator = 5;
 926                         break;
 927                 default:
 928                         dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
 929                                 tx_port);
 930                         return -EINVAL;
 931                 }
 932
 933                 snd_soc_component_update_bits(comp,
 934                                       WCD934X_CDC_TX_PATH_CTL(decimator),
 935                                       WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
 936                                       rate_val);
 937         }
 938
 939         return 0;
 940 }
 941
 942 static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
 943                                       struct wcd_slim_codec_dai_data *dai_data,
 944                                       int direction)
 945 {
 946         struct list_head *slim_ch_list = &dai_data->slim_ch_list;
 947         struct slim_stream_config *cfg = &dai_data->sconfig;
 948         struct wcd934x_slim_ch *ch;
 949         u16 payload = 0;
 950         int ret, i;
 951
 952         cfg->ch_count = 0;
 953         cfg->direction = direction;
 954         cfg->port_mask = 0;
 955
 956         /* Configure slave interface device */
 957         list_for_each_entry(ch, slim_ch_list, list) {
 958                 cfg->ch_count++;
 959                 payload |= 1 << ch->shift;
 960                 cfg->port_mask |= BIT(ch->port);
 961         }
 962
 963         cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
 964         if (!cfg->chs)
 965                 return -ENOMEM;
 966
 967         i = 0;
 968         list_for_each_entry(ch, slim_ch_list, list) {
 969                 cfg->chs[i++] = ch->ch_num;
 970                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
 971                         /* write to interface device */
 972                         ret = regmap_write(wcd->if_regmap,
 973                            WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
 974                            payload);
 975
 976                         if (ret < 0)
 977                                 goto err;
 978
 979                         /* configure the slave port for water mark and enable*/
 980                         ret = regmap_write(wcd->if_regmap,
 981                                         WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
 982                                         WCD934X_SLIM_WATER_MARK_VAL);
 983                         if (ret < 0)
 984                                 goto err;
 985                 } else {
 986                         ret = regmap_write(wcd->if_regmap,
 987                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
 988                                 payload & 0x00FF);
 989                         if (ret < 0)
 990                                 goto err;
 991
 992                         /* ports 8,9 */
 993                         ret = regmap_write(wcd->if_regmap,
 994                                 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
 995                                 (payload & 0xFF00) >> 8);
 996                         if (ret < 0)
 997                                 goto err;
 998
 999                         /* configure the slave port for water mark and enable*/
1000                         ret = regmap_write(wcd->if_regmap,
1001                                         WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1002                                         WCD934X_SLIM_WATER_MARK_VAL);
1003
1004                         if (ret < 0)
1005                                 goto err;
1006                 }
1007         }
1008
1009         dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1010
1011         return 0;
1012
1013 err:
1014         dev_err(wcd->dev, "Error Setting slim hw params\n");
1015         kfree(cfg->chs);
1016         cfg->chs = NULL;
1017
1018         return ret;
1019 }
1020
1021 static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1022                              struct snd_pcm_hw_params *params,
1023                              struct snd_soc_dai *dai)
1024 {
1025         struct wcd934x_codec *wcd;
1026         int ret, tx_fs_rate = 0;
1027
1028         wcd = snd_soc_component_get_drvdata(dai->component);
1029
1030         switch (substream->stream) {
1031         case SNDRV_PCM_STREAM_PLAYBACK:
1032                 ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1033                 if (ret) {
1034                         dev_err(wcd->dev, "cannot set sample rate: %u\n",
1035                                 params_rate(params));
1036                         return ret;
1037                 }
1038                 switch (params_width(params)) {
1039                 case 16 ... 24:
1040                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1041                         break;
1042                 default:
1043                         dev_err(wcd->dev, "Invalid format 0x%x\n",
1044                                 params_width(params));
1045                         return -EINVAL;
1046                 }
1047                 break;
1048
1049         case SNDRV_PCM_STREAM_CAPTURE:
1050                 switch (params_rate(params)) {
1051                 case 8000:
1052                         tx_fs_rate = 0;
1053                         break;
1054                 case 16000:
1055                         tx_fs_rate = 1;
1056                         break;
1057                 case 32000:
1058                         tx_fs_rate = 3;
1059                         break;
1060                 case 48000:
1061                         tx_fs_rate = 4;
1062                         break;
1063                 case 96000:
1064                         tx_fs_rate = 5;
1065                         break;
1066                 case 192000:
1067                         tx_fs_rate = 6;
1068                         break;
1069                 case 384000:
1070                         tx_fs_rate = 7;
1071                         break;
1072                 default:
1073                         dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1074                                 params_rate(params));
1075                         return -EINVAL;
1076
1077                 };
1078
1079                 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1080                                                  params_rate(params));
1081                 if (ret < 0) {
1082                         dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1083                         return ret;
1084                 }
1085                 switch (params_width(params)) {
1086                 case 16 ... 32:
1087                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1088                         break;
1089                 default:
1090                         dev_err(wcd->dev, "Invalid format 0x%x\n",
1091                                 params_width(params));
1092                         return -EINVAL;
1093                 };
1094                 break;
1095         default:
1096                 dev_err(wcd->dev, "Invalid stream type %d\n",
1097                         substream->stream);
1098                 return -EINVAL;
1099         };
1100
1101         wcd->dai[dai->id].sconfig.rate = params_rate(params);
1102         wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1103
1104         return 0;
1105 }
1106
1107 static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1108                            struct snd_soc_dai *dai)
1109 {
1110         struct wcd_slim_codec_dai_data *dai_data;
1111         struct wcd934x_codec *wcd;
1112
1113         wcd = snd_soc_component_get_drvdata(dai->component);
1114
1115         dai_data = &wcd->dai[dai->id];
1116
1117         kfree(dai_data->sconfig.chs);
1118
1119         return 0;
1120 }
1121
1122 static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1123                            struct snd_soc_dai *dai)
1124 {
1125         struct wcd_slim_codec_dai_data *dai_data;
1126         struct wcd934x_codec *wcd;
1127         struct slim_stream_config *cfg;
1128
1129         wcd = snd_soc_component_get_drvdata(dai->component);
1130
1131         dai_data = &wcd->dai[dai->id];
1132
1133         switch (cmd) {
1134         case SNDRV_PCM_TRIGGER_START:
1135         case SNDRV_PCM_TRIGGER_RESUME:
1136         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1137                 cfg = &dai_data->sconfig;
1138                 slim_stream_prepare(dai_data->sruntime, cfg);
1139                 slim_stream_enable(dai_data->sruntime);
1140                 break;
1141         case SNDRV_PCM_TRIGGER_STOP:
1142         case SNDRV_PCM_TRIGGER_SUSPEND:
1143         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1144                 slim_stream_unprepare(dai_data->sruntime);
1145                 slim_stream_disable(dai_data->sruntime);
1146                 break;
1147         default:
1148                 break;
1149         }
1150
1151         return 0;
1152 }
1153
1154 static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1155                                    unsigned int tx_num, unsigned int *tx_slot,
1156                                    unsigned int rx_num, unsigned int *rx_slot)
1157 {
1158         struct wcd934x_codec *wcd;
1159         int i;
1160
1161         wcd = snd_soc_component_get_drvdata(dai->component);
1162
1163         if (!tx_slot || !rx_slot) {
1164                 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1165                         tx_slot, rx_slot);
1166                 return -EINVAL;
1167         }
1168
1169         if (wcd->rx_chs) {
1170                 wcd->num_rx_port = rx_num;
1171                 for (i = 0; i < rx_num; i++) {
1172                         wcd->rx_chs[i].ch_num = rx_slot[i];
1173                         INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1174                 }
1175         }
1176
1177         if (wcd->tx_chs) {
1178                 wcd->num_tx_port = tx_num;
1179                 for (i = 0; i < tx_num; i++) {
1180                         wcd->tx_chs[i].ch_num = tx_slot[i];
1181                         INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1182                 }
1183         }
1184
1185         return 0;
1186 }
1187
1188 static int wcd934x_get_channel_map(struct snd_soc_dai *dai,
1189                                    unsigned int *tx_num, unsigned int *tx_slot,
1190                                    unsigned int *rx_num, unsigned int *rx_slot)
1191 {
1192         struct wcd934x_slim_ch *ch;
1193         struct wcd934x_codec *wcd;
1194         int i = 0;
1195
1196         wcd = snd_soc_component_get_drvdata(dai->component);
1197
1198         switch (dai->id) {
1199         case AIF1_PB:
1200         case AIF2_PB:
1201         case AIF3_PB:
1202         case AIF4_PB:
1203                 if (!rx_slot || !rx_num) {
1204                         dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1205                                 rx_slot, rx_num);
1206                         return -EINVAL;
1207                 }
1208
1209                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1210                         rx_slot[i++] = ch->ch_num;
1211
1212                 *rx_num = i;
1213                 break;
1214         case AIF1_CAP:
1215         case AIF2_CAP:
1216         case AIF3_CAP:
1217                 if (!tx_slot || !tx_num) {
1218                         dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1219                                 tx_slot, tx_num);
1220                         return -EINVAL;
1221                 }
1222
1223                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1224                         tx_slot[i++] = ch->ch_num;
1225
1226                 *tx_num = i;
1227                 break;
1228         default:
1229                 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
1230                 break;
1231         }
1232
1233         return 0;
1234 }
1235
1236 static struct snd_soc_dai_ops wcd934x_dai_ops = {
1237         .hw_params = wcd934x_hw_params,
1238         .hw_free = wcd934x_hw_free,
1239         .trigger = wcd934x_trigger,
1240         .set_channel_map = wcd934x_set_channel_map,
1241         .get_channel_map = wcd934x_get_channel_map,
1242 };
1243
1244 static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
1245         [0] = {
1246                 .name = "wcd934x_rx1",
1247                 .id = AIF1_PB,
1248                 .playback = {
1249                         .stream_name = "AIF1 Playback",
1250                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1251                         .formats = WCD934X_FORMATS_S16_S24_LE,
1252                         .rate_max = 192000,
1253                         .rate_min = 8000,
1254                         .channels_min = 1,
1255                         .channels_max = 2,
1256                 },
1257                 .ops = &wcd934x_dai_ops,
1258         },
1259         [1] = {
1260                 .name = "wcd934x_tx1",
1261                 .id = AIF1_CAP,
1262                 .capture = {
1263                         .stream_name = "AIF1 Capture",
1264                         .rates = WCD934X_RATES_MASK,
1265                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1266                         .rate_min = 8000,
1267                         .rate_max = 192000,
1268                         .channels_min = 1,
1269                         .channels_max = 4,
1270                 },
1271                 .ops = &wcd934x_dai_ops,
1272         },
1273         [2] = {
1274                 .name = "wcd934x_rx2",
1275                 .id = AIF2_PB,
1276                 .playback = {
1277                         .stream_name = "AIF2 Playback",
1278                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1279                         .formats = WCD934X_FORMATS_S16_S24_LE,
1280                         .rate_min = 8000,
1281                         .rate_max = 192000,
1282                         .channels_min = 1,
1283                         .channels_max = 2,
1284                 },
1285                 .ops = &wcd934x_dai_ops,
1286         },
1287         [3] = {
1288                 .name = "wcd934x_tx2",
1289                 .id = AIF2_CAP,
1290                 .capture = {
1291                         .stream_name = "AIF2 Capture",
1292                         .rates = WCD934X_RATES_MASK,
1293                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1294                         .rate_min = 8000,
1295                         .rate_max = 192000,
1296                         .channels_min = 1,
1297                         .channels_max = 4,
1298                 },
1299                 .ops = &wcd934x_dai_ops,
1300         },
1301         [4] = {
1302                 .name = "wcd934x_rx3",
1303                 .id = AIF3_PB,
1304                 .playback = {
1305                         .stream_name = "AIF3 Playback",
1306                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1307                         .formats = WCD934X_FORMATS_S16_S24_LE,
1308                         .rate_min = 8000,
1309                         .rate_max = 192000,
1310                         .channels_min = 1,
1311                         .channels_max = 2,
1312                 },
1313                 .ops = &wcd934x_dai_ops,
1314         },
1315         [5] = {
1316                 .name = "wcd934x_tx3",
1317                 .id = AIF3_CAP,
1318                 .capture = {
1319                         .stream_name = "AIF3 Capture",
1320                         .rates = WCD934X_RATES_MASK,
1321                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
1322                         .rate_min = 8000,
1323                         .rate_max = 192000,
1324                         .channels_min = 1,
1325                         .channels_max = 4,
1326                 },
1327                 .ops = &wcd934x_dai_ops,
1328         },
1329         [6] = {
1330                 .name = "wcd934x_rx4",
1331                 .id = AIF4_PB,
1332                 .playback = {
1333                         .stream_name = "AIF4 Playback",
1334                         .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
1335                         .formats = WCD934X_FORMATS_S16_S24_LE,
1336                         .rate_min = 8000,
1337                         .rate_max = 192000,
1338                         .channels_min = 1,
1339                         .channels_max = 2,
1340                 },
1341                 .ops = &wcd934x_dai_ops,
1342         },
1343 };
1344
1345 static int swclk_gate_enable(struct clk_hw *hw)
1346 {
1347         return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
1348 }
1349
1350 static void swclk_gate_disable(struct clk_hw *hw)
1351 {
1352         wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
1353 }
1354
1355 static int swclk_gate_is_enabled(struct clk_hw *hw)
1356 {
1357         struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
1358         int ret, val;
1359
1360         regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
1361         ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
1362
1363         return ret;
1364 }
1365
1366 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
1367                                        unsigned long parent_rate)
1368 {
1369         return parent_rate / 2;
1370 }
1371
1372 static const struct clk_ops swclk_gate_ops = {
1373         .prepare = swclk_gate_enable,
1374         .unprepare = swclk_gate_disable,
1375         .is_enabled = swclk_gate_is_enabled,
1376         .recalc_rate = swclk_recalc_rate,
1377
1378 };
1379
1380 static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
1381 {
1382         struct clk *parent = wcd->extclk;
1383         struct device *dev = wcd->dev;
1384         struct device_node *np = dev->parent->of_node;
1385         const char *parent_clk_name = NULL;
1386         const char *clk_name = "mclk";
1387         struct clk_hw *hw;
1388         struct clk_init_data init;
1389         int ret;
1390
1391         if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
1392                 return NULL;
1393
1394         parent_clk_name = __clk_get_name(parent);
1395
1396         of_property_read_string(np, "clock-output-names", &clk_name);
1397
1398         init.name = clk_name;
1399         init.ops = &swclk_gate_ops;
1400         init.flags = 0;
1401         init.parent_names = &parent_clk_name;
1402         init.num_parents = 1;
1403         wcd->hw.init = &init;
1404
1405         hw = &wcd->hw;
1406         ret = clk_hw_register(wcd->dev->parent, hw);
1407         if (ret)
1408                 return ERR_PTR(ret);
1409
1410         of_clk_add_provider(np, of_clk_src_simple_get, hw->clk);
1411
1412         return NULL;
1413 }
1414
1415 static int wcd934x_get_micbias_val(struct device *dev, const char *micbias)
1416 {
1417         int mv;
1418
1419         if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
1420                 dev_err(dev, "%s value not found, using default\n", micbias);
1421                 mv = WCD934X_DEF_MICBIAS_MV;
1422         } else {
1423                 /* convert it to milli volts */
1424                 mv = mv/1000;
1425         }
1426
1427         if (mv < 1000 || mv > 2850) {
1428                 dev_err(dev, "%s value not in valid range, using default\n",
1429                         micbias);
1430                 mv = WCD934X_DEF_MICBIAS_MV;
1431         }
1432
1433         return (mv - 1000) / 50;
1434 }
1435
1436 static int wcd934x_init_dmic(struct snd_soc_component *comp)
1437 {
1438         int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
1439         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1440         u32 def_dmic_rate, dmic_clk_drv;
1441
1442         vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
1443                                              "qcom,micbias1-microvolt");
1444         vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
1445                                              "qcom,micbias2-microvolt");
1446         vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
1447                                              "qcom,micbias3-microvolt");
1448         vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
1449                                              "qcom,micbias4-microvolt");
1450
1451         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
1452                                       WCD934X_MICB_VAL_MASK, vout_ctl_1);
1453         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
1454                                       WCD934X_MICB_VAL_MASK, vout_ctl_2);
1455         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
1456                                       WCD934X_MICB_VAL_MASK, vout_ctl_3);
1457         snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
1458                                       WCD934X_MICB_VAL_MASK, vout_ctl_4);
1459
1460         if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
1461                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
1462         else
1463                 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
1464
1465         wcd->dmic_sample_rate = def_dmic_rate;
1466
1467         dmic_clk_drv = 0;
1468         snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
1469                                       0x0C, dmic_clk_drv << 2);
1470
1471         return 0;
1472 }
1473
1474 static void wcd934x_hw_init(struct wcd934x_codec *wcd)
1475 {
1476         struct regmap *rm = wcd->regmap;
1477
1478         /* set SPKR rate to FS_2P4_3P072 */
1479         regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
1480         regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
1481
1482         /* Take DMICs out of reset */
1483         regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
1484 }
1485
1486 static int wcd934x_comp_init(struct snd_soc_component *component)
1487 {
1488         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1489
1490         wcd934x_hw_init(wcd);
1491         wcd934x_enable_efuse_sensing(wcd);
1492         wcd934x_get_version(wcd);
1493
1494         return 0;
1495 }
1496
1497 static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
1498 {
1499         struct wcd934x_codec *wcd = data;
1500         unsigned long status = 0;
1501         int i, j, port_id;
1502         unsigned int val, int_val = 0;
1503         irqreturn_t ret = IRQ_NONE;
1504         bool tx;
1505         unsigned short reg = 0;
1506
1507         for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
1508              i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
1509                 regmap_read(wcd->if_regmap, i, &val);
1510                 status |= ((u32)val << (8 * j));
1511         }
1512
1513         for_each_set_bit(j, &status, 32) {
1514                 tx = false;
1515                 port_id = j;
1516
1517                 if (j >= 16) {
1518                         tx = true;
1519                         port_id = j - 16;
1520                 }
1521
1522                 regmap_read(wcd->if_regmap,
1523                             WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
1524                 if (val) {
1525                         if (!tx)
1526                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
1527                                         (port_id / 8);
1528                         else
1529                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
1530                                         (port_id / 8);
1531                         regmap_read(wcd->if_regmap, reg, &int_val);
1532                 }
1533
1534                 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
1535                         dev_err_ratelimited(wcd->dev,
1536                                             "overflow error on %s port %d, value %x\n",
1537                                             (tx ? "TX" : "RX"), port_id, val);
1538
1539                 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
1540                         dev_err_ratelimited(wcd->dev,
1541                                             "underflow error on %s port %d, value %x\n",
1542                                             (tx ? "TX" : "RX"), port_id, val);
1543
1544                 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
1545                     (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
1546                         if (!tx)
1547                                 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
1548                                         (port_id / 8);
1549                         else
1550                                 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
1551                                         (port_id / 8);
1552                         regmap_read(
1553                                 wcd->if_regmap, reg, &int_val);
1554                         if (int_val & (1 << (port_id % 8))) {
1555                                 int_val = int_val ^ (1 << (port_id % 8));
1556                                 regmap_write(wcd->if_regmap,
1557                                              reg, int_val);
1558                         }
1559                 }
1560
1561                 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
1562                         dev_err_ratelimited(wcd->dev,
1563                                             "Port Closed %s port %d, value %x\n",
1564                                             (tx ? "TX" : "RX"), port_id, val);
1565
1566                 regmap_write(wcd->if_regmap,
1567                              WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
1568                                 BIT(j % 8));
1569                 ret = IRQ_HANDLED;
1570         }
1571
1572         return ret;
1573 }
1574
1575 static int wcd934x_comp_probe(struct snd_soc_component *component)
1576 {
1577         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1578         int i;
1579
1580         snd_soc_component_init_regmap(component, wcd->regmap);
1581         wcd->component = component;
1582
1583         /* Class-H Init*/
1584         wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
1585         if (IS_ERR(wcd->clsh_ctrl))
1586                 return PTR_ERR(wcd->clsh_ctrl);
1587
1588         /* Default HPH Mode to Class-H Low HiFi */
1589         wcd->hph_mode = CLS_H_LOHIFI;
1590
1591         wcd934x_comp_init(component);
1592
1593         for (i = 0; i < NUM_CODEC_DAIS; i++)
1594                 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
1595
1596         wcd934x_init_dmic(component);
1597         return 0;
1598 }
1599
1600 static void wcd934x_comp_remove(struct snd_soc_component *comp)
1601 {
1602         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1603
1604         wcd_clsh_ctrl_free(wcd->clsh_ctrl);
1605 }
1606
1607 static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
1608                                    int clk_id, int source,
1609                                    unsigned int freq, int dir)
1610 {
1611         struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1612         int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
1613
1614         wcd->rate = freq;
1615
1616         if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
1617                 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
1618
1619         snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
1620                                       WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
1621                                       val);
1622
1623         return clk_set_rate(wcd->extclk, freq);
1624 }
1625
1626 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
1627                                    int iir_idx, int band_idx, int coeff_idx)
1628 {
1629         u32 value = 0;
1630         int reg, b2_reg;
1631
1632         /* Address does not automatically update if reading */
1633         reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
1634         b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
1635
1636         snd_soc_component_write(component, reg,
1637                                 ((band_idx * BAND_MAX + coeff_idx) *
1638                                  sizeof(uint32_t)) & 0x7F);
1639
1640         value |= snd_soc_component_read32(component, b2_reg);
1641         snd_soc_component_write(component, reg,
1642                                 ((band_idx * BAND_MAX + coeff_idx)
1643                                  * sizeof(uint32_t) + 1) & 0x7F);
1644
1645         value |= (snd_soc_component_read32(component, b2_reg) << 8);
1646         snd_soc_component_write(component, reg,
1647                                 ((band_idx * BAND_MAX + coeff_idx)
1648                                  * sizeof(uint32_t) + 2) & 0x7F);
1649
1650         value |= (snd_soc_component_read32(component, b2_reg) << 16);
1651         snd_soc_component_write(component, reg,
1652                 ((band_idx * BAND_MAX + coeff_idx)
1653                 * sizeof(uint32_t) + 3) & 0x7F);
1654
1655         /* Mask bits top 2 bits since they are reserved */
1656         value |= (snd_soc_component_read32(component, b2_reg) << 24);
1657         return value;
1658 }
1659
1660 static void set_iir_band_coeff(struct snd_soc_component *component,
1661                                int iir_idx, int band_idx, uint32_t value)
1662 {
1663         int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
1664
1665         snd_soc_component_write(component, reg, (value & 0xFF));
1666         snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
1667         snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
1668         /* Mask top 2 bits, 7-8 are reserved */
1669         snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
1670 }
1671
1672 static int wcd934x_put_iir_band_audio_mixer(
1673                                         struct snd_kcontrol *kcontrol,
1674                                         struct snd_ctl_elem_value *ucontrol)
1675 {
1676         struct snd_soc_component *component =
1677                         snd_soc_kcontrol_component(kcontrol);
1678         struct wcd_iir_filter_ctl *ctl =
1679                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
1680         struct soc_bytes_ext *params = &ctl->bytes_ext;
1681         int iir_idx = ctl->iir_idx;
1682         int band_idx = ctl->band_idx;
1683         u32 coeff[BAND_MAX];
1684         int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
1685
1686         memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
1687
1688         /* Mask top bit it is reserved */
1689         /* Updates addr automatically for each B2 write */
1690         snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
1691                                                  sizeof(uint32_t)) & 0x7F);
1692
1693         set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
1694         set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
1695         set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
1696         set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
1697         set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
1698
1699         return 0;
1700 }
1701
1702 static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
1703                                     struct snd_ctl_elem_value *ucontrol)
1704 {
1705         struct snd_soc_component *component =
1706                         snd_soc_kcontrol_component(kcontrol);
1707         struct wcd_iir_filter_ctl *ctl =
1708                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
1709         struct soc_bytes_ext *params = &ctl->bytes_ext;
1710         int iir_idx = ctl->iir_idx;
1711         int band_idx = ctl->band_idx;
1712         u32 coeff[BAND_MAX];
1713
1714         coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
1715         coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
1716         coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
1717         coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
1718         coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
1719
1720         memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
1721
1722         return 0;
1723 }
1724
1725 static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
1726                                    struct snd_ctl_elem_info *ucontrol)
1727 {
1728         struct wcd_iir_filter_ctl *ctl =
1729                 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
1730         struct soc_bytes_ext *params = &ctl->bytes_ext;
1731
1732         ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1733         ucontrol->count = params->max;
1734
1735         return 0;
1736 }
1737
1738 static int wcd934x_compander_get(struct snd_kcontrol *kc,
1739                                  struct snd_ctl_elem_value *ucontrol)
1740 {
1741         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
1742         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
1743         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1744
1745         ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
1746
1747         return 0;
1748 }
1749
1750 static int wcd934x_compander_set(struct snd_kcontrol *kc,
1751                                  struct snd_ctl_elem_value *ucontrol)
1752 {
1753         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
1754         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1755         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
1756         int value = ucontrol->value.integer.value[0];
1757         int sel;
1758
1759         wcd->comp_enabled[comp] = value;
1760         sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
1761                 WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
1762
1763         /* Any specific register configuration for compander */
1764         switch (comp) {
1765         case COMPANDER_1:
1766                 /* Set Gain Source Select based on compander enable/disable */
1767                 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
1768                                               WCD934X_HPH_GAIN_SRC_SEL_MASK,
1769                                               sel);
1770                 break;
1771         case COMPANDER_2:
1772                 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
1773                                               WCD934X_HPH_GAIN_SRC_SEL_MASK,
1774                                               sel);
1775                 break;
1776         case COMPANDER_3:
1777         case COMPANDER_4:
1778         case COMPANDER_7:
1779         case COMPANDER_8:
1780                 break;
1781         default:
1782                 break;
1783         };
1784
1785         return 0;
1786 }
1787
1788 static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
1789                                    struct snd_ctl_elem_value *ucontrol)
1790 {
1791         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
1792         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1793
1794         ucontrol->value.enumerated.item[0] = wcd->hph_mode;
1795
1796         return 0;
1797 }
1798
1799 static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
1800                                    struct snd_ctl_elem_value *ucontrol)
1801 {
1802         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
1803         struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1804         u32 mode_val;
1805
1806         mode_val = ucontrol->value.enumerated.item[0];
1807
1808         if (mode_val == 0) {
1809                 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
1810                 mode_val = CLS_H_LOHIFI;
1811         }
1812         wcd->hph_mode = mode_val;
1813
1814         return 0;
1815 }
1816
1817 static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
1818         /* Gain Controls */
1819         SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
1820         SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
1821         SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
1822         SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
1823                        3, 16, 1, line_gain),
1824         SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
1825                        3, 16, 1, line_gain),
1826
1827         SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
1828         SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
1829         SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
1830         SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
1831
1832         SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
1833                           -84, 40, digital_gain), /* -84dB min - 40dB max */
1834         SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
1835                           -84, 40, digital_gain),
1836         SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
1837                           -84, 40, digital_gain),
1838         SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
1839                           -84, 40, digital_gain),
1840         SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
1841                           -84, 40, digital_gain),
1842         SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
1843                           -84, 40, digital_gain),
1844         SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
1845                           -84, 40, digital_gain),
1846         SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
1847                           WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
1848                           -84, 40, digital_gain),
1849         SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
1850                           WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
1851                           -84, 40, digital_gain),
1852         SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
1853                           WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
1854                           -84, 40, digital_gain),
1855         SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
1856                           WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
1857                           -84, 40, digital_gain),
1858         SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
1859                           WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
1860                           -84, 40, digital_gain),
1861         SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
1862                           WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
1863                           -84, 40, digital_gain),
1864         SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
1865                           WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
1866                           -84, 40, digital_gain),
1867
1868         SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
1869                           -84, 40, digital_gain),
1870         SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
1871                           -84, 40, digital_gain),
1872         SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
1873                           -84, 40, digital_gain),
1874         SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
1875                           -84, 40, digital_gain),
1876         SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
1877                           -84, 40, digital_gain),
1878         SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
1879                           -84, 40, digital_gain),
1880         SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
1881                           -84, 40, digital_gain),
1882         SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
1883                           -84, 40, digital_gain),
1884         SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
1885                           -84, 40, digital_gain),
1886
1887         SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
1888                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
1889                           digital_gain),
1890         SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
1891                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
1892                           digital_gain),
1893         SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
1894                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
1895                           digital_gain),
1896         SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
1897                           WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
1898                           digital_gain),
1899         SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
1900                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
1901                           digital_gain),
1902         SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
1903                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
1904                           digital_gain),
1905         SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
1906                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
1907                           digital_gain),
1908         SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
1909                           WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
1910                           digital_gain),
1911
1912         SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
1913         SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
1914         SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
1915         SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
1916         SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
1917         SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
1918         SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
1919         SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
1920         SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
1921
1922         SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
1923         SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
1924         SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
1925         SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
1926         SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
1927         SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
1928         SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
1929         SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
1930         SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
1931         SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
1932         SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
1933         SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
1934         SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
1935         SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
1936
1937         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
1938                      wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
1939
1940         SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
1941                    0, 1, 0),
1942         SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
1943                    1, 1, 0),
1944         SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
1945                    2, 1, 0),
1946         SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
1947                    3, 1, 0),
1948         SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
1949                    4, 1, 0),
1950         SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
1951                    0, 1, 0),
1952         SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
1953                    1, 1, 0),
1954         SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
1955                    2, 1, 0),
1956         SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
1957                    3, 1, 0),
1958         SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
1959                    4, 1, 0),
1960         WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
1961         WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
1962         WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
1963         WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
1964         WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
1965
1966         WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
1967         WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
1968         WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
1969         WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
1970         WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
1971
1972         SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
1973                        wcd934x_compander_get, wcd934x_compander_set),
1974         SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
1975                        wcd934x_compander_get, wcd934x_compander_set),
1976         SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
1977                        wcd934x_compander_get, wcd934x_compander_set),
1978         SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
1979                        wcd934x_compander_get, wcd934x_compander_set),
1980         SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
1981                        wcd934x_compander_get, wcd934x_compander_set),
1982         SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
1983                        wcd934x_compander_get, wcd934x_compander_set),
1984 };
1985
1986 static const struct snd_soc_component_driver wcd934x_component_drv = {
1987         .probe = wcd934x_comp_probe,
1988         .remove = wcd934x_comp_remove,
1989         .set_sysclk = wcd934x_comp_set_sysclk,
1990         .controls = wcd934x_snd_controls,
1991         .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
1992 };
1993
1994 static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
1995 {
1996         struct device *dev = &wcd->sdev->dev;
1997         struct device_node *ifc_dev_np;
1998
1999         ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
2000         if (!ifc_dev_np) {
2001                 dev_err(dev, "No Interface device found\n");
2002                 return -EINVAL;
2003         }
2004
2005         wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
2006         if (!wcd->sidev) {
2007                 dev_err(dev, "Unable to get SLIM Interface device\n");
2008                 return -EINVAL;
2009         }
2010
2011         slim_get_logical_addr(wcd->sidev);
2012         wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
2013                                   &wcd934x_ifc_regmap_config);
2014         if (IS_ERR(wcd->if_regmap)) {
2015                 dev_err(dev, "Failed to allocate ifc register map\n");
2016                 return PTR_ERR(wcd->if_regmap);
2017         }
2018
2019         of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
2020                              &wcd->dmic_sample_rate);
2021
2022         return 0;
2023 }
2024
2025 static int wcd934x_codec_probe(struct platform_device *pdev)
2026 {
2027         struct wcd934x_ddata *data = dev_get_drvdata(pdev->dev.parent);
2028         struct wcd934x_codec *wcd;
2029         struct device *dev = &pdev->dev;
2030         int ret, irq;
2031
2032         wcd = devm_kzalloc(&pdev->dev, sizeof(*wcd), GFP_KERNEL);
2033         if (!wcd)
2034                 return -ENOMEM;
2035
2036         wcd->dev = dev;
2037         wcd->regmap = data->regmap;
2038         wcd->extclk = data->extclk;
2039         wcd->sdev = to_slim_device(data->dev);
2040         mutex_init(&wcd->sysclk_mutex);
2041
2042         ret = wcd934x_codec_parse_data(wcd);
2043         if (ret) {
2044                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
2045                 return ret;
2046         }
2047
2048         /* set default rate 9P6MHz */
2049         regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
2050                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
2051                            WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
2052         memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
2053         memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
2054
2055         irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
2056         if (irq < 0) {
2057                 dev_err(wcd->dev, "Failed to get SLIM IRQ\n");
2058                 return irq;
2059         }
2060
2061         ret = devm_request_threaded_irq(dev, irq, NULL,
2062                                         wcd934x_slim_irq_handler,
2063                                         IRQF_TRIGGER_RISING,
2064                                         "slim", wcd);
2065         if (ret) {
2066                 dev_err(dev, "Failed to request slimbus irq\n");
2067                 return ret;
2068         }
2069
2070         wcd934x_register_mclk_output(wcd);
2071         platform_set_drvdata(pdev, wcd);
2072
2073         return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
2074                                                wcd934x_slim_dais,
2075                                                ARRAY_SIZE(wcd934x_slim_dais));
2076 }
2077
2078 static const struct platform_device_id wcd934x_driver_id[] = {
2079         {
2080                 .name = "wcd934x-codec",
2081         },
2082         {},
2083 };
2084 MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
2085
2086 static struct platform_driver wcd934x_codec_driver = {
2087         .probe  = &wcd934x_codec_probe,
2088         .id_table = wcd934x_driver_id,
2089         .driver = {
2090                 .name   = "wcd934x-codec",
2091         }
2092 };
2093
2094 MODULE_ALIAS("platform:wcd934x-codec");
2095 module_platform_driver(wcd934x_codec_driver);
2096 MODULE_DESCRIPTION("WCD934x codec driver");
2097 MODULE_LICENSE("GPL v2");