sound/soc/codecs/wcd9335.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   3 // Copyright (c) 2017-2018, Linaro Limited
   4
   5 #include <linux/module.h>
   6 #include <linux/init.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/device.h>
   9 #include <linux/wait.h>
  10 #include <linux/bitops.h>
  11 #include <linux/regulator/consumer.h>
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slimbus.h>
  16 #include <sound/soc.h>
  17 #include <sound/pcm_params.h>
  18 #include <sound/soc-dapm.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22 #include <sound/tlv.h>
  23 #include <sound/info.h>
  24 #include "wcd9335.h"
  25 #include "wcd-clsh-v2.h"
  26
  27 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  28                             SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  29                             SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  30 /* Fractional Rates */
  31 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
  32 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  33                                   SNDRV_PCM_FMTBIT_S24_LE)
  34
  35 /* slave port water mark level
  36  *   (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
  37  */
  38 #define SLAVE_PORT_WATER_MARK_6BYTES  0
  39 #define SLAVE_PORT_WATER_MARK_9BYTES  1
  40 #define SLAVE_PORT_WATER_MARK_12BYTES 2
  41 #define SLAVE_PORT_WATER_MARK_15BYTES 3
  42 #define SLAVE_PORT_WATER_MARK_SHIFT 1
  43 #define SLAVE_PORT_ENABLE           1
  44 #define SLAVE_PORT_DISABLE          0
  45 #define WCD9335_SLIM_WATER_MARK_VAL \
  46         ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
  47          (SLAVE_PORT_ENABLE))
  48
  49 #define WCD9335_SLIM_NUM_PORT_REG 3
  50 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2)
  51
  52 #define WCD9335_MCLK_CLK_12P288MHZ      12288000
  53 #define WCD9335_MCLK_CLK_9P6MHZ         9600000
  54
  55 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000
  56 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0)
  57 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1)
  58 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2)
  59
  60 #define WCD9335_NUM_INTERPOLATORS 9
  61 #define WCD9335_RX_START        16
  62 #define WCD9335_SLIM_CH_START 128
  63 #define WCD9335_MAX_MICBIAS 4
  64 #define WCD9335_MAX_VALID_ADC_MUX  13
  65 #define WCD9335_INVALID_ADC_MUX 9
  66
  67 #define  TX_HPF_CUT_OFF_FREQ_MASK       0x60
  68 #define  CF_MIN_3DB_4HZ                 0x0
  69 #define  CF_MIN_3DB_75HZ                0x1
  70 #define  CF_MIN_3DB_150HZ               0x2
  71 #define WCD9335_DMIC_CLK_DIV_2  0x0
  72 #define WCD9335_DMIC_CLK_DIV_3  0x1
  73 #define WCD9335_DMIC_CLK_DIV_4  0x2
  74 #define WCD9335_DMIC_CLK_DIV_6  0x3
  75 #define WCD9335_DMIC_CLK_DIV_8  0x4
  76 #define WCD9335_DMIC_CLK_DIV_16  0x5
  77 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02
  78 #define WCD9335_AMIC_PWR_LEVEL_LP 0
  79 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
  80 #define WCD9335_AMIC_PWR_LEVEL_HP 2
  81 #define WCD9335_AMIC_PWR_LVL_MASK 0x60
  82 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
  83
  84 #define WCD9335_DEC_PWR_LVL_MASK 0x06
  85 #define WCD9335_DEC_PWR_LVL_LP 0x02
  86 #define WCD9335_DEC_PWR_LVL_HP 0x04
  87 #define WCD9335_DEC_PWR_LVL_DF 0x00
  88
  89 #define WCD9335_SLIM_RX_CH(p) \
  90         {.port = p + WCD9335_RX_START, .shift = p,}
  91
  92 #define WCD9335_SLIM_TX_CH(p) \
  93         {.port = p, .shift = p,}
  94
  95 /* vout step value */
  96 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
  97
  98 #define WCD9335_INTERPOLATOR_PATH(id)                   \
  99         {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"},       \
 100         {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"},       \
 101         {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"},       \
 102         {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"},       \
 103         {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"},       \
 104         {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"},       \
 105         {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"},       \
 106         {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"},       \
 107         {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"},       \
 108         {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"},       \
 109         {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"},       \
 110         {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"},       \
 111         {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"},       \
 112         {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"},       \
 113         {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"},       \
 114         {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"},       \
 115         {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"},       \
 116         {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"},       \
 117         {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"},       \
 118         {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"},       \
 119         {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"},       \
 120         {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"},       \
 121         {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"},       \
 122         {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"},       \
 123         {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"},     \
 124         {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"},     \
 125         {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"},     \
 126         {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"},     \
 127         {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"},     \
 128         {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"},     \
 129         {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"},     \
 130         {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"},     \
 131         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"},    \
 132         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"},    \
 133         {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"},    \
 134         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"},         \
 135         {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"},        \
 136         {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"},          \
 137         {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"}
 138
 139 #define WCD9335_ADC_MUX_PATH(id)                        \
 140         {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
 141         {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
 142         {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
 143         {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \
 144         {"ADC MUX" #id, "DMIC", "DMIC MUX" #id},        \
 145         {"ADC MUX" #id, "AMIC", "AMIC MUX" #id},        \
 146         {"DMIC MUX" #id, "DMIC0", "DMIC0"},             \
 147         {"DMIC MUX" #id, "DMIC1", "DMIC1"},             \
 148         {"DMIC MUX" #id, "DMIC2", "DMIC2"},             \
 149         {"DMIC MUX" #id, "DMIC3", "DMIC3"},             \
 150         {"DMIC MUX" #id, "DMIC4", "DMIC4"},             \
 151         {"DMIC MUX" #id, "DMIC5", "DMIC5"},             \
 152         {"AMIC MUX" #id, "ADC1", "ADC1"},               \
 153         {"AMIC MUX" #id, "ADC2", "ADC2"},               \
 154         {"AMIC MUX" #id, "ADC3", "ADC3"},               \
 155         {"AMIC MUX" #id, "ADC4", "ADC4"},               \
 156         {"AMIC MUX" #id, "ADC5", "ADC5"},               \
 157         {"AMIC MUX" #id, "ADC6", "ADC6"}
 158
 159 enum {
 160         WCD9335_RX0 = 0,
 161         WCD9335_RX1,
 162         WCD9335_RX2,
 163         WCD9335_RX3,
 164         WCD9335_RX4,
 165         WCD9335_RX5,
 166         WCD9335_RX6,
 167         WCD9335_RX7,
 168         WCD9335_RX8,
 169         WCD9335_RX9,
 170         WCD9335_RX10,
 171         WCD9335_RX11,
 172         WCD9335_RX12,
 173         WCD9335_RX_MAX,
 174 };
 175
 176 enum {
 177         WCD9335_TX0 = 0,
 178         WCD9335_TX1,
 179         WCD9335_TX2,
 180         WCD9335_TX3,
 181         WCD9335_TX4,
 182         WCD9335_TX5,
 183         WCD9335_TX6,
 184         WCD9335_TX7,
 185         WCD9335_TX8,
 186         WCD9335_TX9,
 187         WCD9335_TX10,
 188         WCD9335_TX11,
 189         WCD9335_TX12,
 190         WCD9335_TX13,
 191         WCD9335_TX14,
 192         WCD9335_TX15,
 193         WCD9335_TX_MAX,
 194 };
 195
 196 enum {
 197         SIDO_SOURCE_INTERNAL = 0,
 198         SIDO_SOURCE_RCO_BG,
 199 };
 200
 201 enum wcd9335_sido_voltage {
 202         SIDO_VOLTAGE_SVS_MV = 950,
 203         SIDO_VOLTAGE_NOMINAL_MV = 1100,
 204 };
 205
 206 enum {
 207         AIF1_PB = 0,
 208         AIF1_CAP,
 209         AIF2_PB,
 210         AIF2_CAP,
 211         AIF3_PB,
 212         AIF3_CAP,
 213         AIF4_PB,
 214         NUM_CODEC_DAIS,
 215 };
 216
 217 enum {
 218         COMPANDER_1, /* HPH_L */
 219         COMPANDER_2, /* HPH_R */
 220         COMPANDER_3, /* LO1_DIFF */
 221         COMPANDER_4, /* LO2_DIFF */
 222         COMPANDER_5, /* LO3_SE */
 223         COMPANDER_6, /* LO4_SE */
 224         COMPANDER_7, /* SWR SPK CH1 */
 225         COMPANDER_8, /* SWR SPK CH2 */
 226         COMPANDER_MAX,
 227 };
 228
 229 enum {
 230         INTn_2_INP_SEL_ZERO = 0,
 231         INTn_2_INP_SEL_RX0,
 232         INTn_2_INP_SEL_RX1,
 233         INTn_2_INP_SEL_RX2,
 234         INTn_2_INP_SEL_RX3,
 235         INTn_2_INP_SEL_RX4,
 236         INTn_2_INP_SEL_RX5,
 237         INTn_2_INP_SEL_RX6,
 238         INTn_2_INP_SEL_RX7,
 239         INTn_2_INP_SEL_PROXIMITY,
 240 };
 241
 242 enum {
 243         INTn_1_MIX_INP_SEL_ZERO = 0,
 244         INTn_1_MIX_INP_SEL_DEC0,
 245         INTn_1_MIX_INP_SEL_DEC1,
 246         INTn_1_MIX_INP_SEL_IIR0,
 247         INTn_1_MIX_INP_SEL_IIR1,
 248         INTn_1_MIX_INP_SEL_RX0,
 249         INTn_1_MIX_INP_SEL_RX1,
 250         INTn_1_MIX_INP_SEL_RX2,
 251         INTn_1_MIX_INP_SEL_RX3,
 252         INTn_1_MIX_INP_SEL_RX4,
 253         INTn_1_MIX_INP_SEL_RX5,
 254         INTn_1_MIX_INP_SEL_RX6,
 255         INTn_1_MIX_INP_SEL_RX7,
 256
 257 };
 258
 259 enum {
 260         INTERP_EAR = 0,
 261         INTERP_HPHL,
 262         INTERP_HPHR,
 263         INTERP_LO1,
 264         INTERP_LO2,
 265         INTERP_LO3,
 266         INTERP_LO4,
 267         INTERP_SPKR1,
 268         INTERP_SPKR2,
 269 };
 270
 271 enum wcd_clock_type {
 272         WCD_CLK_OFF,
 273         WCD_CLK_RCO,
 274         WCD_CLK_MCLK,
 275 };
 276
 277 enum {
 278         MIC_BIAS_1 = 1,
 279         MIC_BIAS_2,
 280         MIC_BIAS_3,
 281         MIC_BIAS_4
 282 };
 283
 284 enum {
 285         MICB_PULLUP_ENABLE,
 286         MICB_PULLUP_DISABLE,
 287         MICB_ENABLE,
 288         MICB_DISABLE,
 289 };
 290
 291 struct wcd9335_slim_ch {
 292         u32 ch_num;
 293         u16 port;
 294         u16 shift;
 295         struct list_head list;
 296 };
 297
 298 struct wcd_slim_codec_dai_data {
 299         struct list_head slim_ch_list;
 300         struct slim_stream_config sconfig;
 301         struct slim_stream_runtime *sruntime;
 302 };
 303
 304 struct wcd9335_codec {
 305         struct device *dev;
 306         struct clk *mclk;
 307         struct clk *native_clk;
 308         u32 mclk_rate;
 309         u8 version;
 310
 311         struct slim_device *slim;
 312         struct slim_device *slim_ifc_dev;
 313         struct regmap *regmap;
 314         struct regmap *if_regmap;
 315         struct regmap_irq_chip_data *irq_data;
 316
 317         struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX];
 318         struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX];
 319         u32 num_rx_port;
 320         u32 num_tx_port;
 321
 322         int sido_input_src;
 323         enum wcd9335_sido_voltage sido_voltage;
 324
 325         struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
 326         struct snd_soc_component *component;
 327
 328         int master_bias_users;
 329         int clk_mclk_users;
 330         int clk_rco_users;
 331         int sido_ccl_cnt;
 332         enum wcd_clock_type clk_type;
 333
 334         struct wcd_clsh_ctrl *clsh_ctrl;
 335         u32 hph_mode;
 336         int prim_int_users[WCD9335_NUM_INTERPOLATORS];
 337
 338         int comp_enabled[COMPANDER_MAX];
 339
 340         int intr1;
 341         int reset_gpio;
 342         struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY];
 343
 344         unsigned int rx_port_value[WCD9335_RX_MAX];
 345         unsigned int tx_port_value;
 346         int hph_l_gain;
 347         int hph_r_gain;
 348         u32 rx_bias_count;
 349
 350         /*TX*/
 351         int micb_ref[WCD9335_MAX_MICBIAS];
 352         int pullup_ref[WCD9335_MAX_MICBIAS];
 353
 354         int dmic_0_1_clk_cnt;
 355         int dmic_2_3_clk_cnt;
 356         int dmic_4_5_clk_cnt;
 357         int dmic_sample_rate;
 358         int mad_dmic_sample_rate;
 359
 360         int native_clk_users;
 361 };
 362
 363 struct wcd9335_irq {
 364         int irq;
 365         irqreturn_t (*handler)(int irq, void *data);
 366         char *name;
 367 };
 368
 369 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = {
 370         WCD9335_SLIM_TX_CH(0),
 371         WCD9335_SLIM_TX_CH(1),
 372         WCD9335_SLIM_TX_CH(2),
 373         WCD9335_SLIM_TX_CH(3),
 374         WCD9335_SLIM_TX_CH(4),
 375         WCD9335_SLIM_TX_CH(5),
 376         WCD9335_SLIM_TX_CH(6),
 377         WCD9335_SLIM_TX_CH(7),
 378         WCD9335_SLIM_TX_CH(8),
 379         WCD9335_SLIM_TX_CH(9),
 380         WCD9335_SLIM_TX_CH(10),
 381         WCD9335_SLIM_TX_CH(11),
 382         WCD9335_SLIM_TX_CH(12),
 383         WCD9335_SLIM_TX_CH(13),
 384         WCD9335_SLIM_TX_CH(14),
 385         WCD9335_SLIM_TX_CH(15),
 386 };
 387
 388 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = {
 389         WCD9335_SLIM_RX_CH(0),   /* 16 */
 390         WCD9335_SLIM_RX_CH(1),   /* 17 */
 391         WCD9335_SLIM_RX_CH(2),
 392         WCD9335_SLIM_RX_CH(3),
 393         WCD9335_SLIM_RX_CH(4),
 394         WCD9335_SLIM_RX_CH(5),
 395         WCD9335_SLIM_RX_CH(6),
 396         WCD9335_SLIM_RX_CH(7),
 397         WCD9335_SLIM_RX_CH(8),
 398         WCD9335_SLIM_RX_CH(9),
 399         WCD9335_SLIM_RX_CH(10),
 400         WCD9335_SLIM_RX_CH(11),
 401         WCD9335_SLIM_RX_CH(12),
 402 };
 403
 404 struct interp_sample_rate {
 405         int rate;
 406         int rate_val;
 407 };
 408
 409 static struct interp_sample_rate int_mix_rate_val[] = {
 410         {48000, 0x4},   /* 48K */
 411         {96000, 0x5},   /* 96K */
 412         {192000, 0x6},  /* 192K */
 413 };
 414
 415 static struct interp_sample_rate int_prim_rate_val[] = {
 416         {8000, 0x0},    /* 8K */
 417         {16000, 0x1},   /* 16K */
 418         {24000, -EINVAL},/* 24K */
 419         {32000, 0x3},   /* 32K */
 420         {48000, 0x4},   /* 48K */
 421         {96000, 0x5},   /* 96K */
 422         {192000, 0x6},  /* 192K */
 423         {384000, 0x7},  /* 384K */
 424         {44100, 0x8}, /* 44.1K */
 425 };
 426
 427 struct wcd9335_reg_mask_val {
 428         u16 reg;
 429         u8 mask;
 430         u8 val;
 431 };
 432
 433 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
 434         /* Rbuckfly/R_EAR(32) */
 435         {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
 436         {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
 437         {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
 438         {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
 439         {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
 440         {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
 441         {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
 442         {WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
 443         {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
 444         {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
 445         {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
 446         {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
 447         {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
 448         {WCD9335_EAR_CMBUFF, 0x08, 0x00},
 449         {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 450         {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 451         {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 452         {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
 453         {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
 454         {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
 455         {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
 456         {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
 457         {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
 458         {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
 459         {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
 460         {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
 461         {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
 462         {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
 463         {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
 464         {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
 465         {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
 466         {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
 467         {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
 468         {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
 469         {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
 470         {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
 471         {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
 472         {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
 473         {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
 474         {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
 475         {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
 476         {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
 477         {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
 478         {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
 479         {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A},
 480         {WCD9335_HPH_L_TEST, 0x01, 0x01},
 481         {WCD9335_HPH_R_TEST, 0x01, 0x01},
 482         {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
 483         {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
 484         {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
 485         {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
 486         {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
 487         {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
 488         {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
 489         {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
 490         {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
 491         {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
 492 };
 493
 494 /* Cutoff frequency for high pass filter */
 495 static const char * const cf_text[] = {
 496         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
 497 };
 498
 499 static const char * const rx_cf_text[] = {
 500         "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
 501         "CF_NEG_3DB_0P48HZ"
 502 };
 503
 504 static const char * const rx_int0_7_mix_mux_text[] = {
 505         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 506         "RX6", "RX7", "PROXIMITY"
 507 };
 508
 509 static const char * const rx_int_mix_mux_text[] = {
 510         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
 511         "RX6", "RX7"
 512 };
 513
 514 static const char * const rx_prim_mix_text[] = {
 515         "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
 516         "RX3", "RX4", "RX5", "RX6", "RX7"
 517 };
 518
 519 static const char * const rx_int_dem_inp_mux_text[] = {
 520         "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
 521 };
 522
 523 static const char * const rx_int0_interp_mux_text[] = {
 524         "ZERO", "RX INT0 MIX2",
 525 };
 526
 527 static const char * const rx_int1_interp_mux_text[] = {
 528         "ZERO", "RX INT1 MIX2",
 529 };
 530
 531 static const char * const rx_int2_interp_mux_text[] = {
 532         "ZERO", "RX INT2 MIX2",
 533 };
 534
 535 static const char * const rx_int3_interp_mux_text[] = {
 536         "ZERO", "RX INT3 MIX2",
 537 };
 538
 539 static const char * const rx_int4_interp_mux_text[] = {
 540         "ZERO", "RX INT4 MIX2",
 541 };
 542
 543 static const char * const rx_int5_interp_mux_text[] = {
 544         "ZERO", "RX INT5 MIX2",
 545 };
 546
 547 static const char * const rx_int6_interp_mux_text[] = {
 548         "ZERO", "RX INT6 MIX2",
 549 };
 550
 551 static const char * const rx_int7_interp_mux_text[] = {
 552         "ZERO", "RX INT7 MIX2",
 553 };
 554
 555 static const char * const rx_int8_interp_mux_text[] = {
 556         "ZERO", "RX INT8 SEC MIX"
 557 };
 558
 559 static const char * const rx_hph_mode_mux_text[] = {
 560         "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
 561         "Class-H Hi-Fi Low Power"
 562 };
 563
 564 static const char *const slim_rx_mux_text[] = {
 565         "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
 566 };
 567
 568 static const char * const adc_mux_text[] = {
 569         "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
 570 };
 571
 572 static const char * const dmic_mux_text[] = {
 573         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
 574         "SMIC0", "SMIC1", "SMIC2", "SMIC3"
 575 };
 576
 577 static const char * const dmic_mux_alt_text[] = {
 578         "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
 579 };
 580
 581 static const char * const amic_mux_text[] = {
 582         "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
 583 };
 584
 585 static const char * const sb_tx0_mux_text[] = {
 586         "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
 587 };
 588
 589 static const char * const sb_tx1_mux_text[] = {
 590         "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
 591 };
 592
 593 static const char * const sb_tx2_mux_text[] = {
 594         "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
 595 };
 596
 597 static const char * const sb_tx3_mux_text[] = {
 598         "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
 599 };
 600
 601 static const char * const sb_tx4_mux_text[] = {
 602         "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
 603 };
 604
 605 static const char * const sb_tx5_mux_text[] = {
 606         "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
 607 };
 608
 609 static const char * const sb_tx6_mux_text[] = {
 610         "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
 611 };
 612
 613 static const char * const sb_tx7_mux_text[] = {
 614         "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
 615 };
 616
 617 static const char * const sb_tx8_mux_text[] = {
 618         "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
 619 };
 620
 621 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
 622 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 623 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 624 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
 625
 626 static const struct soc_enum cf_dec0_enum =
 627         SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
 628
 629 static const struct soc_enum cf_dec1_enum =
 630         SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
 631
 632 static const struct soc_enum cf_dec2_enum =
 633         SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
 634
 635 static const struct soc_enum cf_dec3_enum =
 636         SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
 637
 638 static const struct soc_enum cf_dec4_enum =
 639         SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
 640
 641 static const struct soc_enum cf_dec5_enum =
 642         SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
 643
 644 static const struct soc_enum cf_dec6_enum =
 645         SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
 646
 647 static const struct soc_enum cf_dec7_enum =
 648         SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
 649
 650 static const struct soc_enum cf_dec8_enum =
 651         SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
 652
 653 static const struct soc_enum cf_int0_1_enum =
 654         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
 655
 656 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
 657                      rx_cf_text);
 658
 659 static const struct soc_enum cf_int1_1_enum =
 660         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
 661
 662 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
 663                      rx_cf_text);
 664
 665 static const struct soc_enum cf_int2_1_enum =
 666         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
 667
 668 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
 669                      rx_cf_text);
 670
 671 static const struct soc_enum cf_int3_1_enum =
 672         SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
 673
 674 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
 675                      rx_cf_text);
 676
 677 static const struct soc_enum cf_int4_1_enum =
 678         SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
 679
 680 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
 681                      rx_cf_text);
 682
 683 static const struct soc_enum cf_int5_1_enum =
 684         SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
 685
 686 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
 687                      rx_cf_text);
 688
 689 static const struct soc_enum cf_int6_1_enum =
 690         SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
 691
 692 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
 693                      rx_cf_text);
 694
 695 static const struct soc_enum cf_int7_1_enum =
 696         SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
 697
 698 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
 699                      rx_cf_text);
 700
 701 static const struct soc_enum cf_int8_1_enum =
 702         SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
 703
 704 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
 705                      rx_cf_text);
 706
 707 static const struct soc_enum rx_hph_mode_mux_enum =
 708         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
 709                             rx_hph_mode_mux_text);
 710
 711 static const struct soc_enum slim_rx_mux_enum =
 712         SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
 713
 714 static const struct soc_enum rx_int0_2_mux_chain_enum =
 715         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
 716                         rx_int0_7_mix_mux_text);
 717
 718 static const struct soc_enum rx_int1_2_mux_chain_enum =
 719         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
 720                         rx_int_mix_mux_text);
 721
 722 static const struct soc_enum rx_int2_2_mux_chain_enum =
 723         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
 724                         rx_int_mix_mux_text);
 725
 726 static const struct soc_enum rx_int3_2_mux_chain_enum =
 727         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
 728                         rx_int_mix_mux_text);
 729
 730 static const struct soc_enum rx_int4_2_mux_chain_enum =
 731         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
 732                         rx_int_mix_mux_text);
 733
 734 static const struct soc_enum rx_int5_2_mux_chain_enum =
 735         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
 736                         rx_int_mix_mux_text);
 737
 738 static const struct soc_enum rx_int6_2_mux_chain_enum =
 739         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
 740                         rx_int_mix_mux_text);
 741
 742 static const struct soc_enum rx_int7_2_mux_chain_enum =
 743         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
 744                         rx_int0_7_mix_mux_text);
 745
 746 static const struct soc_enum rx_int8_2_mux_chain_enum =
 747         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
 748                         rx_int_mix_mux_text);
 749
 750 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
 751         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
 752                         rx_prim_mix_text);
 753
 754 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
 755         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
 756                         rx_prim_mix_text);
 757
 758 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
 759         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
 760                         rx_prim_mix_text);
 761
 762 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
 763         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
 764                         rx_prim_mix_text);
 765
 766 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
 767         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
 768                         rx_prim_mix_text);
 769
 770 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
 771         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
 772                         rx_prim_mix_text);
 773
 774 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
 775         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
 776                         rx_prim_mix_text);
 777
 778 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
 779         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
 780                         rx_prim_mix_text);
 781
 782 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
 783         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
 784                         rx_prim_mix_text);
 785
 786 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
 787         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
 788                         rx_prim_mix_text);
 789
 790 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
 791         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
 792                         rx_prim_mix_text);
 793
 794 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
 795         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
 796                         rx_prim_mix_text);
 797
 798 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
 799         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
 800                         rx_prim_mix_text);
 801
 802 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
 803         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
 804                         rx_prim_mix_text);
 805
 806 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
 807         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
 808                         rx_prim_mix_text);
 809
 810 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
 811         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
 812                         rx_prim_mix_text);
 813
 814 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
 815         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
 816                         rx_prim_mix_text);
 817
 818 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
 819         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
 820                         rx_prim_mix_text);
 821
 822 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
 823         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
 824                         rx_prim_mix_text);
 825
 826 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
 827         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
 828                         rx_prim_mix_text);
 829
 830 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
 831         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
 832                         rx_prim_mix_text);
 833
 834 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
 835         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
 836                         rx_prim_mix_text);
 837
 838 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
 839         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
 840                         rx_prim_mix_text);
 841
 842 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
 843         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
 844                         rx_prim_mix_text);
 845
 846 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
 847         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
 848                         rx_prim_mix_text);
 849
 850 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
 851         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
 852                         rx_prim_mix_text);
 853
 854 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
 855         SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
 856                         rx_prim_mix_text);
 857
 858 static const struct soc_enum rx_int0_dem_inp_mux_enum =
 859         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
 860                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 861                         rx_int_dem_inp_mux_text);
 862
 863 static const struct soc_enum rx_int1_dem_inp_mux_enum =
 864         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
 865                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 866                         rx_int_dem_inp_mux_text);
 867
 868 static const struct soc_enum rx_int2_dem_inp_mux_enum =
 869         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
 870                         ARRAY_SIZE(rx_int_dem_inp_mux_text),
 871                         rx_int_dem_inp_mux_text);
 872
 873 static const struct soc_enum rx_int0_interp_mux_enum =
 874         SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
 875                         rx_int0_interp_mux_text);
 876
 877 static const struct soc_enum rx_int1_interp_mux_enum =
 878         SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
 879                         rx_int1_interp_mux_text);
 880
 881 static const struct soc_enum rx_int2_interp_mux_enum =
 882         SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
 883                         rx_int2_interp_mux_text);
 884
 885 static const struct soc_enum rx_int3_interp_mux_enum =
 886         SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
 887                         rx_int3_interp_mux_text);
 888
 889 static const struct soc_enum rx_int4_interp_mux_enum =
 890         SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
 891                         rx_int4_interp_mux_text);
 892
 893 static const struct soc_enum rx_int5_interp_mux_enum =
 894         SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
 895                         rx_int5_interp_mux_text);
 896
 897 static const struct soc_enum rx_int6_interp_mux_enum =
 898         SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
 899                         rx_int6_interp_mux_text);
 900
 901 static const struct soc_enum rx_int7_interp_mux_enum =
 902         SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
 903                         rx_int7_interp_mux_text);
 904
 905 static const struct soc_enum rx_int8_interp_mux_enum =
 906         SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
 907                         rx_int8_interp_mux_text);
 908
 909 static const struct soc_enum tx_adc_mux0_chain_enum =
 910         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
 911                         adc_mux_text);
 912
 913 static const struct soc_enum tx_adc_mux1_chain_enum =
 914         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
 915                         adc_mux_text);
 916
 917 static const struct soc_enum tx_adc_mux2_chain_enum =
 918         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
 919                         adc_mux_text);
 920
 921 static const struct soc_enum tx_adc_mux3_chain_enum =
 922         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
 923                         adc_mux_text);
 924
 925 static const struct soc_enum tx_adc_mux4_chain_enum =
 926         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
 927                         adc_mux_text);
 928
 929 static const struct soc_enum tx_adc_mux5_chain_enum =
 930         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
 931                         adc_mux_text);
 932
 933 static const struct soc_enum tx_adc_mux6_chain_enum =
 934         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
 935                         adc_mux_text);
 936
 937 static const struct soc_enum tx_adc_mux7_chain_enum =
 938         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
 939                         adc_mux_text);
 940
 941 static const struct soc_enum tx_adc_mux8_chain_enum =
 942         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
 943                         adc_mux_text);
 944
 945 static const struct soc_enum tx_dmic_mux0_enum =
 946         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
 947                         dmic_mux_text);
 948
 949 static const struct soc_enum tx_dmic_mux1_enum =
 950         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
 951                         dmic_mux_text);
 952
 953 static const struct soc_enum tx_dmic_mux2_enum =
 954         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
 955                         dmic_mux_text);
 956
 957 static const struct soc_enum tx_dmic_mux3_enum =
 958         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
 959                         dmic_mux_text);
 960
 961 static const struct soc_enum tx_dmic_mux4_enum =
 962         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
 963                         dmic_mux_alt_text);
 964
 965 static const struct soc_enum tx_dmic_mux5_enum =
 966         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
 967                         dmic_mux_alt_text);
 968
 969 static const struct soc_enum tx_dmic_mux6_enum =
 970         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
 971                         dmic_mux_alt_text);
 972
 973 static const struct soc_enum tx_dmic_mux7_enum =
 974         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
 975                         dmic_mux_alt_text);
 976
 977 static const struct soc_enum tx_dmic_mux8_enum =
 978         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
 979                         dmic_mux_alt_text);
 980
 981 static const struct soc_enum tx_amic_mux0_enum =
 982         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
 983                         amic_mux_text);
 984
 985 static const struct soc_enum tx_amic_mux1_enum =
 986         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
 987                         amic_mux_text);
 988
 989 static const struct soc_enum tx_amic_mux2_enum =
 990         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
 991                         amic_mux_text);
 992
 993 static const struct soc_enum tx_amic_mux3_enum =
 994         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
 995                         amic_mux_text);
 996
 997 static const struct soc_enum tx_amic_mux4_enum =
 998         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
 999                         amic_mux_text);
1000
1001 static const struct soc_enum tx_amic_mux5_enum =
1002         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
1003                         amic_mux_text);
1004
1005 static const struct soc_enum tx_amic_mux6_enum =
1006         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
1007                         amic_mux_text);
1008
1009 static const struct soc_enum tx_amic_mux7_enum =
1010         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
1011                         amic_mux_text);
1012
1013 static const struct soc_enum tx_amic_mux8_enum =
1014         SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
1015                         amic_mux_text);
1016
1017 static const struct soc_enum sb_tx0_mux_enum =
1018         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
1019                         sb_tx0_mux_text);
1020
1021 static const struct soc_enum sb_tx1_mux_enum =
1022         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
1023                         sb_tx1_mux_text);
1024
1025 static const struct soc_enum sb_tx2_mux_enum =
1026         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
1027                         sb_tx2_mux_text);
1028
1029 static const struct soc_enum sb_tx3_mux_enum =
1030         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
1031                         sb_tx3_mux_text);
1032
1033 static const struct soc_enum sb_tx4_mux_enum =
1034         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
1035                         sb_tx4_mux_text);
1036
1037 static const struct soc_enum sb_tx5_mux_enum =
1038         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
1039                         sb_tx5_mux_text);
1040
1041 static const struct soc_enum sb_tx6_mux_enum =
1042         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
1043                         sb_tx6_mux_text);
1044
1045 static const struct soc_enum sb_tx7_mux_enum =
1046         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
1047                         sb_tx7_mux_text);
1048
1049 static const struct soc_enum sb_tx8_mux_enum =
1050         SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
1051                         sb_tx8_mux_text);
1052
1053 static const struct snd_kcontrol_new rx_int0_2_mux =
1054         SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
1055
1056 static const struct snd_kcontrol_new rx_int1_2_mux =
1057         SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
1058
1059 static const struct snd_kcontrol_new rx_int2_2_mux =
1060         SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
1061
1062 static const struct snd_kcontrol_new rx_int3_2_mux =
1063         SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
1064
1065 static const struct snd_kcontrol_new rx_int4_2_mux =
1066         SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
1067
1068 static const struct snd_kcontrol_new rx_int5_2_mux =
1069         SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
1070
1071 static const struct snd_kcontrol_new rx_int6_2_mux =
1072         SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
1073
1074 static const struct snd_kcontrol_new rx_int7_2_mux =
1075         SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
1076
1077 static const struct snd_kcontrol_new rx_int8_2_mux =
1078         SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
1079
1080 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
1081         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
1082
1083 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
1084         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
1085
1086 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
1087         SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
1088
1089 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
1090         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
1091
1092 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
1093         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
1094
1095 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
1096         SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
1097
1098 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
1099         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
1100
1101 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
1102         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
1103
1104 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
1105         SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
1106
1107 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
1108         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
1109
1110 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
1111         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
1112
1113 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
1114         SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
1115
1116 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
1117         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
1118
1119 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
1120         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
1121
1122 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
1123         SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
1124
1125 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
1126         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
1127
1128 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
1129         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
1130
1131 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
1132         SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
1133
1134 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
1135         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
1136
1137 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
1138         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
1139
1140 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
1141         SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
1142
1143 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
1144         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
1145
1146 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
1147         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
1148
1149 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
1150         SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
1151
1152 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
1153         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
1154
1155 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
1156         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
1157
1158 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
1159         SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
1160
1161 static const struct snd_kcontrol_new rx_int0_interp_mux =
1162         SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
1163
1164 static const struct snd_kcontrol_new rx_int1_interp_mux =
1165         SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
1166
1167 static const struct snd_kcontrol_new rx_int2_interp_mux =
1168         SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
1169
1170 static const struct snd_kcontrol_new rx_int3_interp_mux =
1171         SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
1172
1173 static const struct snd_kcontrol_new rx_int4_interp_mux =
1174         SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
1175
1176 static const struct snd_kcontrol_new rx_int5_interp_mux =
1177         SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
1178
1179 static const struct snd_kcontrol_new rx_int6_interp_mux =
1180         SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
1181
1182 static const struct snd_kcontrol_new rx_int7_interp_mux =
1183         SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
1184
1185 static const struct snd_kcontrol_new rx_int8_interp_mux =
1186         SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
1187
1188 static const struct snd_kcontrol_new tx_dmic_mux0 =
1189         SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
1190
1191 static const struct snd_kcontrol_new tx_dmic_mux1 =
1192         SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
1193
1194 static const struct snd_kcontrol_new tx_dmic_mux2 =
1195         SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
1196
1197 static const struct snd_kcontrol_new tx_dmic_mux3 =
1198         SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
1199
1200 static const struct snd_kcontrol_new tx_dmic_mux4 =
1201         SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
1202
1203 static const struct snd_kcontrol_new tx_dmic_mux5 =
1204         SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
1205
1206 static const struct snd_kcontrol_new tx_dmic_mux6 =
1207         SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
1208
1209 static const struct snd_kcontrol_new tx_dmic_mux7 =
1210         SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
1211
1212 static const struct snd_kcontrol_new tx_dmic_mux8 =
1213         SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
1214
1215 static const struct snd_kcontrol_new tx_amic_mux0 =
1216         SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
1217
1218 static const struct snd_kcontrol_new tx_amic_mux1 =
1219         SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
1220
1221 static const struct snd_kcontrol_new tx_amic_mux2 =
1222         SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
1223
1224 static const struct snd_kcontrol_new tx_amic_mux3 =
1225         SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
1226
1227 static const struct snd_kcontrol_new tx_amic_mux4 =
1228         SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
1229
1230 static const struct snd_kcontrol_new tx_amic_mux5 =
1231         SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
1232
1233 static const struct snd_kcontrol_new tx_amic_mux6 =
1234         SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
1235
1236 static const struct snd_kcontrol_new tx_amic_mux7 =
1237         SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
1238
1239 static const struct snd_kcontrol_new tx_amic_mux8 =
1240         SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
1241
1242 static const struct snd_kcontrol_new sb_tx0_mux =
1243         SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
1244
1245 static const struct snd_kcontrol_new sb_tx1_mux =
1246         SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
1247
1248 static const struct snd_kcontrol_new sb_tx2_mux =
1249         SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
1250
1251 static const struct snd_kcontrol_new sb_tx3_mux =
1252         SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
1253
1254 static const struct snd_kcontrol_new sb_tx4_mux =
1255         SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
1256
1257 static const struct snd_kcontrol_new sb_tx5_mux =
1258         SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
1259
1260 static const struct snd_kcontrol_new sb_tx6_mux =
1261         SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
1262
1263 static const struct snd_kcontrol_new sb_tx7_mux =
1264         SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
1265
1266 static const struct snd_kcontrol_new sb_tx8_mux =
1267         SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
1268
1269 static int slim_rx_mux_get(struct snd_kcontrol *kc,
1270                            struct snd_ctl_elem_value *ucontrol)
1271 {
1272         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1273         struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1274         u32 port_id = w->shift;
1275
1276         ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id];
1277
1278         return 0;
1279 }
1280
1281 static int slim_rx_mux_put(struct snd_kcontrol *kc,
1282                            struct snd_ctl_elem_value *ucontrol)
1283 {
1284         struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1285         struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1286         struct soc_enum *e = (struct soc_enum *)kc->private_value;
1287         struct snd_soc_dapm_update *update = NULL;
1288         u32 port_id = w->shift;
1289
1290         if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
1291                 return 0;
1292
1293         wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
1294
1295         /* Remove channel from any list it's in before adding it to a new one */
1296         list_del_init(&wcd->rx_chs[port_id].list);
1297
1298         switch (wcd->rx_port_value[port_id]) {
1299         case 0:
1300                 /* Channel already removed from lists. Nothing to do here */
1301                 break;
1302         case 1:
1303                 list_add_tail(&wcd->rx_chs[port_id].list,
1304                               &wcd->dai[AIF1_PB].slim_ch_list);
1305                 break;
1306         case 2:
1307                 list_add_tail(&wcd->rx_chs[port_id].list,
1308                               &wcd->dai[AIF2_PB].slim_ch_list);
1309                 break;
1310         case 3:
1311                 list_add_tail(&wcd->rx_chs[port_id].list,
1312                               &wcd->dai[AIF3_PB].slim_ch_list);
1313                 break;
1314         case 4:
1315                 list_add_tail(&wcd->rx_chs[port_id].list,
1316                               &wcd->dai[AIF4_PB].slim_ch_list);
1317                 break;
1318         default:
1319                 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]);
1320                 goto err;
1321         }
1322
1323         snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
1324                                       e, update);
1325
1326         return 0;
1327 err:
1328         return -EINVAL;
1329 }
1330
1331 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
1332                              struct snd_ctl_elem_value *ucontrol)
1333 {
1334
1335         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1336         struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
1337
1338         ucontrol->value.integer.value[0] = wcd->tx_port_value;
1339
1340         return 0;
1341 }
1342
1343 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
1344                              struct snd_ctl_elem_value *ucontrol)
1345 {
1346
1347         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1348         struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev);
1349         struct snd_soc_dapm_update *update = NULL;
1350         struct soc_mixer_control *mixer =
1351                         (struct soc_mixer_control *)kc->private_value;
1352         int enable = ucontrol->value.integer.value[0];
1353         int dai_id = widget->shift;
1354         int port_id = mixer->shift;
1355
1356         switch (dai_id) {
1357         case AIF1_CAP:
1358         case AIF2_CAP:
1359         case AIF3_CAP:
1360                 /* only add to the list if value not set */
1361                 if (enable && !(wcd->tx_port_value & BIT(port_id))) {
1362                         wcd->tx_port_value |= BIT(port_id);
1363                         list_add_tail(&wcd->tx_chs[port_id].list,
1364                                         &wcd->dai[dai_id].slim_ch_list);
1365                 } else if (!enable && (wcd->tx_port_value & BIT(port_id))) {
1366                         wcd->tx_port_value &= ~BIT(port_id);
1367                         list_del_init(&wcd->tx_chs[port_id].list);
1368                 }
1369                 break;
1370         default:
1371                 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id);
1372                 return -EINVAL;
1373         }
1374
1375         snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
1376
1377         return 0;
1378 }
1379
1380 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = {
1381         SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
1382                           slim_rx_mux_get, slim_rx_mux_put),
1383         SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
1384                           slim_rx_mux_get, slim_rx_mux_put),
1385         SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
1386                           slim_rx_mux_get, slim_rx_mux_put),
1387         SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
1388                           slim_rx_mux_get, slim_rx_mux_put),
1389         SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
1390                           slim_rx_mux_get, slim_rx_mux_put),
1391         SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
1392                           slim_rx_mux_get, slim_rx_mux_put),
1393         SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
1394                           slim_rx_mux_get, slim_rx_mux_put),
1395         SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
1396                           slim_rx_mux_get, slim_rx_mux_put),
1397 };
1398
1399 static const struct snd_kcontrol_new aif1_cap_mixer[] = {
1400         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1401                         slim_tx_mixer_get, slim_tx_mixer_put),
1402         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1403                         slim_tx_mixer_get, slim_tx_mixer_put),
1404         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1405                         slim_tx_mixer_get, slim_tx_mixer_put),
1406         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1407                         slim_tx_mixer_get, slim_tx_mixer_put),
1408         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1409                         slim_tx_mixer_get, slim_tx_mixer_put),
1410         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1411                         slim_tx_mixer_get, slim_tx_mixer_put),
1412         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1413                         slim_tx_mixer_get, slim_tx_mixer_put),
1414         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1415                         slim_tx_mixer_get, slim_tx_mixer_put),
1416         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1417                         slim_tx_mixer_get, slim_tx_mixer_put),
1418         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1419                         slim_tx_mixer_get, slim_tx_mixer_put),
1420         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1421                         slim_tx_mixer_get, slim_tx_mixer_put),
1422         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1423                         slim_tx_mixer_get, slim_tx_mixer_put),
1424         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1425                         slim_tx_mixer_get, slim_tx_mixer_put),
1426 };
1427
1428 static const struct snd_kcontrol_new aif2_cap_mixer[] = {
1429         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1430                         slim_tx_mixer_get, slim_tx_mixer_put),
1431         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1432                         slim_tx_mixer_get, slim_tx_mixer_put),
1433         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1434                         slim_tx_mixer_get, slim_tx_mixer_put),
1435         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1436                         slim_tx_mixer_get, slim_tx_mixer_put),
1437         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1438                         slim_tx_mixer_get, slim_tx_mixer_put),
1439         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1440                         slim_tx_mixer_get, slim_tx_mixer_put),
1441         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1442                         slim_tx_mixer_get, slim_tx_mixer_put),
1443         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1444                         slim_tx_mixer_get, slim_tx_mixer_put),
1445         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1446                         slim_tx_mixer_get, slim_tx_mixer_put),
1447         SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1448                         slim_tx_mixer_get, slim_tx_mixer_put),
1449         SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1450                         slim_tx_mixer_get, slim_tx_mixer_put),
1451         SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1452                         slim_tx_mixer_get, slim_tx_mixer_put),
1453         SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1454                         slim_tx_mixer_get, slim_tx_mixer_put),
1455 };
1456
1457 static const struct snd_kcontrol_new aif3_cap_mixer[] = {
1458         SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1459                         slim_tx_mixer_get, slim_tx_mixer_put),
1460         SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1461                         slim_tx_mixer_get, slim_tx_mixer_put),
1462         SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1463                         slim_tx_mixer_get, slim_tx_mixer_put),
1464         SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1465                         slim_tx_mixer_get, slim_tx_mixer_put),
1466         SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1467                         slim_tx_mixer_get, slim_tx_mixer_put),
1468         SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1469                         slim_tx_mixer_get, slim_tx_mixer_put),
1470         SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1471                         slim_tx_mixer_get, slim_tx_mixer_put),
1472         SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1473                         slim_tx_mixer_get, slim_tx_mixer_put),
1474         SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1475                         slim_tx_mixer_get, slim_tx_mixer_put),
1476 };
1477
1478 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc,
1479                                 struct snd_ctl_elem_value *ucontrol)
1480 {
1481         struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1482         struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1483         struct soc_enum *e = (struct soc_enum *)kc->private_value;
1484         unsigned int val, reg, sel;
1485
1486         val = ucontrol->value.enumerated.item[0];
1487
1488         switch (e->reg) {
1489         case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
1490                 reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
1491                 break;
1492         case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
1493                 reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
1494                 break;
1495         case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
1496                 reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
1497                 break;
1498         case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
1499                 reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
1500                 break;
1501         case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
1502                 reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
1503                 break;
1504         case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
1505                 reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
1506                 break;
1507         case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
1508                 reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
1509                 break;
1510         case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
1511                 reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
1512                 break;
1513         case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
1514                 reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
1515                 break;
1516         default:
1517                 return -EINVAL;
1518         }
1519
1520         /* AMIC: 0, DMIC: 1 */
1521         sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL;
1522         snd_soc_component_update_bits(component, reg,
1523                                       WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK,
1524                                       sel);
1525
1526         return snd_soc_dapm_put_enum_double(kc, ucontrol);
1527 }
1528
1529 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc,
1530                                  struct snd_ctl_elem_value *ucontrol)
1531 {
1532         struct soc_enum *e = (struct soc_enum *)kc->private_value;
1533         struct snd_soc_component *component;
1534         int reg, val;
1535
1536         component = snd_soc_dapm_kcontrol_component(kc);
1537         val = ucontrol->value.enumerated.item[0];
1538
1539         if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
1540                 reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
1541         else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
1542                 reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
1543         else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
1544                 reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
1545         else
1546                 return -EINVAL;
1547
1548         /* Set Look Ahead Delay */
1549         snd_soc_component_update_bits(component, reg,
1550                                 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK,
1551                                 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0);
1552         /* Set DEM INP Select */
1553         return snd_soc_dapm_put_enum_double(kc, ucontrol);
1554 }
1555
1556 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1557         SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
1558                           snd_soc_dapm_get_enum_double,
1559                           wcd9335_int_dem_inp_mux_put);
1560
1561 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1562         SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
1563                           snd_soc_dapm_get_enum_double,
1564                           wcd9335_int_dem_inp_mux_put);
1565
1566 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
1567         SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
1568                           snd_soc_dapm_get_enum_double,
1569                           wcd9335_int_dem_inp_mux_put);
1570
1571 static const struct snd_kcontrol_new tx_adc_mux0 =
1572         SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
1573                           snd_soc_dapm_get_enum_double,
1574                           wcd9335_put_dec_enum);
1575
1576 static const struct snd_kcontrol_new tx_adc_mux1 =
1577         SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
1578                           snd_soc_dapm_get_enum_double,
1579                           wcd9335_put_dec_enum);
1580
1581 static const struct snd_kcontrol_new tx_adc_mux2 =
1582         SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
1583                           snd_soc_dapm_get_enum_double,
1584                           wcd9335_put_dec_enum);
1585
1586 static const struct snd_kcontrol_new tx_adc_mux3 =
1587         SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
1588                           snd_soc_dapm_get_enum_double,
1589                           wcd9335_put_dec_enum);
1590
1591 static const struct snd_kcontrol_new tx_adc_mux4 =
1592         SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
1593                           snd_soc_dapm_get_enum_double,
1594                           wcd9335_put_dec_enum);
1595
1596 static const struct snd_kcontrol_new tx_adc_mux5 =
1597         SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
1598                           snd_soc_dapm_get_enum_double,
1599                           wcd9335_put_dec_enum);
1600
1601 static const struct snd_kcontrol_new tx_adc_mux6 =
1602         SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
1603                           snd_soc_dapm_get_enum_double,
1604                           wcd9335_put_dec_enum);
1605
1606 static const struct snd_kcontrol_new tx_adc_mux7 =
1607         SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
1608                           snd_soc_dapm_get_enum_double,
1609                           wcd9335_put_dec_enum);
1610
1611 static const struct snd_kcontrol_new tx_adc_mux8 =
1612         SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
1613                           snd_soc_dapm_get_enum_double,
1614                           wcd9335_put_dec_enum);
1615
1616 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1617                                              int rate_val,
1618                                              u32 rate)
1619 {
1620         struct snd_soc_component *component = dai->component;
1621         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
1622         struct wcd9335_slim_ch *ch;
1623         int val, j;
1624
1625         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1626                 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1627                         val = snd_soc_component_read(component,
1628                                         WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1629                                         WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1630
1631                         if (val == (ch->shift + INTn_2_INP_SEL_RX0))
1632                                 snd_soc_component_update_bits(component,
1633                                                 WCD9335_CDC_RX_PATH_MIX_CTL(j),
1634                                                 WCD9335_CDC_MIX_PCM_RATE_MASK,
1635                                                 rate_val);
1636                 }
1637         }
1638
1639         return 0;
1640 }
1641
1642 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1643                                               u8 rate_val,
1644                                               u32 rate)
1645 {
1646         struct snd_soc_component *comp = dai->component;
1647         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
1648         struct wcd9335_slim_ch *ch;
1649         u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1650         int inp, j;
1651
1652         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1653                 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0;
1654                 /*
1655                  * Loop through all interpolator MUX inputs and find out
1656                  * to which interpolator input, the slim rx port
1657                  * is connected
1658                  */
1659                 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1660                         cfg0 = snd_soc_component_read(comp,
1661                                         WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1662                         cfg1 = snd_soc_component_read(comp,
1663                                         WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1664
1665                         inp0_sel = cfg0 &
1666                                  WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1667                         inp1_sel = (cfg0 >> 4) &
1668                                  WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1669                         inp2_sel = (cfg1 >> 4) &
1670                                  WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1671
1672                         if ((inp0_sel == inp) ||  (inp1_sel == inp) ||
1673                             (inp2_sel == inp)) {
1674                                 /* rate is in Hz */
1675                                 if ((j == 0) && (rate == 44100))
1676                                         dev_info(wcd->dev,
1677                                                 "Cannot set 44.1KHz on INT0\n");
1678                                 else
1679                                         snd_soc_component_update_bits(comp,
1680                                                 WCD9335_CDC_RX_PATH_CTL(j),
1681                                                 WCD9335_CDC_MIX_PCM_RATE_MASK,
1682                                                 rate_val);
1683                         }
1684                 }
1685         }
1686
1687         return 0;
1688 }
1689
1690 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate)
1691 {
1692         int i;
1693
1694         /* set mixing path rate */
1695         for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) {
1696                 if (rate == int_mix_rate_val[i].rate) {
1697                         wcd9335_set_mix_interpolator_rate(dai,
1698                                         int_mix_rate_val[i].rate_val, rate);
1699                         break;
1700                 }
1701         }
1702
1703         /* set primary path sample rate */
1704         for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) {
1705                 if (rate == int_prim_rate_val[i].rate) {
1706                         wcd9335_set_prim_interpolator_rate(dai,
1707                                         int_prim_rate_val[i].rate_val, rate);
1708                         break;
1709                 }
1710         }
1711
1712         return 0;
1713 }
1714
1715 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd,
1716                                  struct wcd_slim_codec_dai_data *dai_data,
1717                                  int direction)
1718 {
1719         struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1720         struct slim_stream_config *cfg = &dai_data->sconfig;
1721         struct wcd9335_slim_ch *ch;
1722         u16 payload = 0;
1723         int ret, i;
1724
1725         cfg->ch_count = 0;
1726         cfg->direction = direction;
1727         cfg->port_mask = 0;
1728
1729         /* Configure slave interface device */
1730         list_for_each_entry(ch, slim_ch_list, list) {
1731                 cfg->ch_count++;
1732                 payload |= 1 << ch->shift;
1733                 cfg->port_mask |= BIT(ch->port);
1734         }
1735
1736         cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1737         if (!cfg->chs)
1738                 return -ENOMEM;
1739
1740         i = 0;
1741         list_for_each_entry(ch, slim_ch_list, list) {
1742                 cfg->chs[i++] = ch->ch_num;
1743                 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1744                         /* write to interface device */
1745                         ret = regmap_write(wcd->if_regmap,
1746                                 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1747                                 payload);
1748
1749                         if (ret < 0)
1750                                 goto err;
1751
1752                         /* configure the slave port for water mark and enable*/
1753                         ret = regmap_write(wcd->if_regmap,
1754                                         WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port),
1755                                         WCD9335_SLIM_WATER_MARK_VAL);
1756                         if (ret < 0)
1757                                 goto err;
1758                 } else {
1759                         ret = regmap_write(wcd->if_regmap,
1760                                 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1761                                 payload & 0x00FF);
1762                         if (ret < 0)
1763                                 goto err;
1764
1765                         /* ports 8,9 */
1766                         ret = regmap_write(wcd->if_regmap,
1767                                 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1768                                 (payload & 0xFF00)>>8);
1769                         if (ret < 0)
1770                                 goto err;
1771
1772                         /* configure the slave port for water mark and enable*/
1773                         ret = regmap_write(wcd->if_regmap,
1774                                         WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port),
1775                                         WCD9335_SLIM_WATER_MARK_VAL);
1776
1777                         if (ret < 0)
1778                                 goto err;
1779                 }
1780         }
1781
1782         dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM");
1783
1784         return 0;
1785
1786 err:
1787         dev_err(wcd->dev, "Error Setting slim hw params\n");
1788         kfree(cfg->chs);
1789         cfg->chs = NULL;
1790
1791         return ret;
1792 }
1793
1794 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai,
1795                                       u8 rate_val, u32 rate)
1796 {
1797         struct snd_soc_component *comp = dai->component;
1798         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
1799         u8 shift = 0, shift_val = 0, tx_mux_sel;
1800         struct wcd9335_slim_ch *ch;
1801         int tx_port, tx_port_reg;
1802         int decimator = -1;
1803
1804         list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1805                 tx_port = ch->port;
1806                 if ((tx_port == 12) || (tx_port >= 14)) {
1807                         dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1808                                 tx_port, dai->id);
1809                         return -EINVAL;
1810                 }
1811                 /* Find the SB TX MUX input - which decimator is connected */
1812                 if (tx_port < 4) {
1813                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
1814                         shift = (tx_port << 1);
1815                         shift_val = 0x03;
1816                 } else if ((tx_port >= 4) && (tx_port < 8)) {
1817                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
1818                         shift = ((tx_port - 4) << 1);
1819                         shift_val = 0x03;
1820                 } else if ((tx_port >= 8) && (tx_port < 11)) {
1821                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
1822                         shift = ((tx_port - 8) << 1);
1823                         shift_val = 0x03;
1824                 } else if (tx_port == 11) {
1825                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1826                         shift = 0;
1827                         shift_val = 0x0F;
1828                 } else if (tx_port == 13) {
1829                         tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1830                         shift = 4;
1831                         shift_val = 0x03;
1832                 } else {
1833                         return -EINVAL;
1834                 }
1835
1836                 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1837                                                       (shift_val << shift);
1838
1839                 tx_mux_sel = tx_mux_sel >> shift;
1840                 if (tx_port <= 8) {
1841                         if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1842                                 decimator = tx_port;
1843                 } else if (tx_port <= 10) {
1844                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1845                                 decimator = ((tx_port == 9) ? 7 : 6);
1846                 } else if (tx_port == 11) {
1847                         if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1848                                 decimator = tx_mux_sel - 1;
1849                 } else if (tx_port == 13) {
1850                         if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1851                                 decimator = 5;
1852                 }
1853
1854                 if (decimator >= 0) {
1855                         snd_soc_component_update_bits(comp,
1856                                         WCD9335_CDC_TX_PATH_CTL(decimator),
1857                                         WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1858                                         rate_val);
1859                 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
1860                         /* Check if the TX Mux input is RX MIX TXn */
1861                         dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n",
1862                                 tx_port, tx_port);
1863                 } else {
1864                         dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n",
1865                                 decimator);
1866                         return -EINVAL;
1867                 }
1868         }
1869
1870         return 0;
1871 }
1872
1873 static int wcd9335_hw_params(struct snd_pcm_substream *substream,
1874                            struct snd_pcm_hw_params *params,
1875                            struct snd_soc_dai *dai)
1876 {
1877         struct wcd9335_codec *wcd;
1878         int ret, tx_fs_rate = 0;
1879
1880         wcd = snd_soc_component_get_drvdata(dai->component);
1881
1882         switch (substream->stream) {
1883         case SNDRV_PCM_STREAM_PLAYBACK:
1884                 ret = wcd9335_set_interpolator_rate(dai, params_rate(params));
1885                 if (ret) {
1886                         dev_err(wcd->dev, "cannot set sample rate: %u\n",
1887                                 params_rate(params));
1888                         return ret;
1889                 }
1890                 switch (params_width(params)) {
1891                 case 16 ... 24:
1892                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1893                         break;
1894                 default:
1895                         dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1896                                 __func__, params_width(params));
1897                         return -EINVAL;
1898                 }
1899                 break;
1900
1901         case SNDRV_PCM_STREAM_CAPTURE:
1902                 switch (params_rate(params)) {
1903                 case 8000:
1904                         tx_fs_rate = 0;
1905                         break;
1906                 case 16000:
1907                         tx_fs_rate = 1;
1908                         break;
1909                 case 32000:
1910                         tx_fs_rate = 3;
1911                         break;
1912                 case 48000:
1913                         tx_fs_rate = 4;
1914                         break;
1915                 case 96000:
1916                         tx_fs_rate = 5;
1917                         break;
1918                 case 192000:
1919                         tx_fs_rate = 6;
1920                         break;
1921                 case 384000:
1922                         tx_fs_rate = 7;
1923                         break;
1924                 default:
1925                         dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n",
1926                                 __func__, params_rate(params));
1927                         return -EINVAL;
1928
1929                 }
1930
1931                 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate,
1932                                                 params_rate(params));
1933                 if (ret < 0) {
1934                         dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1935                         return ret;
1936                 }
1937                 switch (params_width(params)) {
1938                 case 16 ... 32:
1939                         wcd->dai[dai->id].sconfig.bps = params_width(params);
1940                         break;
1941                 default:
1942                         dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1943                                 __func__, params_width(params));
1944                         return -EINVAL;
1945                 }
1946                 break;
1947         default:
1948                 dev_err(wcd->dev, "Invalid stream type %d\n",
1949                         substream->stream);
1950                 return -EINVAL;
1951         }
1952
1953         wcd->dai[dai->id].sconfig.rate = params_rate(params);
1954         wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1955
1956         return 0;
1957 }
1958
1959 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd,
1960                            struct snd_soc_dai *dai)
1961 {
1962         struct wcd_slim_codec_dai_data *dai_data;
1963         struct wcd9335_codec *wcd;
1964         struct slim_stream_config *cfg;
1965
1966         wcd = snd_soc_component_get_drvdata(dai->component);
1967
1968         dai_data = &wcd->dai[dai->id];
1969
1970         switch (cmd) {
1971         case SNDRV_PCM_TRIGGER_START:
1972         case SNDRV_PCM_TRIGGER_RESUME:
1973         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1974                 cfg = &dai_data->sconfig;
1975                 slim_stream_prepare(dai_data->sruntime, cfg);
1976                 slim_stream_enable(dai_data->sruntime);
1977                 break;
1978         case SNDRV_PCM_TRIGGER_STOP:
1979         case SNDRV_PCM_TRIGGER_SUSPEND:
1980         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1981                 slim_stream_unprepare(dai_data->sruntime);
1982                 slim_stream_disable(dai_data->sruntime);
1983                 break;
1984         default:
1985                 break;
1986         }
1987
1988         return 0;
1989 }
1990
1991 static int wcd9335_set_channel_map(struct snd_soc_dai *dai,
1992                                    unsigned int tx_num, unsigned int *tx_slot,
1993                                    unsigned int rx_num, unsigned int *rx_slot)
1994 {
1995         struct wcd9335_codec *wcd;
1996         int i;
1997
1998         wcd = snd_soc_component_get_drvdata(dai->component);
1999
2000         if (!tx_slot || !rx_slot) {
2001                 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
2002                         tx_slot, rx_slot);
2003                 return -EINVAL;
2004         }
2005
2006         wcd->num_rx_port = rx_num;
2007         for (i = 0; i < rx_num; i++) {
2008                 wcd->rx_chs[i].ch_num = rx_slot[i];
2009                 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
2010         }
2011
2012         wcd->num_tx_port = tx_num;
2013         for (i = 0; i < tx_num; i++) {
2014                 wcd->tx_chs[i].ch_num = tx_slot[i];
2015                 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
2016         }
2017
2018         return 0;
2019 }
2020
2021 static int wcd9335_get_channel_map(struct snd_soc_dai *dai,
2022                                    unsigned int *tx_num, unsigned int *tx_slot,
2023                                    unsigned int *rx_num, unsigned int *rx_slot)
2024 {
2025         struct wcd9335_slim_ch *ch;
2026         struct wcd9335_codec *wcd;
2027         int i = 0;
2028
2029         wcd = snd_soc_component_get_drvdata(dai->component);
2030
2031         switch (dai->id) {
2032         case AIF1_PB:
2033         case AIF2_PB:
2034         case AIF3_PB:
2035         case AIF4_PB:
2036                 if (!rx_slot || !rx_num) {
2037                         dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
2038                                 rx_slot, rx_num);
2039                         return -EINVAL;
2040                 }
2041
2042                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2043                         rx_slot[i++] = ch->ch_num;
2044
2045                 *rx_num = i;
2046                 break;
2047         case AIF1_CAP:
2048         case AIF2_CAP:
2049         case AIF3_CAP:
2050                 if (!tx_slot || !tx_num) {
2051                         dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
2052                                 tx_slot, tx_num);
2053                         return -EINVAL;
2054                 }
2055                 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2056                         tx_slot[i++] = ch->ch_num;
2057
2058                 *tx_num = i;
2059                 break;
2060         default:
2061                 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2062                 break;
2063         }
2064
2065         return 0;
2066 }
2067
2068 static const struct snd_soc_dai_ops wcd9335_dai_ops = {
2069         .hw_params = wcd9335_hw_params,
2070         .trigger = wcd9335_trigger,
2071         .set_channel_map = wcd9335_set_channel_map,
2072         .get_channel_map = wcd9335_get_channel_map,
2073 };
2074
2075 static struct snd_soc_dai_driver wcd9335_slim_dais[] = {
2076         [0] = {
2077                 .name = "wcd9335_rx1",
2078                 .id = AIF1_PB,
2079                 .playback = {
2080                         .stream_name = "AIF1 Playback",
2081                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2082                                  SNDRV_PCM_RATE_384000,
2083                         .formats = WCD9335_FORMATS_S16_S24_LE,
2084                         .rate_max = 384000,
2085                         .rate_min = 8000,
2086                         .channels_min = 1,
2087                         .channels_max = 2,
2088                 },
2089                 .ops = &wcd9335_dai_ops,
2090         },
2091         [1] = {
2092                 .name = "wcd9335_tx1",
2093                 .id = AIF1_CAP,
2094                 .capture = {
2095                         .stream_name = "AIF1 Capture",
2096                         .rates = WCD9335_RATES_MASK,
2097                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2098                         .rate_min = 8000,
2099                         .rate_max = 192000,
2100                         .channels_min = 1,
2101                         .channels_max = 4,
2102                 },
2103                 .ops = &wcd9335_dai_ops,
2104         },
2105         [2] = {
2106                 .name = "wcd9335_rx2",
2107                 .id = AIF2_PB,
2108                 .playback = {
2109                         .stream_name = "AIF2 Playback",
2110                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2111                                  SNDRV_PCM_RATE_384000,
2112                         .formats = WCD9335_FORMATS_S16_S24_LE,
2113                         .rate_min = 8000,
2114                         .rate_max = 384000,
2115                         .channels_min = 1,
2116                         .channels_max = 2,
2117                 },
2118                 .ops = &wcd9335_dai_ops,
2119         },
2120         [3] = {
2121                 .name = "wcd9335_tx2",
2122                 .id = AIF2_CAP,
2123                 .capture = {
2124                         .stream_name = "AIF2 Capture",
2125                         .rates = WCD9335_RATES_MASK,
2126                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2127                         .rate_min = 8000,
2128                         .rate_max = 192000,
2129                         .channels_min = 1,
2130                         .channels_max = 4,
2131                 },
2132                 .ops = &wcd9335_dai_ops,
2133         },
2134         [4] = {
2135                 .name = "wcd9335_rx3",
2136                 .id = AIF3_PB,
2137                 .playback = {
2138                         .stream_name = "AIF3 Playback",
2139                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2140                                  SNDRV_PCM_RATE_384000,
2141                         .formats = WCD9335_FORMATS_S16_S24_LE,
2142                         .rate_min = 8000,
2143                         .rate_max = 384000,
2144                         .channels_min = 1,
2145                         .channels_max = 2,
2146                 },
2147                 .ops = &wcd9335_dai_ops,
2148         },
2149         [5] = {
2150                 .name = "wcd9335_tx3",
2151                 .id = AIF3_CAP,
2152                 .capture = {
2153                         .stream_name = "AIF3 Capture",
2154                         .rates = WCD9335_RATES_MASK,
2155                         .formats = SNDRV_PCM_FMTBIT_S16_LE,
2156                         .rate_min = 8000,
2157                         .rate_max = 192000,
2158                         .channels_min = 1,
2159                         .channels_max = 4,
2160                 },
2161                 .ops = &wcd9335_dai_ops,
2162         },
2163         [6] = {
2164                 .name = "wcd9335_rx4",
2165                 .id = AIF4_PB,
2166                 .playback = {
2167                         .stream_name = "AIF4 Playback",
2168                         .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2169                                  SNDRV_PCM_RATE_384000,
2170                         .formats = WCD9335_FORMATS_S16_S24_LE,
2171                         .rate_min = 8000,
2172                         .rate_max = 384000,
2173                         .channels_min = 1,
2174                         .channels_max = 2,
2175                 },
2176                 .ops = &wcd9335_dai_ops,
2177         },
2178 };
2179
2180 static int wcd9335_get_compander(struct snd_kcontrol *kc,
2181                                struct snd_ctl_elem_value *ucontrol)
2182 {
2183
2184         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2185         int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2186         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2187
2188         ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2189         return 0;
2190 }
2191
2192 static int wcd9335_set_compander(struct snd_kcontrol *kc,
2193                                  struct snd_ctl_elem_value *ucontrol)
2194 {
2195         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2196         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2197         int comp = ((struct soc_mixer_control *) kc->private_value)->shift;
2198         int value = ucontrol->value.integer.value[0];
2199         int sel;
2200
2201         wcd->comp_enabled[comp] = value;
2202         sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER :
2203                 WCD9335_HPH_GAIN_SRC_SEL_REGISTER;
2204
2205         /* Any specific register configuration for compander */
2206         switch (comp) {
2207         case COMPANDER_1:
2208                 /* Set Gain Source Select based on compander enable/disable */
2209                 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
2210                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2211                 break;
2212         case COMPANDER_2:
2213                 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
2214                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2215                 break;
2216         case COMPANDER_5:
2217                 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN,
2218                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2219                 break;
2220         case COMPANDER_6:
2221                 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN,
2222                                       WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2223                 break;
2224         default:
2225                 break;
2226         }
2227
2228         return 0;
2229 }
2230
2231 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc,
2232                                  struct snd_ctl_elem_value *ucontrol)
2233 {
2234         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2235         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2236
2237         ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2238
2239         return 0;
2240 }
2241
2242 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc,
2243                                  struct snd_ctl_elem_value *ucontrol)
2244 {
2245         struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2246         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2247         u32 mode_val;
2248
2249         mode_val = ucontrol->value.enumerated.item[0];
2250
2251         if (mode_val == 0) {
2252                 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2253                 mode_val = CLS_H_HIFI;
2254         }
2255         wcd->hph_mode = mode_val;
2256
2257         return 0;
2258 }
2259
2260 static const struct snd_kcontrol_new wcd9335_snd_controls[] = {
2261         /* -84dB min - 40dB max */
2262         SOC_SINGLE_SX_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
2263                 0, -84, 40, digital_gain),
2264         SOC_SINGLE_SX_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
2265                 0, -84, 40, digital_gain),
2266         SOC_SINGLE_SX_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
2267                 0, -84, 40, digital_gain),
2268         SOC_SINGLE_SX_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
2269                 0, -84, 40, digital_gain),
2270         SOC_SINGLE_SX_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
2271                 0, -84, 40, digital_gain),
2272         SOC_SINGLE_SX_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
2273                 0, -84, 40, digital_gain),
2274         SOC_SINGLE_SX_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
2275                 0, -84, 40, digital_gain),
2276         SOC_SINGLE_SX_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
2277                 0, -84, 40, digital_gain),
2278         SOC_SINGLE_SX_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
2279                 0, -84, 40, digital_gain),
2280         SOC_SINGLE_SX_TLV("RX0 Mix Digital Volume",
2281                           WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
2282                           0, -84, 40, digital_gain),
2283         SOC_SINGLE_SX_TLV("RX1 Mix Digital Volume",
2284                           WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
2285                           0, -84, 40, digital_gain),
2286         SOC_SINGLE_SX_TLV("RX2 Mix Digital Volume",
2287                           WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
2288                           0, -84, 40, digital_gain),
2289         SOC_SINGLE_SX_TLV("RX3 Mix Digital Volume",
2290                           WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
2291                           0, -84, 40, digital_gain),
2292         SOC_SINGLE_SX_TLV("RX4 Mix Digital Volume",
2293                           WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
2294                           0, -84, 40, digital_gain),
2295         SOC_SINGLE_SX_TLV("RX5 Mix Digital Volume",
2296                           WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
2297                           0, -84, 40, digital_gain),
2298         SOC_SINGLE_SX_TLV("RX6 Mix Digital Volume",
2299                           WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
2300                           0, -84, 40, digital_gain),
2301         SOC_SINGLE_SX_TLV("RX7 Mix Digital Volume",
2302                           WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
2303                           0, -84, 40, digital_gain),
2304         SOC_SINGLE_SX_TLV("RX8 Mix Digital Volume",
2305                           WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
2306                           0, -84, 40, digital_gain),
2307         SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
2308         SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
2309         SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
2310         SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
2311         SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
2312         SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
2313         SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
2314         SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
2315         SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
2316         SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
2317         SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
2318         SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
2319         SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
2320         SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
2321         SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
2322         SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
2323         SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
2324         SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
2325         SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
2326                        wcd9335_get_compander, wcd9335_set_compander),
2327         SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
2328                        wcd9335_get_compander, wcd9335_set_compander),
2329         SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
2330                        wcd9335_get_compander, wcd9335_set_compander),
2331         SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
2332                        wcd9335_get_compander, wcd9335_set_compander),
2333         SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
2334                        wcd9335_get_compander, wcd9335_set_compander),
2335         SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
2336                        wcd9335_get_compander, wcd9335_set_compander),
2337         SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
2338                        wcd9335_get_compander, wcd9335_set_compander),
2339         SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
2340                        wcd9335_get_compander, wcd9335_set_compander),
2341         SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2342                        wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put),
2343
2344         /* Gain Controls */
2345         SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1,
2346                 ear_pa_gain),
2347         SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
2348                 line_gain),
2349         SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
2350                 line_gain),
2351         SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
2352                         3, 16, 1, line_gain),
2353         SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
2354                         3, 16, 1, line_gain),
2355         SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
2356                         line_gain),
2357         SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
2358                         line_gain),
2359
2360         SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
2361                         analog_gain),
2362         SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
2363                         analog_gain),
2364         SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
2365                         analog_gain),
2366         SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
2367                         analog_gain),
2368         SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
2369                         analog_gain),
2370         SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
2371                         analog_gain),
2372
2373         SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
2374         SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
2375         SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
2376         SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
2377         SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
2378         SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
2379         SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
2380         SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
2381         SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
2382 };
2383
2384 static const struct snd_soc_dapm_route wcd9335_audio_map[] = {
2385         {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
2386         {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
2387         {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
2388         {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
2389         {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
2390         {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
2391         {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
2392         {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
2393
2394         {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
2395         {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
2396         {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
2397         {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
2398         {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
2399         {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
2400         {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
2401         {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
2402
2403         {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
2404         {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
2405         {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
2406         {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
2407         {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
2408         {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
2409         {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
2410         {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
2411
2412         {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
2413         {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
2414         {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
2415         {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
2416         {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
2417         {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
2418         {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
2419         {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
2420
2421         {"SLIM RX0", NULL, "SLIM RX0 MUX"},
2422         {"SLIM RX1", NULL, "SLIM RX1 MUX"},
2423         {"SLIM RX2", NULL, "SLIM RX2 MUX"},
2424         {"SLIM RX3", NULL, "SLIM RX3 MUX"},
2425         {"SLIM RX4", NULL, "SLIM RX4 MUX"},
2426         {"SLIM RX5", NULL, "SLIM RX5 MUX"},
2427         {"SLIM RX6", NULL, "SLIM RX6 MUX"},
2428         {"SLIM RX7", NULL, "SLIM RX7 MUX"},
2429
2430         WCD9335_INTERPOLATOR_PATH(0),
2431         WCD9335_INTERPOLATOR_PATH(1),
2432         WCD9335_INTERPOLATOR_PATH(2),
2433         WCD9335_INTERPOLATOR_PATH(3),
2434         WCD9335_INTERPOLATOR_PATH(4),
2435         WCD9335_INTERPOLATOR_PATH(5),
2436         WCD9335_INTERPOLATOR_PATH(6),
2437         WCD9335_INTERPOLATOR_PATH(7),
2438         WCD9335_INTERPOLATOR_PATH(8),
2439
2440         /* EAR PA */
2441         {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
2442         {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
2443         {"RX INT0 DAC", NULL, "RX_BIAS"},
2444         {"EAR PA", NULL, "RX INT0 DAC"},
2445         {"EAR", NULL, "EAR PA"},
2446
2447         /* HPHL */
2448         {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
2449         {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
2450         {"RX INT1 DAC", NULL, "RX_BIAS"},
2451         {"HPHL PA", NULL, "RX INT1 DAC"},
2452         {"HPHL", NULL, "HPHL PA"},
2453
2454         /* HPHR */
2455         {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
2456         {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
2457         {"RX INT2 DAC", NULL, "RX_BIAS"},
2458         {"HPHR PA", NULL, "RX INT2 DAC"},
2459         {"HPHR", NULL, "HPHR PA"},
2460
2461         /* LINEOUT1 */
2462         {"RX INT3 DAC", NULL, "RX INT3 INTERP"},
2463         {"RX INT3 DAC", NULL, "RX_BIAS"},
2464         {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
2465         {"LINEOUT1", NULL, "LINEOUT1 PA"},
2466
2467         /* LINEOUT2 */
2468         {"RX INT4 DAC", NULL, "RX INT4 INTERP"},
2469         {"RX INT4 DAC", NULL, "RX_BIAS"},
2470         {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
2471         {"LINEOUT2", NULL, "LINEOUT2 PA"},
2472
2473         /* LINEOUT3 */
2474         {"RX INT5 DAC", NULL, "RX INT5 INTERP"},
2475         {"RX INT5 DAC", NULL, "RX_BIAS"},
2476         {"LINEOUT3 PA", NULL, "RX INT5 DAC"},
2477         {"LINEOUT3", NULL, "LINEOUT3 PA"},
2478
2479         /* LINEOUT4 */
2480         {"RX INT6 DAC", NULL, "RX INT6 INTERP"},
2481         {"RX INT6 DAC", NULL, "RX_BIAS"},
2482         {"LINEOUT4 PA", NULL, "RX INT6 DAC"},
2483         {"LINEOUT4", NULL, "LINEOUT4 PA"},
2484
2485         /* SLIMBUS Connections */
2486         {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
2487         {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
2488         {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
2489
2490         /* ADC Mux */
2491         WCD9335_ADC_MUX_PATH(0),
2492         WCD9335_ADC_MUX_PATH(1),
2493         WCD9335_ADC_MUX_PATH(2),
2494         WCD9335_ADC_MUX_PATH(3),
2495         WCD9335_ADC_MUX_PATH(4),
2496         WCD9335_ADC_MUX_PATH(5),
2497         WCD9335_ADC_MUX_PATH(6),
2498         WCD9335_ADC_MUX_PATH(7),
2499         WCD9335_ADC_MUX_PATH(8),
2500
2501         /* ADC Connections */
2502         {"ADC1", NULL, "AMIC1"},
2503         {"ADC2", NULL, "AMIC2"},
2504         {"ADC3", NULL, "AMIC3"},
2505         {"ADC4", NULL, "AMIC4"},
2506         {"ADC5", NULL, "AMIC5"},
2507         {"ADC6", NULL, "AMIC6"},
2508 };
2509
2510 static int wcd9335_micbias_control(struct snd_soc_component *component,
2511                                    int micb_num, int req, bool is_dapm)
2512 {
2513         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component);
2514         int micb_index = micb_num - 1;
2515         u16 micb_reg;
2516
2517         if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) {
2518                 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n",
2519                         micb_index);
2520                 return -EINVAL;
2521         }
2522
2523         switch (micb_num) {
2524         case MIC_BIAS_1:
2525                 micb_reg = WCD9335_ANA_MICB1;
2526                 break;
2527         case MIC_BIAS_2:
2528                 micb_reg = WCD9335_ANA_MICB2;
2529                 break;
2530         case MIC_BIAS_3:
2531                 micb_reg = WCD9335_ANA_MICB3;
2532                 break;
2533         case MIC_BIAS_4:
2534                 micb_reg = WCD9335_ANA_MICB4;
2535                 break;
2536         default:
2537                 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2538                         __func__, micb_num);
2539                 return -EINVAL;
2540         }
2541
2542         switch (req) {
2543         case MICB_PULLUP_ENABLE:
2544                 wcd->pullup_ref[micb_index]++;
2545                 if ((wcd->pullup_ref[micb_index] == 1) &&
2546                     (wcd->micb_ref[micb_index] == 0))
2547                         snd_soc_component_update_bits(component, micb_reg,
2548                                                         0xC0, 0x80);
2549                 break;
2550         case MICB_PULLUP_DISABLE:
2551                 wcd->pullup_ref[micb_index]--;
2552                 if ((wcd->pullup_ref[micb_index] == 0) &&
2553                     (wcd->micb_ref[micb_index] == 0))
2554                         snd_soc_component_update_bits(component, micb_reg,
2555                                                         0xC0, 0x00);
2556                 break;
2557         case MICB_ENABLE:
2558                 wcd->micb_ref[micb_index]++;
2559                 if (wcd->micb_ref[micb_index] == 1)
2560                         snd_soc_component_update_bits(component, micb_reg,
2561                                                         0xC0, 0x40);
2562                 break;
2563         case MICB_DISABLE:
2564                 wcd->micb_ref[micb_index]--;
2565                 if ((wcd->micb_ref[micb_index] == 0) &&
2566                     (wcd->pullup_ref[micb_index] > 0))
2567                         snd_soc_component_update_bits(component, micb_reg,
2568                                                         0xC0, 0x80);
2569                 else if ((wcd->micb_ref[micb_index] == 0) &&
2570                          (wcd->pullup_ref[micb_index] == 0)) {
2571                         snd_soc_component_update_bits(component, micb_reg,
2572                                                         0xC0, 0x00);
2573                 }
2574                 break;
2575         }
2576
2577         return 0;
2578 }
2579
2580 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2581                                         int event)
2582 {
2583         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2584         int micb_num;
2585
2586         if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
2587                 micb_num = MIC_BIAS_1;
2588         else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
2589                 micb_num = MIC_BIAS_2;
2590         else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
2591                 micb_num = MIC_BIAS_3;
2592         else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
2593                 micb_num = MIC_BIAS_4;
2594         else
2595                 return -EINVAL;
2596
2597         switch (event) {
2598         case SND_SOC_DAPM_PRE_PMU:
2599                 /*
2600                  * MIC BIAS can also be requested by MBHC,
2601                  * so use ref count to handle micbias pullup
2602                  * and enable requests
2603                  */
2604                 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true);
2605                 break;
2606         case SND_SOC_DAPM_POST_PMU:
2607                 /* wait for cnp time */
2608                 usleep_range(1000, 1100);
2609                 break;
2610         case SND_SOC_DAPM_POST_PMD:
2611                 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true);
2612                 break;
2613         }
2614
2615         return 0;
2616 }
2617
2618 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2619                 struct snd_kcontrol *kc, int event)
2620 {
2621         return __wcd9335_codec_enable_micbias(w, event);
2622 }
2623
2624 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp,
2625                                       u16 amic_reg, bool set)
2626 {
2627         u8 mask = 0x20;
2628         u8 val;
2629
2630         if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 ||
2631             amic_reg == WCD9335_ANA_AMIC5)
2632                 mask = 0x40;
2633
2634         val = set ? mask : 0x00;
2635
2636         switch (amic_reg) {
2637         case WCD9335_ANA_AMIC1:
2638         case WCD9335_ANA_AMIC2:
2639                 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask,
2640                                                 val);
2641                 break;
2642         case WCD9335_ANA_AMIC3:
2643         case WCD9335_ANA_AMIC4:
2644                 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask,
2645                                                 val);
2646                 break;
2647         case WCD9335_ANA_AMIC5:
2648         case WCD9335_ANA_AMIC6:
2649                 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask,
2650                                                 val);
2651                 break;
2652         default:
2653                 dev_err(comp->dev, "%s: invalid amic: %d\n",
2654                         __func__, amic_reg);
2655                 break;
2656         }
2657 }
2658
2659 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w,
2660                 struct snd_kcontrol *kc, int event)
2661 {
2662         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2663
2664         switch (event) {
2665         case SND_SOC_DAPM_PRE_PMU:
2666                 wcd9335_codec_set_tx_hold(comp, w->reg, true);
2667                 break;
2668         default:
2669                 break;
2670         }
2671
2672         return 0;
2673 }
2674
2675 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp,
2676                                          int adc_mux_n)
2677 {
2678         int mux_sel, reg, mreg;
2679
2680         if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
2681             adc_mux_n == WCD9335_INVALID_ADC_MUX)
2682                 return 0;
2683
2684         /* Check whether adc mux input is AMIC or DMIC */
2685         if (adc_mux_n < 4) {
2686                 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
2687                 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
2688                 mux_sel = snd_soc_component_read(comp, reg) & 0x3;
2689         } else {
2690                 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
2691                 mreg = reg;
2692                 mux_sel = snd_soc_component_read(comp, reg) >> 6;
2693         }
2694
2695         if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
2696                 return 0;
2697
2698         return snd_soc_component_read(comp, mreg) & 0x07;
2699 }
2700
2701 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
2702                                             int amic)
2703 {
2704         u16 pwr_level_reg = 0;
2705
2706         switch (amic) {
2707         case 1:
2708         case 2:
2709                 pwr_level_reg = WCD9335_ANA_AMIC1;
2710                 break;
2711
2712         case 3:
2713         case 4:
2714                 pwr_level_reg = WCD9335_ANA_AMIC3;
2715                 break;
2716
2717         case 5:
2718         case 6:
2719                 pwr_level_reg = WCD9335_ANA_AMIC5;
2720                 break;
2721         default:
2722                 dev_err(comp->dev, "invalid amic: %d\n", amic);
2723                 break;
2724         }
2725
2726         return pwr_level_reg;
2727 }
2728
2729 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w,
2730         struct snd_kcontrol *kc, int event)
2731 {
2732         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2733         unsigned int decimator;
2734         char *dec_adc_mux_name = NULL;
2735         char *widget_name = NULL;
2736         char *wname;
2737         int ret = 0, amic_n;
2738         u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
2739         u16 tx_gain_ctl_reg;
2740         char *dec;
2741         u8 hpf_coff_freq;
2742
2743         widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL);
2744         if (!widget_name)
2745                 return -ENOMEM;
2746
2747         wname = widget_name;
2748         dec_adc_mux_name = strsep(&widget_name, " ");
2749         if (!dec_adc_mux_name) {
2750                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2751                         __func__, w->name);
2752                 ret =  -EINVAL;
2753                 goto out;
2754         }
2755         dec_adc_mux_name = widget_name;
2756
2757         dec = strpbrk(dec_adc_mux_name, "012345678");
2758         if (!dec) {
2759                 dev_err(comp->dev, "%s: decimator index not found\n",
2760                         __func__);
2761                 ret =  -EINVAL;
2762                 goto out;
2763         }
2764
2765         ret = kstrtouint(dec, 10, &decimator);
2766         if (ret < 0) {
2767                 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2768                         __func__, wname);
2769                 ret =  -EINVAL;
2770                 goto out;
2771         }
2772
2773         tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
2774         hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
2775         dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
2776         tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
2777
2778         switch (event) {
2779         case SND_SOC_DAPM_PRE_PMU:
2780                 amic_n = wcd9335_codec_find_amic_input(comp, decimator);
2781                 if (amic_n)
2782                         pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp,
2783                                                                        amic_n);
2784
2785                 if (pwr_level_reg) {
2786                         switch ((snd_soc_component_read(comp, pwr_level_reg) &
2787                                               WCD9335_AMIC_PWR_LVL_MASK) >>
2788                                               WCD9335_AMIC_PWR_LVL_SHIFT) {
2789                         case WCD9335_AMIC_PWR_LEVEL_LP:
2790                                 snd_soc_component_update_bits(comp, dec_cfg_reg,
2791                                                     WCD9335_DEC_PWR_LVL_MASK,
2792                                                     WCD9335_DEC_PWR_LVL_LP);
2793                                 break;
2794
2795                         case WCD9335_AMIC_PWR_LEVEL_HP:
2796                                 snd_soc_component_update_bits(comp, dec_cfg_reg,
2797                                                     WCD9335_DEC_PWR_LVL_MASK,
2798                                                     WCD9335_DEC_PWR_LVL_HP);
2799                                 break;
2800                         case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
2801                         default:
2802                                 snd_soc_component_update_bits(comp, dec_cfg_reg,
2803                                                     WCD9335_DEC_PWR_LVL_MASK,
2804                                                     WCD9335_DEC_PWR_LVL_DF);
2805                                 break;
2806                         }
2807                 }
2808                 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2809                                    TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2810
2811                 if (hpf_coff_freq != CF_MIN_3DB_150HZ)
2812                         snd_soc_component_update_bits(comp, dec_cfg_reg,
2813                                             TX_HPF_CUT_OFF_FREQ_MASK,
2814                                             CF_MIN_3DB_150HZ << 5);
2815                 /* Enable TX PGA Mute */
2816                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2817                                                 0x10, 0x10);
2818                 /* Enable APC */
2819                 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08);
2820                 break;
2821         case SND_SOC_DAPM_POST_PMU:
2822                 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00);
2823
2824                 if (decimator == 0) {
2825                         snd_soc_component_write(comp,
2826                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2827                         snd_soc_component_write(comp,
2828                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
2829                         snd_soc_component_write(comp,
2830                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2831                         snd_soc_component_write(comp,
2832                                         WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
2833                 }
2834
2835                 snd_soc_component_update_bits(comp, hpf_gate_reg,
2836                                                 0x01, 0x01);
2837                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2838                                                 0x10, 0x00);
2839                 snd_soc_component_write(comp, tx_gain_ctl_reg,
2840                               snd_soc_component_read(comp, tx_gain_ctl_reg));
2841                 break;
2842         case SND_SOC_DAPM_PRE_PMD:
2843                 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2844                                    TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2845                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
2846                 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
2847                 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
2848                         snd_soc_component_update_bits(comp, dec_cfg_reg,
2849                                                       TX_HPF_CUT_OFF_FREQ_MASK,
2850                                                       hpf_coff_freq << 5);
2851                 }
2852                 break;
2853         case SND_SOC_DAPM_POST_PMD:
2854                 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00);
2855                 break;
2856         }
2857 out:
2858         kfree(wname);
2859         return ret;
2860 }
2861
2862 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component,
2863                                  u32 mclk_rate, u32 dmic_clk_rate)
2864 {
2865         u32 div_factor;
2866         u8 dmic_ctl_val;
2867
2868         dev_err(component->dev,
2869                 "%s: mclk_rate = %d, dmic_sample_rate = %d\n",
2870                 __func__, mclk_rate, dmic_clk_rate);
2871
2872         /* Default value to return in case of error */
2873         if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
2874                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2875         else
2876                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2877
2878         if (dmic_clk_rate == 0) {
2879                 dev_err(component->dev,
2880                         "%s: dmic_sample_rate cannot be 0\n",
2881                         __func__);
2882                 goto done;
2883         }
2884
2885         div_factor = mclk_rate / dmic_clk_rate;
2886         switch (div_factor) {
2887         case 2:
2888                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2889                 break;
2890         case 3:
2891                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2892                 break;
2893         case 4:
2894                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4;
2895                 break;
2896         case 6:
2897                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6;
2898                 break;
2899         case 8:
2900                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8;
2901                 break;
2902         case 16:
2903                 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16;
2904                 break;
2905         default:
2906                 dev_err(component->dev,
2907                         "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
2908                         __func__, div_factor, mclk_rate, dmic_clk_rate);
2909                 break;
2910         }
2911
2912 done:
2913         return dmic_ctl_val;
2914 }
2915
2916 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2917                 struct snd_kcontrol *kc, int event)
2918 {
2919         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2920         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2921         u8  dmic_clk_en = 0x01;
2922         u16 dmic_clk_reg;
2923         s32 *dmic_clk_cnt;
2924         u8 dmic_rate_val, dmic_rate_shift = 1;
2925         unsigned int dmic;
2926         int ret;
2927         char *wname;
2928
2929         wname = strpbrk(w->name, "012345");
2930         if (!wname) {
2931                 dev_err(comp->dev, "%s: widget not found\n", __func__);
2932                 return -EINVAL;
2933         }
2934
2935         ret = kstrtouint(wname, 10, &dmic);
2936         if (ret < 0) {
2937                 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
2938                         __func__);
2939                 return -EINVAL;
2940         }
2941
2942         switch (dmic) {
2943         case 0:
2944         case 1:
2945                 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt);
2946                 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
2947                 break;
2948         case 2:
2949         case 3:
2950                 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt);
2951                 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
2952                 break;
2953         case 4:
2954         case 5:
2955                 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt);
2956                 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
2957                 break;
2958         default:
2959                 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
2960                         __func__);
2961                 return -EINVAL;
2962         }
2963
2964         switch (event) {
2965         case SND_SOC_DAPM_PRE_PMU:
2966                 dmic_rate_val =
2967                         wcd9335_get_dmic_clk_val(comp,
2968                                         wcd->mclk_rate,
2969                                         wcd->dmic_sample_rate);
2970
2971                 (*dmic_clk_cnt)++;
2972                 if (*dmic_clk_cnt == 1) {
2973                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2974                                 0x07 << dmic_rate_shift,
2975                                 dmic_rate_val << dmic_rate_shift);
2976                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2977                                         dmic_clk_en, dmic_clk_en);
2978                 }
2979
2980                 break;
2981         case SND_SOC_DAPM_POST_PMD:
2982                 dmic_rate_val =
2983                         wcd9335_get_dmic_clk_val(comp,
2984                                         wcd->mclk_rate,
2985                                         wcd->mad_dmic_sample_rate);
2986                 (*dmic_clk_cnt)--;
2987                 if (*dmic_clk_cnt  == 0) {
2988                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2989                                         dmic_clk_en, 0);
2990                         snd_soc_component_update_bits(comp, dmic_clk_reg,
2991                                 0x07 << dmic_rate_shift,
2992                                 dmic_rate_val << dmic_rate_shift);
2993                 }
2994                 break;
2995         }
2996
2997         return 0;
2998 }
2999
3000 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
3001                                         struct snd_soc_component *component)
3002 {
3003         int port_num = 0;
3004         unsigned short reg = 0;
3005         unsigned int val = 0;
3006         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3007         struct wcd9335_slim_ch *ch;
3008
3009         list_for_each_entry(ch, &dai->slim_ch_list, list) {
3010                 if (ch->port >= WCD9335_RX_START) {
3011                         port_num = ch->port - WCD9335_RX_START;
3012                         reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
3013                 } else {
3014                         port_num = ch->port;
3015                         reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
3016                 }
3017
3018                 regmap_read(wcd->if_regmap, reg, &val);
3019                 if (!(val & BIT(port_num % 8)))
3020                         regmap_write(wcd->if_regmap, reg,
3021                                         val | BIT(port_num % 8));
3022         }
3023 }
3024
3025 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w,
3026                                        struct snd_kcontrol *kc,
3027                                        int event)
3028 {
3029         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3030         struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
3031         struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
3032
3033         switch (event) {
3034         case SND_SOC_DAPM_POST_PMU:
3035                 wcd9335_codec_enable_int_port(dai, comp);
3036                 break;
3037         case SND_SOC_DAPM_POST_PMD:
3038                 kfree(dai->sconfig.chs);
3039
3040                 break;
3041         }
3042
3043         return 0;
3044 }
3045
3046 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
3047                 struct snd_kcontrol *kc, int event)
3048 {
3049         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3050         u16 gain_reg;
3051         int offset_val = 0;
3052         int val = 0;
3053
3054         switch (w->reg) {
3055         case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3056                 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
3057                 break;
3058         case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3059                 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
3060                 break;
3061         case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3062                 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
3063                 break;
3064         case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3065                 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
3066                 break;
3067         case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3068                 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
3069                 break;
3070         case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3071                 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
3072                 break;
3073         case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3074                 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
3075                 break;
3076         case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3077                 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
3078                 break;
3079         case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3080                 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
3081                 break;
3082         default:
3083                 dev_err(comp->dev, "%s: No gain register avail for %s\n",
3084                         __func__, w->name);
3085                 return 0;
3086         }
3087
3088         switch (event) {
3089         case SND_SOC_DAPM_POST_PMU:
3090                 val = snd_soc_component_read(comp, gain_reg);
3091                 val += offset_val;
3092                 snd_soc_component_write(comp, gain_reg, val);
3093                 break;
3094         case SND_SOC_DAPM_POST_PMD:
3095                 break;
3096         }
3097
3098         return 0;
3099 }
3100
3101 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind)
3102 {
3103         u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3104
3105         switch (reg) {
3106         case WCD9335_CDC_RX0_RX_PATH_CTL:
3107         case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3108                 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3109                 *ind = 0;
3110                 break;
3111         case WCD9335_CDC_RX1_RX_PATH_CTL:
3112         case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3113                 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3114                 *ind = 1;
3115                 break;
3116         case WCD9335_CDC_RX2_RX_PATH_CTL:
3117         case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3118                 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3119                 *ind = 2;
3120                 break;
3121         case WCD9335_CDC_RX3_RX_PATH_CTL:
3122         case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3123                 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3124                 *ind = 3;
3125                 break;
3126         case WCD9335_CDC_RX4_RX_PATH_CTL:
3127         case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3128                 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3129                 *ind = 4;
3130                 break;
3131         case WCD9335_CDC_RX5_RX_PATH_CTL:
3132         case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3133                 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3134                 *ind = 5;
3135                 break;
3136         case WCD9335_CDC_RX6_RX_PATH_CTL:
3137         case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3138                 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3139                 *ind = 6;
3140                 break;
3141         case WCD9335_CDC_RX7_RX_PATH_CTL:
3142         case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3143                 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3144                 *ind = 7;
3145                 break;
3146         case WCD9335_CDC_RX8_RX_PATH_CTL:
3147         case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3148                 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3149                 *ind = 8;
3150                 break;
3151         }
3152
3153         return prim_int_reg;
3154 }
3155
3156 static void wcd9335_codec_hd2_control(struct snd_soc_component *component,
3157                                     u16 prim_int_reg, int event)
3158 {
3159         u16 hd2_scale_reg;
3160         u16 hd2_enable_reg = 0;
3161
3162         if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
3163                 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
3164                 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
3165         }
3166         if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
3167                 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
3168                 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
3169         }
3170
3171         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
3172                 snd_soc_component_update_bits(component, hd2_scale_reg,
3173                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3174                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500);
3175                 snd_soc_component_update_bits(component, hd2_scale_reg,
3176                                 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3177                                 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2);
3178                 snd_soc_component_update_bits(component, hd2_enable_reg,
3179                                 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3180                                 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE);
3181         }
3182
3183         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
3184                 snd_soc_component_update_bits(component, hd2_enable_reg,
3185                                         WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3186                                         WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE);
3187                 snd_soc_component_update_bits(component, hd2_scale_reg,
3188                                         WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3189                                         WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1);
3190                 snd_soc_component_update_bits(component, hd2_scale_reg,
3191                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3192                                 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3193         }
3194 }
3195
3196 static int wcd9335_codec_enable_prim_interpolator(
3197                                                 struct snd_soc_component *comp,
3198                                                 u16 reg, int event)
3199 {
3200         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3201         u16 ind = 0;
3202         int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind);
3203
3204         switch (event) {
3205         case SND_SOC_DAPM_PRE_PMU:
3206                 wcd->prim_int_users[ind]++;
3207                 if (wcd->prim_int_users[ind] == 1) {
3208                         snd_soc_component_update_bits(comp, prim_int_reg,
3209                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3210                                         WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3211                         wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3212                         snd_soc_component_update_bits(comp, prim_int_reg,
3213                                         WCD9335_CDC_RX_CLK_EN_MASK,
3214                                         WCD9335_CDC_RX_CLK_ENABLE);
3215                 }
3216
3217                 if ((reg != prim_int_reg) &&
3218                         ((snd_soc_component_read(comp, prim_int_reg)) &
3219                          WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
3220                         snd_soc_component_update_bits(comp, reg,
3221                                                 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3222                                                 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3223                 break;
3224         case SND_SOC_DAPM_POST_PMD:
3225                 wcd->prim_int_users[ind]--;
3226                 if (wcd->prim_int_users[ind] == 0) {
3227                         snd_soc_component_update_bits(comp, prim_int_reg,
3228                                         WCD9335_CDC_RX_CLK_EN_MASK,
3229                                         WCD9335_CDC_RX_CLK_DISABLE);
3230                         snd_soc_component_update_bits(comp, prim_int_reg,
3231                                         WCD9335_CDC_RX_RESET_MASK,
3232                                         WCD9335_CDC_RX_RESET_ENABLE);
3233                         snd_soc_component_update_bits(comp, prim_int_reg,
3234                                         WCD9335_CDC_RX_RESET_MASK,
3235                                         WCD9335_CDC_RX_RESET_DISABLE);
3236                         wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3237                 }
3238                 break;
3239         }
3240
3241         return 0;
3242 }
3243
3244 static int wcd9335_config_compander(struct snd_soc_component *component,
3245                                     int interp_n, int event)
3246 {
3247         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3248         int comp;
3249         u16 comp_ctl0_reg, rx_path_cfg0_reg;
3250
3251         /* EAR does not have compander */
3252         if (!interp_n)
3253                 return 0;
3254
3255         comp = interp_n - 1;
3256         if (!wcd->comp_enabled[comp])
3257                 return 0;
3258
3259         comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp);
3260         rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp);
3261
3262         if (SND_SOC_DAPM_EVENT_ON(event)) {
3263                 /* Enable Compander Clock */
3264                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3265                                         WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3266                                         WCD9335_CDC_COMPANDER_CLK_ENABLE);
3267                 /* Reset comander */
3268                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3269                                         WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3270                                         WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3271                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3272                                 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3273                                 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3274                 /* Enables DRE in this path */
3275                 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3276                                         WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3277                                         WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE);
3278         }
3279
3280         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3281                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3282                                         WCD9335_CDC_COMPANDER_HALT_MASK,
3283                                         WCD9335_CDC_COMPANDER_HALT);
3284                 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3285                                         WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3286                                         WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE);
3287
3288                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3289                                         WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3290                                         WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3291                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3292                                 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3293                                 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3294                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3295                                         WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3296                                         WCD9335_CDC_COMPANDER_CLK_DISABLE);
3297                 snd_soc_component_update_bits(component, comp_ctl0_reg,
3298                                         WCD9335_CDC_COMPANDER_HALT_MASK,
3299                                         WCD9335_CDC_COMPANDER_NOHALT);
3300         }
3301
3302         return 0;
3303 }
3304
3305 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
3306                 struct snd_kcontrol *kc, int event)
3307 {
3308         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3309         u16 gain_reg;
3310         u16 reg;
3311         int val;
3312         int offset_val = 0;
3313
3314         if (!(strcmp(w->name, "RX INT0 INTERP"))) {
3315                 reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3316                 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
3317         } else if (!(strcmp(w->name, "RX INT1 INTERP"))) {
3318                 reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3319                 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
3320         } else if (!(strcmp(w->name, "RX INT2 INTERP"))) {
3321                 reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3322                 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
3323         } else if (!(strcmp(w->name, "RX INT3 INTERP"))) {
3324                 reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3325                 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
3326         } else if (!(strcmp(w->name, "RX INT4 INTERP"))) {
3327                 reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3328                 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
3329         } else if (!(strcmp(w->name, "RX INT5 INTERP"))) {
3330                 reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3331                 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
3332         } else if (!(strcmp(w->name, "RX INT6 INTERP"))) {
3333                 reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3334                 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
3335         } else if (!(strcmp(w->name, "RX INT7 INTERP"))) {
3336                 reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3337                 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
3338         } else if (!(strcmp(w->name, "RX INT8 INTERP"))) {
3339                 reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3340                 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
3341         } else {
3342                 dev_err(comp->dev, "%s: Interpolator reg not found\n",
3343                         __func__);
3344                 return -EINVAL;
3345         }
3346
3347         switch (event) {
3348         case SND_SOC_DAPM_PRE_PMU:
3349                 /* Reset if needed */
3350                 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3351                 break;
3352         case SND_SOC_DAPM_POST_PMU:
3353                 wcd9335_config_compander(comp, w->shift, event);
3354                 val = snd_soc_component_read(comp, gain_reg);
3355                 val += offset_val;
3356                 snd_soc_component_write(comp, gain_reg, val);
3357                 break;
3358         case SND_SOC_DAPM_POST_PMD:
3359                 wcd9335_config_compander(comp, w->shift, event);
3360                 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3361                 break;
3362         }
3363
3364         return 0;
3365 }
3366
3367 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component,
3368                                             u8 gain)
3369 {
3370         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3371         u8 hph_l_en, hph_r_en;
3372         u8 l_val, r_val;
3373         u8 hph_pa_status;
3374         bool is_hphl_pa, is_hphr_pa;
3375
3376         hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH);
3377         is_hphl_pa = hph_pa_status >> 7;
3378         is_hphr_pa = (hph_pa_status & 0x40) >> 6;
3379
3380         hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN);
3381         hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN);
3382
3383         l_val = (hph_l_en & 0xC0) | 0x20 | gain;
3384         r_val = (hph_r_en & 0xC0) | 0x20 | gain;
3385
3386         /*
3387          * Set HPH_L & HPH_R gain source selection to REGISTER
3388          * for better click and pop only if corresponding PAs are
3389          * not enabled. Also cache the values of the HPHL/R
3390          * PA gains to be applied after PAs are enabled
3391          */
3392         if ((l_val != hph_l_en) && !is_hphl_pa) {
3393                 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val);
3394                 wcd->hph_l_gain = hph_l_en & 0x1F;
3395         }
3396
3397         if ((r_val != hph_r_en) && !is_hphr_pa) {
3398                 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val);
3399                 wcd->hph_r_gain = hph_r_en & 0x1F;
3400         }
3401 }
3402
3403 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp,
3404                                           int event)
3405 {
3406         if (SND_SOC_DAPM_EVENT_ON(event)) {
3407                 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3408                                         WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3409                                         0x06);
3410                 snd_soc_component_update_bits(comp,
3411                                         WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3412                                         0xF0, 0x40);
3413                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3414                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3415                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3416                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3417                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3418                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3419                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3420                                 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3421                                 0x0C);
3422                 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3423         }
3424
3425         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3426                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3427                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3428                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3429                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3430                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3431                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3432                 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3433                                         0x8A);
3434                 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3435                                         WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3436                                         0x0A);
3437         }
3438 }
3439
3440 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp,
3441                                       int event)
3442 {
3443         if (SND_SOC_DAPM_EVENT_ON(event)) {
3444                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3445                                 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3446                                 0x0C);
3447                 wcd9335_codec_hph_mode_gain_opt(comp, 0x10);
3448                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3449                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3450                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3451                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3452                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3453                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3454                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3455                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3456                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE);
3457                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3458                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3459                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE);
3460                 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3461                                 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK,
3462                                 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60);
3463                 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3464                                 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK,
3465                                 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60);
3466                 snd_soc_component_update_bits(comp,
3467                                 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01);
3468                 snd_soc_component_update_bits(comp,
3469                                 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10);
3470         }
3471
3472         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3473                 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO,
3474                                         0x88);
3475                 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL,
3476                                         0x33);
3477                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3478                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3479                                 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE);
3480                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3481                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3482                                 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE);
3483                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3484                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3485                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3486                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3487                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3488                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3489                 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN,
3490                                 WCD9335_HPH_CONST_SEL_L_MASK,
3491                                 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3492                 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN,
3493                                 WCD9335_HPH_CONST_SEL_L_MASK,
3494                                 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3495         }
3496 }
3497
3498 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp,
3499                                         int event)
3500 {
3501         if (SND_SOC_DAPM_EVENT_ON(event)) {
3502                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3503                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3504                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3505                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3506                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3507                                 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3508                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3509                                 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3510                                 0x0C);
3511                 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3512         }
3513
3514         if (SND_SOC_DAPM_EVENT_OFF(event)) {
3515                 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3516                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3517                         WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3518                 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3519                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3520                                 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3521         }
3522 }
3523
3524 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component,
3525                                           int event, int mode)
3526 {
3527         switch (mode) {
3528         case CLS_H_LP:
3529                 wcd9335_codec_hph_lp_config(component, event);
3530                 break;
3531         case CLS_H_LOHIFI:
3532                 wcd9335_codec_hph_lohifi_config(component, event);
3533                 break;
3534         case CLS_H_HIFI:
3535                 wcd9335_codec_hph_hifi_config(component, event);
3536                 break;
3537         }
3538 }
3539
3540 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3541                                         struct snd_kcontrol *kc,
3542                                         int event)
3543 {
3544         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3545         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3546         int hph_mode = wcd->hph_mode;
3547         u8 dem_inp;
3548
3549         switch (event) {
3550         case SND_SOC_DAPM_PRE_PMU:
3551                 /* Read DEM INP Select */
3552                 dem_inp = snd_soc_component_read(comp,
3553                                 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
3554                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3555                                 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3556                         dev_err(comp->dev, "Incorrect DEM Input\n");
3557                         return -EINVAL;
3558                 }
3559                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3560                                         WCD_CLSH_STATE_HPHL,
3561                                         ((hph_mode == CLS_H_LOHIFI) ?
3562                                          CLS_H_HIFI : hph_mode));
3563
3564                 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3565
3566                 break;
3567         case SND_SOC_DAPM_POST_PMU:
3568                 usleep_range(1000, 1100);
3569                 break;
3570         case SND_SOC_DAPM_PRE_PMD:
3571                 break;
3572         case SND_SOC_DAPM_POST_PMD:
3573                 /* 1000us required as per HW requirement */
3574                 usleep_range(1000, 1100);
3575
3576                 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3577                                 WCD_CLSH_STATE_HPHR))
3578                         wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3579
3580                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3581                                 WCD_CLSH_STATE_HPHL,
3582                                 ((hph_mode == CLS_H_LOHIFI) ?
3583                                  CLS_H_HIFI : hph_mode));
3584                 break;
3585         }
3586
3587         return 0;
3588 }
3589
3590 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3591                                            struct snd_kcontrol *kc, int event)
3592 {
3593         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3594         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3595
3596         switch (event) {
3597         case SND_SOC_DAPM_PRE_PMU:
3598                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3599                                         WCD_CLSH_STATE_LO, CLS_AB);
3600                 break;
3601         case SND_SOC_DAPM_POST_PMD:
3602                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3603                                         WCD_CLSH_STATE_LO, CLS_AB);
3604                 break;
3605         }
3606
3607         return 0;
3608 }
3609
3610 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3611                                        struct snd_kcontrol *kc, int event)
3612 {
3613         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3614         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3615
3616         switch (event) {
3617         case SND_SOC_DAPM_PRE_PMU:
3618                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3619                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3620
3621                 break;
3622         case SND_SOC_DAPM_POST_PMD:
3623                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3624                                         WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3625                 break;
3626         }
3627
3628         return 0;
3629 }
3630
3631 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd,
3632                                              int mode, int event)
3633 {
3634         u8 scale_val = 0;
3635
3636         switch (event) {
3637         case SND_SOC_DAPM_POST_PMU:
3638                 switch (mode) {
3639                 case CLS_H_HIFI:
3640                         scale_val = 0x3;
3641                         break;
3642                 case CLS_H_LOHIFI:
3643                         scale_val = 0x1;
3644                         break;
3645                 }
3646                 break;
3647         case SND_SOC_DAPM_PRE_PMD:
3648                 scale_val = 0x6;
3649                 break;
3650         }
3651
3652         if (scale_val)
3653                 snd_soc_component_update_bits(wcd->component,
3654                                         WCD9335_HPH_PA_CTL1,
3655                                         WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3656                                         scale_val << 1);
3657         if (SND_SOC_DAPM_EVENT_ON(event)) {
3658                 if (wcd->comp_enabled[COMPANDER_1] ||
3659                     wcd->comp_enabled[COMPANDER_2]) {
3660                         /* GAIN Source Selection */
3661                         snd_soc_component_update_bits(wcd->component,
3662                                         WCD9335_HPH_L_EN,
3663                                         WCD9335_HPH_GAIN_SRC_SEL_MASK,
3664                                         WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3665                         snd_soc_component_update_bits(wcd->component,
3666                                         WCD9335_HPH_R_EN,
3667                                         WCD9335_HPH_GAIN_SRC_SEL_MASK,
3668                                         WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3669                         snd_soc_component_update_bits(wcd->component,
3670                                         WCD9335_HPH_AUTO_CHOP,
3671                                         WCD9335_HPH_AUTO_CHOP_MASK,
3672                                         WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE);
3673                 }
3674                 snd_soc_component_update_bits(wcd->component,
3675                                                 WCD9335_HPH_L_EN,
3676                                                 WCD9335_HPH_PA_GAIN_MASK,
3677                                                 wcd->hph_l_gain);
3678                 snd_soc_component_update_bits(wcd->component,
3679                                                 WCD9335_HPH_R_EN,
3680                                                 WCD9335_HPH_PA_GAIN_MASK,
3681                                                 wcd->hph_r_gain);
3682         }
3683
3684         if (SND_SOC_DAPM_EVENT_OFF(event))
3685                 snd_soc_component_update_bits(wcd->component,
3686                                 WCD9335_HPH_AUTO_CHOP,
3687                                 WCD9335_HPH_AUTO_CHOP_MASK,
3688                                 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN);
3689 }
3690
3691 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3692                                       struct snd_kcontrol *kc,
3693                                       int event)
3694 {
3695         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3696         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3697         int hph_mode = wcd->hph_mode;
3698         u8 dem_inp;
3699
3700         switch (event) {
3701         case SND_SOC_DAPM_PRE_PMU:
3702
3703                 /* Read DEM INP Select */
3704                 dem_inp = snd_soc_component_read(comp,
3705                                 WCD9335_CDC_RX2_RX_PATH_SEC0) &
3706                                 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
3707                 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3708                      (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3709                         dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n",
3710                                 hph_mode);
3711                         return -EINVAL;
3712                 }
3713
3714                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl,
3715                              WCD_CLSH_EVENT_PRE_DAC,
3716                              WCD_CLSH_STATE_HPHR,
3717                              ((hph_mode == CLS_H_LOHIFI) ?
3718                                CLS_H_HIFI : hph_mode));
3719
3720                 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3721
3722                 break;
3723         case SND_SOC_DAPM_POST_PMD:
3724                 /* 1000us required as per HW requirement */
3725                 usleep_range(1000, 1100);
3726
3727                 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3728                                         WCD_CLSH_STATE_HPHL))
3729                         wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3730
3731                 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3732                              WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ?
3733                                                 CLS_H_HIFI : hph_mode));
3734                 break;
3735         }
3736
3737         return 0;
3738 }
3739
3740 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3741                                       struct snd_kcontrol *kc,
3742                                       int event)
3743 {
3744         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3745         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3746         int hph_mode = wcd->hph_mode;
3747
3748         switch (event) {
3749         case SND_SOC_DAPM_PRE_PMU:
3750                 break;
3751         case SND_SOC_DAPM_POST_PMU:
3752                 /*
3753                  * 7ms sleep is required after PA is enabled as per
3754                  * HW requirement
3755                  */
3756                 usleep_range(7000, 7100);
3757
3758                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3759                 snd_soc_component_update_bits(comp,
3760                                         WCD9335_CDC_RX1_RX_PATH_CTL,
3761                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3762                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3763
3764                 /* Remove mix path mute if it is enabled */
3765                 if ((snd_soc_component_read(comp,
3766                                         WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
3767                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3768                         snd_soc_component_update_bits(comp,
3769                                             WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
3770                                             WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3771                                             WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3772
3773                 break;
3774         case SND_SOC_DAPM_PRE_PMD:
3775                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3776                 break;
3777         case SND_SOC_DAPM_POST_PMD:
3778                 /* 5ms sleep is required after PA is disabled as per
3779                  * HW requirement
3780                  */
3781                 usleep_range(5000, 5500);
3782                 break;
3783         }
3784
3785         return 0;
3786 }
3787
3788 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
3789                                          struct snd_kcontrol *kc,
3790                                          int event)
3791 {
3792         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3793         int vol_reg = 0, mix_vol_reg = 0;
3794
3795         if (w->reg == WCD9335_ANA_LO_1_2) {
3796                 if (w->shift == 7) {
3797                         vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3798                         mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
3799                 } else if (w->shift == 6) {
3800                         vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3801                         mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
3802                 }
3803         } else if (w->reg == WCD9335_ANA_LO_3_4) {
3804                 if (w->shift == 7) {
3805                         vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3806                         mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
3807                 } else if (w->shift == 6) {
3808                         vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3809                         mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
3810                 }
3811         } else {
3812                 dev_err(comp->dev, "Error enabling lineout PA\n");
3813                 return -EINVAL;
3814         }
3815
3816         switch (event) {
3817         case SND_SOC_DAPM_POST_PMU:
3818                 /* 5ms sleep is required after PA is enabled as per
3819                  * HW requirement
3820                  */
3821                 usleep_range(5000, 5500);
3822                 snd_soc_component_update_bits(comp, vol_reg,
3823                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3824                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3825
3826                 /* Remove mix path mute if it is enabled */
3827                 if ((snd_soc_component_read(comp, mix_vol_reg)) &
3828                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3829                         snd_soc_component_update_bits(comp,  mix_vol_reg,
3830                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3831                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3832                 break;
3833         case SND_SOC_DAPM_POST_PMD:
3834                 /* 5ms sleep is required after PA is disabled as per
3835                  * HW requirement
3836                  */
3837                 usleep_range(5000, 5500);
3838                 break;
3839         }
3840
3841         return 0;
3842 }
3843
3844 static void wcd9335_codec_init_flyback(struct snd_soc_component *component)
3845 {
3846         snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
3847                                         WCD9335_HPH_CONST_SEL_L_MASK,
3848                                         WCD9335_HPH_CONST_SEL_L_BYPASS);
3849         snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
3850                                         WCD9335_HPH_CONST_SEL_L_MASK,
3851                                         WCD9335_HPH_CONST_SEL_L_BYPASS);
3852         snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3853                                         WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK,
3854                                         WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3855         snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3856                                         WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK,
3857                                         WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3858 }
3859
3860 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
3861                 struct snd_kcontrol *kc, int event)
3862 {
3863         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3864         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3865
3866         switch (event) {
3867         case SND_SOC_DAPM_PRE_PMU:
3868                 wcd->rx_bias_count++;
3869                 if (wcd->rx_bias_count == 1) {
3870                         wcd9335_codec_init_flyback(comp);
3871                         snd_soc_component_update_bits(comp,
3872                                                 WCD9335_ANA_RX_SUPPLIES,
3873                                                 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3874                                                 WCD9335_ANA_RX_BIAS_ENABLE);
3875                 }
3876                 break;
3877         case SND_SOC_DAPM_POST_PMD:
3878                 wcd->rx_bias_count--;
3879                 if (!wcd->rx_bias_count)
3880                         snd_soc_component_update_bits(comp,
3881                                         WCD9335_ANA_RX_SUPPLIES,
3882                                         WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3883                                         WCD9335_ANA_RX_BIAS_DISABLE);
3884                 break;
3885         }
3886
3887         return 0;
3888 }
3889
3890 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3891                                         struct snd_kcontrol *kc, int event)
3892 {
3893         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3894         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3895         int hph_mode = wcd->hph_mode;
3896
3897         switch (event) {
3898         case SND_SOC_DAPM_PRE_PMU:
3899                 break;
3900         case SND_SOC_DAPM_POST_PMU:
3901                 /*
3902                  * 7ms sleep is required after PA is enabled as per
3903                  * HW requirement
3904                  */
3905                 usleep_range(7000, 7100);
3906                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3907                 snd_soc_component_update_bits(comp,
3908                                         WCD9335_CDC_RX2_RX_PATH_CTL,
3909                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3910                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3911                 /* Remove mix path mute if it is enabled */
3912                 if ((snd_soc_component_read(comp,
3913                                         WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
3914                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3915                         snd_soc_component_update_bits(comp,
3916                                         WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
3917                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3918                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3919
3920                 break;
3921
3922         case SND_SOC_DAPM_PRE_PMD:
3923                 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3924                 break;
3925         case SND_SOC_DAPM_POST_PMD:
3926                 /* 5ms sleep is required after PA is disabled as per
3927                  * HW requirement
3928                  */
3929                 usleep_range(5000, 5500);
3930                 break;
3931         }
3932
3933         return 0;
3934 }
3935
3936 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
3937                                        struct snd_kcontrol *kc, int event)
3938 {
3939         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3940
3941         switch (event) {
3942         case SND_SOC_DAPM_POST_PMU:
3943                 /* 5ms sleep is required after PA is enabled as per
3944                  * HW requirement
3945                  */
3946                 usleep_range(5000, 5500);
3947                 snd_soc_component_update_bits(comp,
3948                                         WCD9335_CDC_RX0_RX_PATH_CTL,
3949                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3950                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3951                 /* Remove mix path mute if it is enabled */
3952                 if ((snd_soc_component_read(comp,
3953                                         WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
3954                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3955                         snd_soc_component_update_bits(comp,
3956                                         WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
3957                                         WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3958                                         WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3959                 break;
3960         case SND_SOC_DAPM_POST_PMD:
3961                 /* 5ms sleep is required after PA is disabled as per
3962                  * HW requirement
3963                  */
3964                 usleep_range(5000, 5500);
3965
3966                 break;
3967         }
3968
3969         return 0;
3970 }
3971
3972 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data)
3973 {
3974         struct wcd9335_codec *wcd = data;
3975         unsigned long status = 0;
3976         int i, j, port_id;
3977         unsigned int val, int_val = 0;
3978         irqreturn_t ret = IRQ_NONE;
3979         bool tx;
3980         unsigned short reg = 0;
3981
3982         for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
3983              i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
3984                 regmap_read(wcd->if_regmap, i, &val);
3985                 status |= ((u32)val << (8 * j));
3986         }
3987
3988         for_each_set_bit(j, &status, 32) {
3989                 tx = (j >= 16);
3990                 port_id = (tx ? j - 16 : j);
3991                 regmap_read(wcd->if_regmap,
3992                                 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
3993                 if (val) {
3994                         if (!tx)
3995                                 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3996                                         (port_id / 8);
3997                         else
3998                                 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3999                                         (port_id / 8);
4000                         regmap_read(
4001                                 wcd->if_regmap, reg, &int_val);
4002                         /*
4003                          * Ignore interrupts for ports for which the
4004                          * interrupts are not specifically enabled.
4005                          */
4006                         if (!(int_val & (1 << (port_id % 8))))
4007                                 continue;
4008                 }
4009
4010                 if (val & WCD9335_SLIM_IRQ_OVERFLOW)
4011                         dev_err_ratelimited(wcd->dev,
4012                            "%s: overflow error on %s port %d, value %x\n",
4013                            __func__, (tx ? "TX" : "RX"), port_id, val);
4014
4015                 if (val & WCD9335_SLIM_IRQ_UNDERFLOW)
4016                         dev_err_ratelimited(wcd->dev,
4017                            "%s: underflow error on %s port %d, value %x\n",
4018                            __func__, (tx ? "TX" : "RX"), port_id, val);
4019
4020                 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) ||
4021                         (val & WCD9335_SLIM_IRQ_UNDERFLOW)) {
4022                         if (!tx)
4023                                 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
4024                                         (port_id / 8);
4025                         else
4026                                 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
4027                                         (port_id / 8);
4028                         regmap_read(
4029                                 wcd->if_regmap, reg, &int_val);
4030                         if (int_val & (1 << (port_id % 8))) {
4031                                 int_val = int_val ^ (1 << (port_id % 8));
4032                                 regmap_write(wcd->if_regmap,
4033                                         reg, int_val);
4034                         }
4035                 }
4036
4037                 regmap_write(wcd->if_regmap,
4038                                 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
4039                                 BIT(j % 8));
4040                 ret = IRQ_HANDLED;
4041         }
4042
4043         return ret;
4044 }
4045
4046 static struct wcd9335_irq wcd9335_irqs[] = {
4047         {
4048                 .irq = WCD9335_IRQ_SLIMBUS,
4049                 .handler = wcd9335_slimbus_irq,
4050                 .name = "SLIM Slave",
4051         },
4052 };
4053
4054 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd)
4055 {
4056         int irq, ret, i;
4057
4058         for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) {
4059                 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq);
4060                 if (irq < 0) {
4061                         dev_err(wcd->dev, "Failed to get %s\n",
4062                                         wcd9335_irqs[i].name);
4063                         return irq;
4064                 }
4065
4066                 ret = devm_request_threaded_irq(wcd->dev, irq, NULL,
4067                                                 wcd9335_irqs[i].handler,
4068                                                 IRQF_TRIGGER_RISING |
4069                                                 IRQF_ONESHOT,
4070                                                 wcd9335_irqs[i].name, wcd);
4071                 if (ret) {
4072                         dev_err(wcd->dev, "Failed to request %s\n",
4073                                         wcd9335_irqs[i].name);
4074                         return ret;
4075                 }
4076         }
4077
4078         /* enable interrupts on all slave ports */
4079         for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4080                 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4081                              0xFF);
4082
4083         return ret;
4084 }
4085
4086 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd)
4087 {
4088         int i;
4089
4090         /* disable interrupts on all slave ports */
4091         for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4092                 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4093                              0x00);
4094 }
4095
4096 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
4097                                         bool ccl_flag)
4098 {
4099         struct snd_soc_component *comp = wcd->component;
4100
4101         if (ccl_flag) {
4102                 if (++wcd->sido_ccl_cnt == 1)
4103                         snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4104                                         WCD9335_SIDO_SIDO_CCL_DEF_VALUE);
4105         } else {
4106                 if (wcd->sido_ccl_cnt == 0) {
4107                         dev_err(wcd->dev, "sido_ccl already disabled\n");
4108                         return;
4109                 }
4110                 if (--wcd->sido_ccl_cnt == 0)
4111                         snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4112                                 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF);
4113         }
4114 }
4115
4116 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd)
4117 {
4118         wcd->master_bias_users++;
4119         if (wcd->master_bias_users == 1) {
4120                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4121                                         WCD9335_ANA_BIAS_EN_MASK,
4122                                         WCD9335_ANA_BIAS_ENABLE);
4123                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4124                                         WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4125                                         WCD9335_ANA_BIAS_PRECHRG_ENABLE);
4126                 /*
4127                  * 1ms delay is required after pre-charge is enabled
4128                  * as per HW requirement
4129                  */
4130                 usleep_range(1000, 1100);
4131                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4132                                         WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4133                                         WCD9335_ANA_BIAS_PRECHRG_DISABLE);
4134                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4135                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4136                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4137         }
4138
4139         return 0;
4140 }
4141
4142 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd)
4143 {
4144         /* Enable mclk requires master bias to be enabled first */
4145         if (wcd->master_bias_users <= 0)
4146                 return -EINVAL;
4147
4148         if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||
4149             ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {
4150                 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n",
4151                         wcd->clk_type);
4152                 return -EINVAL;
4153         }
4154
4155         if (++wcd->clk_mclk_users == 1) {
4156                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4157                                         WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4158                                         WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE);
4159                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4160                                         WCD9335_ANA_CLK_MCLK_SRC_MASK,
4161                                         WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL);
4162                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4163                                         WCD9335_ANA_CLK_MCLK_EN_MASK,
4164                                         WCD9335_ANA_CLK_MCLK_ENABLE);
4165                 regmap_update_bits(wcd->regmap,
4166                                    WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
4167                                    WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK,
4168                                    WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE);
4169                 regmap_update_bits(wcd->regmap,
4170                                    WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
4171                                    WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK,
4172                                    WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE);
4173                 /*
4174                  * 10us sleep is required after clock is enabled
4175                  * as per HW requirement
4176                  */
4177                 usleep_range(10, 15);
4178         }
4179
4180         wcd->clk_type = WCD_CLK_MCLK;
4181
4182         return 0;
4183 }
4184
4185 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd)
4186 {
4187         if (wcd->clk_mclk_users <= 0)
4188                 return -EINVAL;
4189
4190         if (--wcd->clk_mclk_users == 0) {
4191                 if (wcd->clk_rco_users > 0) {
4192                         /* MCLK to RCO switch */
4193                         regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4194                                         WCD9335_ANA_CLK_MCLK_SRC_MASK,
4195                                         WCD9335_ANA_CLK_MCLK_SRC_RCO);
4196                         wcd->clk_type = WCD_CLK_RCO;
4197                 } else {
4198                         regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4199                                         WCD9335_ANA_CLK_MCLK_EN_MASK,
4200                                         WCD9335_ANA_CLK_MCLK_DISABLE);
4201                         wcd->clk_type = WCD_CLK_OFF;
4202                 }
4203
4204                 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4205                                         WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4206                                         WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE);
4207         }
4208
4209         return 0;
4210 }
4211
4212 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd)
4213 {
4214         if (wcd->master_bias_users <= 0)
4215                 return -EINVAL;
4216
4217         wcd->master_bias_users--;
4218         if (wcd->master_bias_users == 0) {
4219                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4220                                 WCD9335_ANA_BIAS_EN_MASK,
4221                                 WCD9335_ANA_BIAS_DISABLE);
4222                 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4223                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4224                                 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4225         }
4226         return 0;
4227 }
4228
4229 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd,
4230                                      bool enable)
4231 {
4232         int ret = 0;
4233
4234         if (enable) {
4235                 wcd9335_cdc_sido_ccl_enable(wcd, true);
4236                 ret = clk_prepare_enable(wcd->mclk);
4237                 if (ret) {
4238                         dev_err(wcd->dev, "%s: ext clk enable failed\n",
4239                                 __func__);
4240                         goto err;
4241                 }
4242                 /* get BG */
4243                 wcd9335_enable_master_bias(wcd);
4244                 /* get MCLK */
4245                 wcd9335_enable_mclk(wcd);
4246
4247         } else {
4248                 /* put MCLK */
4249                 wcd9335_disable_mclk(wcd);
4250                 /* put BG */
4251                 wcd9335_disable_master_bias(wcd);
4252                 clk_disable_unprepare(wcd->mclk);
4253                 wcd9335_cdc_sido_ccl_enable(wcd, false);
4254         }
4255 err:
4256         return ret;
4257 }
4258
4259 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd,
4260                                              enum wcd9335_sido_voltage req_mv)
4261 {
4262         struct snd_soc_component *comp = wcd->component;
4263         int vout_d_val;
4264
4265         if (req_mv == wcd->sido_voltage)
4266                 return;
4267
4268         /* compute the vout_d step value */
4269         vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) &
4270                         WCD9335_ANA_BUCK_VOUT_MASK;
4271         snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val);
4272         snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4273                                 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4274                                 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE);
4275
4276         /* 1 msec sleep required after SIDO Vout_D voltage change */
4277         usleep_range(1000, 1100);
4278         wcd->sido_voltage = req_mv;
4279         snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4280                                 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4281                                 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE);
4282 }
4283
4284 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd,
4285                                              enum wcd9335_sido_voltage req_mv)
4286 {
4287         int ret = 0;
4288
4289         /* enable mclk before setting SIDO voltage */
4290         ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4291         if (ret) {
4292                 dev_err(wcd->dev, "Ext clk enable failed\n");
4293                 goto err;
4294         }
4295
4296         wcd9335_codec_apply_sido_voltage(wcd, req_mv);
4297         wcd9335_cdc_req_mclk_enable(wcd, false);
4298
4299 err:
4300         return ret;
4301 }
4302
4303 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component,
4304                                       int enable)
4305 {
4306         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4307         int ret;
4308
4309         if (enable) {
4310                 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4311                 if (ret)
4312                         return ret;
4313
4314                 wcd9335_codec_apply_sido_voltage(wcd,
4315                                 SIDO_VOLTAGE_NOMINAL_MV);
4316         } else {
4317                 wcd9335_codec_update_sido_voltage(wcd,
4318                                         wcd->sido_voltage);
4319                 wcd9335_cdc_req_mclk_enable(wcd, false);
4320         }
4321
4322         return 0;
4323 }
4324
4325 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w,
4326                                      struct snd_kcontrol *kc, int event)
4327 {
4328         struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4329
4330         switch (event) {
4331         case SND_SOC_DAPM_PRE_PMU:
4332                 return _wcd9335_codec_enable_mclk(comp, true);
4333         case SND_SOC_DAPM_POST_PMD:
4334                 return _wcd9335_codec_enable_mclk(comp, false);
4335         }
4336
4337         return 0;
4338 }
4339
4340 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = {
4341         /* TODO SPK1 & SPK2 OUT*/
4342         SND_SOC_DAPM_OUTPUT("EAR"),
4343         SND_SOC_DAPM_OUTPUT("HPHL"),
4344         SND_SOC_DAPM_OUTPUT("HPHR"),
4345         SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4346         SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4347         SND_SOC_DAPM_OUTPUT("LINEOUT3"),
4348         SND_SOC_DAPM_OUTPUT("LINEOUT4"),
4349         SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4350                                 AIF1_PB, 0, wcd9335_codec_enable_slim,
4351                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4352         SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4353                                 AIF2_PB, 0, wcd9335_codec_enable_slim,
4354                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4355         SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4356                                 AIF3_PB, 0, wcd9335_codec_enable_slim,
4357                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4358         SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4359                                 AIF4_PB, 0, wcd9335_codec_enable_slim,
4360                                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4361         SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0,
4362                                 &slim_rx_mux[WCD9335_RX0]),
4363         SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0,
4364                                 &slim_rx_mux[WCD9335_RX1]),
4365         SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0,
4366                                 &slim_rx_mux[WCD9335_RX2]),
4367         SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0,
4368                                 &slim_rx_mux[WCD9335_RX3]),
4369         SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0,
4370                                 &slim_rx_mux[WCD9335_RX4]),
4371         SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0,
4372                                 &slim_rx_mux[WCD9335_RX5]),
4373         SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0,
4374                                 &slim_rx_mux[WCD9335_RX6]),
4375         SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0,
4376                                 &slim_rx_mux[WCD9335_RX7]),
4377         SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4378         SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4379         SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4380         SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4381         SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4382         SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4383         SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4384         SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4385         SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
4386                         5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path,
4387                         SND_SOC_DAPM_POST_PMU),
4388         SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
4389                         5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path,
4390                         SND_SOC_DAPM_POST_PMU),
4391         SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
4392                         5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path,
4393                         SND_SOC_DAPM_POST_PMU),
4394         SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
4395                         5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path,
4396                         SND_SOC_DAPM_POST_PMU),
4397         SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
4398                         5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path,
4399                         SND_SOC_DAPM_POST_PMU),
4400         SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
4401                         5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path,
4402                         SND_SOC_DAPM_POST_PMU),
4403         SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
4404                         5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path,
4405                         SND_SOC_DAPM_POST_PMU),
4406         SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
4407                         5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path,
4408                         SND_SOC_DAPM_POST_PMU),
4409         SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
4410                         5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path,
4411                         SND_SOC_DAPM_POST_PMU),
4412         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4413                 &rx_int0_1_mix_inp0_mux),
4414         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4415                 &rx_int0_1_mix_inp1_mux),
4416         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4417                 &rx_int0_1_mix_inp2_mux),
4418         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4419                 &rx_int1_1_mix_inp0_mux),
4420         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4421                 &rx_int1_1_mix_inp1_mux),
4422         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4423                 &rx_int1_1_mix_inp2_mux),
4424         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4425                 &rx_int2_1_mix_inp0_mux),
4426         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4427                 &rx_int2_1_mix_inp1_mux),
4428         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4429                 &rx_int2_1_mix_inp2_mux),
4430         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4431                 &rx_int3_1_mix_inp0_mux),
4432         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4433                 &rx_int3_1_mix_inp1_mux),
4434         SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4435                 &rx_int3_1_mix_inp2_mux),
4436         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4437                 &rx_int4_1_mix_inp0_mux),
4438         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4439                 &rx_int4_1_mix_inp1_mux),
4440         SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4441                 &rx_int4_1_mix_inp2_mux),
4442         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4443                 &rx_int5_1_mix_inp0_mux),
4444         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4445                 &rx_int5_1_mix_inp1_mux),
4446         SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4447                 &rx_int5_1_mix_inp2_mux),
4448         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4449                 &rx_int6_1_mix_inp0_mux),
4450         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4451                 &rx_int6_1_mix_inp1_mux),
4452         SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4453                 &rx_int6_1_mix_inp2_mux),
4454         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4455                 &rx_int7_1_mix_inp0_mux),
4456         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4457                 &rx_int7_1_mix_inp1_mux),
4458         SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4459                 &rx_int7_1_mix_inp2_mux),
4460         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4461                 &rx_int8_1_mix_inp0_mux),
4462         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4463                 &rx_int8_1_mix_inp1_mux),
4464         SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4465                 &rx_int8_1_mix_inp2_mux),
4466
4467         SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4468         SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4469         SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4470         SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4471         SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4472         SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4473         SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4474         SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4475         SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4476         SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4477         SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4478         SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4479         SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4480         SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4481         SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4482         SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4483         SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4484         SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4485
4486         SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4487         SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4488         SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4489         SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4490         SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4491         SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4492         SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4493         SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4494         SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4495
4496         SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4497                 &rx_int0_dem_inp_mux),
4498         SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4499                 &rx_int1_dem_inp_mux),
4500         SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4501                 &rx_int2_dem_inp_mux),
4502
4503         SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
4504                 INTERP_EAR, 0, &rx_int0_interp_mux,
4505                 wcd9335_codec_enable_interpolator,
4506                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4507                 SND_SOC_DAPM_POST_PMD),
4508         SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
4509                 INTERP_HPHL, 0, &rx_int1_interp_mux,
4510                 wcd9335_codec_enable_interpolator,
4511                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4512                 SND_SOC_DAPM_POST_PMD),
4513         SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
4514                 INTERP_HPHR, 0, &rx_int2_interp_mux,
4515                 wcd9335_codec_enable_interpolator,
4516                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4517                 SND_SOC_DAPM_POST_PMD),
4518         SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
4519                 INTERP_LO1, 0, &rx_int3_interp_mux,
4520                 wcd9335_codec_enable_interpolator,
4521                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4522                 SND_SOC_DAPM_POST_PMD),
4523         SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
4524                 INTERP_LO2, 0, &rx_int4_interp_mux,
4525                 wcd9335_codec_enable_interpolator,
4526                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4527                 SND_SOC_DAPM_POST_PMD),
4528         SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
4529                 INTERP_LO3, 0, &rx_int5_interp_mux,
4530                 wcd9335_codec_enable_interpolator,
4531                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4532                 SND_SOC_DAPM_POST_PMD),
4533         SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
4534                 INTERP_LO4, 0, &rx_int6_interp_mux,
4535                 wcd9335_codec_enable_interpolator,
4536                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4537                 SND_SOC_DAPM_POST_PMD),
4538         SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
4539                 INTERP_SPKR1, 0, &rx_int7_interp_mux,
4540                 wcd9335_codec_enable_interpolator,
4541                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4542                 SND_SOC_DAPM_POST_PMD),
4543         SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
4544                 INTERP_SPKR2, 0, &rx_int8_interp_mux,
4545                 wcd9335_codec_enable_interpolator,
4546                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4547                 SND_SOC_DAPM_POST_PMD),
4548
4549         SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4550                 0, 0, wcd9335_codec_ear_dac_event,
4551                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4552                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4553         SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH,
4554                 5, 0, wcd9335_codec_hphl_dac_event,
4555                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4556                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4557         SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH,
4558                 4, 0, wcd9335_codec_hphr_dac_event,
4559                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4560                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4561         SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4562                 0, 0, wcd9335_codec_lineout_dac_event,
4563                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4564         SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4565                 0, 0, wcd9335_codec_lineout_dac_event,
4566                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4567         SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
4568                 0, 0, wcd9335_codec_lineout_dac_event,
4569                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4570         SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
4571                 0, 0, wcd9335_codec_lineout_dac_event,
4572                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4573         SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0,
4574                            wcd9335_codec_enable_hphl_pa,
4575                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4576                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4577         SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0,
4578                            wcd9335_codec_enable_hphr_pa,
4579                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4580                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4581         SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
4582                            wcd9335_codec_enable_ear_pa,
4583                            SND_SOC_DAPM_POST_PMU |
4584                            SND_SOC_DAPM_POST_PMD),
4585         SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
4586                            wcd9335_codec_enable_lineout_pa,
4587                            SND_SOC_DAPM_POST_PMU |
4588                            SND_SOC_DAPM_POST_PMD),
4589         SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
4590                            wcd9335_codec_enable_lineout_pa,
4591                            SND_SOC_DAPM_POST_PMU |
4592                            SND_SOC_DAPM_POST_PMD),
4593         SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
4594                            wcd9335_codec_enable_lineout_pa,
4595                            SND_SOC_DAPM_POST_PMU |
4596                            SND_SOC_DAPM_POST_PMD),
4597         SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
4598                            wcd9335_codec_enable_lineout_pa,
4599                            SND_SOC_DAPM_POST_PMU |
4600                            SND_SOC_DAPM_POST_PMD),
4601         SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
4602                 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
4603                 SND_SOC_DAPM_POST_PMD),
4604         SND_SOC_DAPM_SUPPLY("MCLK",  SND_SOC_NOPM, 0, 0,
4605                 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU |
4606                 SND_SOC_DAPM_POST_PMD),
4607
4608         /* TX */
4609         SND_SOC_DAPM_INPUT("AMIC1"),
4610         SND_SOC_DAPM_INPUT("AMIC2"),
4611         SND_SOC_DAPM_INPUT("AMIC3"),
4612         SND_SOC_DAPM_INPUT("AMIC4"),
4613         SND_SOC_DAPM_INPUT("AMIC5"),
4614         SND_SOC_DAPM_INPUT("AMIC6"),
4615
4616         SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4617                 AIF1_CAP, 0, wcd9335_codec_enable_slim,
4618                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4619
4620         SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4621                 AIF2_CAP, 0, wcd9335_codec_enable_slim,
4622                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4623
4624         SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4625                 AIF3_CAP, 0, wcd9335_codec_enable_slim,
4626                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4627
4628         SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
4629                                wcd9335_codec_enable_micbias,
4630                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4631                                SND_SOC_DAPM_POST_PMD),
4632         SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
4633                                wcd9335_codec_enable_micbias,
4634                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4635                                SND_SOC_DAPM_POST_PMD),
4636         SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
4637                                wcd9335_codec_enable_micbias,
4638                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4639                                SND_SOC_DAPM_POST_PMD),
4640         SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
4641                                wcd9335_codec_enable_micbias,
4642                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4643                                SND_SOC_DAPM_POST_PMD),
4644
4645         SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
4646                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4647         SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
4648                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4649         SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
4650                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4651         SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
4652                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4653         SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
4654                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4655         SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
4656                            wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4657
4658         /* Digital Mic Inputs */
4659         SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4660                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4661                 SND_SOC_DAPM_POST_PMD),
4662
4663         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4664                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4665                 SND_SOC_DAPM_POST_PMD),
4666
4667         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4668                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4669                 SND_SOC_DAPM_POST_PMD),
4670
4671         SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4672                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4673                 SND_SOC_DAPM_POST_PMD),
4674
4675         SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4676                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4677                 SND_SOC_DAPM_POST_PMD),
4678
4679         SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4680                 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4681                 SND_SOC_DAPM_POST_PMD),
4682
4683         SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
4684                 &tx_dmic_mux0),
4685         SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
4686                 &tx_dmic_mux1),
4687         SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
4688                 &tx_dmic_mux2),
4689         SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
4690                 &tx_dmic_mux3),
4691         SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
4692                 &tx_dmic_mux4),
4693         SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
4694                 &tx_dmic_mux5),
4695         SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
4696                 &tx_dmic_mux6),
4697         SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
4698                 &tx_dmic_mux7),
4699         SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
4700                 &tx_dmic_mux8),
4701
4702         SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
4703                 &tx_amic_mux0),
4704         SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
4705                 &tx_amic_mux1),
4706         SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
4707                 &tx_amic_mux2),
4708         SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
4709                 &tx_amic_mux3),
4710         SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
4711                 &tx_amic_mux4),
4712         SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
4713                 &tx_amic_mux5),
4714         SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
4715                 &tx_amic_mux6),
4716         SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
4717                 &tx_amic_mux7),
4718         SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
4719                 &tx_amic_mux8),
4720
4721         SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4722                 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
4723
4724         SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4725                 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
4726
4727         SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4728                 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
4729
4730         SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0,
4731                 &sb_tx0_mux),
4732         SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0,
4733                 &sb_tx1_mux),
4734         SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0,
4735                 &sb_tx2_mux),
4736         SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0,
4737                 &sb_tx3_mux),
4738         SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0,
4739                 &sb_tx4_mux),
4740         SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0,
4741                 &sb_tx5_mux),
4742         SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0,
4743                 &sb_tx6_mux),
4744         SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0,
4745                 &sb_tx7_mux),
4746         SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0,
4747                 &sb_tx8_mux),
4748
4749         SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
4750                            &tx_adc_mux0, wcd9335_codec_enable_dec,
4751                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4752                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4753
4754         SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
4755                            &tx_adc_mux1, wcd9335_codec_enable_dec,
4756                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4757                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4758
4759         SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
4760                            &tx_adc_mux2, wcd9335_codec_enable_dec,
4761                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4762                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4763
4764         SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
4765                            &tx_adc_mux3, wcd9335_codec_enable_dec,
4766                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4767                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4768
4769         SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
4770                            &tx_adc_mux4, wcd9335_codec_enable_dec,
4771                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4772                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4773
4774         SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
4775                            &tx_adc_mux5, wcd9335_codec_enable_dec,
4776                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4777                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4778
4779         SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
4780                            &tx_adc_mux6, wcd9335_codec_enable_dec,
4781                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4782                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4783
4784         SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
4785                            &tx_adc_mux7, wcd9335_codec_enable_dec,
4786                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4787                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4788
4789         SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
4790                            &tx_adc_mux8, wcd9335_codec_enable_dec,
4791                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4792                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4793 };
4794
4795 static void wcd9335_enable_sido_buck(struct snd_soc_component *component)
4796 {
4797         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4798
4799         snd_soc_component_update_bits(component, WCD9335_ANA_RCO,
4800                                         WCD9335_ANA_RCO_BG_EN_MASK,
4801                                         WCD9335_ANA_RCO_BG_ENABLE);
4802         snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4803                                         WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK,
4804                                         WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT);
4805         /* 100us sleep needed after IREF settings */
4806         usleep_range(100, 110);
4807         snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4808                                         WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK,
4809                                         WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT);
4810         /* 100us sleep needed after VREF settings */
4811         usleep_range(100, 110);
4812         wcd->sido_input_src = SIDO_SOURCE_RCO_BG;
4813 }
4814
4815 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp)
4816 {
4817         _wcd9335_codec_enable_mclk(comp, true);
4818         snd_soc_component_update_bits(comp,
4819                                 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
4820                                 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK,
4821                                 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE);
4822         /*
4823          * 5ms sleep required after enabling efuse control
4824          * before checking the status.
4825          */
4826         usleep_range(5000, 5500);
4827
4828         if (!(snd_soc_component_read(comp,
4829                                         WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
4830                                         WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
4831                 WARN(1, "%s: Efuse sense is not complete\n", __func__);
4832
4833         wcd9335_enable_sido_buck(comp);
4834         _wcd9335_codec_enable_mclk(comp, false);
4835
4836         return 0;
4837 }
4838
4839 static void wcd9335_codec_init(struct snd_soc_component *component)
4840 {
4841         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4842         int i;
4843
4844         /* ungate MCLK and set clk rate */
4845         regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE,
4846                                 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0);
4847
4848         regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4849                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4850                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4851
4852         for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++)
4853                 snd_soc_component_update_bits(component,
4854                                         wcd9335_codec_reg_init[i].reg,
4855                                         wcd9335_codec_reg_init[i].mask,
4856                                         wcd9335_codec_reg_init[i].val);
4857
4858         wcd9335_enable_efuse_sensing(component);
4859 }
4860
4861 static int wcd9335_codec_probe(struct snd_soc_component *component)
4862 {
4863         struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4864         int ret;
4865         int i;
4866
4867         snd_soc_component_init_regmap(component, wcd->regmap);
4868         /* Class-H Init*/
4869         wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335);
4870         if (IS_ERR(wcd->clsh_ctrl))
4871                 return PTR_ERR(wcd->clsh_ctrl);
4872
4873         /* Default HPH Mode to Class-H HiFi */
4874         wcd->hph_mode = CLS_H_HIFI;
4875         wcd->component = component;
4876
4877         wcd9335_codec_init(component);
4878
4879         for (i = 0; i < NUM_CODEC_DAIS; i++)
4880                 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
4881
4882         ret = wcd9335_setup_irqs(wcd);
4883         if (ret)
4884                 goto free_clsh_ctrl;
4885
4886         return 0;
4887
4888 free_clsh_ctrl:
4889         wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4890         return ret;
4891 }
4892
4893 static void wcd9335_codec_remove(struct snd_soc_component *comp)
4894 {
4895         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4896
4897         wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4898         wcd9335_teardown_irqs(wcd);
4899 }
4900
4901 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,
4902                                     int clk_id, int source,
4903                                     unsigned int freq, int dir)
4904 {
4905         struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4906
4907         wcd->mclk_rate = freq;
4908
4909         if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ)
4910                 snd_soc_component_update_bits(comp,
4911                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4912                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4913                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ);
4914         else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
4915                 snd_soc_component_update_bits(comp,
4916                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4917                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4918                                 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4919
4920         return clk_set_rate(wcd->mclk, freq);
4921 }
4922
4923 static const struct snd_soc_component_driver wcd9335_component_drv = {
4924         .probe = wcd9335_codec_probe,
4925         .remove = wcd9335_codec_remove,
4926         .set_sysclk = wcd9335_codec_set_sysclk,
4927         .controls = wcd9335_snd_controls,
4928         .num_controls = ARRAY_SIZE(wcd9335_snd_controls),
4929         .dapm_widgets = wcd9335_dapm_widgets,
4930         .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets),
4931         .dapm_routes = wcd9335_audio_map,
4932         .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map),
4933         .endianness = 1,
4934 };
4935
4936 static int wcd9335_probe(struct wcd9335_codec *wcd)
4937 {
4938         struct device *dev = wcd->dev;
4939
4940         memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs));
4941         memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs));
4942
4943         wcd->sido_input_src = SIDO_SOURCE_INTERNAL;
4944         wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
4945
4946         return devm_snd_soc_register_component(dev, &wcd9335_component_drv,
4947                                                wcd9335_slim_dais,
4948                                                ARRAY_SIZE(wcd9335_slim_dais));
4949 }
4950
4951 static const struct regmap_range_cfg wcd9335_ranges[] = {
4952         {
4953                 .name = "WCD9335",
4954                 .range_min =  0x0,
4955                 .range_max =  WCD9335_MAX_REGISTER,
4956                 .selector_reg = WCD9335_SEL_REGISTER,
4957                 .selector_mask = 0xff,
4958                 .selector_shift = 0,
4959                 .window_start = 0x800,
4960                 .window_len = 0x100,
4961         },
4962 };
4963
4964 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
4965 {
4966         switch (reg) {
4967         case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3:
4968         case WCD9335_ANA_MBHC_RESULT_3:
4969         case WCD9335_ANA_MBHC_RESULT_2:
4970         case WCD9335_ANA_MBHC_RESULT_1:
4971         case WCD9335_ANA_MBHC_MECH:
4972         case WCD9335_ANA_MBHC_ELECT:
4973         case WCD9335_ANA_MBHC_ZDET:
4974         case WCD9335_ANA_MICB2:
4975         case WCD9335_ANA_RCO:
4976         case WCD9335_ANA_BIAS:
4977                 return true;
4978         default:
4979                 return false;
4980         }
4981 }
4982
4983 static struct regmap_config wcd9335_regmap_config = {
4984         .reg_bits = 16,
4985         .val_bits = 8,
4986         .cache_type = REGCACHE_RBTREE,
4987         .max_register = WCD9335_MAX_REGISTER,
4988         .can_multi_write = true,
4989         .ranges = wcd9335_ranges,
4990         .num_ranges = ARRAY_SIZE(wcd9335_ranges),
4991         .volatile_reg = wcd9335_is_volatile_register,
4992 };
4993
4994 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = {
4995         {
4996                 .name = "WCD9335-IFC-DEV",
4997                 .range_min =  0x0,
4998                 .range_max = WCD9335_MAX_REGISTER,
4999                 .selector_reg = WCD9335_SEL_REGISTER,
5000                 .selector_mask = 0xfff,
5001                 .selector_shift = 0,
5002                 .window_start = 0x800,
5003                 .window_len = 0x400,
5004         },
5005 };
5006
5007 static struct regmap_config wcd9335_ifc_regmap_config = {
5008         .reg_bits = 16,
5009         .val_bits = 8,
5010         .can_multi_write = true,
5011         .max_register = WCD9335_MAX_REGISTER,
5012         .ranges = wcd9335_ifc_ranges,
5013         .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges),
5014 };
5015
5016 static const struct regmap_irq wcd9335_codec_irqs[] = {
5017         /* INTR_REG 0 */
5018         [WCD9335_IRQ_SLIMBUS] = {
5019                 .reg_offset = 0,
5020                 .mask = BIT(0),
5021                 .type = {
5022                         .type_reg_offset = 0,
5023                         .types_supported = IRQ_TYPE_EDGE_BOTH,
5024                         .type_reg_mask  = BIT(0),
5025                 },
5026         },
5027 };
5028
5029 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = {
5030         .name = "wcd9335_pin1_irq",
5031         .status_base = WCD9335_INTR_PIN1_STATUS0,
5032         .mask_base = WCD9335_INTR_PIN1_MASK0,
5033         .ack_base = WCD9335_INTR_PIN1_CLEAR0,
5034         .type_base = WCD9335_INTR_LEVEL0,
5035         .num_type_reg = 4,
5036         .num_regs = 4,
5037         .irqs = wcd9335_codec_irqs,
5038         .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs),
5039 };
5040
5041 static int wcd9335_parse_dt(struct wcd9335_codec *wcd)
5042 {
5043         struct device *dev = wcd->dev;
5044         struct device_node *np = dev->of_node;
5045         int ret;
5046
5047         wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0);
5048         if (wcd->reset_gpio < 0) {
5049                 dev_err(dev, "Reset GPIO missing from DT\n");
5050                 return wcd->reset_gpio;
5051         }
5052
5053         wcd->mclk = devm_clk_get(dev, "mclk");
5054         if (IS_ERR(wcd->mclk)) {
5055                 dev_err(dev, "mclk not found\n");
5056                 return PTR_ERR(wcd->mclk);
5057         }
5058
5059         wcd->native_clk = devm_clk_get(dev, "slimbus");
5060         if (IS_ERR(wcd->native_clk)) {
5061                 dev_err(dev, "slimbus clock not found\n");
5062                 return PTR_ERR(wcd->native_clk);
5063         }
5064
5065         wcd->supplies[0].supply = "vdd-buck";
5066         wcd->supplies[1].supply = "vdd-buck-sido";
5067         wcd->supplies[2].supply = "vdd-tx";
5068         wcd->supplies[3].supply = "vdd-rx";
5069         wcd->supplies[4].supply = "vdd-io";
5070
5071         ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies);
5072         if (ret) {
5073                 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
5074                 return ret;
5075         }
5076
5077         return 0;
5078 }
5079
5080 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd)
5081 {
5082         struct device *dev = wcd->dev;
5083         int ret;
5084
5085         ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies);
5086         if (ret) {
5087                 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
5088                 return ret;
5089         }
5090
5091         /*
5092          * For WCD9335, it takes about 600us for the Vout_A and
5093          * Vout_D to be ready after BUCK_SIDO is powered up.
5094          * SYS_RST_N shouldn't be pulled high during this time
5095          * Toggle the reset line to make sure the reset pulse is
5096          * correctly applied
5097          */
5098         usleep_range(600, 650);
5099
5100         gpio_direction_output(wcd->reset_gpio, 0);
5101         msleep(20);
5102         gpio_set_value(wcd->reset_gpio, 1);
5103         msleep(20);
5104
5105         return 0;
5106 }
5107
5108 static int wcd9335_bring_up(struct wcd9335_codec *wcd)
5109 {
5110         struct regmap *rm = wcd->regmap;
5111         int val, byte0;
5112
5113         regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
5114         regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
5115
5116         if ((val < 0) || (byte0 < 0)) {
5117                 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n");
5118                 return -EINVAL;
5119         }
5120
5121         if (byte0 == 0x1) {
5122                 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n");
5123                 wcd->version = WCD9335_VERSION_2_0;
5124                 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01);
5125                 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00);
5126                 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
5127                 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
5128                 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
5129                 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
5130                 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
5131                 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3);
5132         } else {
5133                 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n");
5134                 return -EINVAL;
5135         }
5136
5137         return 0;
5138 }
5139
5140 static int wcd9335_irq_init(struct wcd9335_codec *wcd)
5141 {
5142         int ret;
5143
5144         /*
5145          * INTR1 consists of all possible interrupt sources Ear OCP,
5146          * HPH OCP, MBHC, MAD, VBAT, and SVA
5147          * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA
5148          */
5149         wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1");
5150         if (wcd->intr1 < 0) {
5151                 if (wcd->intr1 != -EPROBE_DEFER)
5152                         dev_err(wcd->dev, "Unable to configure IRQ\n");
5153
5154                 return wcd->intr1;
5155         }
5156
5157         ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1,
5158                                  IRQF_TRIGGER_HIGH, 0,
5159                                  &wcd9335_regmap_irq1_chip, &wcd->irq_data);
5160         if (ret)
5161                 dev_err(wcd->dev, "Failed to register IRQ chip: %d\n", ret);
5162
5163         return ret;
5164 }
5165
5166 static int wcd9335_slim_probe(struct slim_device *slim)
5167 {
5168         struct device *dev = &slim->dev;
5169         struct wcd9335_codec *wcd;
5170         int ret;
5171
5172         wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5173         if (!wcd)
5174                 return  -ENOMEM;
5175
5176         wcd->dev = dev;
5177         ret = wcd9335_parse_dt(wcd);
5178         if (ret) {
5179                 dev_err(dev, "Error parsing DT: %d\n", ret);
5180                 return ret;
5181         }
5182
5183         ret = wcd9335_power_on_reset(wcd);
5184         if (ret)
5185                 return ret;
5186
5187         dev_set_drvdata(dev, wcd);
5188
5189         return 0;
5190 }
5191
5192 static int wcd9335_slim_status(struct slim_device *sdev,
5193                                enum slim_device_status status)
5194 {
5195         struct device *dev = &sdev->dev;
5196         struct device_node *ifc_dev_np;
5197         struct wcd9335_codec *wcd;
5198         int ret;
5199
5200         wcd = dev_get_drvdata(dev);
5201
5202         ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5203         if (!ifc_dev_np) {
5204                 dev_err(dev, "No Interface device found\n");
5205                 return -EINVAL;
5206         }
5207
5208         wcd->slim = sdev;
5209         wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np);
5210         of_node_put(ifc_dev_np);
5211         if (!wcd->slim_ifc_dev) {
5212                 dev_err(dev, "Unable to get SLIM Interface device\n");
5213                 return -EINVAL;
5214         }
5215
5216         slim_get_logical_addr(wcd->slim_ifc_dev);
5217
5218         wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config);
5219         if (IS_ERR(wcd->regmap)) {
5220                 dev_err(dev, "Failed to allocate slim register map\n");
5221                 return PTR_ERR(wcd->regmap);
5222         }
5223
5224         wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev,
5225                                                   &wcd9335_ifc_regmap_config);
5226         if (IS_ERR(wcd->if_regmap)) {
5227                 dev_err(dev, "Failed to allocate ifc register map\n");
5228                 return PTR_ERR(wcd->if_regmap);
5229         }
5230
5231         ret = wcd9335_bring_up(wcd);
5232         if (ret) {
5233                 dev_err(dev, "Failed to bringup WCD9335\n");
5234                 return ret;
5235         }
5236
5237         ret = wcd9335_irq_init(wcd);
5238         if (ret)
5239                 return ret;
5240
5241         wcd9335_probe(wcd);
5242
5243         return 0;
5244 }
5245
5246 static const struct slim_device_id wcd9335_slim_id[] = {
5247         {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0},
5248         {}
5249 };
5250 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id);
5251
5252 static struct slim_driver wcd9335_slim_driver = {
5253         .driver = {
5254                 .name = "wcd9335-slim",
5255         },
5256         .probe = wcd9335_slim_probe,
5257         .device_status = wcd9335_slim_status,
5258         .id_table = wcd9335_slim_id,
5259 };
5260
5261 module_slim_driver(wcd9335_slim_driver);
5262 MODULE_DESCRIPTION("WCD9335 slim driver");
5263 MODULE_LICENSE("GPL v2");
5264 MODULE_ALIAS("slim:217:1a0:*");