sound/soc/codecs/tscs454.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // tscs454.c -- TSCS454 ALSA SoC Audio driver
   3 // Copyright 2018 Tempo Semiconductor, Inc.
   4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
   5
   6 #include <linux/kernel.h>
   7 #include <linux/clk.h>
   8 #include <linux/device.h>
   9 #include <linux/regmap.h>
  10 #include <linux/i2c.h>
  11 #include <linux/err.h>
  12 #include <linux/string.h>
  13 #include <linux/module.h>
  14 #include <linux/delay.h>
  15 #include <linux/mutex.h>
  16
  17 #include <sound/tlv.h>
  18 #include <sound/pcm_params.h>
  19 #include <sound/pcm.h>
  20 #include <sound/soc.h>
  21 #include <sound/soc-dapm.h>
  22
  23 #include "tscs454.h"
  24
  25 static const unsigned int PLL_44_1K_RATE = (44100 * 256);
  26
  27 #define COEFF_SIZE 3
  28 #define BIQUAD_COEFF_COUNT 5
  29 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT)
  30
  31 #define COEFF_RAM_MAX_ADDR 0xcd
  32 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1)
  33 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT)
  34
  35 enum {
  36         TSCS454_DAI1_ID,
  37         TSCS454_DAI2_ID,
  38         TSCS454_DAI3_ID,
  39         TSCS454_DAI_COUNT,
  40 };
  41
  42 struct pll {
  43         int id;
  44         unsigned int users;
  45         struct mutex lock;
  46 };
  47
  48 static inline void pll_init(struct pll *pll, int id)
  49 {
  50         pll->id = id;
  51         mutex_init(&pll->lock);
  52 }
  53
  54 struct internal_rate {
  55         struct pll *pll;
  56 };
  57
  58 struct aif {
  59         unsigned int id;
  60         bool master;
  61         struct pll *pll;
  62 };
  63
  64 static inline void aif_init(struct aif *aif, unsigned int id)
  65 {
  66         aif->id = id;
  67 }
  68
  69 struct coeff_ram {
  70         u8 cache[COEFF_RAM_SIZE];
  71         bool synced;
  72         struct mutex lock;
  73 };
  74
  75 static inline void init_coeff_ram_cache(u8 *cache)
  76 {
  77         static const u8 norm_addrs[] = { 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19,
  78                 0x1f, 0x20, 0x25, 0x2a, 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45,
  79                 0x4a, 0x4f, 0x54, 0x59, 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74,
  80                 0x79, 0x7f, 0x80, 0x85, 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3,
  81                 0xa8, 0xad, 0xaf, 0xb0, 0xb5, 0xba, 0xbf, 0xc4, 0xc9};
  82         int i;
  83
  84         for (i = 0; i < ARRAY_SIZE(norm_addrs); i++)
  85                 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40;
  86 }
  87
  88 static inline void coeff_ram_init(struct coeff_ram *ram)
  89 {
  90         init_coeff_ram_cache(ram->cache);
  91         mutex_init(&ram->lock);
  92 }
  93
  94 struct aifs_status {
  95         u8 streams;
  96 };
  97
  98 static inline void set_aif_status_active(struct aifs_status *status,
  99                 int aif_id, bool playback)
 100 {
 101         u8 mask = 0x01 << (aif_id * 2 + !playback);
 102
 103         status->streams |= mask;
 104 }
 105
 106 static inline void set_aif_status_inactive(struct aifs_status *status,
 107                 int aif_id, bool playback)
 108 {
 109         u8 mask = ~(0x01 << (aif_id * 2 + !playback));
 110
 111         status->streams &= mask;
 112 }
 113
 114 static bool aifs_active(struct aifs_status *status)
 115 {
 116         return status->streams;
 117 }
 118
 119 static bool aif_active(struct aifs_status *status, int aif_id)
 120 {
 121         return (0x03 << aif_id * 2) & status->streams;
 122 }
 123
 124 struct tscs454 {
 125         struct regmap *regmap;
 126         struct aif aifs[TSCS454_DAI_COUNT];
 127
 128         struct aifs_status aifs_status;
 129         struct mutex aifs_status_lock;
 130
 131         struct pll pll1;
 132         struct pll pll2;
 133         struct internal_rate internal_rate;
 134
 135         struct coeff_ram dac_ram;
 136         struct coeff_ram spk_ram;
 137         struct coeff_ram sub_ram;
 138
 139         struct clk *sysclk;
 140         int sysclk_src_id;
 141         unsigned int bclk_freq;
 142 };
 143
 144 struct coeff_ram_ctl {
 145         unsigned int addr;
 146         struct soc_bytes_ext bytes_ext;
 147 };
 148
 149 static const struct reg_sequence tscs454_patch[] = {
 150         /* Assign ASRC out of the box so DAI 1 just works */
 151         { R_AUDIOMUX1, FV_ASRCIMUX_I2S1 | FV_I2S2MUX_I2S2 },
 152         { R_AUDIOMUX2, FV_ASRCOMUX_I2S1 | FV_DACMUX_I2S1 | FV_I2S3MUX_I2S3 },
 153         { R_AUDIOMUX3, FV_CLSSDMUX_I2S1 | FV_SUBMUX_I2S1_LR },
 154         { R_TDMCTL0, FV_TDMMD_256 },
 155         { VIRT_ADDR(0x0A, 0x13), 1 << 3 },
 156 };
 157
 158 static bool tscs454_volatile(struct device *dev, unsigned int reg)
 159 {
 160         switch (reg) {
 161         case R_PLLSTAT:
 162
 163         case R_SPKCRRDL:
 164         case R_SPKCRRDM:
 165         case R_SPKCRRDH:
 166         case R_SPKCRS:
 167
 168         case R_DACCRRDL:
 169         case R_DACCRRDM:
 170         case R_DACCRRDH:
 171         case R_DACCRS:
 172
 173         case R_SUBCRRDL:
 174         case R_SUBCRRDM:
 175         case R_SUBCRRDH:
 176         case R_SUBCRS:
 177                 return true;
 178         default:
 179                 return false;
 180         };
 181 }
 182
 183 static bool tscs454_writable(struct device *dev, unsigned int reg)
 184 {
 185         switch (reg) {
 186         case R_SPKCRRDL:
 187         case R_SPKCRRDM:
 188         case R_SPKCRRDH:
 189
 190         case R_DACCRRDL:
 191         case R_DACCRRDM:
 192         case R_DACCRRDH:
 193
 194         case R_SUBCRRDL:
 195         case R_SUBCRRDM:
 196         case R_SUBCRRDH:
 197                 return false;
 198         default:
 199                 return true;
 200         };
 201 }
 202
 203 static bool tscs454_readable(struct device *dev, unsigned int reg)
 204 {
 205         switch (reg) {
 206         case R_SPKCRWDL:
 207         case R_SPKCRWDM:
 208         case R_SPKCRWDH:
 209
 210         case R_DACCRWDL:
 211         case R_DACCRWDM:
 212         case R_DACCRWDH:
 213
 214         case R_SUBCRWDL:
 215         case R_SUBCRWDM:
 216         case R_SUBCRWDH:
 217                 return false;
 218         default:
 219                 return true;
 220         };
 221 }
 222
 223 static bool tscs454_precious(struct device *dev, unsigned int reg)
 224 {
 225         switch (reg) {
 226         case R_SPKCRWDL:
 227         case R_SPKCRWDM:
 228         case R_SPKCRWDH:
 229         case R_SPKCRRDL:
 230         case R_SPKCRRDM:
 231         case R_SPKCRRDH:
 232
 233         case R_DACCRWDL:
 234         case R_DACCRWDM:
 235         case R_DACCRWDH:
 236         case R_DACCRRDL:
 237         case R_DACCRRDM:
 238         case R_DACCRRDH:
 239
 240         case R_SUBCRWDL:
 241         case R_SUBCRWDM:
 242         case R_SUBCRWDH:
 243         case R_SUBCRRDL:
 244         case R_SUBCRRDM:
 245         case R_SUBCRRDH:
 246                 return true;
 247         default:
 248                 return false;
 249         };
 250 }
 251
 252 static const struct regmap_range_cfg tscs454_regmap_range_cfg = {
 253         .name = "Pages",
 254         .range_min = VIRT_BASE,
 255         .range_max = VIRT_ADDR(0xFE, 0x02),
 256         .selector_reg = R_PAGESEL,
 257         .selector_mask = 0xff,
 258         .selector_shift = 0,
 259         .window_start = 0,
 260         .window_len = 0x100,
 261 };
 262
 263 static struct regmap_config const tscs454_regmap_cfg = {
 264         .reg_bits = 8,
 265         .val_bits = 8,
 266         .writeable_reg = tscs454_writable,
 267         .readable_reg = tscs454_readable,
 268         .volatile_reg = tscs454_volatile,
 269         .precious_reg = tscs454_precious,
 270         .ranges = &tscs454_regmap_range_cfg,
 271         .num_ranges = 1,
 272         .max_register = VIRT_ADDR(0xFE, 0x02),
 273         .cache_type = REGCACHE_RBTREE,
 274 };
 275
 276 static inline int tscs454_data_init(struct tscs454 *tscs454,
 277                 struct i2c_client *i2c)
 278 {
 279         int i;
 280         int ret;
 281
 282         tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg);
 283         if (IS_ERR(tscs454->regmap)) {
 284                 ret = PTR_ERR(tscs454->regmap);
 285                 return ret;
 286         }
 287
 288         for (i = 0; i < TSCS454_DAI_COUNT; i++)
 289                 aif_init(&tscs454->aifs[i], i);
 290
 291         mutex_init(&tscs454->aifs_status_lock);
 292         pll_init(&tscs454->pll1, 1);
 293         pll_init(&tscs454->pll2, 2);
 294
 295         coeff_ram_init(&tscs454->dac_ram);
 296         coeff_ram_init(&tscs454->spk_ram);
 297         coeff_ram_init(&tscs454->sub_ram);
 298
 299         return 0;
 300 }
 301
 302 struct reg_setting {
 303         unsigned int addr;
 304         unsigned int val;
 305 };
 306
 307 static int coeff_ram_get(struct snd_kcontrol *kcontrol,
 308         struct snd_ctl_elem_value *ucontrol)
 309 {
 310         struct snd_soc_component *component =
 311                 snd_soc_kcontrol_component(kcontrol);
 312         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 313         struct coeff_ram_ctl *ctl =
 314                 (struct coeff_ram_ctl *)kcontrol->private_value;
 315         struct soc_bytes_ext *params = &ctl->bytes_ext;
 316         u8 *coeff_ram;
 317         struct mutex *coeff_ram_lock;
 318
 319         if (strstr(kcontrol->id.name, "DAC")) {
 320                 coeff_ram = tscs454->dac_ram.cache;
 321                 coeff_ram_lock = &tscs454->dac_ram.lock;
 322         } else if (strstr(kcontrol->id.name, "Speaker")) {
 323                 coeff_ram = tscs454->spk_ram.cache;
 324                 coeff_ram_lock = &tscs454->spk_ram.lock;
 325         } else if (strstr(kcontrol->id.name, "Sub")) {
 326                 coeff_ram = tscs454->sub_ram.cache;
 327                 coeff_ram_lock = &tscs454->sub_ram.lock;
 328         } else {
 329                 return -EINVAL;
 330         }
 331
 332         mutex_lock(coeff_ram_lock);
 333
 334         memcpy(ucontrol->value.bytes.data,
 335                 &coeff_ram[ctl->addr * COEFF_SIZE], params->max);
 336
 337         mutex_unlock(coeff_ram_lock);
 338
 339         return 0;
 340 }
 341
 342 #define DACCRSTAT_MAX_TRYS 10
 343 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram,
 344                 unsigned int r_stat, unsigned int r_addr, unsigned int r_wr,
 345                 unsigned int coeff_addr, unsigned int coeff_cnt)
 346 {
 347         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 348         unsigned int val;
 349         int cnt;
 350         int trys;
 351         int ret;
 352
 353         for (cnt = 0; cnt < coeff_cnt; cnt++, coeff_addr++) {
 354
 355                 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
 356                         val = snd_soc_component_read(component, r_stat);
 357                         if (!val)
 358                                 break;
 359                 }
 360
 361                 if (trys == DACCRSTAT_MAX_TRYS) {
 362                         ret = -EIO;
 363                         dev_err(component->dev,
 364                                 "Coefficient write error (%d)\n", ret);
 365                         return ret;
 366                 }
 367
 368                 ret = regmap_write(tscs454->regmap, r_addr, coeff_addr);
 369                 if (ret < 0) {
 370                         dev_err(component->dev,
 371                                 "Failed to write dac ram address (%d)\n", ret);
 372                         return ret;
 373                 }
 374
 375                 ret = regmap_bulk_write(tscs454->regmap, r_wr,
 376                         &coeff_ram[coeff_addr * COEFF_SIZE],
 377                         COEFF_SIZE);
 378                 if (ret < 0) {
 379                         dev_err(component->dev,
 380                                 "Failed to write dac ram (%d)\n", ret);
 381                         return ret;
 382                 }
 383         }
 384
 385         return 0;
 386 }
 387
 388 static int coeff_ram_put(struct snd_kcontrol *kcontrol,
 389         struct snd_ctl_elem_value *ucontrol)
 390 {
 391         struct snd_soc_component *component =
 392                 snd_soc_kcontrol_component(kcontrol);
 393         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 394         struct coeff_ram_ctl *ctl =
 395                 (struct coeff_ram_ctl *)kcontrol->private_value;
 396         struct soc_bytes_ext *params = &ctl->bytes_ext;
 397         unsigned int coeff_cnt = params->max / COEFF_SIZE;
 398         u8 *coeff_ram;
 399         struct mutex *coeff_ram_lock;
 400         bool *coeff_ram_synced;
 401         unsigned int r_stat;
 402         unsigned int r_addr;
 403         unsigned int r_wr;
 404         unsigned int val;
 405         int ret;
 406
 407         if (strstr(kcontrol->id.name, "DAC")) {
 408                 coeff_ram = tscs454->dac_ram.cache;
 409                 coeff_ram_lock = &tscs454->dac_ram.lock;
 410                 coeff_ram_synced = &tscs454->dac_ram.synced;
 411                 r_stat = R_DACCRS;
 412                 r_addr = R_DACCRADD;
 413                 r_wr = R_DACCRWDL;
 414         } else if (strstr(kcontrol->id.name, "Speaker")) {
 415                 coeff_ram = tscs454->spk_ram.cache;
 416                 coeff_ram_lock = &tscs454->spk_ram.lock;
 417                 coeff_ram_synced = &tscs454->spk_ram.synced;
 418                 r_stat = R_SPKCRS;
 419                 r_addr = R_SPKCRADD;
 420                 r_wr = R_SPKCRWDL;
 421         } else if (strstr(kcontrol->id.name, "Sub")) {
 422                 coeff_ram = tscs454->sub_ram.cache;
 423                 coeff_ram_lock = &tscs454->sub_ram.lock;
 424                 coeff_ram_synced = &tscs454->sub_ram.synced;
 425                 r_stat = R_SUBCRS;
 426                 r_addr = R_SUBCRADD;
 427                 r_wr = R_SUBCRWDL;
 428         } else {
 429                 return -EINVAL;
 430         }
 431
 432         mutex_lock(coeff_ram_lock);
 433
 434         *coeff_ram_synced = false;
 435
 436         memcpy(&coeff_ram[ctl->addr * COEFF_SIZE],
 437                 ucontrol->value.bytes.data, params->max);
 438
 439         mutex_lock(&tscs454->pll1.lock);
 440         mutex_lock(&tscs454->pll2.lock);
 441
 442         val = snd_soc_component_read(component, R_PLLSTAT);
 443         if (val) { /* PLLs locked */
 444                 ret = write_coeff_ram(component, coeff_ram,
 445                         r_stat, r_addr, r_wr,
 446                         ctl->addr, coeff_cnt);
 447                 if (ret < 0) {
 448                         dev_err(component->dev,
 449                                 "Failed to flush coeff ram cache (%d)\n", ret);
 450                         goto exit;
 451                 }
 452                 *coeff_ram_synced = true;
 453         }
 454
 455         ret = 0;
 456 exit:
 457         mutex_unlock(&tscs454->pll2.lock);
 458         mutex_unlock(&tscs454->pll1.lock);
 459         mutex_unlock(coeff_ram_lock);
 460
 461         return ret;
 462 }
 463
 464 static inline int coeff_ram_sync(struct snd_soc_component *component,
 465                 struct tscs454 *tscs454)
 466 {
 467         int ret;
 468
 469         mutex_lock(&tscs454->dac_ram.lock);
 470         if (!tscs454->dac_ram.synced) {
 471                 ret = write_coeff_ram(component, tscs454->dac_ram.cache,
 472                                 R_DACCRS, R_DACCRADD, R_DACCRWDL,
 473                                 0x00, COEFF_RAM_COEFF_COUNT);
 474                 if (ret < 0) {
 475                         mutex_unlock(&tscs454->dac_ram.lock);
 476                         return ret;
 477                 }
 478         }
 479         mutex_unlock(&tscs454->dac_ram.lock);
 480
 481         mutex_lock(&tscs454->spk_ram.lock);
 482         if (!tscs454->spk_ram.synced) {
 483                 ret = write_coeff_ram(component, tscs454->spk_ram.cache,
 484                                 R_SPKCRS, R_SPKCRADD, R_SPKCRWDL,
 485                                 0x00, COEFF_RAM_COEFF_COUNT);
 486                 if (ret < 0) {
 487                         mutex_unlock(&tscs454->spk_ram.lock);
 488                         return ret;
 489                 }
 490         }
 491         mutex_unlock(&tscs454->spk_ram.lock);
 492
 493         mutex_lock(&tscs454->sub_ram.lock);
 494         if (!tscs454->sub_ram.synced) {
 495                 ret = write_coeff_ram(component, tscs454->sub_ram.cache,
 496                                 R_SUBCRS, R_SUBCRADD, R_SUBCRWDL,
 497                                 0x00, COEFF_RAM_COEFF_COUNT);
 498                 if (ret < 0) {
 499                         mutex_unlock(&tscs454->sub_ram.lock);
 500                         return ret;
 501                 }
 502         }
 503         mutex_unlock(&tscs454->sub_ram.lock);
 504
 505         return 0;
 506 }
 507
 508 #define PLL_REG_SETTINGS_COUNT 11
 509 struct pll_ctl {
 510         int freq_in;
 511         struct reg_setting settings[PLL_REG_SETTINGS_COUNT];
 512 };
 513
 514 #define PLL_CTL(f, t, c1, r1, o1, f1l, f1h, c2, r2, o2, f2l, f2h)       \
 515         {                                                               \
 516                 .freq_in = f,                                           \
 517                 .settings = {                                           \
 518                         {R_PLL1CTL,     c1},                            \
 519                         {R_PLL1RDIV,    r1},                            \
 520                         {R_PLL1ODIV,    o1},                            \
 521                         {R_PLL1FDIVL,   f1l},                           \
 522                         {R_PLL1FDIVH,   f1h},                           \
 523                         {R_PLL2CTL,     c2},                            \
 524                         {R_PLL2RDIV,    r2},                            \
 525                         {R_PLL2ODIV,    o2},                            \
 526                         {R_PLL2FDIVL,   f2l},                           \
 527                         {R_PLL2FDIVH,   f2h},                           \
 528                         {R_TIMEBASE,    t},                             \
 529                 },                                                      \
 530         }
 531
 532 static const struct pll_ctl pll_ctls[] = {
 533         PLL_CTL(1411200, 0x05,
 534                 0xB9, 0x07, 0x02, 0xC3, 0x04,
 535                 0x5A, 0x02, 0x03, 0xE0, 0x01),
 536         PLL_CTL(1536000, 0x05,
 537                 0x5A, 0x02, 0x03, 0xE0, 0x01,
 538                 0x5A, 0x02, 0x03, 0xB9, 0x01),
 539         PLL_CTL(2822400, 0x0A,
 540                 0x63, 0x07, 0x04, 0xC3, 0x04,
 541                 0x62, 0x07, 0x03, 0x48, 0x03),
 542         PLL_CTL(3072000, 0x0B,
 543                 0x62, 0x07, 0x03, 0x48, 0x03,
 544                 0x5A, 0x04, 0x03, 0xB9, 0x01),
 545         PLL_CTL(5644800, 0x15,
 546                 0x63, 0x0E, 0x04, 0xC3, 0x04,
 547                 0x5A, 0x08, 0x03, 0xE0, 0x01),
 548         PLL_CTL(6144000, 0x17,
 549                 0x5A, 0x08, 0x03, 0xE0, 0x01,
 550                 0x5A, 0x08, 0x03, 0xB9, 0x01),
 551         PLL_CTL(12000000, 0x2E,
 552                 0x5B, 0x19, 0x03, 0x00, 0x03,
 553                 0x6A, 0x19, 0x05, 0x98, 0x04),
 554         PLL_CTL(19200000, 0x4A,
 555                 0x53, 0x14, 0x03, 0x80, 0x01,
 556                 0x5A, 0x19, 0x03, 0xB9, 0x01),
 557         PLL_CTL(22000000, 0x55,
 558                 0x6A, 0x37, 0x05, 0x00, 0x06,
 559                 0x62, 0x26, 0x03, 0x49, 0x02),
 560         PLL_CTL(22579200, 0x57,
 561                 0x62, 0x31, 0x03, 0x20, 0x03,
 562                 0x53, 0x1D, 0x03, 0xB3, 0x01),
 563         PLL_CTL(24000000, 0x5D,
 564                 0x53, 0x19, 0x03, 0x80, 0x01,
 565                 0x5B, 0x19, 0x05, 0x4C, 0x02),
 566         PLL_CTL(24576000, 0x5F,
 567                 0x53, 0x1D, 0x03, 0xB3, 0x01,
 568                 0x62, 0x40, 0x03, 0x72, 0x03),
 569         PLL_CTL(27000000, 0x68,
 570                 0x62, 0x4B, 0x03, 0x00, 0x04,
 571                 0x6A, 0x7D, 0x03, 0x20, 0x06),
 572         PLL_CTL(36000000, 0x8C,
 573                 0x5B, 0x4B, 0x03, 0x00, 0x03,
 574                 0x6A, 0x7D, 0x03, 0x98, 0x04),
 575         PLL_CTL(11289600, 0x2B,
 576                 0x6A, 0x31, 0x03, 0x40, 0x06,
 577                 0x5A, 0x12, 0x03, 0x1C, 0x02),
 578         PLL_CTL(26000000, 0x65,
 579                 0x63, 0x41, 0x05, 0x00, 0x06,
 580                 0x5A, 0x26, 0x03, 0xEF, 0x01),
 581         PLL_CTL(12288000, 0x2F,
 582                 0x5A, 0x12, 0x03, 0x1C, 0x02,
 583                 0x62, 0x20, 0x03, 0x72, 0x03),
 584         PLL_CTL(40000000, 0x9B,
 585                 0xA2, 0x7D, 0x03, 0x80, 0x04,
 586                 0x63, 0x7D, 0x05, 0xE4, 0x06),
 587         PLL_CTL(512000, 0x01,
 588                 0x62, 0x01, 0x03, 0xD0, 0x02,
 589                 0x5B, 0x01, 0x04, 0x72, 0x03),
 590         PLL_CTL(705600, 0x02,
 591                 0x62, 0x02, 0x03, 0x15, 0x04,
 592                 0x62, 0x01, 0x04, 0x80, 0x02),
 593         PLL_CTL(1024000, 0x03,
 594                 0x62, 0x02, 0x03, 0xD0, 0x02,
 595                 0x5B, 0x02, 0x04, 0x72, 0x03),
 596         PLL_CTL(2048000, 0x07,
 597                 0x62, 0x04, 0x03, 0xD0, 0x02,
 598                 0x5B, 0x04, 0x04, 0x72, 0x03),
 599         PLL_CTL(2400000, 0x08,
 600                 0x62, 0x05, 0x03, 0x00, 0x03,
 601                 0x63, 0x05, 0x05, 0x98, 0x04),
 602 };
 603
 604 static inline const struct pll_ctl *get_pll_ctl(unsigned long freq_in)
 605 {
 606         int i;
 607         struct pll_ctl const *pll_ctl = NULL;
 608
 609         for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i)
 610                 if (pll_ctls[i].freq_in == freq_in) {
 611                         pll_ctl = &pll_ctls[i];
 612                         break;
 613                 }
 614
 615         return pll_ctl;
 616 }
 617
 618 enum {
 619         PLL_INPUT_XTAL = 0,
 620         PLL_INPUT_MCLK1,
 621         PLL_INPUT_MCLK2,
 622         PLL_INPUT_BCLK,
 623 };
 624
 625 static int set_sysclk(struct snd_soc_component *component)
 626 {
 627         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 628         struct pll_ctl const *pll_ctl;
 629         unsigned long freq;
 630         int i;
 631         int ret;
 632
 633         if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
 634                 freq = clk_get_rate(tscs454->sysclk);
 635         else
 636                 freq = tscs454->bclk_freq;
 637         pll_ctl = get_pll_ctl(freq);
 638         if (!pll_ctl) {
 639                 ret = -EINVAL;
 640                 dev_err(component->dev,
 641                                 "Invalid PLL input %lu (%d)\n", freq, ret);
 642                 return ret;
 643         }
 644
 645         for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) {
 646                 ret = snd_soc_component_write(component,
 647                                 pll_ctl->settings[i].addr,
 648                                 pll_ctl->settings[i].val);
 649                 if (ret < 0) {
 650                         dev_err(component->dev,
 651                                         "Failed to set pll setting (%d)\n",
 652                                         ret);
 653                         return ret;
 654                 }
 655         }
 656
 657         return 0;
 658 }
 659
 660 static inline void reserve_pll(struct pll *pll)
 661 {
 662         mutex_lock(&pll->lock);
 663         pll->users++;
 664         mutex_unlock(&pll->lock);
 665 }
 666
 667 static inline void free_pll(struct pll *pll)
 668 {
 669         mutex_lock(&pll->lock);
 670         pll->users--;
 671         mutex_unlock(&pll->lock);
 672 }
 673
 674 static int pll_connected(struct snd_soc_dapm_widget *source,
 675                 struct snd_soc_dapm_widget *sink)
 676 {
 677         struct snd_soc_component *component =
 678                 snd_soc_dapm_to_component(source->dapm);
 679         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 680         int users;
 681
 682         if (strstr(source->name, "PLL 1")) {
 683                 mutex_lock(&tscs454->pll1.lock);
 684                 users = tscs454->pll1.users;
 685                 mutex_unlock(&tscs454->pll1.lock);
 686                 dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__,
 687                                 users);
 688         } else {
 689                 mutex_lock(&tscs454->pll2.lock);
 690                 users = tscs454->pll2.users;
 691                 mutex_unlock(&tscs454->pll2.lock);
 692                 dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__,
 693                                 users);
 694         }
 695
 696         return users;
 697 }
 698
 699 /*
 700  * PLL must be enabled after power up and must be disabled before power down
 701  * for proper clock switching.
 702  */
 703 static int pll_power_event(struct snd_soc_dapm_widget *w,
 704                 struct snd_kcontrol *kcontrol, int event)
 705 {
 706         struct snd_soc_component *component =
 707                 snd_soc_dapm_to_component(w->dapm);
 708         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 709         bool enable;
 710         bool pll1;
 711         unsigned int msk;
 712         unsigned int val;
 713         int ret;
 714
 715         if (strstr(w->name, "PLL 1"))
 716                 pll1 = true;
 717         else
 718                 pll1 = false;
 719
 720         msk = pll1 ? FM_PLLCTL_PLL1CLKEN : FM_PLLCTL_PLL2CLKEN;
 721
 722         if (event == SND_SOC_DAPM_POST_PMU)
 723                 enable = true;
 724         else
 725                 enable = false;
 726
 727         if (enable)
 728                 val = pll1 ? FV_PLL1CLKEN_ENABLE : FV_PLL2CLKEN_ENABLE;
 729         else
 730                 val = pll1 ? FV_PLL1CLKEN_DISABLE : FV_PLL2CLKEN_DISABLE;
 731
 732         ret = snd_soc_component_update_bits(component, R_PLLCTL, msk, val);
 733         if (ret < 0) {
 734                 dev_err(component->dev, "Failed to %s PLL %d  (%d)\n",
 735                                 enable ? "enable" : "disable",
 736                                 pll1 ? 1 : 2,
 737                                 ret);
 738                 return ret;
 739         }
 740
 741         if (enable) {
 742                 msleep(20); // Wait for lock
 743                 ret = coeff_ram_sync(component, tscs454);
 744                 if (ret < 0) {
 745                         dev_err(component->dev,
 746                                         "Failed to sync coeff ram (%d)\n", ret);
 747                         return ret;
 748                 }
 749         }
 750
 751         return 0;
 752 }
 753
 754 static inline int aif_set_master(struct snd_soc_component *component,
 755                 unsigned int aif_id, bool master)
 756 {
 757         unsigned int reg;
 758         unsigned int mask;
 759         unsigned int val;
 760         int ret;
 761
 762         switch (aif_id) {
 763         case TSCS454_DAI1_ID:
 764                 reg = R_I2SP1CTL;
 765                 break;
 766         case TSCS454_DAI2_ID:
 767                 reg = R_I2SP2CTL;
 768                 break;
 769         case TSCS454_DAI3_ID:
 770                 reg = R_I2SP3CTL;
 771                 break;
 772         default:
 773                 ret = -ENODEV;
 774                 dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret);
 775                 return ret;
 776         }
 777         mask = FM_I2SPCTL_PORTMS;
 778         val = master ? FV_PORTMS_MASTER : FV_PORTMS_SLAVE;
 779
 780         ret = snd_soc_component_update_bits(component, reg, mask, val);
 781         if (ret < 0) {
 782                 dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n",
 783                         aif_id, master ? "master" : "slave", ret);
 784                 return ret;
 785         }
 786
 787         return 0;
 788 }
 789
 790 static inline
 791 int aif_prepare(struct snd_soc_component *component, struct aif *aif)
 792 {
 793         int ret;
 794
 795         ret = aif_set_master(component, aif->id, aif->master);
 796         if (ret < 0)
 797                 return ret;
 798
 799         return 0;
 800 }
 801
 802 static inline int aif_free(struct snd_soc_component *component,
 803                 struct aif *aif, bool playback)
 804 {
 805         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
 806
 807         mutex_lock(&tscs454->aifs_status_lock);
 808
 809         dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id);
 810
 811         set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback);
 812
 813         dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n",
 814                 aif->id, tscs454->aifs_status.streams);
 815
 816         if (!aif_active(&tscs454->aifs_status, aif->id)) {
 817                 /* Do config in slave mode */
 818                 aif_set_master(component, aif->id, false);
 819                 dev_dbg(component->dev, "Freeing pll %d from aif %d\n",
 820                                 aif->pll->id, aif->id);
 821                 free_pll(aif->pll);
 822         }
 823
 824         if (!aifs_active(&tscs454->aifs_status)) {
 825                 dev_dbg(component->dev, "Freeing pll %d from ir\n",
 826                                 tscs454->internal_rate.pll->id);
 827                 free_pll(tscs454->internal_rate.pll);
 828         }
 829
 830         mutex_unlock(&tscs454->aifs_status_lock);
 831
 832         return 0;
 833 }
 834
 835 /* R_PLLCTL PG 0 ADDR 0x15 */
 836 static char const * const bclk_sel_txt[] = {
 837                 "BCLK 1", "BCLK 2", "BCLK 3"};
 838
 839 static struct soc_enum const bclk_sel_enum =
 840                 SOC_ENUM_SINGLE(R_PLLCTL, FB_PLLCTL_BCLKSEL,
 841                                 ARRAY_SIZE(bclk_sel_txt), bclk_sel_txt);
 842
 843 /* R_ISRC PG 0 ADDR 0x16 */
 844 static char const * const isrc_br_txt[] = {
 845                 "44.1kHz", "48kHz"};
 846
 847 static struct soc_enum const isrc_br_enum =
 848                 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBR,
 849                                 ARRAY_SIZE(isrc_br_txt), isrc_br_txt);
 850
 851 static char const * const isrc_bm_txt[] = {
 852                 "0.25x", "0.5x", "1.0x", "2.0x"};
 853
 854 static struct soc_enum const isrc_bm_enum =
 855                 SOC_ENUM_SINGLE(R_ISRC, FB_ISRC_IBM,
 856                                 ARRAY_SIZE(isrc_bm_txt), isrc_bm_txt);
 857
 858 /* R_SCLKCTL PG 0 ADDR 0x18 */
 859 static char const * const modular_rate_txt[] = {
 860         "Reserved", "Half", "Full", "Auto",};
 861
 862 static struct soc_enum const adc_modular_rate_enum =
 863         SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_ASDM,
 864                         ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
 865
 866 static struct soc_enum const dac_modular_rate_enum =
 867         SOC_ENUM_SINGLE(R_SCLKCTL, FB_SCLKCTL_DSDM,
 868                         ARRAY_SIZE(modular_rate_txt), modular_rate_txt);
 869
 870 /* R_I2SIDCTL PG 0 ADDR 0x38 */
 871 static char const * const data_ctrl_txt[] = {
 872         "L/R", "L/L", "R/R", "R/L"};
 873
 874 static struct soc_enum const data_in_ctrl_enums[] = {
 875         SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI1DCTL,
 876                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 877         SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI2DCTL,
 878                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 879         SOC_ENUM_SINGLE(R_I2SIDCTL, FB_I2SIDCTL_I2SI3DCTL,
 880                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 881 };
 882
 883 /* R_I2SODCTL PG 0 ADDR 0x39 */
 884 static struct soc_enum const data_out_ctrl_enums[] = {
 885         SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO1DCTL,
 886                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 887         SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO2DCTL,
 888                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 889         SOC_ENUM_SINGLE(R_I2SODCTL, FB_I2SODCTL_I2SO3DCTL,
 890                         ARRAY_SIZE(data_ctrl_txt), data_ctrl_txt),
 891 };
 892
 893 /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
 894 static char const * const asrc_mux_txt[] = {
 895                 "None", "DAI 1", "DAI 2", "DAI 3"};
 896
 897 static struct soc_enum const asrc_in_mux_enum =
 898                 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_ASRCIMUX,
 899                                 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
 900
 901 static char const * const dai_mux_txt[] = {
 902                 "CH 0_1", "CH 2_3", "CH 4_5", "ADC/DMic 1",
 903                 "DMic 2", "ClassD", "DAC", "Sub"};
 904
 905 static struct soc_enum const dai2_mux_enum =
 906                 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S2MUX,
 907                                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
 908
 909 static struct snd_kcontrol_new const dai2_mux_dapm_enum =
 910                 SOC_DAPM_ENUM("DAI 2 Mux",  dai2_mux_enum);
 911
 912 static struct soc_enum const dai1_mux_enum =
 913                 SOC_ENUM_SINGLE(R_AUDIOMUX1, FB_AUDIOMUX1_I2S1MUX,
 914                                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
 915
 916 static struct snd_kcontrol_new const dai1_mux_dapm_enum =
 917                 SOC_DAPM_ENUM("DAI 1 Mux", dai1_mux_enum);
 918
 919 /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
 920 static struct soc_enum const asrc_out_mux_enum =
 921                 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_ASRCOMUX,
 922                                 ARRAY_SIZE(asrc_mux_txt), asrc_mux_txt);
 923
 924 static struct soc_enum const dac_mux_enum =
 925                 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_DACMUX,
 926                                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
 927
 928 static struct snd_kcontrol_new const dac_mux_dapm_enum =
 929                 SOC_DAPM_ENUM("DAC Mux", dac_mux_enum);
 930
 931 static struct soc_enum const dai3_mux_enum =
 932                 SOC_ENUM_SINGLE(R_AUDIOMUX2, FB_AUDIOMUX2_I2S3MUX,
 933                                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
 934
 935 static struct snd_kcontrol_new const dai3_mux_dapm_enum =
 936                 SOC_DAPM_ENUM("DAI 3 Mux", dai3_mux_enum);
 937
 938 /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
 939 static char const * const sub_mux_txt[] = {
 940                 "CH 0", "CH 1", "CH 0 + 1",
 941                 "CH 2", "CH 3", "CH 2 + 3",
 942                 "CH 4", "CH 5", "CH 4 + 5",
 943                 "ADC/DMic 1 Left", "ADC/DMic 1 Right",
 944                 "ADC/DMic 1 Left Plus Right",
 945                 "DMic 2 Left", "DMic 2 Right", "DMic 2 Left Plus Right",
 946                 "ClassD Left", "ClassD Right", "ClassD Left Plus Right"};
 947
 948 static struct soc_enum const sub_mux_enum =
 949                 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_SUBMUX,
 950                                 ARRAY_SIZE(sub_mux_txt), sub_mux_txt);
 951
 952 static struct snd_kcontrol_new const sub_mux_dapm_enum =
 953                 SOC_DAPM_ENUM("Sub Mux", sub_mux_enum);
 954
 955 static struct soc_enum const classd_mux_enum =
 956                 SOC_ENUM_SINGLE(R_AUDIOMUX3, FB_AUDIOMUX3_CLSSDMUX,
 957                                 ARRAY_SIZE(dai_mux_txt), dai_mux_txt);
 958
 959 static struct snd_kcontrol_new const classd_mux_dapm_enum =
 960                 SOC_DAPM_ENUM("ClassD Mux", classd_mux_enum);
 961
 962 /* R_HSDCTL1 PG 1 ADDR 0x01 */
 963 static char const * const jack_type_txt[] = {
 964                 "3 Terminal", "4 Terminal"};
 965
 966 static struct soc_enum const hp_jack_type_enum =
 967                 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HPJKTYPE,
 968                                 ARRAY_SIZE(jack_type_txt), jack_type_txt);
 969
 970 static char const * const hs_det_pol_txt[] = {
 971                 "Rising", "Falling"};
 972
 973 static struct soc_enum const hs_det_pol_enum =
 974                 SOC_ENUM_SINGLE(R_HSDCTL1, FB_HSDCTL1_HSDETPOL,
 975                                 ARRAY_SIZE(hs_det_pol_txt), hs_det_pol_txt);
 976
 977 /* R_HSDCTL1 PG 1 ADDR 0x02 */
 978 static char const * const hs_mic_bias_force_txt[] = {
 979                 "Off", "Ring", "Sleeve"};
 980
 981 static struct soc_enum const hs_mic_bias_force_enum =
 982                 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FMICBIAS1,
 983                                 ARRAY_SIZE(hs_mic_bias_force_txt),
 984                                 hs_mic_bias_force_txt);
 985
 986 static char const * const plug_type_txt[] = {
 987                 "OMTP", "CTIA", "Reserved", "Headphone"};
 988
 989 static struct soc_enum const plug_type_force_enum =
 990                 SOC_ENUM_SINGLE(R_HSDCTL2, FB_HSDCTL2_FPLUGTYPE,
 991                 ARRAY_SIZE(plug_type_txt), plug_type_txt);
 992
 993
 994 /* R_CH0AIC PG 1 ADDR 0x06 */
 995 static char const * const in_bst_mux_txt[] = {
 996                 "Input 1", "Input 2", "Input 3", "D2S"};
 997
 998 static struct soc_enum const in_bst_mux_ch0_enum =
 999                 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_INSELL,
1000                                 ARRAY_SIZE(in_bst_mux_txt),
1001                                 in_bst_mux_txt);
1002 static struct snd_kcontrol_new const in_bst_mux_ch0_dapm_enum =
1003                 SOC_DAPM_ENUM("Input Boost Channel 0 Enum",
1004                                 in_bst_mux_ch0_enum);
1005
1006 static DECLARE_TLV_DB_SCALE(in_bst_vol_tlv_arr, 0, 1000, 0);
1007
1008 static char const * const adc_mux_txt[] = {
1009                 "Input 1 Boost Bypass", "Input 2 Boost Bypass",
1010                 "Input 3 Boost Bypass", "Input Boost"};
1011
1012 static struct soc_enum const adc_mux_ch0_enum =
1013                 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_LADCIN,
1014                                 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1015 static struct snd_kcontrol_new const adc_mux_ch0_dapm_enum =
1016                 SOC_DAPM_ENUM("ADC Channel 0 Enum", adc_mux_ch0_enum);
1017
1018 static char const * const in_proc_mux_txt[] = {
1019                 "ADC", "DMic"};
1020
1021 static struct soc_enum const in_proc_ch0_enum =
1022                 SOC_ENUM_SINGLE(R_CH0AIC, FB_CH0AIC_IPCH0S,
1023                                 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1024 static struct snd_kcontrol_new const in_proc_mux_ch0_dapm_enum =
1025                 SOC_DAPM_ENUM("Input Processor Channel 0 Enum",
1026                                 in_proc_ch0_enum);
1027
1028 /* R_CH1AIC PG 1 ADDR 0x07 */
1029 static struct soc_enum const in_bst_mux_ch1_enum =
1030                 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_INSELR,
1031                                 ARRAY_SIZE(in_bst_mux_txt),
1032                                 in_bst_mux_txt);
1033 static struct snd_kcontrol_new const in_bst_mux_ch1_dapm_enum =
1034                 SOC_DAPM_ENUM("Input Boost Channel 1 Enum",
1035                                 in_bst_mux_ch1_enum);
1036
1037 static struct soc_enum const adc_mux_ch1_enum =
1038                 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_RADCIN,
1039                                 ARRAY_SIZE(adc_mux_txt), adc_mux_txt);
1040 static struct snd_kcontrol_new const adc_mux_ch1_dapm_enum =
1041                 SOC_DAPM_ENUM("ADC Channel 1 Enum", adc_mux_ch1_enum);
1042
1043 static struct soc_enum const in_proc_ch1_enum =
1044                 SOC_ENUM_SINGLE(R_CH1AIC, FB_CH1AIC_IPCH1S,
1045                                 ARRAY_SIZE(in_proc_mux_txt), in_proc_mux_txt);
1046 static struct snd_kcontrol_new const in_proc_mux_ch1_dapm_enum =
1047                 SOC_DAPM_ENUM("Input Processor Channel 1 Enum",
1048                                 in_proc_ch1_enum);
1049
1050 /* R_ICTL0 PG 1 ADDR 0x0A */
1051 static char const * const pol_txt[] = {
1052                 "Normal", "Invert"};
1053
1054 static struct soc_enum const in_pol_ch1_enum =
1055                 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN0POL,
1056                                 ARRAY_SIZE(pol_txt), pol_txt);
1057
1058 static struct soc_enum const in_pol_ch0_enum =
1059                 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_IN1POL,
1060                                 ARRAY_SIZE(pol_txt), pol_txt);
1061
1062 static char const * const in_proc_ch_sel_txt[] = {
1063                 "Normal", "Mono Mix to Channel 0",
1064                 "Mono Mix to Channel 1", "Add"};
1065
1066 static struct soc_enum const in_proc_ch01_sel_enum =
1067                 SOC_ENUM_SINGLE(R_ICTL0, FB_ICTL0_INPCH10SEL,
1068                                 ARRAY_SIZE(in_proc_ch_sel_txt),
1069                                 in_proc_ch_sel_txt);
1070
1071 /* R_ICTL1 PG 1 ADDR 0x0B */
1072 static struct soc_enum const in_pol_ch3_enum =
1073                 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN2POL,
1074                                 ARRAY_SIZE(pol_txt), pol_txt);
1075
1076 static struct soc_enum const in_pol_ch2_enum =
1077                 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_IN3POL,
1078                                 ARRAY_SIZE(pol_txt), pol_txt);
1079
1080 static struct soc_enum const in_proc_ch23_sel_enum =
1081                 SOC_ENUM_SINGLE(R_ICTL1, FB_ICTL1_INPCH32SEL,
1082                                 ARRAY_SIZE(in_proc_ch_sel_txt),
1083                                 in_proc_ch_sel_txt);
1084
1085 /* R_MICBIAS PG 1 ADDR 0x0C */
1086 static char const * const mic_bias_txt[] = {
1087                 "2.5V", "2.1V", "1.8V", "Vdd"};
1088
1089 static struct soc_enum const mic_bias_2_enum =
1090                 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV2,
1091                                 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1092
1093 static struct soc_enum const mic_bias_1_enum =
1094                 SOC_ENUM_SINGLE(R_MICBIAS, FB_MICBIAS_MICBOV1,
1095                                 ARRAY_SIZE(mic_bias_txt), mic_bias_txt);
1096
1097 /* R_PGACTL0 PG 1 ADDR 0x0D */
1098 /* R_PGACTL1 PG 1 ADDR 0x0E */
1099 /* R_PGACTL2 PG 1 ADDR 0x0F */
1100 /* R_PGACTL3 PG 1 ADDR 0x10 */
1101 static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
1102
1103 /* R_ICH0VOL PG1 ADDR 0x12 */
1104 /* R_ICH1VOL PG1 ADDR 0x13 */
1105 /* R_ICH2VOL PG1 ADDR 0x14 */
1106 /* R_ICH3VOL PG1 ADDR 0x15 */
1107 static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
1108
1109 /* R_ASRCILVOL PG1 ADDR 0x16 */
1110 /* R_ASRCIRVOL PG1 ADDR 0x17 */
1111 /* R_ASRCOLVOL PG1 ADDR 0x18 */
1112 /* R_ASRCORVOL PG1 ADDR 0x19 */
1113 static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
1114
1115 /* R_ALCCTL0 PG1 ADDR 0x1D */
1116 static char const * const alc_mode_txt[] = {
1117                 "ALC", "Limiter"};
1118
1119 static struct soc_enum const alc_mode_enum =
1120                 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCMODE,
1121                                 ARRAY_SIZE(alc_mode_txt), alc_mode_txt);
1122
1123 static char const * const alc_ref_text[] = {
1124                 "Channel 0", "Channel 1", "Channel 2", "Channel 3", "Peak"};
1125
1126 static struct soc_enum const alc_ref_enum =
1127                 SOC_ENUM_SINGLE(R_ALCCTL0, FB_ALCCTL0_ALCREF,
1128                                 ARRAY_SIZE(alc_ref_text), alc_ref_text);
1129
1130 /* R_ALCCTL1 PG 1 ADDR 0x1E */
1131 static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
1132 static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
1133
1134 /* R_ALCCTL2 PG 1 ADDR 0x1F */
1135 static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
1136
1137 /* R_NGATE PG 1 ADDR 0x21 */
1138 static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
1139
1140 static char const * const ngate_type_txt[] = {
1141                 "PGA Constant", "ADC Mute"};
1142
1143 static struct soc_enum const ngate_type_enum =
1144                 SOC_ENUM_SINGLE(R_NGATE, FB_NGATE_NGG,
1145                                 ARRAY_SIZE(ngate_type_txt), ngate_type_txt);
1146
1147 /* R_DMICCTL PG 1 ADDR 0x22 */
1148 static char const * const dmic_mono_sel_txt[] = {
1149                 "Stereo", "Mono"};
1150
1151 static struct soc_enum const dmic_mono_sel_enum =
1152                 SOC_ENUM_SINGLE(R_DMICCTL, FB_DMICCTL_DMONO,
1153                         ARRAY_SIZE(dmic_mono_sel_txt), dmic_mono_sel_txt);
1154
1155 /* R_DACCTL PG 2 ADDR 0x01 */
1156 static struct soc_enum const dac_pol_r_enum =
1157                 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLR,
1158                         ARRAY_SIZE(pol_txt), pol_txt);
1159
1160 static struct soc_enum const dac_pol_l_enum =
1161                 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACPOLL,
1162                         ARRAY_SIZE(pol_txt), pol_txt);
1163
1164 static char const * const dac_dith_txt[] = {
1165                 "Half", "Full", "Disabled", "Static"};
1166
1167 static struct soc_enum const dac_dith_enum =
1168                 SOC_ENUM_SINGLE(R_DACCTL, FB_DACCTL_DACDITH,
1169                         ARRAY_SIZE(dac_dith_txt), dac_dith_txt);
1170
1171 /* R_SPKCTL PG 2 ADDR 0x02 */
1172 static struct soc_enum const spk_pol_r_enum =
1173                 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLR,
1174                                 ARRAY_SIZE(pol_txt), pol_txt);
1175
1176 static struct soc_enum const spk_pol_l_enum =
1177                 SOC_ENUM_SINGLE(R_SPKCTL, FB_SPKCTL_SPKPOLL,
1178                                 ARRAY_SIZE(pol_txt), pol_txt);
1179
1180 /* R_SUBCTL PG 2 ADDR 0x03 */
1181 static struct soc_enum const sub_pol_enum =
1182                 SOC_ENUM_SINGLE(R_SUBCTL, FB_SUBCTL_SUBPOL,
1183                                 ARRAY_SIZE(pol_txt), pol_txt);
1184
1185 /* R_MVOLL PG 2 ADDR 0x08 */
1186 /* R_MVOLR PG 2 ADDR 0x09 */
1187 static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
1188
1189 /* R_HPVOLL PG 2 ADDR 0x0A */
1190 /* R_HPVOLR PG 2 ADDR 0x0B */
1191 static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
1192
1193 /* R_SPKVOLL PG 2 ADDR 0x0C */
1194 /* R_SPKVOLR PG 2 ADDR 0x0D */
1195 static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
1196
1197 /* R_SPKEQFILT PG 3 ADDR 0x01 */
1198 static char const * const eq_txt[] = {
1199         "Pre Scale",
1200         "Pre Scale + EQ Band 0",
1201         "Pre Scale + EQ Band 0 - 1",
1202         "Pre Scale + EQ Band 0 - 2",
1203         "Pre Scale + EQ Band 0 - 3",
1204         "Pre Scale + EQ Band 0 - 4",
1205         "Pre Scale + EQ Band 0 - 5",
1206 };
1207
1208 static struct soc_enum const spk_eq_enums[] = {
1209         SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ2BE,
1210                 ARRAY_SIZE(eq_txt), eq_txt),
1211         SOC_ENUM_SINGLE(R_SPKEQFILT, FB_SPKEQFILT_EQ1BE,
1212                 ARRAY_SIZE(eq_txt), eq_txt),
1213 };
1214
1215 /* R_SPKMBCCTL PG 3 ADDR 0x0B */
1216 static char const * const lvl_mode_txt[] = {
1217                 "Average", "Peak"};
1218
1219 static struct soc_enum const spk_mbc3_lvl_det_mode_enum =
1220                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE3,
1221                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1222
1223 static char const * const win_sel_txt[] = {
1224                 "512", "64"};
1225
1226 static struct soc_enum const spk_mbc3_win_sel_enum =
1227                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL3,
1228                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1229
1230 static struct soc_enum const spk_mbc2_lvl_det_mode_enum =
1231                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE2,
1232                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1233
1234 static struct soc_enum const spk_mbc2_win_sel_enum =
1235                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL2,
1236                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1237
1238 static struct soc_enum const spk_mbc1_lvl_det_mode_enum =
1239                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_LVLMODE1,
1240                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1241
1242 static struct soc_enum const spk_mbc1_win_sel_enum =
1243                 SOC_ENUM_SINGLE(R_SPKMBCCTL, FB_SPKMBCCTL_WINSEL1,
1244                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1245
1246 /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1247 static struct soc_enum const spk_mbc1_phase_pol_enum =
1248                 SOC_ENUM_SINGLE(R_SPKMBCMUG1, FB_SPKMBCMUG_PHASE,
1249                                 ARRAY_SIZE(pol_txt), pol_txt);
1250
1251 static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
1252
1253 /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1254 static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
1255
1256 /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1257 static char const * const comp_rat_txt[] = {
1258                 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
1259                 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1",
1260                 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1"};
1261
1262 static struct soc_enum const spk_mbc1_comp_rat_enum =
1263                 SOC_ENUM_SINGLE(R_SPKMBCRAT1, FB_SPKMBCRAT_RATIO,
1264                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1265
1266 /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1267 static struct soc_enum const spk_mbc2_phase_pol_enum =
1268                 SOC_ENUM_SINGLE(R_SPKMBCMUG2, FB_SPKMBCMUG_PHASE,
1269                                 ARRAY_SIZE(pol_txt), pol_txt);
1270
1271 /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1272 static struct soc_enum const spk_mbc2_comp_rat_enum =
1273                 SOC_ENUM_SINGLE(R_SPKMBCRAT2, FB_SPKMBCRAT_RATIO,
1274                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1275
1276 /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1277 static struct soc_enum const spk_mbc3_phase_pol_enum =
1278                 SOC_ENUM_SINGLE(R_SPKMBCMUG3, FB_SPKMBCMUG_PHASE,
1279                                 ARRAY_SIZE(pol_txt), pol_txt);
1280
1281 /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1282 static struct soc_enum const spk_mbc3_comp_rat_enum =
1283                 SOC_ENUM_SINGLE(R_SPKMBCRAT3, FB_SPKMBCRAT_RATIO,
1284                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1285
1286 /* R_SPKCLECTL PG 3 ADDR 0x21 */
1287 static struct soc_enum const spk_cle_lvl_mode_enum =
1288                 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_LVLMODE,
1289                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1290
1291 static struct soc_enum const spk_cle_win_sel_enum =
1292                 SOC_ENUM_SINGLE(R_SPKCLECTL, FB_SPKCLECTL_WINSEL,
1293                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1294
1295 /* R_SPKCLEMUG PG 3 ADDR 0x22 */
1296 static DECLARE_TLV_DB_MINMAX(cle_mug_tlv_arr, 0, 4650);
1297
1298 /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1299 static struct soc_enum const spk_comp_rat_enum =
1300                 SOC_ENUM_SINGLE(R_SPKCOMPRAT, FB_SPKCOMPRAT_RATIO,
1301                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1302
1303 /* R_SPKEXPTHR PG 3 ADDR 0x2F */
1304 static char const * const exp_rat_txt[] = {
1305                 "Reserved", "Reserved", "1:2", "1:3",
1306                 "1:4", "1:5", "1:6", "1:7"};
1307
1308 static struct soc_enum const spk_exp_rat_enum =
1309                 SOC_ENUM_SINGLE(R_SPKEXPRAT, FB_SPKEXPRAT_RATIO,
1310                                 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1311
1312 /* R_DACEQFILT PG 4 ADDR 0x01 */
1313 static struct soc_enum const dac_eq_enums[] = {
1314         SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ2BE,
1315                 ARRAY_SIZE(eq_txt), eq_txt),
1316         SOC_ENUM_SINGLE(R_DACEQFILT, FB_DACEQFILT_EQ1BE,
1317                 ARRAY_SIZE(eq_txt), eq_txt),
1318 };
1319
1320 /* R_DACMBCCTL PG 4 ADDR 0x0B */
1321 static struct soc_enum const dac_mbc3_lvl_det_mode_enum =
1322                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3,
1323                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1324
1325 static struct soc_enum const dac_mbc3_win_sel_enum =
1326                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3,
1327                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1328
1329 static struct soc_enum const dac_mbc2_lvl_det_mode_enum =
1330                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2,
1331                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1332
1333 static struct soc_enum const dac_mbc2_win_sel_enum =
1334                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2,
1335                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1336
1337 static struct soc_enum const dac_mbc1_lvl_det_mode_enum =
1338                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1,
1339                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1340
1341 static struct soc_enum const dac_mbc1_win_sel_enum =
1342                 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1,
1343                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1344
1345 /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1346 static struct soc_enum const dac_mbc1_phase_pol_enum =
1347                 SOC_ENUM_SINGLE(R_DACMBCMUG1, FB_DACMBCMUG_PHASE,
1348                                 ARRAY_SIZE(pol_txt), pol_txt);
1349
1350 /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1351 static struct soc_enum const dac_mbc1_comp_rat_enum =
1352                 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT_RATIO,
1353                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1354
1355 /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1356 static struct soc_enum const dac_mbc2_phase_pol_enum =
1357                 SOC_ENUM_SINGLE(R_DACMBCMUG2, FB_DACMBCMUG_PHASE,
1358                                 ARRAY_SIZE(pol_txt), pol_txt);
1359
1360 /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1361 static struct soc_enum const dac_mbc2_comp_rat_enum =
1362                 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT_RATIO,
1363                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1364
1365 /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1366 static struct soc_enum const dac_mbc3_phase_pol_enum =
1367                 SOC_ENUM_SINGLE(R_DACMBCMUG3, FB_DACMBCMUG_PHASE,
1368                                 ARRAY_SIZE(pol_txt), pol_txt);
1369
1370 /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1371 static struct soc_enum const dac_mbc3_comp_rat_enum =
1372                 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT_RATIO,
1373                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1374
1375 /* R_DACCLECTL PG 4 ADDR 0x21 */
1376 static struct soc_enum const dac_cle_lvl_mode_enum =
1377                 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_LVLMODE,
1378                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1379
1380 static struct soc_enum const dac_cle_win_sel_enum =
1381                 SOC_ENUM_SINGLE(R_DACCLECTL, FB_DACCLECTL_WINSEL,
1382                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1383
1384 /* R_DACCOMPRAT PG 4 ADDR 0x24 */
1385 static struct soc_enum const dac_comp_rat_enum =
1386                 SOC_ENUM_SINGLE(R_DACCOMPRAT, FB_DACCOMPRAT_RATIO,
1387                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1388
1389 /* R_DACEXPRAT PG 4 ADDR 0x30 */
1390 static struct soc_enum const dac_exp_rat_enum =
1391                 SOC_ENUM_SINGLE(R_DACEXPRAT, FB_DACEXPRAT_RATIO,
1392                                 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1393
1394 /* R_SUBEQFILT PG 5 ADDR 0x01 */
1395 static struct soc_enum const sub_eq_enums[] = {
1396         SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ2BE,
1397                 ARRAY_SIZE(eq_txt), eq_txt),
1398         SOC_ENUM_SINGLE(R_SUBEQFILT, FB_SUBEQFILT_EQ1BE,
1399                 ARRAY_SIZE(eq_txt), eq_txt),
1400 };
1401
1402 /* R_SUBMBCCTL PG 5 ADDR 0x0B */
1403 static struct soc_enum const sub_mbc3_lvl_det_mode_enum =
1404                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE3,
1405                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1406
1407 static struct soc_enum const sub_mbc3_win_sel_enum =
1408                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL3,
1409                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1410
1411 static struct soc_enum const sub_mbc2_lvl_det_mode_enum =
1412                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE2,
1413                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1414
1415 static struct soc_enum const sub_mbc2_win_sel_enum =
1416                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL2,
1417                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1418
1419 static struct soc_enum const sub_mbc1_lvl_det_mode_enum =
1420                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_LVLMODE1,
1421                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1422
1423 static struct soc_enum const sub_mbc1_win_sel_enum =
1424                 SOC_ENUM_SINGLE(R_SUBMBCCTL, FB_SUBMBCCTL_WINSEL1,
1425                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1426
1427 /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
1428 static struct soc_enum const sub_mbc1_phase_pol_enum =
1429                 SOC_ENUM_SINGLE(R_SUBMBCMUG1, FB_SUBMBCMUG_PHASE,
1430                                 ARRAY_SIZE(pol_txt), pol_txt);
1431
1432 /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
1433 static struct soc_enum const sub_mbc1_comp_rat_enum =
1434                 SOC_ENUM_SINGLE(R_SUBMBCRAT1, FB_SUBMBCRAT_RATIO,
1435                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1436
1437 /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
1438 static struct soc_enum const sub_mbc2_phase_pol_enum =
1439                 SOC_ENUM_SINGLE(R_SUBMBCMUG2, FB_SUBMBCMUG_PHASE,
1440                                 ARRAY_SIZE(pol_txt), pol_txt);
1441
1442 /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
1443 static struct soc_enum const sub_mbc2_comp_rat_enum =
1444                 SOC_ENUM_SINGLE(R_SUBMBCRAT2, FB_SUBMBCRAT_RATIO,
1445                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1446
1447 /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
1448 static struct soc_enum const sub_mbc3_phase_pol_enum =
1449                 SOC_ENUM_SINGLE(R_SUBMBCMUG3, FB_SUBMBCMUG_PHASE,
1450                                 ARRAY_SIZE(pol_txt), pol_txt);
1451
1452 /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
1453 static struct soc_enum const sub_mbc3_comp_rat_enum =
1454                 SOC_ENUM_SINGLE(R_SUBMBCRAT3, FB_SUBMBCRAT_RATIO,
1455                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1456
1457 /* R_SUBCLECTL PG 5 ADDR 0x21 */
1458 static struct soc_enum const sub_cle_lvl_mode_enum =
1459                 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_LVLMODE,
1460                                 ARRAY_SIZE(lvl_mode_txt), lvl_mode_txt);
1461 static struct soc_enum const sub_cle_win_sel_enum =
1462                 SOC_ENUM_SINGLE(R_SUBCLECTL, FB_SUBCLECTL_WINSEL,
1463                                 ARRAY_SIZE(win_sel_txt), win_sel_txt);
1464
1465 /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
1466 static struct soc_enum const sub_comp_rat_enum =
1467                 SOC_ENUM_SINGLE(R_SUBCOMPRAT, FB_SUBCOMPRAT_RATIO,
1468                                 ARRAY_SIZE(comp_rat_txt), comp_rat_txt);
1469
1470 /* R_SUBEXPRAT PG 5 ADDR 0x30 */
1471 static struct soc_enum const sub_exp_rat_enum =
1472                 SOC_ENUM_SINGLE(R_SUBEXPRAT, FB_SUBEXPRAT_RATIO,
1473                                 ARRAY_SIZE(exp_rat_txt), exp_rat_txt);
1474
1475 static int bytes_info_ext(struct snd_kcontrol *kcontrol,
1476         struct snd_ctl_elem_info *ucontrol)
1477 {
1478         struct coeff_ram_ctl *ctl =
1479                 (struct coeff_ram_ctl *)kcontrol->private_value;
1480         struct soc_bytes_ext *params = &ctl->bytes_ext;
1481
1482         ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1483         ucontrol->count = params->max;
1484
1485         return 0;
1486 }
1487
1488 /* CH 0_1 Input Mux */
1489 static char const * const ch_0_1_mux_txt[] = {"DAI 1", "TDM 0_1"};
1490
1491 static struct soc_enum const ch_0_1_mux_enum =
1492                 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1493                                 ARRAY_SIZE(ch_0_1_mux_txt), ch_0_1_mux_txt);
1494
1495 static struct snd_kcontrol_new const ch_0_1_mux_dapm_enum =
1496                 SOC_DAPM_ENUM("CH 0_1 Input Mux", ch_0_1_mux_enum);
1497
1498 /* CH 2_3 Input Mux */
1499 static char const * const ch_2_3_mux_txt[] = {"DAI 2", "TDM 2_3"};
1500
1501 static struct soc_enum const ch_2_3_mux_enum =
1502                 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1503                                 ARRAY_SIZE(ch_2_3_mux_txt), ch_2_3_mux_txt);
1504
1505 static struct snd_kcontrol_new const ch_2_3_mux_dapm_enum =
1506                 SOC_DAPM_ENUM("CH 2_3 Input Mux", ch_2_3_mux_enum);
1507
1508 /* CH 4_5 Input Mux */
1509 static char const * const ch_4_5_mux_txt[] = {"DAI 3", "TDM 4_5"};
1510
1511 static struct soc_enum const ch_4_5_mux_enum =
1512                 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0,
1513                                 ARRAY_SIZE(ch_4_5_mux_txt), ch_4_5_mux_txt);
1514
1515 static struct snd_kcontrol_new const ch_4_5_mux_dapm_enum =
1516                 SOC_DAPM_ENUM("CH 4_5 Input Mux", ch_4_5_mux_enum);
1517
1518 #define COEFF_RAM_CTL(xname, xcount, xaddr) \
1519 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1520         .info = bytes_info_ext, \
1521         .get = coeff_ram_get, .put = coeff_ram_put, \
1522         .private_value = (unsigned long)&(struct coeff_ram_ctl) { \
1523                 .addr = xaddr, \
1524                 .bytes_ext = {.max = xcount, }, \
1525         } \
1526 }
1527
1528 static struct snd_kcontrol_new const tscs454_snd_controls[] = {
1529         /* R_PLLCTL PG 0 ADDR 0x15 */
1530         SOC_ENUM("PLL BCLK Input", bclk_sel_enum),
1531         /* R_ISRC PG 0 ADDR 0x16 */
1532         SOC_ENUM("Internal Rate", isrc_br_enum),
1533         SOC_ENUM("Internal Rate Multiple", isrc_bm_enum),
1534         /* R_SCLKCTL PG 0 ADDR 0x18 */
1535         SOC_ENUM("ADC Modular Rate", adc_modular_rate_enum),
1536         SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum),
1537         /* R_ASRC PG 0 ADDR 0x28 */
1538         SOC_SINGLE("ASRC Out High Bandwidth Switch",
1539                         R_ASRC, FB_ASRC_ASRCOBW, 1, 0),
1540         SOC_SINGLE("ASRC In High Bandwidth Switch",
1541                         R_ASRC, FB_ASRC_ASRCIBW, 1, 0),
1542         /* R_I2SIDCTL PG 0 ADDR 0x38 */
1543         SOC_ENUM("I2S 1 Data In Control", data_in_ctrl_enums[0]),
1544         SOC_ENUM("I2S 2 Data In Control", data_in_ctrl_enums[1]),
1545         SOC_ENUM("I2S 3 Data In Control", data_in_ctrl_enums[2]),
1546         /* R_I2SODCTL PG 0 ADDR 0x39 */
1547         SOC_ENUM("I2S 1 Data Out Control", data_out_ctrl_enums[0]),
1548         SOC_ENUM("I2S 2 Data Out Control", data_out_ctrl_enums[1]),
1549         SOC_ENUM("I2S 3 Data Out Control", data_out_ctrl_enums[2]),
1550         /* R_AUDIOMUX1 PG 0 ADDR 0x3A */
1551         SOC_ENUM("ASRC In", asrc_in_mux_enum),
1552         /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
1553         SOC_ENUM("ASRC Out", asrc_out_mux_enum),
1554         /* R_HSDCTL1 PG 1 ADDR 0x01 */
1555         SOC_ENUM("Headphone Jack Type", hp_jack_type_enum),
1556         SOC_ENUM("Headset Detection Polarity", hs_det_pol_enum),
1557         SOC_SINGLE("Headphone Detection Switch",
1558                         R_HSDCTL1, FB_HSDCTL1_HPID_EN, 1, 0),
1559         SOC_SINGLE("Headset OMTP/CTIA Switch",
1560                         R_HSDCTL1, FB_HSDCTL1_GBLHS_EN, 1, 0),
1561         /* R_HSDCTL1 PG 1 ADDR 0x02 */
1562         SOC_ENUM("Headset Mic Bias Force", hs_mic_bias_force_enum),
1563         SOC_SINGLE("Manual Mic Bias Switch",
1564                         R_HSDCTL2, FB_HSDCTL2_MB1MODE, 1, 0),
1565         SOC_SINGLE("Ring/Sleeve Auto Switch",
1566                         R_HSDCTL2, FB_HSDCTL2_SWMODE, 1, 0),
1567         SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum),
1568         /* R_CH0AIC PG 1 ADDR 0x06 */
1569         SOC_SINGLE_TLV("Input Boost Channel 0 Volume", R_CH0AIC,
1570                         FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1571         /* R_CH1AIC PG 1 ADDR 0x07 */
1572         SOC_SINGLE_TLV("Input Boost Channel 1 Volume", R_CH1AIC,
1573                         FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1574         /* R_CH2AIC PG 1 ADDR 0x08 */
1575         SOC_SINGLE_TLV("Input Boost Channel 2 Volume", R_CH2AIC,
1576                         FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1577         /* R_CH3AIC PG 1 ADDR 0x09 */
1578         SOC_SINGLE_TLV("Input Boost Channel 3 Volume", R_CH3AIC,
1579                         FB_CHAIC_MICBST, 0x3, 0, in_bst_vol_tlv_arr),
1580         /* R_ICTL0 PG 1 ADDR 0x0A */
1581         SOC_ENUM("Input Channel 1 Polarity", in_pol_ch1_enum),
1582         SOC_ENUM("Input Channel 0 Polarity", in_pol_ch0_enum),
1583         SOC_ENUM("Input Processor Channel 0/1 Operation",
1584                         in_proc_ch01_sel_enum),
1585         SOC_SINGLE("Input Channel 1 Mute Switch",
1586                         R_ICTL0, FB_ICTL0_IN1MUTE, 1, 0),
1587         SOC_SINGLE("Input Channel 0 Mute Switch",
1588                         R_ICTL0, FB_ICTL0_IN0MUTE, 1, 0),
1589         SOC_SINGLE("Input Channel 1 HPF Disable Switch",
1590                         R_ICTL0, FB_ICTL0_IN1HP, 1, 0),
1591         SOC_SINGLE("Input Channel 0 HPF Disable Switch",
1592                         R_ICTL0, FB_ICTL0_IN0HP, 1, 0),
1593         /* R_ICTL1 PG 1 ADDR 0x0B */
1594         SOC_ENUM("Input Channel 3 Polarity", in_pol_ch3_enum),
1595         SOC_ENUM("Input Channel 2 Polarity", in_pol_ch2_enum),
1596         SOC_ENUM("Input Processor Channel 2/3 Operation",
1597                         in_proc_ch23_sel_enum),
1598         SOC_SINGLE("Input Channel 3 Mute Switch",
1599                         R_ICTL1, FB_ICTL1_IN3MUTE, 1, 0),
1600         SOC_SINGLE("Input Channel 2 Mute Switch",
1601                         R_ICTL1, FB_ICTL1_IN2MUTE, 1, 0),
1602         SOC_SINGLE("Input Channel 3 HPF Disable Switch",
1603                         R_ICTL1, FB_ICTL1_IN3HP, 1, 0),
1604         SOC_SINGLE("Input Channel 2 HPF Disable Switch",
1605                         R_ICTL1, FB_ICTL1_IN2HP, 1, 0),
1606         /* R_MICBIAS PG 1 ADDR 0x0C */
1607         SOC_ENUM("Mic Bias 2 Voltage", mic_bias_2_enum),
1608         SOC_ENUM("Mic Bias 1 Voltage", mic_bias_1_enum),
1609         /* R_PGACTL0 PG 1 ADDR 0x0D */
1610         SOC_SINGLE("Input Channel 0 PGA Mute Switch",
1611                         R_PGACTL0, FB_PGACTL_PGAMUTE, 1, 0),
1612         SOC_SINGLE_TLV("Input Channel 0 PGA Volume", R_PGACTL0,
1613                         FB_PGACTL_PGAVOL,
1614                         FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1615         /* R_PGACTL1 PG 1 ADDR 0x0E */
1616         SOC_SINGLE("Input Channel 1 PGA Mute Switch",
1617                         R_PGACTL1, FB_PGACTL_PGAMUTE, 1, 0),
1618         SOC_SINGLE_TLV("Input Channel 1 PGA Volume", R_PGACTL1,
1619                         FB_PGACTL_PGAVOL,
1620                         FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1621         /* R_PGACTL2 PG 1 ADDR 0x0F */
1622         SOC_SINGLE("Input Channel 2 PGA Mute Switch",
1623                         R_PGACTL2, FB_PGACTL_PGAMUTE, 1, 0),
1624         SOC_SINGLE_TLV("Input Channel 2 PGA Volume", R_PGACTL2,
1625                         FB_PGACTL_PGAVOL,
1626                         FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1627         /* R_PGACTL3 PG 1 ADDR 0x10 */
1628         SOC_SINGLE("Input Channel 3 PGA Mute Switch",
1629                         R_PGACTL3, FB_PGACTL_PGAMUTE, 1, 0),
1630         SOC_SINGLE_TLV("Input Channel 3 PGA Volume", R_PGACTL3,
1631                         FB_PGACTL_PGAVOL,
1632                         FM_PGACTL_PGAVOL, 0, in_pga_vol_tlv_arr),
1633         /* R_ICH0VOL PG 1 ADDR 0x12 */
1634         SOC_SINGLE_TLV("Input Channel 0 Volume", R_ICH0VOL,
1635                         FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1636         /* R_ICH1VOL PG 1 ADDR 0x13 */
1637         SOC_SINGLE_TLV("Input Channel 1 Volume", R_ICH1VOL,
1638                         FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1639         /* R_ICH2VOL PG 1 ADDR 0x14 */
1640         SOC_SINGLE_TLV("Input Channel 2 Volume", R_ICH2VOL,
1641                         FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1642         /* R_ICH3VOL PG 1 ADDR 0x15 */
1643         SOC_SINGLE_TLV("Input Channel 3 Volume", R_ICH3VOL,
1644                         FB_ICHVOL_ICHVOL, FM_ICHVOL_ICHVOL, 0, in_vol_tlv_arr),
1645         /* R_ASRCILVOL PG 1 ADDR 0x16 */
1646         SOC_SINGLE_TLV("ASRC Input Left Volume", R_ASRCILVOL,
1647                         FB_ASRCILVOL_ASRCILVOL, FM_ASRCILVOL_ASRCILVOL,
1648                         0, asrc_vol_tlv_arr),
1649         /* R_ASRCIRVOL PG 1 ADDR 0x17 */
1650         SOC_SINGLE_TLV("ASRC Input Right Volume", R_ASRCIRVOL,
1651                         FB_ASRCIRVOL_ASRCIRVOL, FM_ASRCIRVOL_ASRCIRVOL,
1652                         0, asrc_vol_tlv_arr),
1653         /* R_ASRCOLVOL PG 1 ADDR 0x18 */
1654         SOC_SINGLE_TLV("ASRC Output Left Volume", R_ASRCOLVOL,
1655                         FB_ASRCOLVOL_ASRCOLVOL, FM_ASRCOLVOL_ASRCOLVOL,
1656                         0, asrc_vol_tlv_arr),
1657         /* R_ASRCORVOL PG 1 ADDR 0x19 */
1658         SOC_SINGLE_TLV("ASRC Output Right Volume", R_ASRCORVOL,
1659                         FB_ASRCORVOL_ASRCOLVOL, FM_ASRCORVOL_ASRCOLVOL,
1660                         0, asrc_vol_tlv_arr),
1661         /* R_IVOLCTLU PG 1 ADDR 0x1C */
1662         /* R_ALCCTL0 PG 1 ADDR 0x1D */
1663         SOC_ENUM("ALC Mode", alc_mode_enum),
1664         SOC_ENUM("ALC Reference", alc_ref_enum),
1665         SOC_SINGLE("Input Channel 3 ALC Switch",
1666                         R_ALCCTL0, FB_ALCCTL0_ALCEN3, 1, 0),
1667         SOC_SINGLE("Input Channel 2 ALC Switch",
1668                         R_ALCCTL0, FB_ALCCTL0_ALCEN2, 1, 0),
1669         SOC_SINGLE("Input Channel 1 ALC Switch",
1670                         R_ALCCTL0, FB_ALCCTL0_ALCEN1, 1, 0),
1671         SOC_SINGLE("Input Channel 0 ALC Switch",
1672                         R_ALCCTL0, FB_ALCCTL0_ALCEN0, 1, 0),
1673         /* R_ALCCTL1 PG 1 ADDR 0x1E */
1674         SOC_SINGLE_TLV("ALC Max Gain Volume", R_ALCCTL1,
1675                         FB_ALCCTL1_MAXGAIN, FM_ALCCTL1_MAXGAIN,
1676                         0, alc_max_gain_tlv_arr),
1677         SOC_SINGLE_TLV("ALC Target Volume", R_ALCCTL1,
1678                         FB_ALCCTL1_ALCL, FM_ALCCTL1_ALCL,
1679                         0, alc_target_tlv_arr),
1680         /* R_ALCCTL2 PG 1 ADDR 0x1F */
1681         SOC_SINGLE("ALC Zero Cross Switch",
1682                         R_ALCCTL2, FB_ALCCTL2_ALCZC, 1, 0),
1683         SOC_SINGLE_TLV("ALC Min Gain Volume", R_ALCCTL2,
1684                         FB_ALCCTL2_MINGAIN, FM_ALCCTL2_MINGAIN,
1685                         0, alc_min_gain_tlv_arr),
1686         SOC_SINGLE_RANGE("ALC Hold", R_ALCCTL2,
1687                         FB_ALCCTL2_HLD, 0, FM_ALCCTL2_HLD, 0),
1688         /* R_ALCCTL3 PG 1 ADDR 0x20 */
1689         SOC_SINGLE_RANGE("ALC Decay", R_ALCCTL3,
1690                         FB_ALCCTL3_DCY, 0, FM_ALCCTL3_DCY, 0),
1691         SOC_SINGLE_RANGE("ALC Attack", R_ALCCTL3,
1692                         FB_ALCCTL3_ATK, 0, FM_ALCCTL3_ATK, 0),
1693         /* R_NGATE PG 1 ADDR 0x21 */
1694         SOC_SINGLE_TLV("Noise Gate Threshold Volume", R_NGATE,
1695                         FB_NGATE_NGTH, FM_NGATE_NGTH, 0, ngth_tlv_arr),
1696         SOC_ENUM("Noise Gate Type", ngate_type_enum),
1697         SOC_SINGLE("Noise Gate Switch", R_NGATE, FB_NGATE_NGAT, 1, 0),
1698         /* R_DMICCTL PG 1 ADDR 0x22 */
1699         SOC_SINGLE("Digital Mic 2 Switch", R_DMICCTL, FB_DMICCTL_DMIC2EN, 1, 0),
1700         SOC_SINGLE("Digital Mic 1 Switch", R_DMICCTL, FB_DMICCTL_DMIC1EN, 1, 0),
1701         SOC_ENUM("Digital Mic Mono Select", dmic_mono_sel_enum),
1702         /* R_DACCTL PG 2 ADDR 0x01 */
1703         SOC_ENUM("DAC Polarity Left", dac_pol_r_enum),
1704         SOC_ENUM("DAC Polarity Right", dac_pol_l_enum),
1705         SOC_ENUM("DAC Dither", dac_dith_enum),
1706         SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0),
1707         SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
1708         /* R_SPKCTL PG 2 ADDR 0x02 */
1709         SOC_ENUM("Speaker Polarity Right", spk_pol_r_enum),
1710         SOC_ENUM("Speaker Polarity Left", spk_pol_l_enum),
1711         SOC_SINGLE("Speaker Mute Switch", R_SPKCTL, FB_SPKCTL_SPKMUTE, 1, 0),
1712         SOC_SINGLE("Speaker De-Emphasis Switch",
1713                         R_SPKCTL, FB_SPKCTL_SPKDEM, 1, 0),
1714         /* R_SUBCTL PG 2 ADDR 0x03 */
1715         SOC_ENUM("Sub Polarity", sub_pol_enum),
1716         SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0),
1717         SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
1718         /* R_DCCTL PG 2 ADDR 0x04 */
1719         SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1),
1720         SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1),
1721         SOC_SINGLE("Speaker DC Removal Switch",
1722                         R_DCCTL, FB_DCCTL_SPKDCBYP, 1, 1),
1723         SOC_SINGLE("DC Removal Coefficient Switch", R_DCCTL, FB_DCCTL_DCCOEFSEL,
1724                         FM_DCCTL_DCCOEFSEL, 0),
1725         /* R_OVOLCTLU PG 2 ADDR 0x06 */
1726         SOC_SINGLE("Output Fade Switch", R_OVOLCTLU, FB_OVOLCTLU_OFADE, 1, 0),
1727         /* R_MVOLL PG 2 ADDR 0x08 */
1728         /* R_MVOLR PG 2 ADDR 0x09 */
1729         SOC_DOUBLE_R_TLV("Master Volume", R_MVOLL, R_MVOLR,
1730                         FB_MVOLL_MVOL_L, FM_MVOLL_MVOL_L, 0, mvol_tlv_arr),
1731         /* R_HPVOLL PG 2 ADDR 0x0A */
1732         /* R_HPVOLR PG 2 ADDR 0x0B */
1733         SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR,
1734                         FB_HPVOLL_HPVOL_L, FM_HPVOLL_HPVOL_L, 0,
1735                         hp_vol_tlv_arr),
1736         /* R_SPKVOLL PG 2 ADDR 0x0C */
1737         /* R_SPKVOLR PG 2 ADDR 0x0D */
1738         SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR,
1739                         FB_SPKVOLL_SPKVOL_L, FM_SPKVOLL_SPKVOL_L, 0,
1740                         spk_vol_tlv_arr),
1741         /* R_SUBVOL PG 2 ADDR 0x10 */
1742         SOC_SINGLE_TLV("Sub Volume", R_SUBVOL,
1743                         FB_SUBVOL_SUBVOL, FM_SUBVOL_SUBVOL, 0, spk_vol_tlv_arr),
1744         /* R_SPKEQFILT PG 3 ADDR 0x01 */
1745         SOC_SINGLE("Speaker EQ 2 Switch",
1746                         R_SPKEQFILT, FB_SPKEQFILT_EQ2EN, 1, 0),
1747         SOC_ENUM("Speaker EQ 2 Band", spk_eq_enums[0]),
1748         SOC_SINGLE("Speaker EQ 1 Switch",
1749                         R_SPKEQFILT, FB_SPKEQFILT_EQ1EN, 1, 0),
1750         SOC_ENUM("Speaker EQ 1 Band", spk_eq_enums[1]),
1751         /* R_SPKMBCEN PG 3 ADDR 0x0A */
1752         SOC_SINGLE("Speaker MBC 3 Switch",
1753                         R_SPKMBCEN, FB_SPKMBCEN_MBCEN3, 1, 0),
1754         SOC_SINGLE("Speaker MBC 2 Switch",
1755                         R_SPKMBCEN, FB_SPKMBCEN_MBCEN2, 1, 0),
1756         SOC_SINGLE("Speaker MBC 1 Switch",
1757                         R_SPKMBCEN, FB_SPKMBCEN_MBCEN1, 1, 0),
1758         /* R_SPKMBCCTL PG 3 ADDR 0x0B */
1759         SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum),
1760         SOC_ENUM("Speaker MBC 3 Window", spk_mbc3_win_sel_enum),
1761         SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum),
1762         SOC_ENUM("Speaker MBC 2 Window", spk_mbc2_win_sel_enum),
1763         SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum),
1764         SOC_ENUM("Speaker MBC 1 Window", spk_mbc1_win_sel_enum),
1765         /* R_SPKMBCMUG1 PG 3 ADDR 0x0C */
1766         SOC_ENUM("Speaker MBC 1 Phase Polarity", spk_mbc1_phase_pol_enum),
1767         SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
1768                         FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1769                         0, mbc_mug_tlv_arr),
1770         /* R_SPKMBCTHR1 PG 3 ADDR 0x0D */
1771         SOC_SINGLE_TLV("Speaker MBC 1 Compressor Threshold Volume",
1772                         R_SPKMBCTHR1, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1773                         0, thr_tlv_arr),
1774         /* R_SPKMBCRAT1 PG 3 ADDR 0x0E */
1775         SOC_ENUM("Speaker MBC 1 Compressor Ratio", spk_mbc1_comp_rat_enum),
1776         /* R_SPKMBCATK1L PG 3 ADDR 0x0F */
1777         /* R_SPKMBCATK1H PG 3 ADDR 0x10 */
1778         SND_SOC_BYTES("Speaker MBC 1 Attack", R_SPKMBCATK1L, 2),
1779         /* R_SPKMBCREL1L PG 3 ADDR 0x11 */
1780         /* R_SPKMBCREL1H PG 3 ADDR 0x12 */
1781         SND_SOC_BYTES("Speaker MBC 1 Release", R_SPKMBCREL1L, 2),
1782         /* R_SPKMBCMUG2 PG 3 ADDR 0x13 */
1783         SOC_ENUM("Speaker MBC 2 Phase Polarity", spk_mbc2_phase_pol_enum),
1784         SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
1785                         FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1786                         0, mbc_mug_tlv_arr),
1787         /* R_SPKMBCTHR2 PG 3 ADDR 0x14 */
1788         SOC_SINGLE_TLV("Speaker MBC 2 Compressor Threshold Volume",
1789                         R_SPKMBCTHR2, FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1790                         0, thr_tlv_arr),
1791         /* R_SPKMBCRAT2 PG 3 ADDR 0x15 */
1792         SOC_ENUM("Speaker MBC 2 Compressor Ratio", spk_mbc2_comp_rat_enum),
1793         /* R_SPKMBCATK2L PG 3 ADDR 0x16 */
1794         /* R_SPKMBCATK2H PG 3 ADDR 0x17 */
1795         SND_SOC_BYTES("Speaker MBC 2 Attack", R_SPKMBCATK2L, 2),
1796         /* R_SPKMBCREL2L PG 3 ADDR 0x18 */
1797         /* R_SPKMBCREL2H PG 3 ADDR 0x19 */
1798         SND_SOC_BYTES("Speaker MBC 2 Release", R_SPKMBCREL2L, 2),
1799         /* R_SPKMBCMUG3 PG 3 ADDR 0x1A */
1800         SOC_ENUM("Speaker MBC 3 Phase Polarity", spk_mbc3_phase_pol_enum),
1801         SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
1802                         FB_SPKMBCMUG_MUGAIN, FM_SPKMBCMUG_MUGAIN,
1803                         0, mbc_mug_tlv_arr),
1804         /* R_SPKMBCTHR3 PG 3 ADDR 0x1B */
1805         SOC_SINGLE_TLV("Speaker MBC 3 Threshold Volume", R_SPKMBCTHR3,
1806                         FB_SPKMBCTHR_THRESH, FM_SPKMBCTHR_THRESH,
1807                         0, thr_tlv_arr),
1808         /* R_SPKMBCRAT3 PG 3 ADDR 0x1C */
1809         SOC_ENUM("Speaker MBC 3 Compressor Ratio", spk_mbc3_comp_rat_enum),
1810         /* R_SPKMBCATK3L PG 3 ADDR 0x1D */
1811         /* R_SPKMBCATK3H PG 3 ADDR 0x1E */
1812         SND_SOC_BYTES("Speaker MBC 3 Attack", R_SPKMBCATK3L, 3),
1813         /* R_SPKMBCREL3L PG 3 ADDR 0x1F */
1814         /* R_SPKMBCREL3H PG 3 ADDR 0x20 */
1815         SND_SOC_BYTES("Speaker MBC 3 Release", R_SPKMBCREL3L, 3),
1816         /* R_SPKCLECTL PG 3 ADDR 0x21 */
1817         SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum),
1818         SOC_ENUM("Speaker CLE Window", spk_cle_win_sel_enum),
1819         SOC_SINGLE("Speaker CLE Expander Switch",
1820                         R_SPKCLECTL, FB_SPKCLECTL_EXPEN, 1, 0),
1821         SOC_SINGLE("Speaker CLE Limiter Switch",
1822                         R_SPKCLECTL, FB_SPKCLECTL_LIMEN, 1, 0),
1823         SOC_SINGLE("Speaker CLE Compressor Switch",
1824                         R_SPKCLECTL, FB_SPKCLECTL_COMPEN, 1, 0),
1825         /* R_SPKCLEMUG PG 3 ADDR 0x22 */
1826         SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
1827                         FB_SPKCLEMUG_MUGAIN, FM_SPKCLEMUG_MUGAIN,
1828                         0, cle_mug_tlv_arr),
1829         /* R_SPKCOMPTHR PG 3 ADDR 0x23 */
1830         SOC_SINGLE_TLV("Speaker Compressor Threshold Volume", R_SPKCOMPTHR,
1831                         FB_SPKCOMPTHR_THRESH, FM_SPKCOMPTHR_THRESH,
1832                         0, thr_tlv_arr),
1833         /* R_SPKCOMPRAT PG 3 ADDR 0x24 */
1834         SOC_ENUM("Speaker Compressor Ratio", spk_comp_rat_enum),
1835         /* R_SPKCOMPATKL PG 3 ADDR 0x25 */
1836         /* R_SPKCOMPATKH PG 3 ADDR 0x26 */
1837         SND_SOC_BYTES("Speaker Compressor Attack", R_SPKCOMPATKL, 2),
1838         /* R_SPKCOMPRELL PG 3 ADDR 0x27 */
1839         /* R_SPKCOMPRELH PG 3 ADDR 0x28 */
1840         SND_SOC_BYTES("Speaker Compressor Release", R_SPKCOMPRELL, 2),
1841         /* R_SPKLIMTHR PG 3 ADDR 0x29 */
1842         SOC_SINGLE_TLV("Speaker Limiter Threshold Volume", R_SPKLIMTHR,
1843                         FB_SPKLIMTHR_THRESH, FM_SPKLIMTHR_THRESH,
1844                         0, thr_tlv_arr),
1845         /* R_SPKLIMTGT PG 3 ADDR 0x2A */
1846         SOC_SINGLE_TLV("Speaker Limiter Target Volume", R_SPKLIMTGT,
1847                         FB_SPKLIMTGT_TARGET, FM_SPKLIMTGT_TARGET,
1848                         0, thr_tlv_arr),
1849         /* R_SPKLIMATKL PG 3 ADDR 0x2B */
1850         /* R_SPKLIMATKH PG 3 ADDR 0x2C */
1851         SND_SOC_BYTES("Speaker Limiter Attack", R_SPKLIMATKL, 2),
1852         /* R_SPKLIMRELL PG 3 ADDR 0x2D */
1853         /* R_SPKLIMRELR PG 3 ADDR 0x2E */
1854         SND_SOC_BYTES("Speaker Limiter Release", R_SPKLIMRELL, 2),
1855         /* R_SPKEXPTHR PG 3 ADDR 0x2F */
1856         SOC_SINGLE_TLV("Speaker Expander Threshold Volume", R_SPKEXPTHR,
1857                         FB_SPKEXPTHR_THRESH, FM_SPKEXPTHR_THRESH,
1858                         0, thr_tlv_arr),
1859         /* R_SPKEXPRAT PG 3 ADDR 0x30 */
1860         SOC_ENUM("Speaker Expander Ratio", spk_exp_rat_enum),
1861         /* R_SPKEXPATKL PG 3 ADDR 0x31 */
1862         /* R_SPKEXPATKR PG 3 ADDR 0x32 */
1863         SND_SOC_BYTES("Speaker Expander Attack", R_SPKEXPATKL, 2),
1864         /* R_SPKEXPRELL PG 3 ADDR 0x33 */
1865         /* R_SPKEXPRELR PG 3 ADDR 0x34 */
1866         SND_SOC_BYTES("Speaker Expander Release", R_SPKEXPRELL, 2),
1867         /* R_SPKFXCTL PG 3 ADDR 0x35 */
1868         SOC_SINGLE("Speaker 3D Switch", R_SPKFXCTL, FB_SPKFXCTL_3DEN, 1, 0),
1869         SOC_SINGLE("Speaker Treble Enhancement Switch",
1870                         R_SPKFXCTL, FB_SPKFXCTL_TEEN, 1, 0),
1871         SOC_SINGLE("Speaker Treble NLF Switch",
1872                         R_SPKFXCTL, FB_SPKFXCTL_TNLFBYP, 1, 1),
1873         SOC_SINGLE("Speaker Bass Enhancement Switch",
1874                         R_SPKFXCTL, FB_SPKFXCTL_BEEN, 1, 0),
1875         SOC_SINGLE("Speaker Bass NLF Switch",
1876                         R_SPKFXCTL, FB_SPKFXCTL_BNLFBYP, 1, 1),
1877         /* R_DACEQFILT PG 4 ADDR 0x01 */
1878         SOC_SINGLE("DAC EQ 2 Switch",
1879                         R_DACEQFILT, FB_DACEQFILT_EQ2EN, 1, 0),
1880         SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]),
1881         SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0),
1882         SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]),
1883         /* R_DACMBCEN PG 4 ADDR 0x0A */
1884         SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
1885         SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
1886         SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
1887         /* R_DACMBCCTL PG 4 ADDR 0x0B */
1888         SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum),
1889         SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum),
1890         SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum),
1891         SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum),
1892         SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum),
1893         SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum),
1894         /* R_DACMBCMUG1 PG 4 ADDR 0x0C */
1895         SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum),
1896         SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
1897                         FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1898                         0, mbc_mug_tlv_arr),
1899         /* R_DACMBCTHR1 PG 4 ADDR 0x0D */
1900         SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1,
1901                         FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1902                         0, thr_tlv_arr),
1903         /* R_DACMBCRAT1 PG 4 ADDR 0x0E */
1904         SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum),
1905         /* R_DACMBCATK1L PG 4 ADDR 0x0F */
1906         /* R_DACMBCATK1H PG 4 ADDR 0x10 */
1907         SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2),
1908         /* R_DACMBCREL1L PG 4 ADDR 0x11 */
1909         /* R_DACMBCREL1H PG 4 ADDR 0x12 */
1910         SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2),
1911         /* R_DACMBCMUG2 PG 4 ADDR 0x13 */
1912         SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum),
1913         SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
1914                         FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1915                         0, mbc_mug_tlv_arr),
1916         /* R_DACMBCTHR2 PG 4 ADDR 0x14 */
1917         SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2,
1918                         FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1919                         0, thr_tlv_arr),
1920         /* R_DACMBCRAT2 PG 4 ADDR 0x15 */
1921         SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum),
1922         /* R_DACMBCATK2L PG 4 ADDR 0x16 */
1923         /* R_DACMBCATK2H PG 4 ADDR 0x17 */
1924         SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2),
1925         /* R_DACMBCREL2L PG 4 ADDR 0x18 */
1926         /* R_DACMBCREL2H PG 4 ADDR 0x19 */
1927         SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2),
1928         /* R_DACMBCMUG3 PG 4 ADDR 0x1A */
1929         SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum),
1930         SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
1931                         FB_DACMBCMUG_MUGAIN, FM_DACMBCMUG_MUGAIN,
1932                         0, mbc_mug_tlv_arr),
1933         /* R_DACMBCTHR3 PG 4 ADDR 0x1B */
1934         SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3,
1935                         FB_DACMBCTHR_THRESH, FM_DACMBCTHR_THRESH,
1936                         0, thr_tlv_arr),
1937         /* R_DACMBCRAT3 PG 4 ADDR 0x1C */
1938         SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum),
1939         /* R_DACMBCATK3L PG 4 ADDR 0x1D */
1940         /* R_DACMBCATK3H PG 4 ADDR 0x1E */
1941         SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3),
1942         /* R_DACMBCREL3L PG 4 ADDR 0x1F */
1943         /* R_DACMBCREL3H PG 4 ADDR 0x20 */
1944         SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3),
1945         /* R_DACCLECTL PG 4 ADDR 0x21 */
1946         SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum),
1947         SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum),
1948         SOC_SINGLE("DAC CLE Expander Switch",
1949                         R_DACCLECTL, FB_DACCLECTL_EXPEN, 1, 0),
1950         SOC_SINGLE("DAC CLE Limiter Switch",
1951                         R_DACCLECTL, FB_DACCLECTL_LIMEN, 1, 0),
1952         SOC_SINGLE("DAC CLE Compressor Switch",
1953                         R_DACCLECTL, FB_DACCLECTL_COMPEN, 1, 0),
1954         /* R_DACCLEMUG PG 4 ADDR 0x22 */
1955         SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
1956                         FB_DACCLEMUG_MUGAIN, FM_DACCLEMUG_MUGAIN,
1957                         0, cle_mug_tlv_arr),
1958         /* R_DACCOMPTHR PG 4 ADDR 0x23 */
1959         SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR,
1960                         FB_DACCOMPTHR_THRESH, FM_DACCOMPTHR_THRESH,
1961                         0, thr_tlv_arr),
1962         /* R_DACCOMPRAT PG 4 ADDR 0x24 */
1963         SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum),
1964         /* R_DACCOMPATKL PG 4 ADDR 0x25 */
1965         /* R_DACCOMPATKH PG 4 ADDR 0x26 */
1966         SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2),
1967         /* R_DACCOMPRELL PG 4 ADDR 0x27 */
1968         /* R_DACCOMPRELH PG 4 ADDR 0x28 */
1969         SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2),
1970         /* R_DACLIMTHR PG 4 ADDR 0x29 */
1971         SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR,
1972                         FB_DACLIMTHR_THRESH, FM_DACLIMTHR_THRESH,
1973                         0, thr_tlv_arr),
1974         /* R_DACLIMTGT PG 4 ADDR 0x2A */
1975         SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT,
1976                         FB_DACLIMTGT_TARGET, FM_DACLIMTGT_TARGET,
1977                         0, thr_tlv_arr),
1978         /* R_DACLIMATKL PG 4 ADDR 0x2B */
1979         /* R_DACLIMATKH PG 4 ADDR 0x2C */
1980         SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2),
1981         /* R_DACLIMRELL PG 4 ADDR 0x2D */
1982         /* R_DACLIMRELR PG 4 ADDR 0x2E */
1983         SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2),
1984         /* R_DACEXPTHR PG 4 ADDR 0x2F */
1985         SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR,
1986                         FB_DACEXPTHR_THRESH, FM_DACEXPTHR_THRESH,
1987                         0, thr_tlv_arr),
1988         /* R_DACEXPRAT PG 4 ADDR 0x30 */
1989         SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum),
1990         /* R_DACEXPATKL PG 4 ADDR 0x31 */
1991         /* R_DACEXPATKR PG 4 ADDR 0x32 */
1992         SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2),
1993         /* R_DACEXPRELL PG 4 ADDR 0x33 */
1994         /* R_DACEXPRELR PG 4 ADDR 0x34 */
1995         SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2),
1996         /* R_DACFXCTL PG 4 ADDR 0x35 */
1997         SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0),
1998         SOC_SINGLE("DAC Treble Enhancement Switch",
1999                         R_DACFXCTL, FB_DACFXCTL_TEEN, 1, 0),
2000         SOC_SINGLE("DAC Treble NLF Switch",
2001                         R_DACFXCTL, FB_DACFXCTL_TNLFBYP, 1, 1),
2002         SOC_SINGLE("DAC Bass Enhancement Switch",
2003                         R_DACFXCTL, FB_DACFXCTL_BEEN, 1, 0),
2004         SOC_SINGLE("DAC Bass NLF Switch",
2005                         R_DACFXCTL, FB_DACFXCTL_BNLFBYP, 1, 1),
2006         /* R_SUBEQFILT PG 5 ADDR 0x01 */
2007         SOC_SINGLE("Sub EQ 2 Switch",
2008                         R_SUBEQFILT, FB_SUBEQFILT_EQ2EN, 1, 0),
2009         SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]),
2010         SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0),
2011         SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]),
2012         /* R_SUBMBCEN PG 5 ADDR 0x0A */
2013         SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0),
2014         SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0),
2015         SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0),
2016         /* R_SUBMBCCTL PG 5 ADDR 0x0B */
2017         SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum),
2018         SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum),
2019         SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum),
2020         SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum),
2021         SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum),
2022         SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum),
2023         /* R_SUBMBCMUG1 PG 5 ADDR 0x0C */
2024         SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum),
2025         SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
2026                         FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2027                         0, mbc_mug_tlv_arr),
2028         /* R_SUBMBCTHR1 PG 5 ADDR 0x0D */
2029         SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1,
2030                         FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2031                         0, thr_tlv_arr),
2032         /* R_SUBMBCRAT1 PG 5 ADDR 0x0E */
2033         SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum),
2034         /* R_SUBMBCATK1L PG 5 ADDR 0x0F */
2035         /* R_SUBMBCATK1H PG 5 ADDR 0x10 */
2036         SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2),
2037         /* R_SUBMBCREL1L PG 5 ADDR 0x11 */
2038         /* R_SUBMBCREL1H PG 5 ADDR 0x12 */
2039         SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2),
2040         /* R_SUBMBCMUG2 PG 5 ADDR 0x13 */
2041         SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum),
2042         SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
2043                         FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2044                         0, mbc_mug_tlv_arr),
2045         /* R_SUBMBCTHR2 PG 5 ADDR 0x14 */
2046         SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2,
2047                         FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2048                         0, thr_tlv_arr),
2049         /* R_SUBMBCRAT2 PG 5 ADDR 0x15 */
2050         SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum),
2051         /* R_SUBMBCATK2L PG 5 ADDR 0x16 */
2052         /* R_SUBMBCATK2H PG 5 ADDR 0x17 */
2053         SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2),
2054         /* R_SUBMBCREL2L PG 5 ADDR 0x18 */
2055         /* R_SUBMBCREL2H PG 5 ADDR 0x19 */
2056         SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2),
2057         /* R_SUBMBCMUG3 PG 5 ADDR 0x1A */
2058         SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum),
2059         SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
2060                         FB_SUBMBCMUG_MUGAIN, FM_SUBMBCMUG_MUGAIN,
2061                         0, mbc_mug_tlv_arr),
2062         /* R_SUBMBCTHR3 PG 5 ADDR 0x1B */
2063         SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3,
2064                         FB_SUBMBCTHR_THRESH, FM_SUBMBCTHR_THRESH,
2065                         0, thr_tlv_arr),
2066         /* R_SUBMBCRAT3 PG 5 ADDR 0x1C */
2067         SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum),
2068         /* R_SUBMBCATK3L PG 5 ADDR 0x1D */
2069         /* R_SUBMBCATK3H PG 5 ADDR 0x1E */
2070         SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3),
2071         /* R_SUBMBCREL3L PG 5 ADDR 0x1F */
2072         /* R_SUBMBCREL3H PG 5 ADDR 0x20 */
2073         SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3),
2074         /* R_SUBCLECTL PG 5 ADDR 0x21 */
2075         SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum),
2076         SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum),
2077         SOC_SINGLE("Sub CLE Expander Switch",
2078                         R_SUBCLECTL, FB_SUBCLECTL_EXPEN, 1, 0),
2079         SOC_SINGLE("Sub CLE Limiter Switch",
2080                         R_SUBCLECTL, FB_SUBCLECTL_LIMEN, 1, 0),
2081         SOC_SINGLE("Sub CLE Compressor Switch",
2082                         R_SUBCLECTL, FB_SUBCLECTL_COMPEN, 1, 0),
2083         /* R_SUBCLEMUG PG 5 ADDR 0x22 */
2084         SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
2085                         FB_SUBCLEMUG_MUGAIN, FM_SUBCLEMUG_MUGAIN,
2086                         0, cle_mug_tlv_arr),
2087         /* R_SUBCOMPTHR PG 5 ADDR 0x23 */
2088         SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR,
2089                         FB_SUBCOMPTHR_THRESH, FM_SUBCOMPTHR_THRESH,
2090                         0, thr_tlv_arr),
2091         /* R_SUBCOMPRAT PG 5 ADDR 0x24 */
2092         SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum),
2093         /* R_SUBCOMPATKL PG 5 ADDR 0x25 */
2094         /* R_SUBCOMPATKH PG 5 ADDR 0x26 */
2095         SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2),
2096         /* R_SUBCOMPRELL PG 5 ADDR 0x27 */
2097         /* R_SUBCOMPRELH PG 5 ADDR 0x28 */
2098         SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2),
2099         /* R_SUBLIMTHR PG 5 ADDR 0x29 */
2100         SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR,
2101                         FB_SUBLIMTHR_THRESH, FM_SUBLIMTHR_THRESH,
2102                         0, thr_tlv_arr),
2103         /* R_SUBLIMTGT PG 5 ADDR 0x2A */
2104         SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT,
2105                         FB_SUBLIMTGT_TARGET, FM_SUBLIMTGT_TARGET,
2106                         0, thr_tlv_arr),
2107         /* R_SUBLIMATKL PG 5 ADDR 0x2B */
2108         /* R_SUBLIMATKH PG 5 ADDR 0x2C */
2109         SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2),
2110         /* R_SUBLIMRELL PG 5 ADDR 0x2D */
2111         /* R_SUBLIMRELR PG 5 ADDR 0x2E */
2112         SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2),
2113         /* R_SUBEXPTHR PG 5 ADDR 0x2F */
2114         SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR,
2115                         FB_SUBEXPTHR_THRESH, FM_SUBEXPTHR_THRESH,
2116                         0, thr_tlv_arr),
2117         /* R_SUBEXPRAT PG 5 ADDR 0x30 */
2118         SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum),
2119         /* R_SUBEXPATKL PG 5 ADDR 0x31 */
2120         /* R_SUBEXPATKR PG 5 ADDR 0x32 */
2121         SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2),
2122         /* R_SUBEXPRELL PG 5 ADDR 0x33 */
2123         /* R_SUBEXPRELR PG 5 ADDR 0x34 */
2124         SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2),
2125         /* R_SUBFXCTL PG 5 ADDR 0x35 */
2126         SOC_SINGLE("Sub Treble Enhancement Switch",
2127                         R_SUBFXCTL, FB_SUBFXCTL_TEEN, 1, 0),
2128         SOC_SINGLE("Sub Treble NLF Switch",
2129                         R_SUBFXCTL, FB_SUBFXCTL_TNLFBYP, 1, 1),
2130         SOC_SINGLE("Sub Bass Enhancement Switch",
2131                         R_SUBFXCTL, FB_SUBFXCTL_BEEN, 1, 0),
2132         SOC_SINGLE("Sub Bass NLF Switch",
2133                         R_SUBFXCTL, FB_SUBFXCTL_BNLFBYP, 1, 1),
2134         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2135         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2136         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2137         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2138         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2139         COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2140
2141         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2142         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2143         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2144         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2145         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2146         COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2147
2148         COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2149         COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2150
2151         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2152         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2153         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2154         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2155         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2156         COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2157
2158         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2159         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2160         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2161         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2162         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2163         COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2164
2165         COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2166         COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2167
2168         COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2169         COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2170
2171         COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2172         COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2173
2174         COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2175
2176         COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2177
2178         COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96),
2179
2180         COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2181         COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2182
2183         COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2184         COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2185
2186         COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2187
2188         COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2189
2190         COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad),
2191
2192         COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae),
2193
2194         COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf),
2195
2196         COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2197         COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2198
2199         COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2200         COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2201
2202         COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2203         COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2204
2205         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2206         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2207         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2208         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2209         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2210         COEFF_RAM_CTL("Speaker Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2211
2212         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2213         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2214         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2215         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2216         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2217         COEFF_RAM_CTL("Speaker Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2218
2219         COEFF_RAM_CTL("Speaker Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2220         COEFF_RAM_CTL("Speaker Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2221
2222         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2223         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2224         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2225         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2226         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2227         COEFF_RAM_CTL("Speaker Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2228
2229         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2230         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2231         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2232         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2233         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2234         COEFF_RAM_CTL("Speaker Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2235
2236         COEFF_RAM_CTL("Speaker Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2237         COEFF_RAM_CTL("Speaker Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2238
2239         COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2240         COEFF_RAM_CTL("Speaker Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2241
2242         COEFF_RAM_CTL("Speaker Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2243         COEFF_RAM_CTL("Speaker Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2244
2245         COEFF_RAM_CTL("Speaker Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2246
2247         COEFF_RAM_CTL("Speaker Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2248
2249         COEFF_RAM_CTL("Speaker Bass Mix", COEFF_SIZE, 0x96),
2250
2251         COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2252         COEFF_RAM_CTL("Speaker Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2253
2254         COEFF_RAM_CTL("Speaker Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2255         COEFF_RAM_CTL("Speaker Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2256
2257         COEFF_RAM_CTL("Speaker Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2258
2259         COEFF_RAM_CTL("Speaker Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2260
2261         COEFF_RAM_CTL("Speaker Treb Mix", COEFF_SIZE, 0xad),
2262
2263         COEFF_RAM_CTL("Speaker 3D", COEFF_SIZE, 0xae),
2264
2265         COEFF_RAM_CTL("Speaker 3D Mix", COEFF_SIZE, 0xaf),
2266
2267         COEFF_RAM_CTL("Speaker MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2268         COEFF_RAM_CTL("Speaker MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2269
2270         COEFF_RAM_CTL("Speaker MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2271         COEFF_RAM_CTL("Speaker MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2272
2273         COEFF_RAM_CTL("Speaker MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2274         COEFF_RAM_CTL("Speaker MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2275
2276         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2277         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2278         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2279         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2280         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2281         COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2282
2283         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2284         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2285         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2286         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2287         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2288         COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2289
2290         COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2291         COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2292
2293         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2294         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2295         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2296         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2297         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2298         COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2299
2300         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2301         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2302         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2303         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2304         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2305         COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2306
2307         COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2308         COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2309
2310         COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2311         COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2312
2313         COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2314         COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2315
2316         COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2317
2318         COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2319
2320         COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96),
2321
2322         COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2323         COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2324
2325         COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2326         COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2327
2328         COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2329
2330         COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2331
2332         COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad),
2333
2334         COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae),
2335
2336         COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf),
2337
2338         COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2339         COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2340
2341         COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2342         COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2343
2344         COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2345         COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2346 };
2347
2348 static struct snd_soc_dapm_widget const tscs454_dapm_widgets[] = {
2349         /* R_PLLCTL PG 0 ADDR 0x15 */
2350         SND_SOC_DAPM_SUPPLY("PLL 1 Power", R_PLLCTL, FB_PLLCTL_PU_PLL1, 0,
2351                         pll_power_event,
2352                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2353         SND_SOC_DAPM_SUPPLY("PLL 2 Power", R_PLLCTL, FB_PLLCTL_PU_PLL2, 0,
2354                         pll_power_event,
2355                         SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
2356         /* R_I2SPINC0 PG 0 ADDR 0x22 */
2357         SND_SOC_DAPM_AIF_OUT("DAI 3 Out", "DAI 3 Capture", 0,
2358                         R_I2SPINC0, FB_I2SPINC0_SDO3TRI, 1),
2359         SND_SOC_DAPM_AIF_OUT("DAI 2 Out", "DAI 2 Capture", 0,
2360                         R_I2SPINC0, FB_I2SPINC0_SDO2TRI, 1),
2361         SND_SOC_DAPM_AIF_OUT("DAI 1 Out", "DAI 1 Capture", 0,
2362                         R_I2SPINC0, FB_I2SPINC0_SDO1TRI, 1),
2363         /* R_PWRM0 PG 0 ADDR 0x33 */
2364         SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL,
2365                         R_PWRM0, FB_PWRM0_INPROC3PU, 0),
2366         SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL,
2367                         R_PWRM0, FB_PWRM0_INPROC2PU, 0),
2368         SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL,
2369                         R_PWRM0, FB_PWRM0_INPROC1PU, 0),
2370         SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL,
2371                         R_PWRM0, FB_PWRM0_INPROC0PU, 0),
2372         SND_SOC_DAPM_SUPPLY("Mic Bias 2",
2373                         R_PWRM0, FB_PWRM0_MICB2PU, 0, NULL, 0),
2374         SND_SOC_DAPM_SUPPLY("Mic Bias 1", R_PWRM0,
2375                         FB_PWRM0_MICB1PU, 0, NULL, 0),
2376         /* R_PWRM1 PG 0 ADDR 0x34 */
2377         SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0),
2378         SND_SOC_DAPM_SUPPLY("Headphone Left Power",
2379                         R_PWRM1, FB_PWRM1_HPLPU, 0, NULL, 0),
2380         SND_SOC_DAPM_SUPPLY("Headphone Right Power",
2381                         R_PWRM1, FB_PWRM1_HPRPU, 0, NULL, 0),
2382         SND_SOC_DAPM_SUPPLY("Speaker Left Power",
2383                         R_PWRM1, FB_PWRM1_SPKLPU, 0, NULL, 0),
2384         SND_SOC_DAPM_SUPPLY("Speaker Right Power",
2385                         R_PWRM1, FB_PWRM1_SPKRPU, 0, NULL, 0),
2386         SND_SOC_DAPM_SUPPLY("Differential Input 2 Power",
2387                         R_PWRM1, FB_PWRM1_D2S2PU, 0, NULL, 0),
2388         SND_SOC_DAPM_SUPPLY("Differential Input 1 Power",
2389                         R_PWRM1, FB_PWRM1_D2S1PU, 0, NULL, 0),
2390         /* R_PWRM2 PG 0 ADDR 0x35 */
2391         SND_SOC_DAPM_SUPPLY("DAI 3 Out Power",
2392                         R_PWRM2, FB_PWRM2_I2S3OPU, 0, NULL, 0),
2393         SND_SOC_DAPM_SUPPLY("DAI 2 Out Power",
2394                         R_PWRM2, FB_PWRM2_I2S2OPU, 0, NULL, 0),
2395         SND_SOC_DAPM_SUPPLY("DAI 1 Out Power",
2396                         R_PWRM2, FB_PWRM2_I2S1OPU, 0, NULL, 0),
2397         SND_SOC_DAPM_SUPPLY("DAI 3 In Power",
2398                         R_PWRM2, FB_PWRM2_I2S3IPU, 0, NULL, 0),
2399         SND_SOC_DAPM_SUPPLY("DAI 2 In Power",
2400                         R_PWRM2, FB_PWRM2_I2S2IPU, 0, NULL, 0),
2401         SND_SOC_DAPM_SUPPLY("DAI 1 In Power",
2402                         R_PWRM2, FB_PWRM2_I2S1IPU, 0, NULL, 0),
2403         /* R_PWRM3 PG 0 ADDR 0x36 */
2404         SND_SOC_DAPM_SUPPLY("Line Out Left Power",
2405                         R_PWRM3, FB_PWRM3_LLINEPU, 0, NULL, 0),
2406         SND_SOC_DAPM_SUPPLY("Line Out Right Power",
2407                         R_PWRM3, FB_PWRM3_RLINEPU, 0, NULL, 0),
2408         /* R_PWRM4 PG 0 ADDR 0x37 */
2409         SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0),
2410         SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0),
2411         SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0),
2412         SND_SOC_DAPM_DAC("ClassD Left", NULL, R_PWRM4, FB_PWRM4_OPSPKLPU, 0),
2413         SND_SOC_DAPM_DAC("ClassD Right", NULL, R_PWRM4, FB_PWRM4_OPSPKRPU, 0),
2414         /* R_AUDIOMUX1  PG 0 ADDR 0x3A */
2415         SND_SOC_DAPM_MUX("DAI 2 Out Mux", SND_SOC_NOPM, 0, 0,
2416                         &dai2_mux_dapm_enum),
2417         SND_SOC_DAPM_MUX("DAI 1 Out Mux", SND_SOC_NOPM, 0, 0,
2418                         &dai1_mux_dapm_enum),
2419         /* R_AUDIOMUX2 PG 0 ADDR 0x3B */
2420         SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
2421                         &dac_mux_dapm_enum),
2422         SND_SOC_DAPM_MUX("DAI 3 Out Mux", SND_SOC_NOPM, 0, 0,
2423                         &dai3_mux_dapm_enum),
2424         /* R_AUDIOMUX3 PG 0 ADDR 0x3C */
2425         SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0,
2426                         &sub_mux_dapm_enum),
2427         SND_SOC_DAPM_MUX("Speaker Mux", SND_SOC_NOPM, 0, 0,
2428                         &classd_mux_dapm_enum),
2429         /* R_HSDCTL1 PG 1 ADDR 0x01 */
2430         SND_SOC_DAPM_SUPPLY("GHS Detect Power", R_HSDCTL1,
2431                         FB_HSDCTL1_CON_DET_PWD, 1, NULL, 0),
2432         /* R_CH0AIC PG 1 ADDR 0x06 */
2433         SND_SOC_DAPM_MUX("Input Boost Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2434                         &in_bst_mux_ch0_dapm_enum),
2435         SND_SOC_DAPM_MUX("ADC Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2436                         &adc_mux_ch0_dapm_enum),
2437         SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2438                         &in_proc_mux_ch0_dapm_enum),
2439         /* R_CH1AIC PG 1 ADDR 0x07 */
2440         SND_SOC_DAPM_MUX("Input Boost Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2441                         &in_bst_mux_ch1_dapm_enum),
2442         SND_SOC_DAPM_MUX("ADC Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2443                         &adc_mux_ch1_dapm_enum),
2444         SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2445                         &in_proc_mux_ch1_dapm_enum),
2446         /* Virtual */
2447         SND_SOC_DAPM_AIF_IN("DAI 3 In", "DAI 3 Playback", 0,
2448                         SND_SOC_NOPM, 0, 0),
2449         SND_SOC_DAPM_AIF_IN("DAI 2 In", "DAI 2 Playback", 0,
2450                         SND_SOC_NOPM, 0, 0),
2451         SND_SOC_DAPM_AIF_IN("DAI 1 In", "DAI 1 Playback", 0,
2452                         SND_SOC_NOPM, 0, 0),
2453         SND_SOC_DAPM_SUPPLY("PLLs", SND_SOC_NOPM, 0, 0, NULL, 0),
2454         SND_SOC_DAPM_OUTPUT("Sub Out"),
2455         SND_SOC_DAPM_OUTPUT("Headphone Left"),
2456         SND_SOC_DAPM_OUTPUT("Headphone Right"),
2457         SND_SOC_DAPM_OUTPUT("Speaker Left"),
2458         SND_SOC_DAPM_OUTPUT("Speaker Right"),
2459         SND_SOC_DAPM_OUTPUT("Line Out Left"),
2460         SND_SOC_DAPM_OUTPUT("Line Out Right"),
2461         SND_SOC_DAPM_INPUT("D2S 2"),
2462         SND_SOC_DAPM_INPUT("D2S 1"),
2463         SND_SOC_DAPM_INPUT("Line In 1 Left"),
2464         SND_SOC_DAPM_INPUT("Line In 1 Right"),
2465         SND_SOC_DAPM_INPUT("Line In 2 Left"),
2466         SND_SOC_DAPM_INPUT("Line In 2 Right"),
2467         SND_SOC_DAPM_INPUT("Line In 3 Left"),
2468         SND_SOC_DAPM_INPUT("Line In 3 Right"),
2469         SND_SOC_DAPM_INPUT("DMic 1"),
2470         SND_SOC_DAPM_INPUT("DMic 2"),
2471
2472         SND_SOC_DAPM_MUX("CH 0_1 Mux", SND_SOC_NOPM, 0, 0,
2473                         &ch_0_1_mux_dapm_enum),
2474         SND_SOC_DAPM_MUX("CH 2_3 Mux", SND_SOC_NOPM, 0, 0,
2475                         &ch_2_3_mux_dapm_enum),
2476         SND_SOC_DAPM_MUX("CH 4_5 Mux", SND_SOC_NOPM, 0, 0,
2477                         &ch_4_5_mux_dapm_enum),
2478 };
2479
2480 static struct snd_soc_dapm_route const tscs454_intercon[] = {
2481         /* PLLs */
2482         {"PLLs", NULL, "PLL 1 Power", pll_connected},
2483         {"PLLs", NULL, "PLL 2 Power", pll_connected},
2484         /* Inputs */
2485         {"DAI 3 In", NULL, "DAI 3 In Power"},
2486         {"DAI 2 In", NULL, "DAI 2 In Power"},
2487         {"DAI 1 In", NULL, "DAI 1 In Power"},
2488         /* Outputs */
2489         {"DAI 3 Out", NULL, "DAI 3 Out Power"},
2490         {"DAI 2 Out", NULL, "DAI 2 Out Power"},
2491         {"DAI 1 Out", NULL, "DAI 1 Out Power"},
2492         /* Ch Muxing */
2493         {"CH 0_1 Mux", "DAI 1", "DAI 1 In"},
2494         {"CH 0_1 Mux", "TDM 0_1", "DAI 1 In"},
2495         {"CH 2_3 Mux", "DAI 2", "DAI 2 In"},
2496         {"CH 2_3 Mux", "TDM 2_3", "DAI 1 In"},
2497         {"CH 4_5 Mux", "DAI 3", "DAI 2 In"},
2498         {"CH 4_5 Mux", "TDM 4_5", "DAI 1 In"},
2499         /* In/Out Muxing */
2500         {"DAI 1 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2501         {"DAI 1 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2502         {"DAI 1 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2503         {"DAI 2 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2504         {"DAI 2 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2505         {"DAI 2 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2506         {"DAI 3 Out Mux", "CH 0_1", "CH 0_1 Mux"},
2507         {"DAI 3 Out Mux", "CH 2_3", "CH 2_3 Mux"},
2508         {"DAI 3 Out Mux", "CH 4_5", "CH 4_5 Mux"},
2509         /******************
2510          * Playback Paths *
2511          ******************/
2512         /* DAC Path */
2513         {"DAC Mux", "CH 4_5", "CH 4_5 Mux"},
2514         {"DAC Mux", "CH 2_3", "CH 2_3 Mux"},
2515         {"DAC Mux", "CH 0_1", "CH 0_1 Mux"},
2516         {"DAC Left", NULL, "DAC Mux"},
2517         {"DAC Right", NULL, "DAC Mux"},
2518         {"DAC Left", NULL, "PLLs"},
2519         {"DAC Right", NULL, "PLLs"},
2520         {"Headphone Left", NULL, "Headphone Left Power"},
2521         {"Headphone Right", NULL, "Headphone Right Power"},
2522         {"Headphone Left", NULL, "DAC Left"},
2523         {"Headphone Right", NULL, "DAC Right"},
2524         /* Line Out */
2525         {"Line Out Left", NULL, "Line Out Left Power"},
2526         {"Line Out Right", NULL, "Line Out Right Power"},
2527         {"Line Out Left", NULL, "DAC Left"},
2528         {"Line Out Right", NULL, "DAC Right"},
2529         /* ClassD Path */
2530         {"Speaker Mux", "CH 4_5", "CH 4_5 Mux"},
2531         {"Speaker Mux", "CH 2_3", "CH 2_3 Mux"},
2532         {"Speaker Mux", "CH 0_1", "CH 0_1 Mux"},
2533         {"ClassD Left", NULL, "Speaker Mux"},
2534         {"ClassD Right", NULL, "Speaker Mux"},
2535         {"ClassD Left", NULL, "PLLs"},
2536         {"ClassD Right", NULL, "PLLs"},
2537         {"Speaker Left", NULL, "Speaker Left Power"},
2538         {"Speaker Right", NULL, "Speaker Right Power"},
2539         {"Speaker Left", NULL, "ClassD Left"},
2540         {"Speaker Right", NULL, "ClassD Right"},
2541         /* Sub Path */
2542         {"Sub Mux", "CH 4", "CH 4_5 Mux"},
2543         {"Sub Mux", "CH 5", "CH 4_5 Mux"},
2544         {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"},
2545         {"Sub Mux", "CH 2", "CH 2_3 Mux"},
2546         {"Sub Mux", "CH 3", "CH 2_3 Mux"},
2547         {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"},
2548         {"Sub Mux", "CH 0", "CH 0_1 Mux"},
2549         {"Sub Mux", "CH 1", "CH 0_1 Mux"},
2550         {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"},
2551         {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"},
2552         {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"},
2553         {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"},
2554         {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"},
2555         {"Sub Mux", "DMic 2 Left", "DMic 2"},
2556         {"Sub Mux", "DMic 2 Right", "DMic 2"},
2557         {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"},
2558         {"Sub Mux", "ClassD Left", "ClassD Left"},
2559         {"Sub Mux", "ClassD Right", "ClassD Right"},
2560         {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"},
2561         {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"},
2562         {"Sub", NULL, "Sub Mux"},
2563         {"Sub", NULL, "PLLs"},
2564         {"Sub Out", NULL, "Sub Power"},
2565         {"Sub Out", NULL, "Sub"},
2566         /*****************
2567          * Capture Paths *
2568          *****************/
2569         {"Input Boost Channel 0 Mux", "Input 3", "Line In 3 Left"},
2570         {"Input Boost Channel 0 Mux", "Input 2", "Line In 2 Left"},
2571         {"Input Boost Channel 0 Mux", "Input 1", "Line In 1 Left"},
2572         {"Input Boost Channel 0 Mux", "D2S", "D2S 1"},
2573
2574         {"Input Boost Channel 1 Mux", "Input 3", "Line In 3 Right"},
2575         {"Input Boost Channel 1 Mux", "Input 2", "Line In 2 Right"},
2576         {"Input Boost Channel 1 Mux", "Input 1", "Line In 1 Right"},
2577         {"Input Boost Channel 1 Mux", "D2S", "D2S 2"},
2578
2579         {"ADC Channel 0 Mux", "Input 3 Boost Bypass", "Line In 3 Left"},
2580         {"ADC Channel 0 Mux", "Input 2 Boost Bypass", "Line In 2 Left"},
2581         {"ADC Channel 0 Mux", "Input 1 Boost Bypass", "Line In 1 Left"},
2582         {"ADC Channel 0 Mux", "Input Boost", "Input Boost Channel 0 Mux"},
2583
2584         {"ADC Channel 1 Mux", "Input 3 Boost Bypass", "Line In 3 Right"},
2585         {"ADC Channel 1 Mux", "Input 2 Boost Bypass", "Line In 2 Right"},
2586         {"ADC Channel 1 Mux", "Input 1 Boost Bypass", "Line In 1 Right"},
2587         {"ADC Channel 1 Mux", "Input Boost", "Input Boost Channel 1 Mux"},
2588
2589         {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"},
2590         {"Input Processor Channel 0 Mux", "DMic", "DMic 1"},
2591
2592         {"Input Processor Channel 0", NULL, "PLLs"},
2593         {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"},
2594
2595         {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"},
2596         {"Input Processor Channel 1 Mux", "DMic", "DMic 1"},
2597
2598         {"Input Processor Channel 1", NULL, "PLLs"},
2599         {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"},
2600
2601         {"Input Processor Channel 2", NULL, "PLLs"},
2602         {"Input Processor Channel 2", NULL, "DMic 2"},
2603
2604         {"Input Processor Channel 3", NULL, "PLLs"},
2605         {"Input Processor Channel 3", NULL, "DMic 2"},
2606
2607         {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2608         {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2609         {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"},
2610         {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"},
2611
2612         {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2613         {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2614         {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"},
2615         {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"},
2616
2617         {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2618         {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2619         {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"},
2620         {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"},
2621
2622         {"DAI 1 Out", NULL, "DAI 1 Out Mux"},
2623         {"DAI 2 Out", NULL, "DAI 2 Out Mux"},
2624         {"DAI 3 Out", NULL, "DAI 3 Out Mux"},
2625 };
2626
2627 /* This is used when BCLK is sourcing the PLLs */
2628 static int tscs454_set_sysclk(struct snd_soc_dai *dai,
2629                 int clk_id, unsigned int freq, int dir)
2630 {
2631         struct snd_soc_component *component = dai->component;
2632         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2633         unsigned int val;
2634         int bclk_dai;
2635
2636         dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq);
2637
2638         val = snd_soc_component_read(component, R_PLLCTL);
2639
2640         bclk_dai = (val & FM_PLLCTL_BCLKSEL) >> FB_PLLCTL_BCLKSEL;
2641         if (bclk_dai != dai->id)
2642                 return 0;
2643
2644         tscs454->bclk_freq = freq;
2645         return set_sysclk(component);
2646 }
2647
2648 static int tscs454_set_bclk_ratio(struct snd_soc_dai *dai,
2649                 unsigned int ratio)
2650 {
2651         unsigned int mask;
2652         int ret;
2653         struct snd_soc_component *component = dai->component;
2654         unsigned int val;
2655         int shift;
2656
2657         dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n",
2658                         dai->id, ratio);
2659
2660         switch (dai->id) {
2661         case TSCS454_DAI1_ID:
2662                 mask = FM_I2SCMC_BCMP1;
2663                 shift = FB_I2SCMC_BCMP1;
2664                 break;
2665         case TSCS454_DAI2_ID:
2666                 mask = FM_I2SCMC_BCMP2;
2667                 shift = FB_I2SCMC_BCMP2;
2668                 break;
2669         case TSCS454_DAI3_ID:
2670                 mask = FM_I2SCMC_BCMP3;
2671                 shift = FB_I2SCMC_BCMP3;
2672                 break;
2673         default:
2674                 ret = -EINVAL;
2675                 dev_err(component->dev, "Unknown audio interface (%d)\n", ret);
2676                 return ret;
2677         }
2678
2679         switch (ratio) {
2680         case 32:
2681                 val = I2SCMC_BCMP_32X;
2682                 break;
2683         case 40:
2684                 val = I2SCMC_BCMP_40X;
2685                 break;
2686         case 64:
2687                 val = I2SCMC_BCMP_64X;
2688                 break;
2689         default:
2690                 ret = -EINVAL;
2691                 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret);
2692                 return ret;
2693         }
2694
2695         ret = snd_soc_component_update_bits(component,
2696                         R_I2SCMC, mask, val << shift);
2697         if (ret < 0) {
2698                 dev_err(component->dev,
2699                                 "Failed to set DAI BCLK ratio (%d)\n", ret);
2700                 return ret;
2701         }
2702
2703         return 0;
2704 }
2705
2706 static inline int set_aif_master_from_fmt(struct snd_soc_component *component,
2707                 struct aif *aif, unsigned int fmt)
2708 {
2709         int ret;
2710
2711         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2712         case SND_SOC_DAIFMT_CBM_CFM:
2713                 aif->master = true;
2714                 break;
2715         case SND_SOC_DAIFMT_CBS_CFS:
2716                 aif->master = false;
2717                 break;
2718         default:
2719                 ret = -EINVAL;
2720                 dev_err(component->dev, "Unsupported format (%d)\n", ret);
2721                 return ret;
2722         }
2723
2724         return 0;
2725 }
2726
2727 static inline int set_aif_tdm_delay(struct snd_soc_component *component,
2728                 unsigned int dai_id, bool delay)
2729 {
2730         unsigned int reg;
2731         int ret;
2732
2733         switch (dai_id) {
2734         case TSCS454_DAI1_ID:
2735                 reg = R_TDMCTL0;
2736                 break;
2737         case TSCS454_DAI2_ID:
2738                 reg = R_PCMP2CTL0;
2739                 break;
2740         case TSCS454_DAI3_ID:
2741                 reg = R_PCMP3CTL0;
2742                 break;
2743         default:
2744                 ret = -EINVAL;
2745                 dev_err(component->dev,
2746                                 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2747                 return ret;
2748         }
2749         ret = snd_soc_component_update_bits(component,
2750                         reg, FM_TDMCTL0_BDELAY, delay);
2751         if (ret < 0) {
2752                 dev_err(component->dev, "Failed to setup tdm format (%d)\n",
2753                                 ret);
2754                 return ret;
2755         }
2756
2757         return 0;
2758 }
2759
2760 static inline int set_aif_format_from_fmt(struct snd_soc_component *component,
2761                 unsigned int dai_id, unsigned int fmt)
2762 {
2763         unsigned int reg;
2764         unsigned int val;
2765         int ret;
2766
2767         switch (dai_id) {
2768         case TSCS454_DAI1_ID:
2769                 reg = R_I2SP1CTL;
2770                 break;
2771         case TSCS454_DAI2_ID:
2772                 reg = R_I2SP2CTL;
2773                 break;
2774         case TSCS454_DAI3_ID:
2775                 reg = R_I2SP3CTL;
2776                 break;
2777         default:
2778                 ret = -EINVAL;
2779                 dev_err(component->dev,
2780                                 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2781                 return ret;
2782         }
2783
2784         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2785         case SND_SOC_DAIFMT_RIGHT_J:
2786                 val = FV_FORMAT_RIGHT;
2787                 break;
2788         case SND_SOC_DAIFMT_LEFT_J:
2789                 val = FV_FORMAT_LEFT;
2790                 break;
2791         case SND_SOC_DAIFMT_I2S:
2792                 val = FV_FORMAT_I2S;
2793                 break;
2794         case SND_SOC_DAIFMT_DSP_A:
2795                 ret = set_aif_tdm_delay(component, dai_id, true);
2796                 if (ret < 0)
2797                         return ret;
2798                 val = FV_FORMAT_TDM;
2799                 break;
2800         case SND_SOC_DAIFMT_DSP_B:
2801                 ret = set_aif_tdm_delay(component, dai_id, false);
2802                 if (ret < 0)
2803                         return ret;
2804                 val = FV_FORMAT_TDM;
2805                 break;
2806         default:
2807                 ret = -EINVAL;
2808                 dev_err(component->dev, "Format unsupported (%d)\n", ret);
2809                 return ret;
2810         }
2811
2812         ret = snd_soc_component_update_bits(component,
2813                         reg, FM_I2SPCTL_FORMAT, val);
2814         if (ret < 0) {
2815                 dev_err(component->dev, "Failed to set DAI %d format (%d)\n",
2816                                 dai_id + 1, ret);
2817                 return ret;
2818         }
2819
2820         return 0;
2821 }
2822
2823 static inline int
2824 set_aif_clock_format_from_fmt(struct snd_soc_component *component,
2825                 unsigned int dai_id, unsigned int fmt)
2826 {
2827         unsigned int reg;
2828         unsigned int val;
2829         int ret;
2830
2831         switch (dai_id) {
2832         case TSCS454_DAI1_ID:
2833                 reg = R_I2SP1CTL;
2834                 break;
2835         case TSCS454_DAI2_ID:
2836                 reg = R_I2SP2CTL;
2837                 break;
2838         case TSCS454_DAI3_ID:
2839                 reg = R_I2SP3CTL;
2840                 break;
2841         default:
2842                 ret = -EINVAL;
2843                 dev_err(component->dev,
2844                                 "DAI %d unknown (%d)\n", dai_id + 1, ret);
2845                 return ret;
2846         }
2847
2848         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2849         case SND_SOC_DAIFMT_NB_NF:
2850                 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_NOT_INVERTED;
2851                 break;
2852         case SND_SOC_DAIFMT_NB_IF:
2853                 val = FV_BCLKP_NOT_INVERTED | FV_LRCLKP_INVERTED;
2854                 break;
2855         case SND_SOC_DAIFMT_IB_NF:
2856                 val = FV_BCLKP_INVERTED | FV_LRCLKP_NOT_INVERTED;
2857                 break;
2858         case SND_SOC_DAIFMT_IB_IF:
2859                 val = FV_BCLKP_INVERTED | FV_LRCLKP_INVERTED;
2860                 break;
2861         default:
2862                 ret = -EINVAL;
2863                 dev_err(component->dev, "Format unknown (%d)\n", ret);
2864                 return ret;
2865         }
2866
2867         ret = snd_soc_component_update_bits(component, reg,
2868                         FM_I2SPCTL_BCLKP | FM_I2SPCTL_LRCLKP, val);
2869         if (ret < 0) {
2870                 dev_err(component->dev,
2871                                 "Failed to set clock polarity for DAI%d (%d)\n",
2872                                 dai_id + 1, ret);
2873                 return ret;
2874         }
2875
2876         return 0;
2877 }
2878
2879 static int tscs454_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2880 {
2881         struct snd_soc_component *component = dai->component;
2882         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
2883         struct aif *aif = &tscs454->aifs[dai->id];
2884         int ret;
2885
2886         ret = set_aif_master_from_fmt(component, aif, fmt);
2887         if (ret < 0)
2888                 return ret;
2889
2890         ret = set_aif_format_from_fmt(component, dai->id, fmt);
2891         if (ret < 0)
2892                 return ret;
2893
2894         ret = set_aif_clock_format_from_fmt(component, dai->id, fmt);
2895         if (ret < 0)
2896                 return ret;
2897
2898         return 0;
2899 }
2900
2901 static int tscs454_dai1_set_tdm_slot(struct snd_soc_dai *dai,
2902                 unsigned int tx_mask, unsigned int rx_mask, int slots,
2903                 int slot_width)
2904 {
2905         struct snd_soc_component *component = dai->component;
2906         unsigned int val;
2907         int ret;
2908
2909         if (!slots)
2910                 return 0;
2911
2912         if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2913                 ret = -EINVAL;
2914                 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2915                 return ret;
2916         }
2917
2918         switch (slots) {
2919         case 2:
2920                 val = FV_TDMSO_2 | FV_TDMSI_2;
2921                 break;
2922         case 4:
2923                 val = FV_TDMSO_4 | FV_TDMSI_4;
2924                 break;
2925         case 6:
2926                 val = FV_TDMSO_6 | FV_TDMSI_6;
2927                 break;
2928         default:
2929                 ret = -EINVAL;
2930                 dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
2931                 return ret;
2932         }
2933
2934         switch (slot_width) {
2935         case 16:
2936                 val = val | FV_TDMDSS_16;
2937                 break;
2938         case 24:
2939                 val = val | FV_TDMDSS_24;
2940                 break;
2941         case 32:
2942                 val = val | FV_TDMDSS_32;
2943                 break;
2944         default:
2945                 ret = -EINVAL;
2946                 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
2947                 return ret;
2948         }
2949         ret = snd_soc_component_write(component, R_TDMCTL1, val);
2950         if (ret < 0) {
2951                 dev_err(component->dev, "Failed to set slots (%d)\n", ret);
2952                 return ret;
2953         }
2954
2955         return 0;
2956 }
2957
2958 static int tscs454_dai23_set_tdm_slot(struct snd_soc_dai *dai,
2959                 unsigned int tx_mask, unsigned int rx_mask, int slots,
2960                 int slot_width)
2961 {
2962         struct snd_soc_component *component = dai->component;
2963         unsigned int reg;
2964         unsigned int val;
2965         int ret;
2966
2967         if (!slots)
2968                 return 0;
2969
2970         if (tx_mask >= (1 << slots) || rx_mask >= (1 << slots)) {
2971                 ret = -EINVAL;
2972                 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret);
2973                 return ret;
2974         }
2975
2976         switch (dai->id) {
2977         case TSCS454_DAI2_ID:
2978                 reg = R_PCMP2CTL1;
2979                 break;
2980         case TSCS454_DAI3_ID:
2981                 reg = R_PCMP3CTL1;
2982                 break;
2983         default:
2984                 ret = -EINVAL;
2985                 dev_err(component->dev, "Unrecognized interface %d (%d)\n",
2986                                 dai->id, ret);
2987                 return ret;
2988         }
2989
2990         switch (slots) {
2991         case 1:
2992                 val = FV_PCMSOP_1 | FV_PCMSIP_1;
2993                 break;
2994         case 2:
2995                 val = FV_PCMSOP_2 | FV_PCMSIP_2;
2996                 break;
2997         default:
2998                 ret = -EINVAL;
2999                 dev_err(component->dev, "Invalid number of slots (%d)\n", ret);
3000                 return ret;
3001         }
3002
3003         switch (slot_width) {
3004         case 16:
3005                 val = val | FV_PCMDSSP_16;
3006                 break;
3007         case 24:
3008                 val = val | FV_PCMDSSP_24;
3009                 break;
3010         case 32:
3011                 val = val | FV_PCMDSSP_32;
3012                 break;
3013         default:
3014                 ret = -EINVAL;
3015                 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret);
3016                 return ret;
3017         }
3018         ret = snd_soc_component_write(component, reg, val);
3019         if (ret < 0) {
3020                 dev_err(component->dev, "Failed to set slots (%d)\n", ret);
3021                 return ret;
3022         }
3023
3024         return 0;
3025 }
3026
3027 static int set_aif_fs(struct snd_soc_component *component,
3028                 unsigned int id,
3029                 unsigned int rate)
3030 {
3031         unsigned int reg;
3032         unsigned int br;
3033         unsigned int bm;
3034         int ret;
3035
3036         switch (rate) {
3037         case 8000:
3038                 br = FV_I2SMBR_32;
3039                 bm = FV_I2SMBM_0PT25;
3040                 break;
3041         case 16000:
3042                 br = FV_I2SMBR_32;
3043                 bm = FV_I2SMBM_0PT5;
3044                 break;
3045         case 24000:
3046                 br = FV_I2SMBR_48;
3047                 bm = FV_I2SMBM_0PT5;
3048                 break;
3049         case 32000:
3050                 br = FV_I2SMBR_32;
3051                 bm = FV_I2SMBM_1;
3052                 break;
3053         case 48000:
3054                 br = FV_I2SMBR_48;
3055                 bm = FV_I2SMBM_1;
3056                 break;
3057         case 96000:
3058                 br = FV_I2SMBR_48;
3059                 bm = FV_I2SMBM_2;
3060                 break;
3061         case 11025:
3062                 br = FV_I2SMBR_44PT1;
3063                 bm = FV_I2SMBM_0PT25;
3064                 break;
3065         case 22050:
3066                 br = FV_I2SMBR_44PT1;
3067                 bm = FV_I2SMBM_0PT5;
3068                 break;
3069         case 44100:
3070                 br = FV_I2SMBR_44PT1;
3071                 bm = FV_I2SMBM_1;
3072                 break;
3073         case 88200:
3074                 br = FV_I2SMBR_44PT1;
3075                 bm = FV_I2SMBM_2;
3076                 break;
3077         default:
3078                 ret = -EINVAL;
3079                 dev_err(component->dev, "Unsupported sample rate (%d)\n", ret);
3080                 return ret;
3081         }
3082
3083         switch (id) {
3084         case TSCS454_DAI1_ID:
3085                 reg = R_I2S1MRATE;
3086                 break;
3087         case TSCS454_DAI2_ID:
3088                 reg = R_I2S2MRATE;
3089                 break;
3090         case TSCS454_DAI3_ID:
3091                 reg = R_I2S3MRATE;
3092                 break;
3093         default:
3094                 ret = -EINVAL;
3095                 dev_err(component->dev, "DAI ID not recognized (%d)\n", ret);
3096                 return ret;
3097         }
3098
3099         ret = snd_soc_component_update_bits(component, reg,
3100                         FM_I2SMRATE_I2SMBR | FM_I2SMRATE_I2SMBM, br|bm);
3101         if (ret < 0) {
3102                 dev_err(component->dev,
3103                                 "Failed to update register (%d)\n", ret);
3104                 return ret;
3105         }
3106
3107         return 0;
3108 }
3109
3110 static int set_aif_sample_format(struct snd_soc_component *component,
3111                 snd_pcm_format_t format,
3112                 int aif_id)
3113 {
3114         unsigned int reg;
3115         unsigned int width;
3116         int ret;
3117
3118         switch (format) {
3119         case SNDRV_PCM_FORMAT_S16_LE:
3120                 width = FV_WL_16;
3121                 break;
3122         case SNDRV_PCM_FORMAT_S20_3LE:
3123                 width = FV_WL_20;
3124                 break;
3125         case SNDRV_PCM_FORMAT_S24_3LE:
3126                 width = FV_WL_24;
3127                 break;
3128         case SNDRV_PCM_FORMAT_S24_LE:
3129         case SNDRV_PCM_FORMAT_S32_LE:
3130                 width = FV_WL_32;
3131                 break;
3132         default:
3133                 ret = -EINVAL;
3134                 dev_err(component->dev, "Unsupported format width (%d)\n", ret);
3135                 return ret;
3136         }
3137
3138         switch (aif_id) {
3139         case TSCS454_DAI1_ID:
3140                 reg = R_I2SP1CTL;
3141                 break;
3142         case TSCS454_DAI2_ID:
3143                 reg = R_I2SP2CTL;
3144                 break;
3145         case TSCS454_DAI3_ID:
3146                 reg = R_I2SP3CTL;
3147                 break;
3148         default:
3149                 ret = -EINVAL;
3150                 dev_err(component->dev, "AIF ID not recognized (%d)\n", ret);
3151                 return ret;
3152         }
3153
3154         ret = snd_soc_component_update_bits(component,
3155                         reg, FM_I2SPCTL_WL, width);
3156         if (ret < 0) {
3157                 dev_err(component->dev,
3158                                 "Failed to set sample width (%d)\n", ret);
3159                 return ret;
3160         }
3161
3162         return 0;
3163 }
3164
3165 static int tscs454_hw_params(struct snd_pcm_substream *substream,
3166                 struct snd_pcm_hw_params *params,
3167                 struct snd_soc_dai *dai)
3168 {
3169         struct snd_soc_component *component = dai->component;
3170         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3171         unsigned int fs = params_rate(params);
3172         struct aif *aif = &tscs454->aifs[dai->id];
3173         unsigned int val;
3174         int ret;
3175
3176         mutex_lock(&tscs454->aifs_status_lock);
3177
3178         dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__,
3179                         aif->id, fs);
3180
3181         if (!aif_active(&tscs454->aifs_status, aif->id)) {
3182                 if (PLL_44_1K_RATE % fs)
3183                         aif->pll = &tscs454->pll1;
3184                 else
3185                         aif->pll = &tscs454->pll2;
3186
3187                 dev_dbg(component->dev, "Reserving pll %d for aif %d\n",
3188                                 aif->pll->id, aif->id);
3189
3190                 reserve_pll(aif->pll);
3191         }
3192
3193         if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */
3194                 val = snd_soc_component_read(component, R_ISRC);
3195                 if ((val & FM_ISRC_IBR) == FV_IBR_48)
3196                         tscs454->internal_rate.pll = &tscs454->pll1;
3197                 else
3198                         tscs454->internal_rate.pll = &tscs454->pll2;
3199
3200                 dev_dbg(component->dev, "Reserving pll %d for ir\n",
3201                                 tscs454->internal_rate.pll->id);
3202
3203                 reserve_pll(tscs454->internal_rate.pll);
3204         }
3205
3206         ret = set_aif_fs(component, aif->id, fs);
3207         if (ret < 0) {
3208                 dev_err(component->dev, "Failed to set aif fs (%d)\n", ret);
3209                 goto exit;
3210         }
3211
3212         ret = set_aif_sample_format(component, params_format(params), aif->id);
3213         if (ret < 0) {
3214                 dev_err(component->dev,
3215                                 "Failed to set aif sample format (%d)\n", ret);
3216                 goto exit;
3217         }
3218
3219         set_aif_status_active(&tscs454->aifs_status, aif->id,
3220                         substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3221
3222         dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n",
3223                 aif->id, tscs454->aifs_status.streams);
3224
3225         ret = 0;
3226 exit:
3227         mutex_unlock(&tscs454->aifs_status_lock);
3228
3229         return ret;
3230 }
3231
3232 static int tscs454_hw_free(struct snd_pcm_substream *substream,
3233                 struct snd_soc_dai *dai)
3234 {
3235         struct snd_soc_component *component = dai->component;
3236         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3237         struct aif *aif = &tscs454->aifs[dai->id];
3238
3239         return aif_free(component, aif,
3240                         substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
3241 }
3242
3243 static int tscs454_prepare(struct snd_pcm_substream *substream,
3244                 struct snd_soc_dai *dai)
3245 {
3246         int ret;
3247         struct snd_soc_component *component = dai->component;
3248         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3249         struct aif *aif = &tscs454->aifs[dai->id];
3250
3251         ret = aif_prepare(component, aif);
3252         if (ret < 0)
3253                 return ret;
3254
3255         return 0;
3256 }
3257
3258 static struct snd_soc_dai_ops const tscs454_dai1_ops = {
3259         .set_sysclk     = tscs454_set_sysclk,
3260         .set_bclk_ratio = tscs454_set_bclk_ratio,
3261         .set_fmt        = tscs454_set_dai_fmt,
3262         .set_tdm_slot   = tscs454_dai1_set_tdm_slot,
3263         .hw_params      = tscs454_hw_params,
3264         .hw_free        = tscs454_hw_free,
3265         .prepare        = tscs454_prepare,
3266 };
3267
3268 static struct snd_soc_dai_ops const tscs454_dai23_ops = {
3269         .set_sysclk     = tscs454_set_sysclk,
3270         .set_bclk_ratio = tscs454_set_bclk_ratio,
3271         .set_fmt        = tscs454_set_dai_fmt,
3272         .set_tdm_slot   = tscs454_dai23_set_tdm_slot,
3273         .hw_params      = tscs454_hw_params,
3274         .hw_free        = tscs454_hw_free,
3275         .prepare        = tscs454_prepare,
3276 };
3277
3278 static int tscs454_probe(struct snd_soc_component *component)
3279 {
3280         struct tscs454 *tscs454 = snd_soc_component_get_drvdata(component);
3281         unsigned int val;
3282         int ret = 0;
3283
3284         switch (tscs454->sysclk_src_id) {
3285         case PLL_INPUT_XTAL:
3286                 val = FV_PLLISEL_XTAL;
3287                 break;
3288         case PLL_INPUT_MCLK1:
3289                 val = FV_PLLISEL_MCLK1;
3290                 break;
3291         case PLL_INPUT_MCLK2:
3292                 val = FV_PLLISEL_MCLK2;
3293                 break;
3294         case PLL_INPUT_BCLK:
3295                 val = FV_PLLISEL_BCLK;
3296                 break;
3297         default:
3298                 ret = -EINVAL;
3299                 dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret);
3300                 return ret;
3301         }
3302
3303         ret = snd_soc_component_update_bits(component, R_PLLCTL,
3304                         FM_PLLCTL_PLLISEL, val);
3305         if (ret < 0) {
3306                 dev_err(component->dev, "Failed to set PLL input (%d)\n", ret);
3307                 return ret;
3308         }
3309
3310         if (tscs454->sysclk_src_id < PLL_INPUT_BCLK)
3311                 ret = set_sysclk(component);
3312
3313         return ret;
3314 }
3315
3316 static const struct snd_soc_component_driver soc_component_dev_tscs454 = {
3317         .probe =        tscs454_probe,
3318         .dapm_widgets = tscs454_dapm_widgets,
3319         .num_dapm_widgets = ARRAY_SIZE(tscs454_dapm_widgets),
3320         .dapm_routes = tscs454_intercon,
3321         .num_dapm_routes = ARRAY_SIZE(tscs454_intercon),
3322         .controls =     tscs454_snd_controls,
3323         .num_controls = ARRAY_SIZE(tscs454_snd_controls),
3324 };
3325
3326 #define TSCS454_RATES SNDRV_PCM_RATE_8000_96000
3327
3328 #define TSCS454_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
3329         | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \
3330         | SNDRV_PCM_FMTBIT_S32_LE)
3331
3332 static struct snd_soc_dai_driver tscs454_dais[] = {
3333         {
3334                 .name = "tscs454-dai1",
3335                 .id = TSCS454_DAI1_ID,
3336                 .playback = {
3337                         .stream_name = "DAI 1 Playback",
3338                         .channels_min = 1,
3339                         .channels_max = 6,
3340                         .rates = TSCS454_RATES,
3341                         .formats = TSCS454_FORMATS,},
3342                 .capture = {
3343                         .stream_name = "DAI 1 Capture",
3344                         .channels_min = 1,
3345                         .channels_max = 6,
3346                         .rates = TSCS454_RATES,
3347                         .formats = TSCS454_FORMATS,},
3348                 .ops = &tscs454_dai1_ops,
3349                 .symmetric_rates = 1,
3350                 .symmetric_channels = 1,
3351                 .symmetric_samplebits = 1,
3352         },
3353         {
3354                 .name = "tscs454-dai2",
3355                 .id = TSCS454_DAI2_ID,
3356                 .playback = {
3357                         .stream_name = "DAI 2 Playback",
3358                         .channels_min = 1,
3359                         .channels_max = 2,
3360                         .rates = TSCS454_RATES,
3361                         .formats = TSCS454_FORMATS,},
3362                 .capture = {
3363                         .stream_name = "DAI 2 Capture",
3364                         .channels_min = 1,
3365                         .channels_max = 2,
3366                         .rates = TSCS454_RATES,
3367                         .formats = TSCS454_FORMATS,},
3368                 .ops = &tscs454_dai23_ops,
3369                 .symmetric_rates = 1,
3370                 .symmetric_channels = 1,
3371                 .symmetric_samplebits = 1,
3372         },
3373         {
3374                 .name = "tscs454-dai3",
3375                 .id = TSCS454_DAI3_ID,
3376                 .playback = {
3377                         .stream_name = "DAI 3 Playback",
3378                         .channels_min = 1,
3379                         .channels_max = 2,
3380                         .rates = TSCS454_RATES,
3381                         .formats = TSCS454_FORMATS,},
3382                 .capture = {
3383                         .stream_name = "DAI 3 Capture",
3384                         .channels_min = 1,
3385                         .channels_max = 2,
3386                         .rates = TSCS454_RATES,
3387                         .formats = TSCS454_FORMATS,},
3388                 .ops = &tscs454_dai23_ops,
3389                 .symmetric_rates = 1,
3390                 .symmetric_channels = 1,
3391                 .symmetric_samplebits = 1,
3392         },
3393 };
3394
3395 static char const * const src_names[] = {
3396         "xtal", "mclk1", "mclk2", "bclk"};
3397
3398 static int tscs454_i2c_probe(struct i2c_client *i2c,
3399                 const struct i2c_device_id *id)
3400 {
3401         struct tscs454 *tscs454;
3402         int src;
3403         int ret;
3404
3405         tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL);
3406         if (!tscs454)
3407                 return -ENOMEM;
3408
3409         ret = tscs454_data_init(tscs454, i2c);
3410         if (ret < 0)
3411                 return ret;
3412
3413         i2c_set_clientdata(i2c, tscs454);
3414
3415         for (src = PLL_INPUT_XTAL; src < PLL_INPUT_BCLK; src++) {
3416                 tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]);
3417                 if (!IS_ERR(tscs454->sysclk)) {
3418                         break;
3419                 } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) {
3420                         ret = PTR_ERR(tscs454->sysclk);
3421                         dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret);
3422                         return ret;
3423                 }
3424         }
3425         dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]);
3426         tscs454->sysclk_src_id = src;
3427
3428         ret = regmap_write(tscs454->regmap,
3429                         R_RESET, FV_RESET_PWR_ON_DEFAULTS);
3430         if (ret < 0) {
3431                 dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret);
3432                 return ret;
3433         }
3434         regcache_mark_dirty(tscs454->regmap);
3435
3436         ret = regmap_register_patch(tscs454->regmap, tscs454_patch,
3437                         ARRAY_SIZE(tscs454_patch));
3438         if (ret < 0) {
3439                 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret);
3440                 return ret;
3441         }
3442         /* Sync pg sel reg with cache */
3443         regmap_write(tscs454->regmap, R_PAGESEL, 0x00);
3444
3445         ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454,
3446                         tscs454_dais, ARRAY_SIZE(tscs454_dais));
3447         if (ret) {
3448                 dev_err(&i2c->dev, "Failed to register component (%d)\n", ret);
3449                 return ret;
3450         }
3451
3452         return 0;
3453 }
3454
3455 static const struct i2c_device_id tscs454_i2c_id[] = {
3456         { "tscs454", 0 },
3457         { }
3458 };
3459 MODULE_DEVICE_TABLE(i2c, tscs454_i2c_id);
3460
3461 static const struct of_device_id tscs454_of_match[] = {
3462         { .compatible = "tempo,tscs454", },
3463         { }
3464 };
3465 MODULE_DEVICE_TABLE(of, tscs454_of_match);
3466
3467 static struct i2c_driver tscs454_i2c_driver = {
3468         .driver = {
3469                 .name = "tscs454",
3470                 .of_match_table = tscs454_of_match,
3471         },
3472         .probe =    tscs454_i2c_probe,
3473         .id_table = tscs454_i2c_id,
3474 };
3475
3476 module_i2c_driver(tscs454_i2c_driver);
3477
3478 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com");
3479 MODULE_DESCRIPTION("ASoC TSCS454 driver");
3480 MODULE_LICENSE("GPL v2");