1 // SPDX-License-Identifier: GPL-2.0
2 // tscs42xx.c -- TSCS42xx ALSA SoC Audio driver
3 // Copyright 2017 Tempo Semiconductor, Inc.
4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com>
6 #include <linux/kernel.h>
7 #include <linux/device.h>
8 #include <linux/regmap.h>
10 #include <linux/err.h>
11 #include <linux/string.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/mutex.h>
15 #include <linux/clk.h>
16 #include <sound/tlv.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc.h>
19 #include <sound/soc-dapm.h>
24 #define BIQUAD_COEFF_COUNT 5
25 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT)
27 #define COEFF_RAM_MAX_ADDR 0xcd
28 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1)
29 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT)
35 struct mutex audio_params_lock;
37 u8 coeff_ram[COEFF_RAM_SIZE];
38 bool coeff_ram_synced;
39 struct mutex coeff_ram_lock;
41 struct mutex pll_lock;
43 struct regmap *regmap;
49 struct coeff_ram_ctl {
51 struct soc_bytes_ext bytes_ext;
54 static bool tscs42xx_volatile(struct device *dev, unsigned int reg)
72 static bool tscs42xx_precious(struct device *dev, unsigned int reg)
87 static const struct regmap_config tscs42xx_regmap = {
91 .volatile_reg = tscs42xx_volatile,
92 .precious_reg = tscs42xx_precious,
93 .max_register = R_DACMBCREL3H,
95 .cache_type = REGCACHE_RBTREE,
96 .can_multi_write = true,
99 #define MAX_PLL_LOCK_20MS_WAITS 1
100 static bool plls_locked(struct snd_soc_component *component)
103 int count = MAX_PLL_LOCK_20MS_WAITS;
106 ret = snd_soc_component_read(component, R_PLLCTL0);
108 dev_err(component->dev,
109 "Failed to read PLL lock status (%d)\n", ret);
111 } else if (ret > 0) {
120 static int sample_rate_to_pll_freq_out(int sample_rate)
122 switch (sample_rate) {
139 #define DACCRSTAT_MAX_TRYS 10
140 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram,
141 unsigned int addr, unsigned int coeff_cnt)
143 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
148 for (cnt = 0; cnt < coeff_cnt; cnt++, addr++) {
150 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) {
151 ret = snd_soc_component_read(component, R_DACCRSTAT);
153 dev_err(component->dev,
154 "Failed to read stat (%d)\n", ret);
161 if (trys == DACCRSTAT_MAX_TRYS) {
163 dev_err(component->dev,
164 "dac coefficient write error (%d)\n", ret);
168 ret = regmap_write(tscs42xx->regmap, R_DACCRADDR, addr);
170 dev_err(component->dev,
171 "Failed to write dac ram address (%d)\n", ret);
175 ret = regmap_bulk_write(tscs42xx->regmap, R_DACCRWRL,
176 &coeff_ram[addr * COEFF_SIZE],
179 dev_err(component->dev,
180 "Failed to write dac ram (%d)\n", ret);
188 static int power_up_audio_plls(struct snd_soc_component *component)
190 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
196 freq_out = sample_rate_to_pll_freq_out(tscs42xx->samplerate);
198 case 122880000: /* 48k */
199 mask = RM_PLLCTL1C_PDB_PLL1;
200 val = RV_PLLCTL1C_PDB_PLL1_ENABLE;
202 case 112896000: /* 44.1k */
203 mask = RM_PLLCTL1C_PDB_PLL2;
204 val = RV_PLLCTL1C_PDB_PLL2_ENABLE;
208 dev_err(component->dev,
209 "Unrecognized PLL output freq (%d)\n", ret);
213 mutex_lock(&tscs42xx->pll_lock);
215 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, mask, val);
217 dev_err(component->dev, "Failed to turn PLL on (%d)\n", ret);
221 if (!plls_locked(component)) {
222 dev_err(component->dev, "Failed to lock plls\n");
229 mutex_unlock(&tscs42xx->pll_lock);
234 static int power_down_audio_plls(struct snd_soc_component *component)
236 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
239 mutex_lock(&tscs42xx->pll_lock);
241 ret = snd_soc_component_update_bits(component, R_PLLCTL1C,
242 RM_PLLCTL1C_PDB_PLL1,
243 RV_PLLCTL1C_PDB_PLL1_DISABLE);
245 dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret);
248 ret = snd_soc_component_update_bits(component, R_PLLCTL1C,
249 RM_PLLCTL1C_PDB_PLL2,
250 RV_PLLCTL1C_PDB_PLL2_DISABLE);
252 dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret);
258 mutex_unlock(&tscs42xx->pll_lock);
263 static int coeff_ram_get(struct snd_kcontrol *kcontrol,
264 struct snd_ctl_elem_value *ucontrol)
266 struct snd_soc_component *component =
267 snd_soc_kcontrol_component(kcontrol);
268 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
269 struct coeff_ram_ctl *ctl =
270 (struct coeff_ram_ctl *)kcontrol->private_value;
271 struct soc_bytes_ext *params = &ctl->bytes_ext;
273 mutex_lock(&tscs42xx->coeff_ram_lock);
275 memcpy(ucontrol->value.bytes.data,
276 &tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], params->max);
278 mutex_unlock(&tscs42xx->coeff_ram_lock);
283 static int coeff_ram_put(struct snd_kcontrol *kcontrol,
284 struct snd_ctl_elem_value *ucontrol)
286 struct snd_soc_component *component =
287 snd_soc_kcontrol_component(kcontrol);
288 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
289 struct coeff_ram_ctl *ctl =
290 (struct coeff_ram_ctl *)kcontrol->private_value;
291 struct soc_bytes_ext *params = &ctl->bytes_ext;
292 unsigned int coeff_cnt = params->max / COEFF_SIZE;
295 mutex_lock(&tscs42xx->coeff_ram_lock);
297 tscs42xx->coeff_ram_synced = false;
299 memcpy(&tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE],
300 ucontrol->value.bytes.data, params->max);
302 mutex_lock(&tscs42xx->pll_lock);
304 if (plls_locked(component)) {
305 ret = write_coeff_ram(component, tscs42xx->coeff_ram,
306 ctl->addr, coeff_cnt);
308 dev_err(component->dev,
309 "Failed to flush coeff ram cache (%d)\n", ret);
312 tscs42xx->coeff_ram_synced = true;
317 mutex_unlock(&tscs42xx->pll_lock);
319 mutex_unlock(&tscs42xx->coeff_ram_lock);
324 /* Input L Capture Route */
325 static char const * const input_select_text[] = {
326 "Line 1", "Line 2", "Line 3", "D2S"
329 static const struct soc_enum left_input_select_enum =
330 SOC_ENUM_SINGLE(R_INSELL, FB_INSELL, ARRAY_SIZE(input_select_text),
333 static const struct snd_kcontrol_new left_input_select =
334 SOC_DAPM_ENUM("LEFT_INPUT_SELECT_ENUM", left_input_select_enum);
336 /* Input R Capture Route */
337 static const struct soc_enum right_input_select_enum =
338 SOC_ENUM_SINGLE(R_INSELR, FB_INSELR, ARRAY_SIZE(input_select_text),
341 static const struct snd_kcontrol_new right_input_select =
342 SOC_DAPM_ENUM("RIGHT_INPUT_SELECT_ENUM", right_input_select_enum);
344 /* Input Channel Mapping */
345 static char const * const ch_map_select_text[] = {
346 "Normal", "Left to Right", "Right to Left", "Swap"
349 static const struct soc_enum ch_map_select_enum =
350 SOC_ENUM_SINGLE(R_AIC2, FB_AIC2_ADCDSEL, ARRAY_SIZE(ch_map_select_text),
353 static int dapm_vref_event(struct snd_soc_dapm_widget *w,
354 struct snd_kcontrol *kcontrol, int event)
360 static int dapm_micb_event(struct snd_soc_dapm_widget *w,
361 struct snd_kcontrol *kcontrol, int event)
367 static int pll_event(struct snd_soc_dapm_widget *w,
368 struct snd_kcontrol *kcontrol, int event)
370 struct snd_soc_component *component =
371 snd_soc_dapm_to_component(w->dapm);
374 if (SND_SOC_DAPM_EVENT_ON(event))
375 ret = power_up_audio_plls(component);
377 ret = power_down_audio_plls(component);
382 static int dac_event(struct snd_soc_dapm_widget *w,
383 struct snd_kcontrol *kcontrol, int event)
385 struct snd_soc_component *component =
386 snd_soc_dapm_to_component(w->dapm);
387 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
390 mutex_lock(&tscs42xx->coeff_ram_lock);
392 if (!tscs42xx->coeff_ram_synced) {
393 ret = write_coeff_ram(component, tscs42xx->coeff_ram, 0x00,
394 COEFF_RAM_COEFF_COUNT);
397 tscs42xx->coeff_ram_synced = true;
402 mutex_unlock(&tscs42xx->coeff_ram_lock);
407 static const struct snd_soc_dapm_widget tscs42xx_dapm_widgets[] = {
409 SND_SOC_DAPM_SUPPLY_S("Vref", 1, R_PWRM2, FB_PWRM2_VREF, 0,
410 dapm_vref_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
413 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, pll_event,
414 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
417 SND_SOC_DAPM_DAC_E("DAC L", "HiFi Playback", R_PWRM2, FB_PWRM2_HPL, 0,
418 dac_event, SND_SOC_DAPM_POST_PMU),
419 SND_SOC_DAPM_DAC_E("DAC R", "HiFi Playback", R_PWRM2, FB_PWRM2_HPR, 0,
420 dac_event, SND_SOC_DAPM_POST_PMU),
421 SND_SOC_DAPM_OUTPUT("Headphone L"),
422 SND_SOC_DAPM_OUTPUT("Headphone R"),
425 SND_SOC_DAPM_DAC_E("ClassD L", "HiFi Playback",
426 R_PWRM2, FB_PWRM2_SPKL, 0,
427 dac_event, SND_SOC_DAPM_POST_PMU),
428 SND_SOC_DAPM_DAC_E("ClassD R", "HiFi Playback",
429 R_PWRM2, FB_PWRM2_SPKR, 0,
430 dac_event, SND_SOC_DAPM_POST_PMU),
431 SND_SOC_DAPM_OUTPUT("Speaker L"),
432 SND_SOC_DAPM_OUTPUT("Speaker R"),
435 SND_SOC_DAPM_PGA("Analog In PGA L", R_PWRM1, FB_PWRM1_PGAL, 0, NULL, 0),
436 SND_SOC_DAPM_PGA("Analog In PGA R", R_PWRM1, FB_PWRM1_PGAR, 0, NULL, 0),
437 SND_SOC_DAPM_PGA("Analog Boost L", R_PWRM1, FB_PWRM1_BSTL, 0, NULL, 0),
438 SND_SOC_DAPM_PGA("Analog Boost R", R_PWRM1, FB_PWRM1_BSTR, 0, NULL, 0),
439 SND_SOC_DAPM_PGA("ADC Mute", R_CNVRTR0, FB_CNVRTR0_HPOR, true, NULL, 0),
440 SND_SOC_DAPM_ADC("ADC L", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCL, 0),
441 SND_SOC_DAPM_ADC("ADC R", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCR, 0),
444 SND_SOC_DAPM_MUX("Input L Capture Route", R_PWRM2,
445 FB_PWRM2_INSELL, 0, &left_input_select),
446 SND_SOC_DAPM_MUX("Input R Capture Route", R_PWRM2,
447 FB_PWRM2_INSELR, 0, &right_input_select),
450 SND_SOC_DAPM_SUPPLY_S("Digital Mic Enable", 2, R_DMICCTL,
451 FB_DMICCTL_DMICEN, 0, NULL,
452 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
455 SND_SOC_DAPM_SUPPLY_S("Mic Bias", 2, R_PWRM1, FB_PWRM1_MICB,
456 0, dapm_micb_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD),
459 SND_SOC_DAPM_INPUT("Line In 1 L"),
460 SND_SOC_DAPM_INPUT("Line In 1 R"),
461 SND_SOC_DAPM_INPUT("Line In 2 L"),
462 SND_SOC_DAPM_INPUT("Line In 2 R"),
463 SND_SOC_DAPM_INPUT("Line In 3 L"),
464 SND_SOC_DAPM_INPUT("Line In 3 R"),
467 static const struct snd_soc_dapm_route tscs42xx_intercon[] = {
468 {"DAC L", NULL, "PLL"},
469 {"DAC R", NULL, "PLL"},
470 {"DAC L", NULL, "Vref"},
471 {"DAC R", NULL, "Vref"},
472 {"Headphone L", NULL, "DAC L"},
473 {"Headphone R", NULL, "DAC R"},
475 {"ClassD L", NULL, "PLL"},
476 {"ClassD R", NULL, "PLL"},
477 {"ClassD L", NULL, "Vref"},
478 {"ClassD R", NULL, "Vref"},
479 {"Speaker L", NULL, "ClassD L"},
480 {"Speaker R", NULL, "ClassD R"},
482 {"Input L Capture Route", NULL, "Vref"},
483 {"Input R Capture Route", NULL, "Vref"},
485 {"Mic Bias", NULL, "Vref"},
487 {"Input L Capture Route", "Line 1", "Line In 1 L"},
488 {"Input R Capture Route", "Line 1", "Line In 1 R"},
489 {"Input L Capture Route", "Line 2", "Line In 2 L"},
490 {"Input R Capture Route", "Line 2", "Line In 2 R"},
491 {"Input L Capture Route", "Line 3", "Line In 3 L"},
492 {"Input R Capture Route", "Line 3", "Line In 3 R"},
494 {"Analog In PGA L", NULL, "Input L Capture Route"},
495 {"Analog In PGA R", NULL, "Input R Capture Route"},
496 {"Analog Boost L", NULL, "Analog In PGA L"},
497 {"Analog Boost R", NULL, "Analog In PGA R"},
498 {"ADC Mute", NULL, "Analog Boost L"},
499 {"ADC Mute", NULL, "Analog Boost R"},
500 {"ADC L", NULL, "PLL"},
501 {"ADC R", NULL, "PLL"},
502 {"ADC L", NULL, "ADC Mute"},
503 {"ADC R", NULL, "ADC Mute"},
510 static char const * const eq_band_enable_text[] = {
520 static char const * const level_detection_text[] = {
525 static char const * const level_detection_window_text[] = {
530 static char const * const compressor_ratio_text[] = {
531 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1",
532 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1",
533 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1",
536 static DECLARE_TLV_DB_SCALE(hpvol_scale, -8850, 75, 0);
537 static DECLARE_TLV_DB_SCALE(spkvol_scale, -7725, 75, 0);
538 static DECLARE_TLV_DB_SCALE(dacvol_scale, -9563, 38, 0);
539 static DECLARE_TLV_DB_SCALE(adcvol_scale, -7125, 38, 0);
540 static DECLARE_TLV_DB_SCALE(invol_scale, -1725, 75, 0);
541 static DECLARE_TLV_DB_SCALE(mic_boost_scale, 0, 1000, 0);
542 static DECLARE_TLV_DB_MINMAX(mugain_scale, 0, 4650);
543 static DECLARE_TLV_DB_MINMAX(compth_scale, -9562, 0);
545 static const struct soc_enum eq1_band_enable_enum =
546 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ1_BE,
547 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text);
549 static const struct soc_enum eq2_band_enable_enum =
550 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ2_BE,
551 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text);
553 static const struct soc_enum cle_level_detection_enum =
554 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_LVL_MODE,
555 ARRAY_SIZE(level_detection_text),
556 level_detection_text);
558 static const struct soc_enum cle_level_detection_window_enum =
559 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_WINDOWSEL,
560 ARRAY_SIZE(level_detection_window_text),
561 level_detection_window_text);
563 static const struct soc_enum mbc_level_detection_enums[] = {
564 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1,
565 ARRAY_SIZE(level_detection_text),
566 level_detection_text),
567 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2,
568 ARRAY_SIZE(level_detection_text),
569 level_detection_text),
570 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3,
571 ARRAY_SIZE(level_detection_text),
572 level_detection_text),
575 static const struct soc_enum mbc_level_detection_window_enums[] = {
576 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1,
577 ARRAY_SIZE(level_detection_window_text),
578 level_detection_window_text),
579 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2,
580 ARRAY_SIZE(level_detection_window_text),
581 level_detection_window_text),
582 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3,
583 ARRAY_SIZE(level_detection_window_text),
584 level_detection_window_text),
587 static const struct soc_enum compressor_ratio_enum =
588 SOC_ENUM_SINGLE(R_CMPRAT, FB_CMPRAT,
589 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
591 static const struct soc_enum dac_mbc1_compressor_ratio_enum =
592 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT1_RATIO,
593 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
595 static const struct soc_enum dac_mbc2_compressor_ratio_enum =
596 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT2_RATIO,
597 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
599 static const struct soc_enum dac_mbc3_compressor_ratio_enum =
600 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT3_RATIO,
601 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text);
603 static int bytes_info_ext(struct snd_kcontrol *kcontrol,
604 struct snd_ctl_elem_info *ucontrol)
606 struct coeff_ram_ctl *ctl =
607 (struct coeff_ram_ctl *)kcontrol->private_value;
608 struct soc_bytes_ext *params = &ctl->bytes_ext;
610 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
611 ucontrol->count = params->max;
616 #define COEFF_RAM_CTL(xname, xcount, xaddr) \
617 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
618 .info = bytes_info_ext, \
619 .get = coeff_ram_get, .put = coeff_ram_put, \
620 .private_value = (unsigned long)&(struct coeff_ram_ctl) { \
622 .bytes_ext = {.max = xcount, }, \
626 static const struct snd_kcontrol_new tscs42xx_snd_controls[] = {
628 SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR,
629 FB_HPVOLL, 0x7F, 0, hpvol_scale),
630 SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR,
631 FB_SPKVOLL, 0x7F, 0, spkvol_scale),
632 SOC_DOUBLE_R_TLV("Master Volume", R_DACVOLL, R_DACVOLR,
633 FB_DACVOLL, 0xFF, 0, dacvol_scale),
634 SOC_DOUBLE_R_TLV("PCM Volume", R_ADCVOLL, R_ADCVOLR,
635 FB_ADCVOLL, 0xFF, 0, adcvol_scale),
636 SOC_DOUBLE_R_TLV("Input Volume", R_INVOLL, R_INVOLR,
637 FB_INVOLL, 0x3F, 0, invol_scale),
640 SOC_DOUBLE_R_TLV("Mic Boost Volume", R_INSELL, R_INSELR,
641 FB_INSELL_MICBSTL, FV_INSELL_MICBSTL_30DB,
644 /* Input Channel Map */
645 SOC_ENUM("Input Channel Map", ch_map_select_enum),
648 SOC_SINGLE("Mic Bias Boost Switch", 0x71, 0x07, 1, 0),
650 /* Headphone Auto Switching */
651 SOC_SINGLE("Headphone Auto Switching Switch",
652 R_CTL, FB_CTL_HPSWEN, 1, 0),
653 SOC_SINGLE("Headphone Detect Polarity Toggle Switch",
654 R_CTL, FB_CTL_HPSWPOL, 1, 0),
656 /* Coefficient Ram */
657 COEFF_RAM_CTL("Cascade1L BiQuad1", BIQUAD_SIZE, 0x00),
658 COEFF_RAM_CTL("Cascade1L BiQuad2", BIQUAD_SIZE, 0x05),
659 COEFF_RAM_CTL("Cascade1L BiQuad3", BIQUAD_SIZE, 0x0a),
660 COEFF_RAM_CTL("Cascade1L BiQuad4", BIQUAD_SIZE, 0x0f),
661 COEFF_RAM_CTL("Cascade1L BiQuad5", BIQUAD_SIZE, 0x14),
662 COEFF_RAM_CTL("Cascade1L BiQuad6", BIQUAD_SIZE, 0x19),
664 COEFF_RAM_CTL("Cascade1R BiQuad1", BIQUAD_SIZE, 0x20),
665 COEFF_RAM_CTL("Cascade1R BiQuad2", BIQUAD_SIZE, 0x25),
666 COEFF_RAM_CTL("Cascade1R BiQuad3", BIQUAD_SIZE, 0x2a),
667 COEFF_RAM_CTL("Cascade1R BiQuad4", BIQUAD_SIZE, 0x2f),
668 COEFF_RAM_CTL("Cascade1R BiQuad5", BIQUAD_SIZE, 0x34),
669 COEFF_RAM_CTL("Cascade1R BiQuad6", BIQUAD_SIZE, 0x39),
671 COEFF_RAM_CTL("Cascade1L Prescale", COEFF_SIZE, 0x1f),
672 COEFF_RAM_CTL("Cascade1R Prescale", COEFF_SIZE, 0x3f),
674 COEFF_RAM_CTL("Cascade2L BiQuad1", BIQUAD_SIZE, 0x40),
675 COEFF_RAM_CTL("Cascade2L BiQuad2", BIQUAD_SIZE, 0x45),
676 COEFF_RAM_CTL("Cascade2L BiQuad3", BIQUAD_SIZE, 0x4a),
677 COEFF_RAM_CTL("Cascade2L BiQuad4", BIQUAD_SIZE, 0x4f),
678 COEFF_RAM_CTL("Cascade2L BiQuad5", BIQUAD_SIZE, 0x54),
679 COEFF_RAM_CTL("Cascade2L BiQuad6", BIQUAD_SIZE, 0x59),
681 COEFF_RAM_CTL("Cascade2R BiQuad1", BIQUAD_SIZE, 0x60),
682 COEFF_RAM_CTL("Cascade2R BiQuad2", BIQUAD_SIZE, 0x65),
683 COEFF_RAM_CTL("Cascade2R BiQuad3", BIQUAD_SIZE, 0x6a),
684 COEFF_RAM_CTL("Cascade2R BiQuad4", BIQUAD_SIZE, 0x6f),
685 COEFF_RAM_CTL("Cascade2R BiQuad5", BIQUAD_SIZE, 0x74),
686 COEFF_RAM_CTL("Cascade2R BiQuad6", BIQUAD_SIZE, 0x79),
688 COEFF_RAM_CTL("Cascade2L Prescale", COEFF_SIZE, 0x5f),
689 COEFF_RAM_CTL("Cascade2R Prescale", COEFF_SIZE, 0x7f),
691 COEFF_RAM_CTL("Bass Extraction BiQuad1", BIQUAD_SIZE, 0x80),
692 COEFF_RAM_CTL("Bass Extraction BiQuad2", BIQUAD_SIZE, 0x85),
694 COEFF_RAM_CTL("Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
695 COEFF_RAM_CTL("Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
697 COEFF_RAM_CTL("Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
699 COEFF_RAM_CTL("Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
701 COEFF_RAM_CTL("Bass Mix", COEFF_SIZE, 0x96),
703 COEFF_RAM_CTL("Treb Extraction BiQuad1", BIQUAD_SIZE, 0x97),
704 COEFF_RAM_CTL("Treb Extraction BiQuad2", BIQUAD_SIZE, 0x9c),
706 COEFF_RAM_CTL("Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
707 COEFF_RAM_CTL("Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
709 COEFF_RAM_CTL("Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
711 COEFF_RAM_CTL("Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
713 COEFF_RAM_CTL("Treb Mix", COEFF_SIZE, 0xad),
715 COEFF_RAM_CTL("3D", COEFF_SIZE, 0xae),
717 COEFF_RAM_CTL("3D Mix", COEFF_SIZE, 0xaf),
719 COEFF_RAM_CTL("MBC1 BiQuad1", BIQUAD_SIZE, 0xb0),
720 COEFF_RAM_CTL("MBC1 BiQuad2", BIQUAD_SIZE, 0xb5),
722 COEFF_RAM_CTL("MBC2 BiQuad1", BIQUAD_SIZE, 0xba),
723 COEFF_RAM_CTL("MBC2 BiQuad2", BIQUAD_SIZE, 0xbf),
725 COEFF_RAM_CTL("MBC3 BiQuad1", BIQUAD_SIZE, 0xc4),
726 COEFF_RAM_CTL("MBC3 BiQuad2", BIQUAD_SIZE, 0xc9),
729 SOC_SINGLE("EQ1 Switch", R_CONFIG1, FB_CONFIG1_EQ1_EN, 1, 0),
730 SOC_SINGLE("EQ2 Switch", R_CONFIG1, FB_CONFIG1_EQ2_EN, 1, 0),
731 SOC_ENUM("EQ1 Band Enable", eq1_band_enable_enum),
732 SOC_ENUM("EQ2 Band Enable", eq2_band_enable_enum),
735 SOC_ENUM("CLE Level Detect",
736 cle_level_detection_enum),
737 SOC_ENUM("CLE Level Detect Win",
738 cle_level_detection_window_enum),
739 SOC_SINGLE("Expander Switch",
740 R_CLECTL, FB_CLECTL_EXP_EN, 1, 0),
741 SOC_SINGLE("Limiter Switch",
742 R_CLECTL, FB_CLECTL_LIMIT_EN, 1, 0),
743 SOC_SINGLE("Comp Switch",
744 R_CLECTL, FB_CLECTL_COMP_EN, 1, 0),
745 SOC_SINGLE_TLV("CLE Make-Up Gain Volume",
746 R_MUGAIN, FB_MUGAIN_CLEMUG, 0x1f, 0, mugain_scale),
747 SOC_SINGLE_TLV("Comp Thresh Volume",
748 R_COMPTH, FB_COMPTH, 0xff, 0, compth_scale),
749 SOC_ENUM("Comp Ratio", compressor_ratio_enum),
750 SND_SOC_BYTES("Comp Atk Time", R_CATKTCL, 2),
753 SOC_SINGLE("3D Switch", R_FXCTL, FB_FXCTL_3DEN, 1, 0),
754 SOC_SINGLE("Treble Switch", R_FXCTL, FB_FXCTL_TEEN, 1, 0),
755 SOC_SINGLE("Treble Bypass Switch", R_FXCTL, FB_FXCTL_TNLFBYPASS, 1, 0),
756 SOC_SINGLE("Bass Switch", R_FXCTL, FB_FXCTL_BEEN, 1, 0),
757 SOC_SINGLE("Bass Bypass Switch", R_FXCTL, FB_FXCTL_BNLFBYPASS, 1, 0),
760 SOC_SINGLE("MBC Band1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
761 SOC_SINGLE("MBC Band2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
762 SOC_SINGLE("MBC Band3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
763 SOC_ENUM("MBC Band1 Level Detect",
764 mbc_level_detection_enums[0]),
765 SOC_ENUM("MBC Band2 Level Detect",
766 mbc_level_detection_enums[1]),
767 SOC_ENUM("MBC Band3 Level Detect",
768 mbc_level_detection_enums[2]),
769 SOC_ENUM("MBC Band1 Level Detect Win",
770 mbc_level_detection_window_enums[0]),
771 SOC_ENUM("MBC Band2 Level Detect Win",
772 mbc_level_detection_window_enums[1]),
773 SOC_ENUM("MBC Band3 Level Detect Win",
774 mbc_level_detection_window_enums[2]),
776 SOC_SINGLE("MBC1 Phase Invert Switch",
777 R_DACMBCMUG1, FB_DACMBCMUG1_PHASE, 1, 0),
778 SOC_SINGLE_TLV("DAC MBC1 Make-Up Gain Volume",
779 R_DACMBCMUG1, FB_DACMBCMUG1_MUGAIN, 0x1f, 0, mugain_scale),
780 SOC_SINGLE_TLV("DAC MBC1 Comp Thresh Volume",
781 R_DACMBCTHR1, FB_DACMBCTHR1_THRESH, 0xff, 0, compth_scale),
782 SOC_ENUM("DAC MBC1 Comp Ratio",
783 dac_mbc1_compressor_ratio_enum),
784 SND_SOC_BYTES("DAC MBC1 Comp Atk Time", R_DACMBCATK1L, 2),
785 SND_SOC_BYTES("DAC MBC1 Comp Rel Time Const",
788 SOC_SINGLE("MBC2 Phase Invert Switch",
789 R_DACMBCMUG2, FB_DACMBCMUG2_PHASE, 1, 0),
790 SOC_SINGLE_TLV("DAC MBC2 Make-Up Gain Volume",
791 R_DACMBCMUG2, FB_DACMBCMUG2_MUGAIN, 0x1f, 0, mugain_scale),
792 SOC_SINGLE_TLV("DAC MBC2 Comp Thresh Volume",
793 R_DACMBCTHR2, FB_DACMBCTHR2_THRESH, 0xff, 0, compth_scale),
794 SOC_ENUM("DAC MBC2 Comp Ratio",
795 dac_mbc2_compressor_ratio_enum),
796 SND_SOC_BYTES("DAC MBC2 Comp Atk Time", R_DACMBCATK2L, 2),
797 SND_SOC_BYTES("DAC MBC2 Comp Rel Time Const",
800 SOC_SINGLE("MBC3 Phase Invert Switch",
801 R_DACMBCMUG3, FB_DACMBCMUG3_PHASE, 1, 0),
802 SOC_SINGLE_TLV("DAC MBC3 Make-Up Gain Volume",
803 R_DACMBCMUG3, FB_DACMBCMUG3_MUGAIN, 0x1f, 0, mugain_scale),
804 SOC_SINGLE_TLV("DAC MBC3 Comp Thresh Volume",
805 R_DACMBCTHR3, FB_DACMBCTHR3_THRESH, 0xff, 0, compth_scale),
806 SOC_ENUM("DAC MBC3 Comp Ratio",
807 dac_mbc3_compressor_ratio_enum),
808 SND_SOC_BYTES("DAC MBC3 Comp Atk Time", R_DACMBCATK3L, 2),
809 SND_SOC_BYTES("DAC MBC3 Comp Rel Time Const",
813 static int setup_sample_format(struct snd_soc_component *component,
814 snd_pcm_format_t format)
820 case SNDRV_PCM_FORMAT_S16_LE:
821 width = RV_AIC1_WL_16;
823 case SNDRV_PCM_FORMAT_S20_3LE:
824 width = RV_AIC1_WL_20;
826 case SNDRV_PCM_FORMAT_S24_LE:
827 width = RV_AIC1_WL_24;
829 case SNDRV_PCM_FORMAT_S32_LE:
830 width = RV_AIC1_WL_32;
834 dev_err(component->dev, "Unsupported format width (%d)\n", ret);
837 ret = snd_soc_component_update_bits(component,
838 R_AIC1, RM_AIC1_WL, width);
840 dev_err(component->dev,
841 "Failed to set sample width (%d)\n", ret);
848 static int setup_sample_rate(struct snd_soc_component *component,
851 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
857 br = RV_DACSR_DBR_32;
858 bm = RV_DACSR_DBM_PT25;
861 br = RV_DACSR_DBR_32;
862 bm = RV_DACSR_DBM_PT5;
865 br = RV_DACSR_DBR_48;
866 bm = RV_DACSR_DBM_PT5;
869 br = RV_DACSR_DBR_32;
873 br = RV_DACSR_DBR_48;
877 br = RV_DACSR_DBR_48;
881 br = RV_DACSR_DBR_44_1;
882 bm = RV_DACSR_DBM_PT25;
885 br = RV_DACSR_DBR_44_1;
886 bm = RV_DACSR_DBM_PT5;
889 br = RV_DACSR_DBR_44_1;
893 br = RV_DACSR_DBR_44_1;
897 dev_err(component->dev, "Unsupported sample rate %d\n", rate);
901 /* DAC and ADC share bit and frame clock */
902 ret = snd_soc_component_update_bits(component,
903 R_DACSR, RM_DACSR_DBR, br);
905 dev_err(component->dev,
906 "Failed to update register (%d)\n", ret);
909 ret = snd_soc_component_update_bits(component,
910 R_DACSR, RM_DACSR_DBM, bm);
912 dev_err(component->dev,
913 "Failed to update register (%d)\n", ret);
916 ret = snd_soc_component_update_bits(component,
917 R_ADCSR, RM_DACSR_DBR, br);
919 dev_err(component->dev,
920 "Failed to update register (%d)\n", ret);
923 ret = snd_soc_component_update_bits(component,
924 R_ADCSR, RM_DACSR_DBM, bm);
926 dev_err(component->dev,
927 "Failed to update register (%d)\n", ret);
931 mutex_lock(&tscs42xx->audio_params_lock);
933 tscs42xx->samplerate = rate;
935 mutex_unlock(&tscs42xx->audio_params_lock);
946 #define PLL_REG_SETTINGS_COUNT 13
949 struct reg_setting settings[PLL_REG_SETTINGS_COUNT];
952 #define PLL_CTL(f, rt, rd, r1b_l, r9, ra, rb, \
953 rc, r12, r1b_h, re, rf, r10, r11) \
957 {R_TIMEBASE, rt, 0xFF}, \
958 {R_PLLCTLD, rd, 0xFF}, \
959 {R_PLLCTL1B, r1b_l, 0x0F}, \
960 {R_PLLCTL9, r9, 0xFF}, \
961 {R_PLLCTLA, ra, 0xFF}, \
962 {R_PLLCTLB, rb, 0xFF}, \
963 {R_PLLCTLC, rc, 0xFF}, \
964 {R_PLLCTL12, r12, 0xFF}, \
965 {R_PLLCTL1B, r1b_h, 0xF0}, \
966 {R_PLLCTLE, re, 0xFF}, \
967 {R_PLLCTLF, rf, 0xFF}, \
968 {R_PLLCTL10, r10, 0xFF}, \
969 {R_PLLCTL11, r11, 0xFF}, \
973 static const struct pll_ctl pll_ctls[] = {
974 PLL_CTL(1411200, 0x05,
975 0x39, 0x04, 0x07, 0x02, 0xC3, 0x04,
976 0x1B, 0x10, 0x03, 0x03, 0xD0, 0x02),
977 PLL_CTL(1536000, 0x05,
978 0x1A, 0x04, 0x02, 0x03, 0xE0, 0x01,
979 0x1A, 0x10, 0x02, 0x03, 0xB9, 0x01),
980 PLL_CTL(2822400, 0x0A,
981 0x23, 0x04, 0x07, 0x04, 0xC3, 0x04,
982 0x22, 0x10, 0x05, 0x03, 0x58, 0x02),
983 PLL_CTL(3072000, 0x0B,
984 0x22, 0x04, 0x07, 0x03, 0x48, 0x03,
985 0x1A, 0x10, 0x04, 0x03, 0xB9, 0x01),
986 PLL_CTL(5644800, 0x15,
987 0x23, 0x04, 0x0E, 0x04, 0xC3, 0x04,
988 0x1A, 0x10, 0x08, 0x03, 0xE0, 0x01),
989 PLL_CTL(6144000, 0x17,
990 0x1A, 0x04, 0x08, 0x03, 0xE0, 0x01,
991 0x1A, 0x10, 0x08, 0x03, 0xB9, 0x01),
992 PLL_CTL(12000000, 0x2E,
993 0x1B, 0x04, 0x19, 0x03, 0x00, 0x03,
994 0x2A, 0x10, 0x19, 0x05, 0x98, 0x04),
995 PLL_CTL(19200000, 0x4A,
996 0x13, 0x04, 0x14, 0x03, 0x80, 0x01,
997 0x1A, 0x10, 0x19, 0x03, 0xB9, 0x01),
998 PLL_CTL(22000000, 0x55,
999 0x2A, 0x04, 0x37, 0x05, 0x00, 0x06,
1000 0x22, 0x10, 0x26, 0x03, 0x49, 0x02),
1001 PLL_CTL(22579200, 0x57,
1002 0x22, 0x04, 0x31, 0x03, 0x20, 0x03,
1003 0x1A, 0x10, 0x1D, 0x03, 0xB3, 0x01),
1004 PLL_CTL(24000000, 0x5D,
1005 0x13, 0x04, 0x19, 0x03, 0x80, 0x01,
1006 0x1B, 0x10, 0x19, 0x05, 0x4C, 0x02),
1007 PLL_CTL(24576000, 0x5F,
1008 0x13, 0x04, 0x1D, 0x03, 0xB3, 0x01,
1009 0x22, 0x10, 0x40, 0x03, 0x72, 0x03),
1010 PLL_CTL(27000000, 0x68,
1011 0x22, 0x04, 0x4B, 0x03, 0x00, 0x04,
1012 0x2A, 0x10, 0x7D, 0x03, 0x20, 0x06),
1013 PLL_CTL(36000000, 0x8C,
1014 0x1B, 0x04, 0x4B, 0x03, 0x00, 0x03,
1015 0x2A, 0x10, 0x7D, 0x03, 0x98, 0x04),
1016 PLL_CTL(25000000, 0x61,
1017 0x1B, 0x04, 0x37, 0x03, 0x2B, 0x03,
1018 0x1A, 0x10, 0x2A, 0x03, 0x39, 0x02),
1019 PLL_CTL(26000000, 0x65,
1020 0x23, 0x04, 0x41, 0x05, 0x00, 0x06,
1021 0x1A, 0x10, 0x26, 0x03, 0xEF, 0x01),
1022 PLL_CTL(12288000, 0x2F,
1023 0x1A, 0x04, 0x12, 0x03, 0x1C, 0x02,
1024 0x22, 0x10, 0x20, 0x03, 0x72, 0x03),
1025 PLL_CTL(40000000, 0x9B,
1026 0x22, 0x08, 0x7D, 0x03, 0x80, 0x04,
1027 0x23, 0x10, 0x7D, 0x05, 0xE4, 0x06),
1028 PLL_CTL(512000, 0x01,
1029 0x22, 0x04, 0x01, 0x03, 0xD0, 0x02,
1030 0x1B, 0x10, 0x01, 0x04, 0x72, 0x03),
1031 PLL_CTL(705600, 0x02,
1032 0x22, 0x04, 0x02, 0x03, 0x15, 0x04,
1033 0x22, 0x10, 0x01, 0x04, 0x80, 0x02),
1034 PLL_CTL(1024000, 0x03,
1035 0x22, 0x04, 0x02, 0x03, 0xD0, 0x02,
1036 0x1B, 0x10, 0x02, 0x04, 0x72, 0x03),
1037 PLL_CTL(2048000, 0x07,
1038 0x22, 0x04, 0x04, 0x03, 0xD0, 0x02,
1039 0x1B, 0x10, 0x04, 0x04, 0x72, 0x03),
1040 PLL_CTL(2400000, 0x08,
1041 0x22, 0x04, 0x05, 0x03, 0x00, 0x03,
1042 0x23, 0x10, 0x05, 0x05, 0x98, 0x04),
1045 static const struct pll_ctl *get_pll_ctl(int input_freq)
1048 const struct pll_ctl *pll_ctl = NULL;
1050 for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i)
1051 if (input_freq == pll_ctls[i].input_freq) {
1052 pll_ctl = &pll_ctls[i];
1059 static int set_pll_ctl_from_input_freq(struct snd_soc_component *component,
1060 const int input_freq)
1064 const struct pll_ctl *pll_ctl;
1066 pll_ctl = get_pll_ctl(input_freq);
1069 dev_err(component->dev, "No PLL input entry for %d (%d)\n",
1074 for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) {
1075 ret = snd_soc_component_update_bits(component,
1076 pll_ctl->settings[i].addr,
1077 pll_ctl->settings[i].mask,
1078 pll_ctl->settings[i].val);
1080 dev_err(component->dev, "Failed to set pll ctl (%d)\n",
1089 static int tscs42xx_hw_params(struct snd_pcm_substream *substream,
1090 struct snd_pcm_hw_params *params,
1091 struct snd_soc_dai *codec_dai)
1093 struct snd_soc_component *component = codec_dai->component;
1096 ret = setup_sample_format(component, params_format(params));
1098 dev_err(component->dev, "Failed to setup sample format (%d)\n",
1103 ret = setup_sample_rate(component, params_rate(params));
1105 dev_err(component->dev,
1106 "Failed to setup sample rate (%d)\n", ret);
1113 static inline int dac_mute(struct snd_soc_component *component)
1117 ret = snd_soc_component_update_bits(component,
1118 R_CNVRTR1, RM_CNVRTR1_DACMU,
1119 RV_CNVRTR1_DACMU_ENABLE);
1121 dev_err(component->dev, "Failed to mute DAC (%d)\n",
1129 static inline int dac_unmute(struct snd_soc_component *component)
1133 ret = snd_soc_component_update_bits(component,
1134 R_CNVRTR1, RM_CNVRTR1_DACMU,
1135 RV_CNVRTR1_DACMU_DISABLE);
1137 dev_err(component->dev, "Failed to unmute DAC (%d)\n",
1145 static inline int adc_mute(struct snd_soc_component *component)
1149 ret = snd_soc_component_update_bits(component,
1150 R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_ENABLE);
1152 dev_err(component->dev, "Failed to mute ADC (%d)\n",
1160 static inline int adc_unmute(struct snd_soc_component *component)
1164 ret = snd_soc_component_update_bits(component,
1165 R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_DISABLE);
1167 dev_err(component->dev, "Failed to unmute ADC (%d)\n",
1175 static int tscs42xx_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
1177 struct snd_soc_component *component = dai->component;
1181 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
1182 ret = dac_mute(component);
1184 ret = adc_mute(component);
1186 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
1187 ret = dac_unmute(component);
1189 ret = adc_unmute(component);
1194 static int tscs42xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
1197 struct snd_soc_component *component = codec_dai->component;
1200 /* Slave mode not supported since it needs always-on frame clock */
1201 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1202 case SND_SOC_DAIFMT_CBM_CFM:
1203 ret = snd_soc_component_update_bits(component,
1204 R_AIC1, RM_AIC1_MS, RV_AIC1_MS_MASTER);
1206 dev_err(component->dev,
1207 "Failed to set codec DAI master (%d)\n", ret);
1213 dev_err(component->dev, "Unsupported format (%d)\n", ret);
1220 static int tscs42xx_set_dai_bclk_ratio(struct snd_soc_dai *codec_dai,
1223 struct snd_soc_component *component = codec_dai->component;
1224 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
1230 value = RV_DACSR_DBCM_32;
1233 value = RV_DACSR_DBCM_40;
1236 value = RV_DACSR_DBCM_64;
1239 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret);
1243 ret = snd_soc_component_update_bits(component,
1244 R_DACSR, RM_DACSR_DBCM, value);
1246 dev_err(component->dev,
1247 "Failed to set DAC BCLK ratio (%d)\n", ret);
1250 ret = snd_soc_component_update_bits(component,
1251 R_ADCSR, RM_ADCSR_ABCM, value);
1253 dev_err(component->dev,
1254 "Failed to set ADC BCLK ratio (%d)\n", ret);
1258 mutex_lock(&tscs42xx->audio_params_lock);
1260 tscs42xx->bclk_ratio = ratio;
1262 mutex_unlock(&tscs42xx->audio_params_lock);
1267 static const struct snd_soc_dai_ops tscs42xx_dai_ops = {
1268 .hw_params = tscs42xx_hw_params,
1269 .mute_stream = tscs42xx_mute_stream,
1270 .set_fmt = tscs42xx_set_dai_fmt,
1271 .set_bclk_ratio = tscs42xx_set_dai_bclk_ratio,
1274 static int part_is_valid(struct tscs42xx *tscs42xx)
1280 ret = regmap_read(tscs42xx->regmap, R_DEVIDH, ®);
1285 ret = regmap_read(tscs42xx->regmap, R_DEVIDL, ®);
1300 static int set_sysclk(struct snd_soc_component *component)
1302 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component);
1306 switch (tscs42xx->sysclk_src_id) {
1307 case TSCS42XX_PLL_SRC_XTAL:
1308 case TSCS42XX_PLL_SRC_MCLK1:
1309 ret = snd_soc_component_write(component, R_PLLREFSEL,
1310 RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 |
1311 RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1);
1313 dev_err(component->dev,
1314 "Failed to set pll reference input (%d)\n",
1319 case TSCS42XX_PLL_SRC_MCLK2:
1320 ret = snd_soc_component_write(component, R_PLLREFSEL,
1321 RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 |
1322 RV_PLLREFSEL_PLL2_REF_SEL_MCLK2);
1324 dev_err(component->dev,
1325 "Failed to set PLL reference (%d)\n", ret);
1330 dev_err(component->dev, "pll src is unsupported\n");
1334 freq = clk_get_rate(tscs42xx->sysclk);
1335 ret = set_pll_ctl_from_input_freq(component, freq);
1337 dev_err(component->dev,
1338 "Failed to setup PLL input freq (%d)\n", ret);
1345 static int tscs42xx_probe(struct snd_soc_component *component)
1347 return set_sysclk(component);
1350 static const struct snd_soc_component_driver soc_codec_dev_tscs42xx = {
1351 .probe = tscs42xx_probe,
1352 .dapm_widgets = tscs42xx_dapm_widgets,
1353 .num_dapm_widgets = ARRAY_SIZE(tscs42xx_dapm_widgets),
1354 .dapm_routes = tscs42xx_intercon,
1355 .num_dapm_routes = ARRAY_SIZE(tscs42xx_intercon),
1356 .controls = tscs42xx_snd_controls,
1357 .num_controls = ARRAY_SIZE(tscs42xx_snd_controls),
1359 .use_pmdown_time = 1,
1361 .non_legacy_dai_naming = 1,
1364 static inline void init_coeff_ram_cache(struct tscs42xx *tscs42xx)
1366 static const u8 norm_addrs[] = {
1367 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 0x1f, 0x20, 0x25, 0x2a,
1368 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45, 0x4a, 0x4f, 0x54, 0x59,
1369 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74, 0x79, 0x7f, 0x80, 0x85,
1370 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3, 0xa8, 0xad, 0xaf, 0xb0,
1371 0xb5, 0xba, 0xbf, 0xc4, 0xc9,
1373 u8 *coeff_ram = tscs42xx->coeff_ram;
1376 for (i = 0; i < ARRAY_SIZE(norm_addrs); i++)
1377 coeff_ram[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40;
1380 #define TSCS42XX_RATES SNDRV_PCM_RATE_8000_96000
1382 #define TSCS42XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1383 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1385 static struct snd_soc_dai_driver tscs42xx_dai = {
1386 .name = "tscs42xx-HiFi",
1388 .stream_name = "HiFi Playback",
1391 .rates = TSCS42XX_RATES,
1392 .formats = TSCS42XX_FORMATS,},
1394 .stream_name = "HiFi Capture",
1397 .rates = TSCS42XX_RATES,
1398 .formats = TSCS42XX_FORMATS,},
1399 .ops = &tscs42xx_dai_ops,
1400 .symmetric_rates = 1,
1401 .symmetric_channels = 1,
1402 .symmetric_samplebits = 1,
1405 static const struct reg_sequence tscs42xx_patch[] = {
1406 { R_AIC2, RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED },
1409 static char const * const src_names[TSCS42XX_PLL_SRC_CNT] = {
1410 "xtal", "mclk1", "mclk2"};
1412 static int tscs42xx_i2c_probe(struct i2c_client *i2c,
1413 const struct i2c_device_id *id)
1415 struct tscs42xx *tscs42xx;
1419 tscs42xx = devm_kzalloc(&i2c->dev, sizeof(*tscs42xx), GFP_KERNEL);
1423 "Failed to allocate memory for data (%d)\n", ret);
1426 i2c_set_clientdata(i2c, tscs42xx);
1428 for (src = TSCS42XX_PLL_SRC_XTAL; src < TSCS42XX_PLL_SRC_CNT; src++) {
1429 tscs42xx->sysclk = devm_clk_get(&i2c->dev, src_names[src]);
1430 if (!IS_ERR(tscs42xx->sysclk)) {
1432 } else if (PTR_ERR(tscs42xx->sysclk) != -ENOENT) {
1433 ret = PTR_ERR(tscs42xx->sysclk);
1434 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret);
1438 if (src == TSCS42XX_PLL_SRC_CNT) {
1440 dev_err(&i2c->dev, "Failed to get a valid clock name (%d)\n",
1444 tscs42xx->sysclk_src_id = src;
1446 tscs42xx->regmap = devm_regmap_init_i2c(i2c, &tscs42xx_regmap);
1447 if (IS_ERR(tscs42xx->regmap)) {
1448 ret = PTR_ERR(tscs42xx->regmap);
1449 dev_err(&i2c->dev, "Failed to allocate regmap (%d)\n", ret);
1453 init_coeff_ram_cache(tscs42xx);
1455 ret = part_is_valid(tscs42xx);
1457 dev_err(&i2c->dev, "No valid part (%d)\n", ret);
1462 ret = regmap_write(tscs42xx->regmap, R_RESET, RV_RESET_ENABLE);
1464 dev_err(&i2c->dev, "Failed to reset device (%d)\n", ret);
1468 ret = regmap_register_patch(tscs42xx->regmap, tscs42xx_patch,
1469 ARRAY_SIZE(tscs42xx_patch));
1471 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret);
1475 mutex_init(&tscs42xx->audio_params_lock);
1476 mutex_init(&tscs42xx->coeff_ram_lock);
1477 mutex_init(&tscs42xx->pll_lock);
1479 ret = devm_snd_soc_register_component(&i2c->dev,
1480 &soc_codec_dev_tscs42xx, &tscs42xx_dai, 1);
1482 dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret);
1489 static const struct i2c_device_id tscs42xx_i2c_id[] = {
1494 MODULE_DEVICE_TABLE(i2c, tscs42xx_i2c_id);
1496 static const struct of_device_id tscs42xx_of_match[] = {
1497 { .compatible = "tempo,tscs42A1", },
1498 { .compatible = "tempo,tscs42A2", },
1501 MODULE_DEVICE_TABLE(of, tscs42xx_of_match);
1503 static struct i2c_driver tscs42xx_i2c_driver = {
1506 .of_match_table = tscs42xx_of_match,
1508 .probe = tscs42xx_i2c_probe,
1509 .id_table = tscs42xx_i2c_id,
1512 module_i2c_driver(tscs42xx_i2c_driver);
1514 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com");
1515 MODULE_DESCRIPTION("ASoC TSCS42xx driver");
1516 MODULE_LICENSE("GPL");