1 // SPDX-License-Identifier: GPL-2.0-only
3 * ALSA SoC TLV320AIC3X codec driver
5 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
6 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
8 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
11 * The AIC3X is a driver for a low power stereo audio
12 * codecs aic31, aic32, aic33, aic3007.
14 * It supports full aic33 codec functionality.
15 * The compatibility with aic32, aic31 and aic3007 is as follows:
16 * aic32/aic3007 | aic31
17 * ---------------------------------------
18 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
24 * truncated internal functionality in
25 * accordance with documentation
26 * ---------------------------------------
28 * Hence the machine layer should disable unsupported inputs/outputs by
29 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
37 #include <linux/i2c.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/consumer.h>
41 #include <linux/of_gpio.h>
42 #include <linux/slab.h>
43 #include <sound/core.h>
44 #include <sound/pcm.h>
45 #include <sound/pcm_params.h>
46 #include <sound/soc.h>
47 #include <sound/initval.h>
48 #include <sound/tlv.h>
49 #include <sound/tlv320aic3x.h>
51 #include "tlv320aic3x.h"
53 #define AIC3X_NUM_SUPPLIES 4
54 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
55 "IOVDD", /* I/O Voltage */
56 "DVDD", /* Digital Core Voltage */
57 "AVDD", /* Analog DAC Voltage */
58 "DRVDD", /* ADC Analog and Output Driver Voltage */
61 static LIST_HEAD(reset_list);
65 struct aic3x_disable_nb {
66 struct notifier_block nb;
67 struct aic3x_priv *aic3x;
70 /* codec private data */
72 struct snd_soc_component *component;
73 struct regmap *regmap;
74 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
75 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
76 struct aic3x_setup_data *setup;
79 unsigned int tdm_delay;
80 unsigned int slot_width;
81 struct list_head list;
85 #define AIC3X_MODEL_3X 0
86 #define AIC3X_MODEL_33 1
87 #define AIC3X_MODEL_3007 2
88 #define AIC3X_MODEL_3104 3
91 /* Selects the micbias voltage */
92 enum aic3x_micbias_voltage micbias_vg;
93 /* Output Common-Mode Voltage */
97 static const struct reg_default aic3x_reg[] = {
98 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 },
99 { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
100 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 },
101 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 },
102 { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 },
103 { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 },
104 { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe },
105 { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 },
106 { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 },
107 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 },
108 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 },
109 { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },
110 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 },
111 { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 },
112 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 },
113 { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 },
114 { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 },
115 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },
116 { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },
117 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },
118 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 },
119 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },
120 { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },
121 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },
122 { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },
123 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 },
124 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },
125 { 108, 0x00 }, { 109, 0x00 },
128 static bool aic3x_volatile_reg(struct device *dev, unsigned int reg)
138 static const struct regmap_config aic3x_regmap = {
142 .max_register = DAC_ICC_ADJ,
143 .reg_defaults = aic3x_reg,
144 .num_reg_defaults = ARRAY_SIZE(aic3x_reg),
146 .volatile_reg = aic3x_volatile_reg,
148 .cache_type = REGCACHE_RBTREE,
151 #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
152 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
153 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
156 * All input lines are connected when !0xf and disconnected with 0xf bit field,
157 * so we have to use specific dapm_put call for input mixer
159 static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
160 struct snd_ctl_elem_value *ucontrol)
162 struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol);
163 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
164 struct soc_mixer_control *mc =
165 (struct soc_mixer_control *)kcontrol->private_value;
166 unsigned int reg = mc->reg;
167 unsigned int shift = mc->shift;
169 unsigned int mask = (1 << fls(max)) - 1;
170 unsigned int invert = mc->invert;
172 struct snd_soc_dapm_update update = {};
175 val = (ucontrol->value.integer.value[0] & mask);
189 change = snd_soc_component_test_bits(component, reg, mask, val);
191 update.kcontrol = kcontrol;
196 snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect,
204 * mic bias power on/off share the same register bits with
205 * output voltage of mic bias. when power on mic bias, we
206 * need reclaim it to voltage value.
208 * 0x1 = MICBIAS output is powered to 2.0V,
209 * 0x2 = MICBIAS output is powered to 2.5V
210 * 0x3 = MICBIAS output is connected to AVDD
212 static int mic_bias_event(struct snd_soc_dapm_widget *w,
213 struct snd_kcontrol *kcontrol, int event)
215 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
216 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
219 case SND_SOC_DAPM_POST_PMU:
220 /* change mic bias voltage to user defined */
221 snd_soc_component_update_bits(component, MICBIAS_CTRL,
223 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
226 case SND_SOC_DAPM_PRE_PMD:
227 snd_soc_component_update_bits(component, MICBIAS_CTRL,
228 MICBIAS_LEVEL_MASK, 0);
234 static const char * const aic3x_left_dac_mux[] = {
235 "DAC_L1", "DAC_L3", "DAC_L2" };
236 static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6,
239 static const char * const aic3x_right_dac_mux[] = {
240 "DAC_R1", "DAC_R3", "DAC_R2" };
241 static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4,
242 aic3x_right_dac_mux);
244 static const char * const aic3x_left_hpcom_mux[] = {
245 "differential of HPLOUT", "constant VCM", "single-ended" };
246 static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4,
247 aic3x_left_hpcom_mux);
249 static const char * const aic3x_right_hpcom_mux[] = {
250 "differential of HPROUT", "constant VCM", "single-ended",
251 "differential of HPLCOM", "external feedback" };
252 static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3,
253 aic3x_right_hpcom_mux);
255 static const char * const aic3x_linein_mode_mux[] = {
256 "single-ended", "differential" };
257 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7,
258 aic3x_linein_mode_mux);
259 static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7,
260 aic3x_linein_mode_mux);
261 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7,
262 aic3x_linein_mode_mux);
263 static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7,
264 aic3x_linein_mode_mux);
265 static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7,
266 aic3x_linein_mode_mux);
267 static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7,
268 aic3x_linein_mode_mux);
270 static const char * const aic3x_adc_hpf[] = {
271 "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
272 static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4,
275 static const char * const aic3x_agc_level[] = {
276 "-5.5dB", "-8dB", "-10dB", "-12dB",
277 "-14dB", "-17dB", "-20dB", "-24dB" };
278 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4,
280 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4,
283 static const char * const aic3x_agc_attack[] = {
284 "8ms", "11ms", "16ms", "20ms" };
285 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2,
287 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2,
290 static const char * const aic3x_agc_decay[] = {
291 "100ms", "200ms", "400ms", "500ms" };
292 static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0,
294 static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0,
297 static const char * const aic3x_poweron_time[] = {
298 "0us", "10us", "100us", "1ms", "10ms", "50ms",
299 "100ms", "200ms", "400ms", "800ms", "2s", "4s" };
300 static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4,
303 static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" };
304 static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2,
308 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
310 static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
311 /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
312 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
314 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
315 * Step size is approximately 0.5 dB over most of the scale but increasing
316 * near the very low levels.
317 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
318 * but having increasing dB difference below that (and where it doesn't count
319 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
320 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
322 static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
324 static const struct snd_kcontrol_new aic3x_snd_controls[] = {
326 SOC_DOUBLE_R_TLV("PCM Playback Volume",
327 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
330 * Output controls that map to output mixer switches. Note these are
331 * only for swapped L-to-R and R-to-L routes. See below stereo controls
332 * for direct L-to-L and R-to-R routes.
334 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
335 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
336 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
337 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
339 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
340 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
341 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
342 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
344 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
345 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
346 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
347 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
349 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
350 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
351 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
352 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
354 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
355 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
356 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
357 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
359 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
360 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
361 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
362 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
364 /* Stereo output controls for direct L-to-L and R-to-R routes */
365 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
366 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
367 0, 118, 1, output_stage_tlv),
368 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
369 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
370 0, 118, 1, output_stage_tlv),
372 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
373 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
374 0, 118, 1, output_stage_tlv),
375 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
376 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
377 0, 118, 1, output_stage_tlv),
379 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
380 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
381 0, 118, 1, output_stage_tlv),
382 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
383 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
384 0, 118, 1, output_stage_tlv),
386 /* Output pin mute controls */
387 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
389 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
391 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
395 * Note: enable Automatic input Gain Controller with care. It can
396 * adjust PGA to max value when ADC is on and will never go back.
398 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
399 SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum),
400 SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum),
401 SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum),
402 SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum),
403 SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum),
404 SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum),
407 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
410 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
412 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
414 SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum),
417 SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum),
418 SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum),
421 /* For other than tlv320aic3104 */
422 static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = {
424 * Output controls that map to output mixer switches. Note these are
425 * only for swapped L-to-R and R-to-L routes. See below stereo controls
426 * for direct L-to-L and R-to-R routes.
428 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
429 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
431 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
432 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
434 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
435 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
437 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
438 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
440 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
441 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
443 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
444 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
446 /* Stereo output controls for direct L-to-L and R-to-R routes */
447 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
448 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
449 0, 118, 1, output_stage_tlv),
451 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
452 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
453 0, 118, 1, output_stage_tlv),
455 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
456 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
457 0, 118, 1, output_stage_tlv),
460 static const struct snd_kcontrol_new aic3x_mono_controls[] = {
461 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
462 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
463 0, 118, 1, output_stage_tlv),
464 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
465 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
466 0, 118, 1, output_stage_tlv),
467 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
468 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
469 0, 118, 1, output_stage_tlv),
471 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
475 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
477 static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
479 static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
480 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
483 static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
484 SOC_DAPM_ENUM("Route", aic3x_left_dac_enum);
487 static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
488 SOC_DAPM_ENUM("Route", aic3x_right_dac_enum);
491 static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
492 SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum);
494 /* Right HPCOM Mux */
495 static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
496 SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum);
498 /* Left Line Mixer */
499 static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
500 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
501 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
502 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
503 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
504 /* Not on tlv320aic3104 */
505 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
506 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
509 /* Right Line Mixer */
510 static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
511 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
512 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
513 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
514 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
515 /* Not on tlv320aic3104 */
516 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
517 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
521 static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
522 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
523 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
524 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
525 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
526 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
527 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
531 static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
532 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
533 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
534 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
535 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
536 /* Not on tlv320aic3104 */
537 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
538 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
542 static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
543 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
544 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
545 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
546 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
547 /* Not on tlv320aic3104 */
548 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
549 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
552 /* Left HPCOM Mixer */
553 static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
554 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
555 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
556 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
557 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
558 /* Not on tlv320aic3104 */
559 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
560 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
563 /* Right HPCOM Mixer */
564 static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
565 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
566 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
567 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
568 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
569 /* Not on tlv320aic3104 */
570 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
571 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
575 static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
576 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
577 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
578 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
579 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
580 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
583 /* Right PGA Mixer */
584 static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
585 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
586 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
587 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
588 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
589 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
592 /* Left PGA Mixer for tlv320aic3104 */
593 static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = {
594 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
595 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
596 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
597 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
600 /* Right PGA Mixer for tlv320aic3104 */
601 static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = {
602 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
603 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
604 SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
605 SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
609 static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
610 SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum);
611 static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
612 SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum);
614 /* Right Line1 Mux */
615 static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
616 SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum);
617 static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
618 SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum);
621 static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
622 SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum);
624 /* Right Line2 Mux */
625 static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
626 SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum);
628 static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
629 /* Left DAC to Left Outputs */
630 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
631 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
632 &aic3x_left_dac_mux_controls),
633 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
634 &aic3x_left_hpcom_mux_controls),
635 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
636 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
637 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
639 /* Right DAC to Right Outputs */
640 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
641 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
642 &aic3x_right_dac_mux_controls),
643 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
644 &aic3x_right_hpcom_mux_controls),
645 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
646 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
647 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
649 /* Inputs to Left ADC */
650 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
651 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
652 &aic3x_left_line1l_mux_controls),
653 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
654 &aic3x_left_line1r_mux_controls),
656 /* Inputs to Right ADC */
657 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
658 LINE1R_2_RADC_CTRL, 2, 0),
659 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
660 &aic3x_right_line1l_mux_controls),
661 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
662 &aic3x_right_line1r_mux_controls),
665 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
667 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
669 SND_SOC_DAPM_OUTPUT("LLOUT"),
670 SND_SOC_DAPM_OUTPUT("RLOUT"),
671 SND_SOC_DAPM_OUTPUT("HPLOUT"),
672 SND_SOC_DAPM_OUTPUT("HPROUT"),
673 SND_SOC_DAPM_OUTPUT("HPLCOM"),
674 SND_SOC_DAPM_OUTPUT("HPRCOM"),
676 SND_SOC_DAPM_INPUT("LINE1L"),
677 SND_SOC_DAPM_INPUT("LINE1R"),
680 * Virtual output pin to detection block inside codec. This can be
681 * used to keep codec bias on if gpio or detection features are needed.
682 * Force pin on or construct a path with an input jack and mic bias
685 SND_SOC_DAPM_OUTPUT("Detection"),
688 /* For other than tlv320aic3104 */
689 static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = {
690 /* Inputs to Left ADC */
691 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
692 &aic3x_left_pga_mixer_controls[0],
693 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
694 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
695 &aic3x_left_line2_mux_controls),
697 /* Inputs to Right ADC */
698 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
699 &aic3x_right_pga_mixer_controls[0],
700 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
701 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
702 &aic3x_right_line2_mux_controls),
705 * Not a real mic bias widget but similar function. This is for dynamic
706 * control of GPIO1 digital mic modulator clock output function when
709 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
710 AIC3X_GPIO1_REG, 4, 0xf,
711 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
712 AIC3X_GPIO1_FUNC_DISABLED),
715 * Also similar function like mic bias. Selects digital mic with
716 * configurable oversampling rate instead of ADC converter.
718 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
719 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
720 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
721 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
722 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
723 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
726 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
727 &aic3x_left_line_mixer_controls[0],
728 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
729 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
730 &aic3x_right_line_mixer_controls[0],
731 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
732 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
733 &aic3x_left_hp_mixer_controls[0],
734 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
735 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
736 &aic3x_right_hp_mixer_controls[0],
737 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
738 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
739 &aic3x_left_hpcom_mixer_controls[0],
740 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
741 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
742 &aic3x_right_hpcom_mixer_controls[0],
743 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
745 SND_SOC_DAPM_INPUT("MIC3L"),
746 SND_SOC_DAPM_INPUT("MIC3R"),
747 SND_SOC_DAPM_INPUT("LINE2L"),
748 SND_SOC_DAPM_INPUT("LINE2R"),
751 /* For tlv320aic3104 */
752 static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = {
753 /* Inputs to Left ADC */
754 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
755 &aic3104_left_pga_mixer_controls[0],
756 ARRAY_SIZE(aic3104_left_pga_mixer_controls)),
758 /* Inputs to Right ADC */
759 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
760 &aic3104_right_pga_mixer_controls[0],
761 ARRAY_SIZE(aic3104_right_pga_mixer_controls)),
764 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
765 &aic3x_left_line_mixer_controls[0],
766 ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2),
767 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
768 &aic3x_right_line_mixer_controls[0],
769 ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2),
770 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
771 &aic3x_left_hp_mixer_controls[0],
772 ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2),
773 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
774 &aic3x_right_hp_mixer_controls[0],
775 ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2),
776 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
777 &aic3x_left_hpcom_mixer_controls[0],
778 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2),
779 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
780 &aic3x_right_hpcom_mixer_controls[0],
781 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2),
783 SND_SOC_DAPM_INPUT("MIC2L"),
784 SND_SOC_DAPM_INPUT("MIC2R"),
787 static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = {
789 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
791 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
792 &aic3x_mono_mixer_controls[0],
793 ARRAY_SIZE(aic3x_mono_mixer_controls)),
795 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
798 static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
799 /* Class-D outputs */
800 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
801 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
803 SND_SOC_DAPM_OUTPUT("SPOP"),
804 SND_SOC_DAPM_OUTPUT("SPOM"),
807 static const struct snd_soc_dapm_route intercon[] = {
809 {"Left Line1L Mux", "single-ended", "LINE1L"},
810 {"Left Line1L Mux", "differential", "LINE1L"},
811 {"Left Line1R Mux", "single-ended", "LINE1R"},
812 {"Left Line1R Mux", "differential", "LINE1R"},
814 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
815 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
817 {"Left ADC", NULL, "Left PGA Mixer"},
820 {"Right Line1R Mux", "single-ended", "LINE1R"},
821 {"Right Line1R Mux", "differential", "LINE1R"},
822 {"Right Line1L Mux", "single-ended", "LINE1L"},
823 {"Right Line1L Mux", "differential", "LINE1L"},
825 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
826 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
828 {"Right ADC", NULL, "Right PGA Mixer"},
830 /* Left DAC Output */
831 {"Left DAC Mux", "DAC_L1", "Left DAC"},
832 {"Left DAC Mux", "DAC_L2", "Left DAC"},
833 {"Left DAC Mux", "DAC_L3", "Left DAC"},
835 /* Right DAC Output */
836 {"Right DAC Mux", "DAC_R1", "Right DAC"},
837 {"Right DAC Mux", "DAC_R2", "Right DAC"},
838 {"Right DAC Mux", "DAC_R3", "Right DAC"},
840 /* Left Line Output */
841 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
842 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
843 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
844 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
846 {"Left Line Out", NULL, "Left Line Mixer"},
847 {"Left Line Out", NULL, "Left DAC Mux"},
848 {"LLOUT", NULL, "Left Line Out"},
850 /* Right Line Output */
851 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
852 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
853 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
854 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
856 {"Right Line Out", NULL, "Right Line Mixer"},
857 {"Right Line Out", NULL, "Right DAC Mux"},
858 {"RLOUT", NULL, "Right Line Out"},
861 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
862 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
863 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
864 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
866 {"Left HP Out", NULL, "Left HP Mixer"},
867 {"Left HP Out", NULL, "Left DAC Mux"},
868 {"HPLOUT", NULL, "Left HP Out"},
870 /* Right HP Output */
871 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
872 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
873 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
874 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
876 {"Right HP Out", NULL, "Right HP Mixer"},
877 {"Right HP Out", NULL, "Right DAC Mux"},
878 {"HPROUT", NULL, "Right HP Out"},
880 /* Left HPCOM Output */
881 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
882 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
883 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
884 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
886 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
887 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
888 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
889 {"Left HP Com", NULL, "Left HPCOM Mux"},
890 {"HPLCOM", NULL, "Left HP Com"},
892 /* Right HPCOM Output */
893 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
894 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
895 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
896 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
898 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
899 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
900 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
901 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
902 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
903 {"Right HP Com", NULL, "Right HPCOM Mux"},
904 {"HPRCOM", NULL, "Right HP Com"},
907 /* For other than tlv320aic3104 */
908 static const struct snd_soc_dapm_route intercon_extra[] = {
910 {"Left Line2L Mux", "single-ended", "LINE2L"},
911 {"Left Line2L Mux", "differential", "LINE2L"},
913 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
914 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
915 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
917 {"Left ADC", NULL, "GPIO1 dmic modclk"},
920 {"Right Line2R Mux", "single-ended", "LINE2R"},
921 {"Right Line2R Mux", "differential", "LINE2R"},
923 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
924 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
925 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
927 {"Right ADC", NULL, "GPIO1 dmic modclk"},
930 * Logical path between digital mic enable and GPIO1 modulator clock
933 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
934 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
935 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
937 /* Left Line Output */
938 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
939 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
941 /* Right Line Output */
942 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
943 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
946 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
947 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
949 /* Right HP Output */
950 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
951 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
953 /* Left HPCOM Output */
954 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
955 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
957 /* Right HPCOM Output */
958 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
959 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
962 /* For tlv320aic3104 */
963 static const struct snd_soc_dapm_route intercon_extra_3104[] = {
965 {"Left PGA Mixer", "Mic2L Switch", "MIC2L"},
966 {"Left PGA Mixer", "Mic2R Switch", "MIC2R"},
969 {"Right PGA Mixer", "Mic2L Switch", "MIC2L"},
970 {"Right PGA Mixer", "Mic2R Switch", "MIC2R"},
973 static const struct snd_soc_dapm_route intercon_mono[] = {
975 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
976 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
977 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
978 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
979 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
980 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
981 {"Mono Out", NULL, "Mono Mixer"},
982 {"MONO_LOUT", NULL, "Mono Out"},
985 static const struct snd_soc_dapm_route intercon_3007[] = {
986 /* Class-D outputs */
987 {"Left Class-D Out", NULL, "Left Line Out"},
988 {"Right Class-D Out", NULL, "Left Line Out"},
989 {"SPOP", NULL, "Left Class-D Out"},
990 {"SPOM", NULL, "Right Class-D Out"},
993 static int aic3x_add_widgets(struct snd_soc_component *component)
995 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
996 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
998 switch (aic3x->model) {
1000 case AIC3X_MODEL_33:
1001 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
1002 ARRAY_SIZE(aic3x_extra_dapm_widgets));
1003 snd_soc_dapm_add_routes(dapm, intercon_extra,
1004 ARRAY_SIZE(intercon_extra));
1005 snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets,
1006 ARRAY_SIZE(aic3x_dapm_mono_widgets));
1007 snd_soc_dapm_add_routes(dapm, intercon_mono,
1008 ARRAY_SIZE(intercon_mono));
1010 case AIC3X_MODEL_3007:
1011 snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets,
1012 ARRAY_SIZE(aic3x_extra_dapm_widgets));
1013 snd_soc_dapm_add_routes(dapm, intercon_extra,
1014 ARRAY_SIZE(intercon_extra));
1015 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
1016 ARRAY_SIZE(aic3007_dapm_widgets));
1017 snd_soc_dapm_add_routes(dapm, intercon_3007,
1018 ARRAY_SIZE(intercon_3007));
1020 case AIC3X_MODEL_3104:
1021 snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets,
1022 ARRAY_SIZE(aic3104_extra_dapm_widgets));
1023 snd_soc_dapm_add_routes(dapm, intercon_extra_3104,
1024 ARRAY_SIZE(intercon_extra_3104));
1031 static int aic3x_hw_params(struct snd_pcm_substream *substream,
1032 struct snd_pcm_hw_params *params,
1033 struct snd_soc_dai *dai)
1035 struct snd_soc_component *component = dai->component;
1036 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1037 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
1038 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
1041 int width = aic3x->slot_width;
1044 width = params_width(params);
1046 /* select data word length */
1047 data = snd_soc_component_read32(component, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
1052 data |= (0x01 << 4);
1055 data |= (0x02 << 4);
1058 data |= (0x03 << 4);
1061 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, data);
1063 /* Fsref can be 44100 or 48000 */
1064 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
1066 /* Try to find a value for Q which allows us to bypass the PLL and
1067 * generate CODEC_CLK directly. */
1068 for (pll_q = 2; pll_q < 18; pll_q++)
1069 if (aic3x->sysclk / (128 * pll_q) == fsref) {
1076 snd_soc_component_write(component, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
1077 snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
1078 /* disable PLL if it is bypassed */
1079 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
1082 snd_soc_component_write(component, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
1083 /* enable PLL when it is used */
1084 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1085 PLL_ENABLE, PLL_ENABLE);
1088 /* Route Left DAC to left channel input and
1089 * right DAC to right channel input */
1090 data = (LDAC2LCH | RDAC2RCH);
1091 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
1092 if (params_rate(params) >= 64000)
1093 data |= DUAL_RATE_MODE;
1094 snd_soc_component_write(component, AIC3X_CODEC_DATAPATH_REG, data);
1096 /* codec sample rate select */
1097 data = (fsref * 20) / params_rate(params);
1098 if (params_rate(params) < 64000)
1102 data |= (data << 4);
1103 snd_soc_component_write(component, AIC3X_SAMPLE_RATE_SEL_REG, data);
1108 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
1109 * one wins the game. Try with d==0 first, next with d!=0.
1110 * Constraints for j are according to the datasheet.
1111 * The sysclk is divided by 1000 to prevent integer overflows.
1114 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
1116 for (r = 1; r <= 16; r++)
1117 for (p = 1; p <= 8; p++) {
1118 for (j = 4; j <= 55; j++) {
1119 /* This is actually 1000*((j+(d/10000))*r)/p
1120 * The term had to be converted to get
1121 * rid of the division by 10000; d = 0 here
1123 int tmp_clk = (1000 * j * r) / p;
1125 /* Check whether this values get closer than
1126 * the best ones we had before
1128 if (abs(codec_clk - tmp_clk) <
1129 abs(codec_clk - last_clk)) {
1130 pll_j = j; pll_d = 0;
1131 pll_r = r; pll_p = p;
1135 /* Early exit for exact matches */
1136 if (tmp_clk == codec_clk)
1141 /* try with d != 0 */
1142 for (p = 1; p <= 8; p++) {
1143 j = codec_clk * p / 1000;
1145 if (j < 4 || j > 11)
1148 /* do not use codec_clk here since we'd loose precision */
1149 d = ((2048 * p * fsref) - j * aic3x->sysclk)
1150 * 100 / (aic3x->sysclk/100);
1152 clk = (10000 * j + d) / (10 * p);
1154 /* check whether this values get closer than the best
1155 * ones we had before */
1156 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
1157 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
1161 /* Early exit for exact matches */
1162 if (clk == codec_clk)
1166 if (last_clk == 0) {
1167 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
1172 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
1173 snd_soc_component_write(component, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1174 pll_r << PLLR_SHIFT);
1175 snd_soc_component_write(component, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1176 snd_soc_component_write(component, AIC3X_PLL_PROGC_REG,
1177 (pll_d >> 6) << PLLD_MSB_SHIFT);
1178 snd_soc_component_write(component, AIC3X_PLL_PROGD_REG,
1179 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1184 static int aic3x_prepare(struct snd_pcm_substream *substream,
1185 struct snd_soc_dai *dai)
1187 struct snd_soc_component *component = dai->component;
1188 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1190 int width = aic3x->slot_width;
1193 width = substream->runtime->sample_bits;
1195 /* TDM slot selection only valid in DSP_A/_B mode */
1196 if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A)
1197 delay += (aic3x->tdm_delay*width + 1);
1198 else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B)
1199 delay += aic3x->tdm_delay*width;
1201 /* Configure data delay */
1202 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLC, delay);
1207 static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1209 struct snd_soc_component *component = dai->component;
1210 u8 ldac_reg = snd_soc_component_read32(component, LDAC_VOL) & ~MUTE_ON;
1211 u8 rdac_reg = snd_soc_component_read32(component, RDAC_VOL) & ~MUTE_ON;
1214 snd_soc_component_write(component, LDAC_VOL, ldac_reg | MUTE_ON);
1215 snd_soc_component_write(component, RDAC_VOL, rdac_reg | MUTE_ON);
1217 snd_soc_component_write(component, LDAC_VOL, ldac_reg);
1218 snd_soc_component_write(component, RDAC_VOL, rdac_reg);
1224 static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1225 int clk_id, unsigned int freq, int dir)
1227 struct snd_soc_component *component = codec_dai->component;
1228 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1230 /* set clock on MCLK or GPIO2 or BCLK */
1231 snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1232 clk_id << PLLCLK_IN_SHIFT);
1233 snd_soc_component_update_bits(component, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1234 clk_id << CLKDIV_IN_SHIFT);
1236 aic3x->sysclk = freq;
1240 static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1243 struct snd_soc_component *component = codec_dai->component;
1244 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1245 u8 iface_areg, iface_breg;
1247 iface_areg = snd_soc_component_read32(component, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1248 iface_breg = snd_soc_component_read32(component, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1250 /* set master/slave audio interface */
1251 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1252 case SND_SOC_DAIFMT_CBM_CFM:
1254 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1256 case SND_SOC_DAIFMT_CBS_CFS:
1258 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1260 case SND_SOC_DAIFMT_CBM_CFS:
1262 iface_areg |= BIT_CLK_MASTER;
1263 iface_areg &= ~WORD_CLK_MASTER;
1265 case SND_SOC_DAIFMT_CBS_CFM:
1267 iface_areg |= WORD_CLK_MASTER;
1268 iface_areg &= ~BIT_CLK_MASTER;
1275 * match both interface format and signal polarities since they
1278 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1279 SND_SOC_DAIFMT_INV_MASK)) {
1280 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1282 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1283 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1284 iface_breg |= (0x01 << 6);
1286 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1287 iface_breg |= (0x02 << 6);
1289 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1290 iface_breg |= (0x03 << 6);
1296 aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
1299 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLA, iface_areg);
1300 snd_soc_component_write(component, AIC3X_ASD_INTF_CTRLB, iface_breg);
1305 static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
1306 unsigned int tx_mask, unsigned int rx_mask,
1307 int slots, int slot_width)
1309 struct snd_soc_component *component = codec_dai->component;
1310 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1313 if (tx_mask != rx_mask) {
1314 dev_err(component->dev, "tx and rx masks must be symmetric\n");
1318 if (unlikely(!tx_mask)) {
1319 dev_err(component->dev, "tx and rx masks need to be non 0\n");
1323 /* TDM based on DSP mode requires slots to be adjacent */
1324 lsb = __ffs(tx_mask);
1325 if ((lsb + 1) != __fls(tx_mask)) {
1326 dev_err(component->dev, "Invalid mask, slots must be adjacent\n");
1330 switch (slot_width) {
1337 dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
1342 aic3x->tdm_delay = lsb;
1343 aic3x->slot_width = slot_width;
1345 /* DOUT in high-impedance on inactive bit clocks */
1346 snd_soc_component_update_bits(component, AIC3X_ASD_INTF_CTRLA,
1347 DOUT_TRISTATE, DOUT_TRISTATE);
1352 static int aic3x_regulator_event(struct notifier_block *nb,
1353 unsigned long event, void *data)
1355 struct aic3x_disable_nb *disable_nb =
1356 container_of(nb, struct aic3x_disable_nb, nb);
1357 struct aic3x_priv *aic3x = disable_nb->aic3x;
1359 if (event & REGULATOR_EVENT_DISABLE) {
1361 * Put codec to reset and require cache sync as at least one
1362 * of the supplies was disabled
1364 if (gpio_is_valid(aic3x->gpio_reset))
1365 gpio_set_value(aic3x->gpio_reset, 0);
1366 regcache_mark_dirty(aic3x->regmap);
1372 static int aic3x_set_power(struct snd_soc_component *component, int power)
1374 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1375 unsigned int pll_c, pll_d;
1379 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1385 if (gpio_is_valid(aic3x->gpio_reset)) {
1387 gpio_set_value(aic3x->gpio_reset, 1);
1390 /* Sync reg_cache with the hardware */
1391 regcache_cache_only(aic3x->regmap, false);
1392 regcache_sync(aic3x->regmap);
1394 /* Rewrite paired PLL D registers in case cached sync skipped
1395 * writing one of them and thus caused other one also not
1398 pll_c = snd_soc_component_read32(component, AIC3X_PLL_PROGC_REG);
1399 pll_d = snd_soc_component_read32(component, AIC3X_PLL_PROGD_REG);
1400 if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def ||
1401 pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) {
1402 snd_soc_component_write(component, AIC3X_PLL_PROGC_REG, pll_c);
1403 snd_soc_component_write(component, AIC3X_PLL_PROGD_REG, pll_d);
1407 * Delay is needed to reduce pop-noise after syncing back the
1413 * Do soft reset to this codec instance in order to clear
1414 * possible VDD leakage currents in case the supply regulators
1417 snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
1418 regcache_mark_dirty(aic3x->regmap);
1420 /* HW writes are needless when bias is off */
1421 regcache_cache_only(aic3x->regmap, true);
1422 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1429 static int aic3x_set_bias_level(struct snd_soc_component *component,
1430 enum snd_soc_bias_level level)
1432 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1435 case SND_SOC_BIAS_ON:
1437 case SND_SOC_BIAS_PREPARE:
1438 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY &&
1441 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1442 PLL_ENABLE, PLL_ENABLE);
1445 case SND_SOC_BIAS_STANDBY:
1447 aic3x_set_power(component, 1);
1448 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_PREPARE &&
1451 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG,
1455 case SND_SOC_BIAS_OFF:
1457 aic3x_set_power(component, 0);
1464 #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1465 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1466 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \
1467 SNDRV_PCM_FMTBIT_S32_LE)
1469 static const struct snd_soc_dai_ops aic3x_dai_ops = {
1470 .hw_params = aic3x_hw_params,
1471 .prepare = aic3x_prepare,
1472 .digital_mute = aic3x_mute,
1473 .set_sysclk = aic3x_set_dai_sysclk,
1474 .set_fmt = aic3x_set_dai_fmt,
1475 .set_tdm_slot = aic3x_set_dai_tdm_slot,
1478 static struct snd_soc_dai_driver aic3x_dai = {
1479 .name = "tlv320aic3x-hifi",
1481 .stream_name = "Playback",
1484 .rates = AIC3X_RATES,
1485 .formats = AIC3X_FORMATS,},
1487 .stream_name = "Capture",
1490 .rates = AIC3X_RATES,
1491 .formats = AIC3X_FORMATS,},
1492 .ops = &aic3x_dai_ops,
1493 .symmetric_rates = 1,
1496 static void aic3x_mono_init(struct snd_soc_component *component)
1498 /* DAC to Mono Line Out default volume and route to Output mixer */
1499 snd_soc_component_write(component, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1500 snd_soc_component_write(component, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1502 /* unmute all outputs */
1503 snd_soc_component_update_bits(component, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1505 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1506 snd_soc_component_write(component, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1507 snd_soc_component_write(component, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1509 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1510 snd_soc_component_write(component, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1511 snd_soc_component_write(component, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1515 * initialise the AIC3X driver
1516 * register the mixer and dsp interfaces with the kernel
1518 static int aic3x_init(struct snd_soc_component *component)
1520 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1522 snd_soc_component_write(component, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1523 snd_soc_component_write(component, AIC3X_RESET, SOFT_RESET);
1525 /* DAC default volume and mute */
1526 snd_soc_component_write(component, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1527 snd_soc_component_write(component, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1529 /* DAC to HP default volume and route to Output mixer */
1530 snd_soc_component_write(component, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1531 snd_soc_component_write(component, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1532 snd_soc_component_write(component, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1533 snd_soc_component_write(component, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1534 /* DAC to Line Out default volume and route to Output mixer */
1535 snd_soc_component_write(component, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1536 snd_soc_component_write(component, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1538 /* unmute all outputs */
1539 snd_soc_component_update_bits(component, LLOPM_CTRL, UNMUTE, UNMUTE);
1540 snd_soc_component_update_bits(component, RLOPM_CTRL, UNMUTE, UNMUTE);
1541 snd_soc_component_update_bits(component, HPLOUT_CTRL, UNMUTE, UNMUTE);
1542 snd_soc_component_update_bits(component, HPROUT_CTRL, UNMUTE, UNMUTE);
1543 snd_soc_component_update_bits(component, HPLCOM_CTRL, UNMUTE, UNMUTE);
1544 snd_soc_component_update_bits(component, HPRCOM_CTRL, UNMUTE, UNMUTE);
1546 /* ADC default volume and unmute */
1547 snd_soc_component_write(component, LADC_VOL, DEFAULT_GAIN);
1548 snd_soc_component_write(component, RADC_VOL, DEFAULT_GAIN);
1549 /* By default route Line1 to ADC PGA mixer */
1550 snd_soc_component_write(component, LINE1L_2_LADC_CTRL, 0x0);
1551 snd_soc_component_write(component, LINE1R_2_RADC_CTRL, 0x0);
1553 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1554 snd_soc_component_write(component, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1555 snd_soc_component_write(component, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1556 snd_soc_component_write(component, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1557 snd_soc_component_write(component, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1558 /* PGA to Line Out default volume, disconnect from Output Mixer */
1559 snd_soc_component_write(component, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1560 snd_soc_component_write(component, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1562 /* On tlv320aic3104, these registers are reserved and must not be written */
1563 if (aic3x->model != AIC3X_MODEL_3104) {
1564 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1565 snd_soc_component_write(component, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1566 snd_soc_component_write(component, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1567 snd_soc_component_write(component, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1568 snd_soc_component_write(component, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1569 /* Line2 Line Out default volume, disconnect from Output Mixer */
1570 snd_soc_component_write(component, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1571 snd_soc_component_write(component, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1574 switch (aic3x->model) {
1575 case AIC3X_MODEL_3X:
1576 case AIC3X_MODEL_33:
1577 aic3x_mono_init(component);
1579 case AIC3X_MODEL_3007:
1580 snd_soc_component_write(component, CLASSD_CTRL, 0);
1584 /* Output common-mode voltage = 1.5 V */
1585 snd_soc_component_update_bits(component, HPOUT_SC, HPOUT_SC_OCMV_MASK,
1586 aic3x->ocmv << HPOUT_SC_OCMV_SHIFT);
1591 static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1593 struct aic3x_priv *a;
1595 list_for_each_entry(a, &reset_list, list) {
1596 if (gpio_is_valid(aic3x->gpio_reset) &&
1597 aic3x->gpio_reset == a->gpio_reset)
1604 static int aic3x_probe(struct snd_soc_component *component)
1606 struct aic3x_priv *aic3x = snd_soc_component_get_drvdata(component);
1609 aic3x->component = component;
1611 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1612 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1613 aic3x->disable_nb[i].aic3x = aic3x;
1614 ret = devm_regulator_register_notifier(
1615 aic3x->supplies[i].consumer,
1616 &aic3x->disable_nb[i].nb);
1618 dev_err(component->dev,
1619 "Failed to request regulator notifier: %d\n",
1625 regcache_mark_dirty(aic3x->regmap);
1626 aic3x_init(component);
1629 if (aic3x->model != AIC3X_MODEL_3104) {
1630 /* setup GPIO functions */
1631 snd_soc_component_write(component, AIC3X_GPIO1_REG,
1632 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1633 snd_soc_component_write(component, AIC3X_GPIO2_REG,
1634 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1636 dev_warn(component->dev, "GPIO functionality is not supported on tlv320aic3104\n");
1640 switch (aic3x->model) {
1641 case AIC3X_MODEL_3X:
1642 case AIC3X_MODEL_33:
1643 snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
1644 ARRAY_SIZE(aic3x_extra_snd_controls));
1645 snd_soc_add_component_controls(component, aic3x_mono_controls,
1646 ARRAY_SIZE(aic3x_mono_controls));
1648 case AIC3X_MODEL_3007:
1649 snd_soc_add_component_controls(component, aic3x_extra_snd_controls,
1650 ARRAY_SIZE(aic3x_extra_snd_controls));
1651 snd_soc_add_component_controls(component,
1652 &aic3x_classd_amp_gain_ctrl, 1);
1654 case AIC3X_MODEL_3104:
1658 /* set mic bias voltage */
1659 switch (aic3x->micbias_vg) {
1660 case AIC3X_MICBIAS_2_0V:
1661 case AIC3X_MICBIAS_2_5V:
1662 case AIC3X_MICBIAS_AVDDV:
1663 snd_soc_component_update_bits(component, MICBIAS_CTRL,
1665 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1667 case AIC3X_MICBIAS_OFF:
1669 * noting to do. target won't enter here. This is just to avoid
1670 * compile time warning "warning: enumeration value
1671 * 'AIC3X_MICBIAS_OFF' not handled in switch"
1676 aic3x_add_widgets(component);
1681 static const struct snd_soc_component_driver soc_component_dev_aic3x = {
1682 .set_bias_level = aic3x_set_bias_level,
1683 .probe = aic3x_probe,
1684 .controls = aic3x_snd_controls,
1685 .num_controls = ARRAY_SIZE(aic3x_snd_controls),
1686 .dapm_widgets = aic3x_dapm_widgets,
1687 .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets),
1688 .dapm_routes = intercon,
1689 .num_dapm_routes = ARRAY_SIZE(intercon),
1690 .use_pmdown_time = 1,
1692 .non_legacy_dai_naming = 1,
1695 static void aic3x_configure_ocmv(struct i2c_client *client)
1697 struct device_node *np = client->dev.of_node;
1698 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1702 if (np && !of_property_read_u32(np, "ai3x-ocmv", &value)) {
1703 /* OCMV setting is forced by DT */
1705 aic3x->ocmv = value;
1710 dvdd = regulator_get_voltage(aic3x->supplies[1].consumer);
1711 avdd = regulator_get_voltage(aic3x->supplies[2].consumer);
1713 if (avdd > 3600000 || dvdd > 1950000) {
1714 dev_warn(&client->dev,
1715 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n",
1717 } else if (avdd == 3600000 && dvdd == 1950000) {
1718 aic3x->ocmv = HPOUT_SC_OCMV_1_8V;
1719 } else if (avdd > 3300000 && dvdd > 1800000) {
1720 aic3x->ocmv = HPOUT_SC_OCMV_1_65V;
1721 } else if (avdd > 3000000 && dvdd > 1650000) {
1722 aic3x->ocmv = HPOUT_SC_OCMV_1_5V;
1723 } else if (avdd >= 2700000 && dvdd >= 1525000) {
1724 aic3x->ocmv = HPOUT_SC_OCMV_1_35V;
1726 dev_warn(&client->dev,
1727 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",
1733 * AIC3X 2 wire address can be up to 4 devices with device addresses
1734 * 0x18, 0x19, 0x1A, 0x1B
1737 static const struct i2c_device_id aic3x_i2c_id[] = {
1738 { "tlv320aic3x", AIC3X_MODEL_3X },
1739 { "tlv320aic33", AIC3X_MODEL_33 },
1740 { "tlv320aic3007", AIC3X_MODEL_3007 },
1741 { "tlv320aic3106", AIC3X_MODEL_3X },
1742 { "tlv320aic3104", AIC3X_MODEL_3104 },
1745 MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1747 static const struct reg_sequence aic3007_class_d[] = {
1748 /* Class-D speaker driver init; datasheet p. 46 */
1749 { AIC3X_PAGE_SELECT, 0x0D },
1754 { AIC3X_PAGE_SELECT, 0x00 },
1758 * If the i2c layer weren't so broken, we could pass this kind of data
1761 static int aic3x_i2c_probe(struct i2c_client *i2c,
1762 const struct i2c_device_id *id)
1764 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1765 struct aic3x_priv *aic3x;
1766 struct aic3x_setup_data *ai3x_setup;
1767 struct device_node *np = i2c->dev.of_node;
1771 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1775 aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap);
1776 if (IS_ERR(aic3x->regmap)) {
1777 ret = PTR_ERR(aic3x->regmap);
1781 regcache_cache_only(aic3x->regmap, true);
1783 i2c_set_clientdata(i2c, aic3x);
1785 aic3x->gpio_reset = pdata->gpio_reset;
1786 aic3x->setup = pdata->setup;
1787 aic3x->micbias_vg = pdata->micbias_vg;
1789 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1794 ret = of_get_named_gpio(np, "reset-gpios", 0);
1796 aic3x->gpio_reset = ret;
1798 ret = of_get_named_gpio(np, "gpio-reset", 0);
1800 dev_warn(&i2c->dev, "Using deprecated property \"gpio-reset\", please update your DT");
1801 aic3x->gpio_reset = ret;
1803 aic3x->gpio_reset = -1;
1807 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1808 ai3x_setup->gpio_func, 2) >= 0) {
1809 aic3x->setup = ai3x_setup;
1812 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1815 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1818 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1821 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1824 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1825 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1829 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1833 aic3x->gpio_reset = -1;
1836 aic3x->model = id->driver_data;
1838 if (gpio_is_valid(aic3x->gpio_reset) &&
1839 !aic3x_is_shared_reset(aic3x)) {
1840 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1843 gpio_direction_output(aic3x->gpio_reset, 0);
1846 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1847 aic3x->supplies[i].supply = aic3x_supply_names[i];
1849 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
1852 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1856 aic3x_configure_ocmv(i2c);
1858 if (aic3x->model == AIC3X_MODEL_3007) {
1859 ret = regmap_register_patch(aic3x->regmap, aic3007_class_d,
1860 ARRAY_SIZE(aic3007_class_d));
1862 dev_err(&i2c->dev, "Failed to init class D: %d\n",
1866 ret = devm_snd_soc_register_component(&i2c->dev,
1867 &soc_component_dev_aic3x, &aic3x_dai, 1);
1872 INIT_LIST_HEAD(&aic3x->list);
1873 list_add(&aic3x->list, &reset_list);
1878 if (gpio_is_valid(aic3x->gpio_reset) &&
1879 !aic3x_is_shared_reset(aic3x))
1880 gpio_free(aic3x->gpio_reset);
1885 static int aic3x_i2c_remove(struct i2c_client *client)
1887 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1889 list_del(&aic3x->list);
1891 if (gpio_is_valid(aic3x->gpio_reset) &&
1892 !aic3x_is_shared_reset(aic3x)) {
1893 gpio_set_value(aic3x->gpio_reset, 0);
1894 gpio_free(aic3x->gpio_reset);
1899 #if defined(CONFIG_OF)
1900 static const struct of_device_id tlv320aic3x_of_match[] = {
1901 { .compatible = "ti,tlv320aic3x", },
1902 { .compatible = "ti,tlv320aic33" },
1903 { .compatible = "ti,tlv320aic3007" },
1904 { .compatible = "ti,tlv320aic3106" },
1905 { .compatible = "ti,tlv320aic3104" },
1908 MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1911 /* machine i2c codec control layer */
1912 static struct i2c_driver aic3x_i2c_driver = {
1914 .name = "tlv320aic3x-codec",
1915 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
1917 .probe = aic3x_i2c_probe,
1918 .remove = aic3x_i2c_remove,
1919 .id_table = aic3x_i2c_id,
1922 module_i2c_driver(aic3x_i2c_driver);
1924 MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1925 MODULE_AUTHOR("Vladimir Barinov");
1926 MODULE_LICENSE("GPL");