1 /* SPDX-License-Identifier: GPL-2.0
3 * Clock Tree for the Texas Instruments TLV320AIC32x4
5 * Copyright 2019 Annaliese McDermond
7 * Author: Annaliese McDermond <nh6z@nh6z.net>
10 #include <linux/clk-provider.h>
11 #include <linux/clkdev.h>
12 #include <linux/regmap.h>
13 #include <linux/device.h>
15 #include "tlv320aic32x4.h"
17 #define to_clk_aic32x4(_hw) container_of(_hw, struct clk_aic32x4, hw)
21 struct regmap *regmap;
26 * struct clk_aic32x4_pll_muldiv - Multiplier/divider settings
28 * @r: first multiplier
29 * @j: integer part of second multiplier
30 * @d: decimal part of second multiplier
32 struct clk_aic32x4_pll_muldiv {
39 struct aic32x4_clkdesc {
41 const char * const *parent_names;
42 unsigned int num_parents;
43 const struct clk_ops *ops;
47 static int clk_aic32x4_pll_prepare(struct clk_hw *hw)
49 struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
51 return regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
52 AIC32X4_PLLEN, AIC32X4_PLLEN);
55 static void clk_aic32x4_pll_unprepare(struct clk_hw *hw)
57 struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
59 regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
63 static int clk_aic32x4_pll_is_prepared(struct clk_hw *hw)
65 struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
70 ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
74 return !!(val & AIC32X4_PLLEN);
77 static int clk_aic32x4_pll_get_muldiv(struct clk_aic32x4 *pll,
78 struct clk_aic32x4_pll_muldiv *settings)
80 /* Change to use regmap_bulk_read? */
84 ret = regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
87 settings->r = val & AIC32X4_PLL_R_MASK;
88 settings->p = (val & AIC32X4_PLL_P_MASK) >> AIC32X4_PLL_P_SHIFT;
90 ret = regmap_read(pll->regmap, AIC32X4_PLLJ, &val);
95 ret = regmap_read(pll->regmap, AIC32X4_PLLDMSB, &val);
98 settings->d = val << 8;
100 ret = regmap_read(pll->regmap, AIC32X4_PLLDLSB, &val);
108 static int clk_aic32x4_pll_set_muldiv(struct clk_aic32x4 *pll,
109 struct clk_aic32x4_pll_muldiv *settings)
112 /* Change to use regmap_bulk_write for some if not all? */
114 ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
115 AIC32X4_PLL_R_MASK, settings->r);
119 ret = regmap_update_bits(pll->regmap, AIC32X4_PLLPR,
121 settings->p << AIC32X4_PLL_P_SHIFT);
125 ret = regmap_write(pll->regmap, AIC32X4_PLLJ, settings->j);
129 ret = regmap_write(pll->regmap, AIC32X4_PLLDMSB, (settings->d >> 8));
132 ret = regmap_write(pll->regmap, AIC32X4_PLLDLSB, (settings->d & 0xff));
139 static unsigned long clk_aic32x4_pll_calc_rate(
140 struct clk_aic32x4_pll_muldiv *settings,
141 unsigned long parent_rate)
145 * We scale j by 10000 to account for the decimal part of P and divide
148 rate = (u64) parent_rate * settings->r *
149 ((settings->j * 10000) + settings->d);
151 return (unsigned long) DIV_ROUND_UP_ULL(rate, settings->p * 10000);
154 static int clk_aic32x4_pll_calc_muldiv(struct clk_aic32x4_pll_muldiv *settings,
155 unsigned long rate, unsigned long parent_rate)
159 settings->p = parent_rate / AIC32X4_MAX_PLL_CLKIN + 1;
164 * We scale this figure by 10000 so that we can get the decimal part
165 * of the multiplier. This is because we can't do floating point
166 * math in the kernel.
168 multiplier = (u64) rate * settings->p * 10000;
169 do_div(multiplier, parent_rate);
172 * J can't be over 64, so R can scale this.
173 * R can't be greater than 4.
175 settings->r = ((u32) multiplier / 640000) + 1;
178 do_div(multiplier, settings->r);
183 if (multiplier < 10000)
186 /* Figure out the integer part, J, and the fractional part, D. */
187 settings->j = (u32) multiplier / 10000;
188 settings->d = (u32) multiplier % 10000;
193 static unsigned long clk_aic32x4_pll_recalc_rate(struct clk_hw *hw,
194 unsigned long parent_rate)
196 struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
197 struct clk_aic32x4_pll_muldiv settings;
200 ret = clk_aic32x4_pll_get_muldiv(pll, &settings);
204 return clk_aic32x4_pll_calc_rate(&settings, parent_rate);
207 static long clk_aic32x4_pll_round_rate(struct clk_hw *hw,
209 unsigned long *parent_rate)
211 struct clk_aic32x4_pll_muldiv settings;
214 ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, *parent_rate);
218 return clk_aic32x4_pll_calc_rate(&settings, *parent_rate);
221 static int clk_aic32x4_pll_set_rate(struct clk_hw *hw,
223 unsigned long parent_rate)
225 struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
226 struct clk_aic32x4_pll_muldiv settings;
229 ret = clk_aic32x4_pll_calc_muldiv(&settings, rate, parent_rate);
233 ret = clk_aic32x4_pll_set_muldiv(pll, &settings);
237 /* 10ms is the delay to wait before the clocks are stable */
243 static int clk_aic32x4_pll_set_parent(struct clk_hw *hw, u8 index)
245 struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
247 return regmap_update_bits(pll->regmap,
249 AIC32X4_PLL_CLKIN_MASK,
250 index << AIC32X4_PLL_CLKIN_SHIFT);
253 static u8 clk_aic32x4_pll_get_parent(struct clk_hw *hw)
255 struct clk_aic32x4 *pll = to_clk_aic32x4(hw);
258 regmap_read(pll->regmap, AIC32X4_PLLPR, &val);
260 return (val & AIC32X4_PLL_CLKIN_MASK) >> AIC32X4_PLL_CLKIN_SHIFT;
264 static const struct clk_ops aic32x4_pll_ops = {
265 .prepare = clk_aic32x4_pll_prepare,
266 .unprepare = clk_aic32x4_pll_unprepare,
267 .is_prepared = clk_aic32x4_pll_is_prepared,
268 .recalc_rate = clk_aic32x4_pll_recalc_rate,
269 .round_rate = clk_aic32x4_pll_round_rate,
270 .set_rate = clk_aic32x4_pll_set_rate,
271 .set_parent = clk_aic32x4_pll_set_parent,
272 .get_parent = clk_aic32x4_pll_get_parent,
275 static int clk_aic32x4_codec_clkin_set_parent(struct clk_hw *hw, u8 index)
277 struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
279 return regmap_update_bits(mux->regmap,
281 AIC32X4_CODEC_CLKIN_MASK, index << AIC32X4_CODEC_CLKIN_SHIFT);
284 static u8 clk_aic32x4_codec_clkin_get_parent(struct clk_hw *hw)
286 struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
289 regmap_read(mux->regmap, AIC32X4_CLKMUX, &val);
291 return (val & AIC32X4_CODEC_CLKIN_MASK) >> AIC32X4_CODEC_CLKIN_SHIFT;
294 static const struct clk_ops aic32x4_codec_clkin_ops = {
295 .set_parent = clk_aic32x4_codec_clkin_set_parent,
296 .get_parent = clk_aic32x4_codec_clkin_get_parent,
299 static int clk_aic32x4_div_prepare(struct clk_hw *hw)
301 struct clk_aic32x4 *div = to_clk_aic32x4(hw);
303 return regmap_update_bits(div->regmap, div->reg,
304 AIC32X4_DIVEN, AIC32X4_DIVEN);
307 static void clk_aic32x4_div_unprepare(struct clk_hw *hw)
309 struct clk_aic32x4 *div = to_clk_aic32x4(hw);
311 regmap_update_bits(div->regmap, div->reg,
315 static int clk_aic32x4_div_set_rate(struct clk_hw *hw, unsigned long rate,
316 unsigned long parent_rate)
318 struct clk_aic32x4 *div = to_clk_aic32x4(hw);
321 divisor = DIV_ROUND_UP(parent_rate, rate);
325 return regmap_update_bits(div->regmap, div->reg,
326 AIC32X4_DIV_MASK, divisor);
329 static long clk_aic32x4_div_round_rate(struct clk_hw *hw, unsigned long rate,
330 unsigned long *parent_rate)
332 unsigned long divisor;
334 divisor = DIV_ROUND_UP(*parent_rate, rate);
338 return DIV_ROUND_UP(*parent_rate, divisor);
341 static unsigned long clk_aic32x4_div_recalc_rate(struct clk_hw *hw,
342 unsigned long parent_rate)
344 struct clk_aic32x4 *div = to_clk_aic32x4(hw);
348 regmap_read(div->regmap, div->reg, &val);
350 return DIV_ROUND_UP(parent_rate, val & AIC32X4_DIV_MASK);
353 static const struct clk_ops aic32x4_div_ops = {
354 .prepare = clk_aic32x4_div_prepare,
355 .unprepare = clk_aic32x4_div_unprepare,
356 .set_rate = clk_aic32x4_div_set_rate,
357 .round_rate = clk_aic32x4_div_round_rate,
358 .recalc_rate = clk_aic32x4_div_recalc_rate,
361 static int clk_aic32x4_bdiv_set_parent(struct clk_hw *hw, u8 index)
363 struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
365 return regmap_update_bits(mux->regmap, AIC32X4_IFACE3,
366 AIC32X4_BDIVCLK_MASK, index);
369 static u8 clk_aic32x4_bdiv_get_parent(struct clk_hw *hw)
371 struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
374 regmap_read(mux->regmap, AIC32X4_IFACE3, &val);
376 return val & AIC32X4_BDIVCLK_MASK;
379 static const struct clk_ops aic32x4_bdiv_ops = {
380 .prepare = clk_aic32x4_div_prepare,
381 .unprepare = clk_aic32x4_div_unprepare,
382 .set_parent = clk_aic32x4_bdiv_set_parent,
383 .get_parent = clk_aic32x4_bdiv_get_parent,
384 .set_rate = clk_aic32x4_div_set_rate,
385 .round_rate = clk_aic32x4_div_round_rate,
386 .recalc_rate = clk_aic32x4_div_recalc_rate,
389 static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
393 (const char* []) { "mclk", "bclk", "gpio", "din" },
395 .ops = &aic32x4_pll_ops,
399 .name = "codec_clkin",
401 (const char *[]) { "mclk", "bclk", "gpio", "pll" },
403 .ops = &aic32x4_codec_clkin_ops,
408 .parent_names = (const char * []) { "codec_clkin" },
410 .ops = &aic32x4_div_ops,
415 .parent_names = (const char * []) { "ndac" },
417 .ops = &aic32x4_div_ops,
422 .parent_names = (const char * []) { "codec_clkin" },
424 .ops = &aic32x4_div_ops,
429 .parent_names = (const char * []) { "nadc" },
431 .ops = &aic32x4_div_ops,
437 (const char *[]) { "ndac", "mdac", "nadc", "madc" },
439 .ops = &aic32x4_bdiv_ops,
440 .reg = AIC32X4_BCLKN,
444 static struct clk *aic32x4_register_clk(struct device *dev,
445 struct aic32x4_clkdesc *desc)
447 struct clk_init_data init;
448 struct clk_aic32x4 *priv;
449 const char *devname = dev_name(dev);
451 init.ops = desc->ops;
452 init.name = desc->name;
453 init.parent_names = desc->parent_names;
454 init.num_parents = desc->num_parents;
457 priv = devm_kzalloc(dev, sizeof(struct clk_aic32x4), GFP_KERNEL);
459 return (struct clk *) -ENOMEM;
462 priv->hw.init = &init;
463 priv->regmap = dev_get_regmap(dev, NULL);
464 priv->reg = desc->reg;
466 clk_hw_register_clkdev(&priv->hw, desc->name, devname);
467 return devm_clk_register(dev, &priv->hw);
470 int aic32x4_register_clocks(struct device *dev, const char *mclk_name)
475 * These lines are here to preserve the current functionality of
476 * the driver with regard to the DT. These should eventually be set
477 * by DT nodes so that the connections can be set up in configuration
480 aic32x4_clkdesc_array[0].parent_names =
481 (const char* []) { mclk_name, "bclk", "gpio", "din" };
482 aic32x4_clkdesc_array[1].parent_names =
483 (const char *[]) { mclk_name, "bclk", "gpio", "pll" };
485 for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i)
486 aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]);
490 EXPORT_SYMBOL_GPL(aic32x4_register_clocks);