1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
5 * Copyright: 2011 Raumfeld GmbH
6 * Author: Johannes Stezenbach <js@sig21.net>
9 * Wolfson Microelectronics PLC.
10 * Mark Brown <broonie@opensource.wolfsonmicro.com>
11 * Freescale Semiconductor, Inc.
12 * Timur Tabi <timur@freescale.com>
15 #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/init.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
23 #include <linux/i2c.h>
24 #include <linux/of_device.h>
25 #include <linux/of_gpio.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/slab.h>
30 #include <linux/workqueue.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/soc.h>
35 #include <sound/soc-dapm.h>
36 #include <sound/initval.h>
37 #include <sound/tlv.h>
39 #include <sound/sta32x.h>
42 #define STA32X_RATES (SNDRV_PCM_RATE_32000 | \
43 SNDRV_PCM_RATE_44100 | \
44 SNDRV_PCM_RATE_48000 | \
45 SNDRV_PCM_RATE_88200 | \
46 SNDRV_PCM_RATE_96000 | \
47 SNDRV_PCM_RATE_176400 | \
48 SNDRV_PCM_RATE_192000)
50 #define STA32X_FORMATS \
51 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S18_3LE | \
52 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE | \
53 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
55 /* Power-up register defaults */
56 static const struct reg_default sta32x_regs[] = {
102 static const struct regmap_range sta32x_write_regs_range[] = {
103 regmap_reg_range(STA32X_CONFA, STA32X_FDRC2),
106 static const struct regmap_range sta32x_read_regs_range[] = {
107 regmap_reg_range(STA32X_CONFA, STA32X_FDRC2),
110 static const struct regmap_range sta32x_volatile_regs_range[] = {
111 regmap_reg_range(STA32X_CFADDR2, STA32X_CFUD),
114 static const struct regmap_access_table sta32x_write_regs = {
115 .yes_ranges = sta32x_write_regs_range,
116 .n_yes_ranges = ARRAY_SIZE(sta32x_write_regs_range),
119 static const struct regmap_access_table sta32x_read_regs = {
120 .yes_ranges = sta32x_read_regs_range,
121 .n_yes_ranges = ARRAY_SIZE(sta32x_read_regs_range),
124 static const struct regmap_access_table sta32x_volatile_regs = {
125 .yes_ranges = sta32x_volatile_regs_range,
126 .n_yes_ranges = ARRAY_SIZE(sta32x_volatile_regs_range),
129 /* regulator power supply names */
130 static const char *sta32x_supply_names[] = {
131 "Vdda", /* analog supply, 3.3VV */
132 "Vdd3", /* digital supply, 3.3V */
133 "Vcc" /* power amp spply, 10V - 36V */
136 /* codec private data */
138 struct regmap *regmap;
140 struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)];
141 struct snd_soc_component *component;
142 struct sta32x_platform_data *pdata;
147 u32 coef_shadow[STA32X_COEF_COUNT];
148 struct delayed_work watchdog_work;
150 struct gpio_desc *gpiod_nreset;
151 struct mutex coeff_lock;
154 static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
155 static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
156 static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0);
158 static const char *sta32x_drc_ac[] = {
159 "Anti-Clipping", "Dynamic Range Compression" };
160 static const char *sta32x_auto_eq_mode[] = {
161 "User", "Preset", "Loudness" };
162 static const char *sta32x_auto_gc_mode[] = {
163 "User", "AC no clipping", "AC limited clipping (10%)",
164 "DRC nighttime listening mode" };
165 static const char *sta32x_auto_xo_mode[] = {
166 "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz",
167 "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" };
168 static const char *sta32x_preset_eq_mode[] = {
169 "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft",
170 "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1",
171 "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2",
172 "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7",
173 "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12",
174 "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" };
175 static const char *sta32x_limiter_select[] = {
176 "Limiter Disabled", "Limiter #1", "Limiter #2" };
177 static const char *sta32x_limiter_attack_rate[] = {
178 "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
179 "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
180 "0.0645", "0.0564", "0.0501", "0.0451" };
181 static const char *sta32x_limiter_release_rate[] = {
182 "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
183 "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
184 "0.0134", "0.0117", "0.0110", "0.0104" };
185 static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_attack_tlv,
186 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
187 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
190 static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_release_tlv,
191 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
192 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
193 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
194 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
195 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
198 static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_attack_tlv,
199 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
200 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
201 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
204 static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_release_tlv,
205 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
206 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
207 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
208 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
209 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
212 static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum,
213 STA32X_CONFD, STA32X_CONFD_DRC_SHIFT,
215 static SOC_ENUM_SINGLE_DECL(sta32x_auto_eq_enum,
216 STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT,
217 sta32x_auto_eq_mode);
218 static SOC_ENUM_SINGLE_DECL(sta32x_auto_gc_enum,
219 STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT,
220 sta32x_auto_gc_mode);
221 static SOC_ENUM_SINGLE_DECL(sta32x_auto_xo_enum,
222 STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT,
223 sta32x_auto_xo_mode);
224 static SOC_ENUM_SINGLE_DECL(sta32x_preset_eq_enum,
225 STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT,
226 sta32x_preset_eq_mode);
227 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch1_enum,
228 STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT,
229 sta32x_limiter_select);
230 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch2_enum,
231 STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT,
232 sta32x_limiter_select);
233 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch3_enum,
234 STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT,
235 sta32x_limiter_select);
236 static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_attack_rate_enum,
237 STA32X_L1AR, STA32X_LxA_SHIFT,
238 sta32x_limiter_attack_rate);
239 static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_attack_rate_enum,
240 STA32X_L2AR, STA32X_LxA_SHIFT,
241 sta32x_limiter_attack_rate);
242 static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_release_rate_enum,
243 STA32X_L1AR, STA32X_LxR_SHIFT,
244 sta32x_limiter_release_rate);
245 static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_release_rate_enum,
246 STA32X_L2AR, STA32X_LxR_SHIFT,
247 sta32x_limiter_release_rate);
249 /* byte array controls for setting biquad, mixer, scaling coefficients;
250 * for biquads all five coefficients need to be set in one go,
251 * mixer and pre/postscale coefs can be set individually;
252 * each coef is 24bit, the bytes are ordered in the same way
253 * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0)
256 static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol,
257 struct snd_ctl_elem_info *uinfo)
259 int numcoef = kcontrol->private_value >> 16;
260 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
261 uinfo->count = 3 * numcoef;
265 static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
266 struct snd_ctl_elem_value *ucontrol)
268 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
269 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
270 int numcoef = kcontrol->private_value >> 16;
271 int index = kcontrol->private_value & 0xffff;
272 unsigned int cfud, val;
275 mutex_lock(&sta32x->coeff_lock);
277 /* preserve reserved bits in STA32X_CFUD */
278 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
281 * chip documentation does not say if the bits are self clearing,
282 * so do it explicitly
284 regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
286 regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
288 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x04);
289 } else if (numcoef == 5) {
290 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x08);
296 for (i = 0; i < 3 * numcoef; i++) {
297 regmap_read(sta32x->regmap, STA32X_B1CF1 + i, &val);
298 ucontrol->value.bytes.data[i] = val;
302 mutex_unlock(&sta32x->coeff_lock);
307 static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
308 struct snd_ctl_elem_value *ucontrol)
310 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
311 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
312 int numcoef = kcontrol->private_value >> 16;
313 int index = kcontrol->private_value & 0xffff;
317 /* preserve reserved bits in STA32X_CFUD */
318 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
321 * chip documentation does not say if the bits are self clearing,
322 * so do it explicitly
324 regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
326 regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
327 for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++)
328 sta32x->coef_shadow[index + i] =
329 (ucontrol->value.bytes.data[3 * i] << 16)
330 | (ucontrol->value.bytes.data[3 * i + 1] << 8)
331 | (ucontrol->value.bytes.data[3 * i + 2]);
332 for (i = 0; i < 3 * numcoef; i++)
333 regmap_write(sta32x->regmap, STA32X_B1CF1 + i,
334 ucontrol->value.bytes.data[i]);
336 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
337 else if (numcoef == 5)
338 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x02);
345 static int sta32x_sync_coef_shadow(struct snd_soc_component *component)
347 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
351 /* preserve reserved bits in STA32X_CFUD */
352 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
355 for (i = 0; i < STA32X_COEF_COUNT; i++) {
356 regmap_write(sta32x->regmap, STA32X_CFADDR2, i);
357 regmap_write(sta32x->regmap, STA32X_B1CF1,
358 (sta32x->coef_shadow[i] >> 16) & 0xff);
359 regmap_write(sta32x->regmap, STA32X_B1CF2,
360 (sta32x->coef_shadow[i] >> 8) & 0xff);
361 regmap_write(sta32x->regmap, STA32X_B1CF3,
362 (sta32x->coef_shadow[i]) & 0xff);
364 * chip documentation does not say if the bits are
365 * self-clearing, so do it explicitly
367 regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
368 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
373 static int sta32x_cache_sync(struct snd_soc_component *component)
375 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
379 /* mute during register sync */
380 regmap_read(sta32x->regmap, STA32X_MMUTE, &mute);
381 regmap_write(sta32x->regmap, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE);
382 sta32x_sync_coef_shadow(component);
383 rc = regcache_sync(sta32x->regmap);
384 regmap_write(sta32x->regmap, STA32X_MMUTE, mute);
388 /* work around ESD issue where sta32x resets and loses all configuration */
389 static void sta32x_watchdog(struct work_struct *work)
391 struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv,
393 struct snd_soc_component *component = sta32x->component;
394 unsigned int confa, confa_cached;
396 /* check if sta32x has reset itself */
397 confa_cached = snd_soc_component_read(component, STA32X_CONFA);
398 regcache_cache_bypass(sta32x->regmap, true);
399 confa = snd_soc_component_read(component, STA32X_CONFA);
400 regcache_cache_bypass(sta32x->regmap, false);
401 if (confa != confa_cached) {
402 regcache_mark_dirty(sta32x->regmap);
403 sta32x_cache_sync(component);
406 if (!sta32x->shutdown)
407 queue_delayed_work(system_power_efficient_wq,
408 &sta32x->watchdog_work,
409 round_jiffies_relative(HZ));
412 static void sta32x_watchdog_start(struct sta32x_priv *sta32x)
414 if (sta32x->pdata->needs_esd_watchdog) {
415 sta32x->shutdown = 0;
416 queue_delayed_work(system_power_efficient_wq,
417 &sta32x->watchdog_work,
418 round_jiffies_relative(HZ));
422 static void sta32x_watchdog_stop(struct sta32x_priv *sta32x)
424 if (sta32x->pdata->needs_esd_watchdog) {
425 sta32x->shutdown = 1;
426 cancel_delayed_work_sync(&sta32x->watchdog_work);
430 #define SINGLE_COEF(xname, index) \
431 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
432 .info = sta32x_coefficient_info, \
433 .get = sta32x_coefficient_get,\
434 .put = sta32x_coefficient_put, \
435 .private_value = index | (1 << 16) }
437 #define BIQUAD_COEFS(xname, index) \
438 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
439 .info = sta32x_coefficient_info, \
440 .get = sta32x_coefficient_get,\
441 .put = sta32x_coefficient_put, \
442 .private_value = index | (5 << 16) }
444 static const struct snd_kcontrol_new sta32x_snd_controls[] = {
445 SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv),
446 SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1),
447 SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1),
448 SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1),
449 SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1),
450 SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv),
451 SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv),
452 SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv),
453 SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0),
454 SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum),
455 SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0),
456 SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0),
457 SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0),
458 SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0),
459 SOC_ENUM("Automode EQ", sta32x_auto_eq_enum),
460 SOC_ENUM("Automode GC", sta32x_auto_gc_enum),
461 SOC_ENUM("Automode XO", sta32x_auto_xo_enum),
462 SOC_ENUM("Preset EQ", sta32x_preset_eq_enum),
463 SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
464 SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
465 SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
466 SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
467 SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
468 SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
469 SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
470 SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum),
471 SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum),
472 SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum),
473 SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv),
474 SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv),
475 SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum),
476 SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum),
477 SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
478 SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter2_release_rate_enum),
480 /* depending on mode, the attack/release thresholds have
481 * two different enum definitions; provide both
483 SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
484 16, 0, sta32x_limiter_ac_attack_tlv),
485 SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
486 16, 0, sta32x_limiter_ac_attack_tlv),
487 SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
488 16, 0, sta32x_limiter_ac_release_tlv),
489 SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
490 16, 0, sta32x_limiter_ac_release_tlv),
491 SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
492 16, 0, sta32x_limiter_drc_attack_tlv),
493 SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
494 16, 0, sta32x_limiter_drc_attack_tlv),
495 SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
496 16, 0, sta32x_limiter_drc_release_tlv),
497 SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
498 16, 0, sta32x_limiter_drc_release_tlv),
500 BIQUAD_COEFS("Ch1 - Biquad 1", 0),
501 BIQUAD_COEFS("Ch1 - Biquad 2", 5),
502 BIQUAD_COEFS("Ch1 - Biquad 3", 10),
503 BIQUAD_COEFS("Ch1 - Biquad 4", 15),
504 BIQUAD_COEFS("Ch2 - Biquad 1", 20),
505 BIQUAD_COEFS("Ch2 - Biquad 2", 25),
506 BIQUAD_COEFS("Ch2 - Biquad 3", 30),
507 BIQUAD_COEFS("Ch2 - Biquad 4", 35),
508 BIQUAD_COEFS("High-pass", 40),
509 BIQUAD_COEFS("Low-pass", 45),
510 SINGLE_COEF("Ch1 - Prescale", 50),
511 SINGLE_COEF("Ch2 - Prescale", 51),
512 SINGLE_COEF("Ch1 - Postscale", 52),
513 SINGLE_COEF("Ch2 - Postscale", 53),
514 SINGLE_COEF("Ch3 - Postscale", 54),
515 SINGLE_COEF("Thermal warning - Postscale", 55),
516 SINGLE_COEF("Ch1 - Mix 1", 56),
517 SINGLE_COEF("Ch1 - Mix 2", 57),
518 SINGLE_COEF("Ch2 - Mix 1", 58),
519 SINGLE_COEF("Ch2 - Mix 2", 59),
520 SINGLE_COEF("Ch3 - Mix 1", 60),
521 SINGLE_COEF("Ch3 - Mix 2", 61),
524 static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = {
525 SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
526 SND_SOC_DAPM_OUTPUT("LEFT"),
527 SND_SOC_DAPM_OUTPUT("RIGHT"),
528 SND_SOC_DAPM_OUTPUT("SUB"),
531 static const struct snd_soc_dapm_route sta32x_dapm_routes[] = {
532 { "LEFT", NULL, "DAC" },
533 { "RIGHT", NULL, "DAC" },
534 { "SUB", NULL, "DAC" },
537 /* MCLK interpolation ratio per fs */
541 } interpolation_ratios[] = {
551 /* MCLK to fs clock ratios */
552 static int mcs_ratio_table[3][7] = {
553 { 768, 512, 384, 256, 128, 576, 0 },
554 { 384, 256, 192, 128, 64, 0 },
555 { 384, 256, 192, 128, 64, 0 },
559 * sta32x_set_dai_sysclk - configure MCLK
560 * @codec_dai: the codec DAI
561 * @clk_id: the clock ID (ignored)
562 * @freq: the MCLK input frequency
563 * @dir: the clock direction (ignored)
565 * The value of MCLK is used to determine which sample rates are supported
566 * by the STA32X, based on the mclk_ratios table.
568 * This function must be called by the machine driver's 'startup' function,
569 * otherwise the list of supported sample rates will not be available in
572 * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause
573 * theoretically possible sample rates to be enabled. Call it again with a
574 * proper value set one the external clock is set (most probably you would do
575 * that from a machine's driver 'hw_param' hook.
577 static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
578 int clk_id, unsigned int freq, int dir)
580 struct snd_soc_component *component = codec_dai->component;
581 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
583 dev_dbg(component->dev, "mclk=%u\n", freq);
590 * sta32x_set_dai_fmt - configure the codec for the selected audio format
591 * @codec_dai: the codec DAI
592 * @fmt: a SND_SOC_DAIFMT_x value indicating the data format
594 * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
597 static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
600 struct snd_soc_component *component = codec_dai->component;
601 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
604 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
605 case SND_SOC_DAIFMT_CBS_CFS:
611 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
612 case SND_SOC_DAIFMT_I2S:
613 case SND_SOC_DAIFMT_RIGHT_J:
614 case SND_SOC_DAIFMT_LEFT_J:
615 sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
621 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
622 case SND_SOC_DAIFMT_NB_NF:
623 confb |= STA32X_CONFB_C2IM;
625 case SND_SOC_DAIFMT_NB_IF:
626 confb |= STA32X_CONFB_C1IM;
632 return regmap_update_bits(sta32x->regmap, STA32X_CONFB,
633 STA32X_CONFB_C1IM | STA32X_CONFB_C2IM, confb);
637 * sta32x_hw_params - program the STA32X with the given hardware parameters.
638 * @substream: the audio stream
639 * @params: the hardware parameters to set
640 * @dai: the SOC DAI (ignored)
642 * This function programs the hardware with the values provided.
643 * Specifically, the sample rate and the data format.
645 static int sta32x_hw_params(struct snd_pcm_substream *substream,
646 struct snd_pcm_hw_params *params,
647 struct snd_soc_dai *dai)
649 struct snd_soc_component *component = dai->component;
650 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
651 int i, mcs = -EINVAL, ir = -EINVAL;
652 unsigned int confa, confb;
653 unsigned int rate, ratio;
657 dev_err(component->dev,
658 "sta32x->mclk is unset. Unable to determine ratio\n");
662 rate = params_rate(params);
663 ratio = sta32x->mclk / rate;
664 dev_dbg(component->dev, "rate: %u, ratio: %u\n", rate, ratio);
666 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
667 if (interpolation_ratios[i].fs == rate) {
668 ir = interpolation_ratios[i].ir;
674 dev_err(component->dev, "Unsupported samplerate: %u\n", rate);
678 for (i = 0; i < 6; i++) {
679 if (mcs_ratio_table[ir][i] == ratio) {
686 dev_err(component->dev, "Unresolvable ratio: %u\n", ratio);
690 confa = (ir << STA32X_CONFA_IR_SHIFT) |
691 (mcs << STA32X_CONFA_MCS_SHIFT);
694 switch (params_width(params)) {
696 dev_dbg(component->dev, "24bit\n");
699 dev_dbg(component->dev, "24bit or 32bit\n");
700 switch (sta32x->format) {
701 case SND_SOC_DAIFMT_I2S:
704 case SND_SOC_DAIFMT_LEFT_J:
707 case SND_SOC_DAIFMT_RIGHT_J:
714 dev_dbg(component->dev, "20bit\n");
715 switch (sta32x->format) {
716 case SND_SOC_DAIFMT_I2S:
719 case SND_SOC_DAIFMT_LEFT_J:
722 case SND_SOC_DAIFMT_RIGHT_J:
729 dev_dbg(component->dev, "18bit\n");
730 switch (sta32x->format) {
731 case SND_SOC_DAIFMT_I2S:
734 case SND_SOC_DAIFMT_LEFT_J:
737 case SND_SOC_DAIFMT_RIGHT_J:
744 dev_dbg(component->dev, "16bit\n");
745 switch (sta32x->format) {
746 case SND_SOC_DAIFMT_I2S:
749 case SND_SOC_DAIFMT_LEFT_J:
752 case SND_SOC_DAIFMT_RIGHT_J:
762 ret = regmap_update_bits(sta32x->regmap, STA32X_CONFA,
763 STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK,
768 ret = regmap_update_bits(sta32x->regmap, STA32X_CONFB,
769 STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB,
777 static int sta32x_startup_sequence(struct sta32x_priv *sta32x)
779 if (sta32x->gpiod_nreset) {
780 gpiod_set_value(sta32x->gpiod_nreset, 0);
782 gpiod_set_value(sta32x->gpiod_nreset, 1);
790 * sta32x_set_bias_level - DAPM callback
791 * @component: the component device
792 * @level: DAPM power level
794 * This is called by ALSA to put the component into low power mode
795 * or to wake it up. If the component is powered off completely
796 * all registers must be restored after power on.
798 static int sta32x_set_bias_level(struct snd_soc_component *component,
799 enum snd_soc_bias_level level)
802 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
804 dev_dbg(component->dev, "level = %d\n", level);
806 case SND_SOC_BIAS_ON:
809 case SND_SOC_BIAS_PREPARE:
811 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
812 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
813 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
816 case SND_SOC_BIAS_STANDBY:
817 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
818 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
821 dev_err(component->dev,
822 "Failed to enable supplies: %d\n", ret);
826 sta32x_startup_sequence(sta32x);
827 sta32x_cache_sync(component);
828 sta32x_watchdog_start(sta32x);
832 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
833 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
838 case SND_SOC_BIAS_OFF:
839 /* The chip runs through the power down sequence for us. */
840 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
841 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 0);
843 sta32x_watchdog_stop(sta32x);
845 gpiod_set_value(sta32x->gpiod_nreset, 0);
847 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies),
854 static const struct snd_soc_dai_ops sta32x_dai_ops = {
855 .hw_params = sta32x_hw_params,
856 .set_sysclk = sta32x_set_dai_sysclk,
857 .set_fmt = sta32x_set_dai_fmt,
860 static struct snd_soc_dai_driver sta32x_dai = {
861 .name = "sta32x-hifi",
863 .stream_name = "Playback",
866 .rates = STA32X_RATES,
867 .formats = STA32X_FORMATS,
869 .ops = &sta32x_dai_ops,
872 static int sta32x_probe(struct snd_soc_component *component)
874 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
875 struct sta32x_platform_data *pdata = sta32x->pdata;
876 int i, ret = 0, thermal = 0;
878 sta32x->component = component;
880 if (sta32x->xti_clk) {
881 ret = clk_prepare_enable(sta32x->xti_clk);
883 dev_err(component->dev,
884 "Failed to enable clock: %d\n", ret);
889 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
892 dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
893 goto err_clk_disable_unprepare;
896 ret = sta32x_startup_sequence(sta32x);
898 dev_err(component->dev, "Failed to startup device\n");
899 goto err_regulator_bulk_disable;
903 if (!pdata->thermal_warning_recovery)
904 thermal |= STA32X_CONFA_TWAB;
905 if (!pdata->thermal_warning_adjustment)
906 thermal |= STA32X_CONFA_TWRB;
907 if (!pdata->fault_detect_recovery)
908 thermal |= STA32X_CONFA_FDRB;
909 regmap_update_bits(sta32x->regmap, STA32X_CONFA,
910 STA32X_CONFA_TWAB | STA32X_CONFA_TWRB |
915 regmap_update_bits(sta32x->regmap, STA32X_CONFC,
916 STA32X_CONFC_CSZ_MASK,
917 pdata->drop_compensation_ns
918 << STA32X_CONFC_CSZ_SHIFT);
921 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
923 pdata->max_power_use_mpcc ?
924 STA32X_CONFE_MPCV : 0);
925 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
927 pdata->max_power_correction ?
928 STA32X_CONFE_MPC : 0);
929 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
931 pdata->am_reduction_mode ?
932 STA32X_CONFE_AME : 0);
933 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
935 pdata->odd_pwm_speed_mode ?
936 STA32X_CONFE_PWMS : 0);
939 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
941 pdata->invalid_input_detect_mute ?
942 STA32X_CONFF_IDE : 0);
944 /* select output configuration */
945 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
946 STA32X_CONFF_OCFG_MASK,
948 << STA32X_CONFF_OCFG_SHIFT);
950 /* channel to output mapping */
951 regmap_update_bits(sta32x->regmap, STA32X_C1CFG,
952 STA32X_CxCFG_OM_MASK,
953 pdata->ch1_output_mapping
954 << STA32X_CxCFG_OM_SHIFT);
955 regmap_update_bits(sta32x->regmap, STA32X_C2CFG,
956 STA32X_CxCFG_OM_MASK,
957 pdata->ch2_output_mapping
958 << STA32X_CxCFG_OM_SHIFT);
959 regmap_update_bits(sta32x->regmap, STA32X_C3CFG,
960 STA32X_CxCFG_OM_MASK,
961 pdata->ch3_output_mapping
962 << STA32X_CxCFG_OM_SHIFT);
964 /* initialize coefficient shadow RAM with reset values */
965 for (i = 4; i <= 49; i += 5)
966 sta32x->coef_shadow[i] = 0x400000;
967 for (i = 50; i <= 54; i++)
968 sta32x->coef_shadow[i] = 0x7fffff;
969 sta32x->coef_shadow[55] = 0x5a9df7;
970 sta32x->coef_shadow[56] = 0x7fffff;
971 sta32x->coef_shadow[59] = 0x7fffff;
972 sta32x->coef_shadow[60] = 0x400000;
973 sta32x->coef_shadow[61] = 0x400000;
975 if (sta32x->pdata->needs_esd_watchdog)
976 INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog);
978 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
979 /* Bias level configuration will have done an extra enable */
980 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
984 err_regulator_bulk_disable:
985 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
986 err_clk_disable_unprepare:
988 clk_disable_unprepare(sta32x->xti_clk);
992 static void sta32x_remove(struct snd_soc_component *component)
994 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
996 sta32x_watchdog_stop(sta32x);
997 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
1000 clk_disable_unprepare(sta32x->xti_clk);
1003 static const struct snd_soc_component_driver sta32x_component = {
1004 .probe = sta32x_probe,
1005 .remove = sta32x_remove,
1006 .set_bias_level = sta32x_set_bias_level,
1007 .controls = sta32x_snd_controls,
1008 .num_controls = ARRAY_SIZE(sta32x_snd_controls),
1009 .dapm_widgets = sta32x_dapm_widgets,
1010 .num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets),
1011 .dapm_routes = sta32x_dapm_routes,
1012 .num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes),
1013 .suspend_bias_off = 1,
1015 .use_pmdown_time = 1,
1017 .non_legacy_dai_naming = 1,
1020 static const struct regmap_config sta32x_regmap = {
1023 .max_register = STA32X_FDRC2,
1024 .reg_defaults = sta32x_regs,
1025 .num_reg_defaults = ARRAY_SIZE(sta32x_regs),
1026 .cache_type = REGCACHE_RBTREE,
1027 .wr_table = &sta32x_write_regs,
1028 .rd_table = &sta32x_read_regs,
1029 .volatile_table = &sta32x_volatile_regs,
1033 static const struct of_device_id st32x_dt_ids[] = {
1034 { .compatible = "st,sta32x", },
1037 MODULE_DEVICE_TABLE(of, st32x_dt_ids);
1039 static int sta32x_probe_dt(struct device *dev, struct sta32x_priv *sta32x)
1041 struct device_node *np = dev->of_node;
1042 struct sta32x_platform_data *pdata;
1045 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1049 of_property_read_u8(np, "st,output-conf",
1050 &pdata->output_conf);
1051 of_property_read_u8(np, "st,ch1-output-mapping",
1052 &pdata->ch1_output_mapping);
1053 of_property_read_u8(np, "st,ch2-output-mapping",
1054 &pdata->ch2_output_mapping);
1055 of_property_read_u8(np, "st,ch3-output-mapping",
1056 &pdata->ch3_output_mapping);
1058 if (of_get_property(np, "st,fault-detect-recovery", NULL))
1059 pdata->fault_detect_recovery = 1;
1060 if (of_get_property(np, "st,thermal-warning-recovery", NULL))
1061 pdata->thermal_warning_recovery = 1;
1062 if (of_get_property(np, "st,thermal-warning-adjustment", NULL))
1063 pdata->thermal_warning_adjustment = 1;
1064 if (of_get_property(np, "st,needs_esd_watchdog", NULL))
1065 pdata->needs_esd_watchdog = 1;
1068 of_property_read_u16(np, "st,drop-compensation-ns", &tmp);
1069 pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20;
1072 if (of_get_property(np, "st,max-power-use-mpcc", NULL))
1073 pdata->max_power_use_mpcc = 1;
1075 if (of_get_property(np, "st,max-power-correction", NULL))
1076 pdata->max_power_correction = 1;
1078 if (of_get_property(np, "st,am-reduction-mode", NULL))
1079 pdata->am_reduction_mode = 1;
1081 if (of_get_property(np, "st,odd-pwm-speed-mode", NULL))
1082 pdata->odd_pwm_speed_mode = 1;
1085 if (of_get_property(np, "st,invalid-input-detect-mute", NULL))
1086 pdata->invalid_input_detect_mute = 1;
1088 sta32x->pdata = pdata;
1094 static int sta32x_i2c_probe(struct i2c_client *i2c)
1096 struct device *dev = &i2c->dev;
1097 struct sta32x_priv *sta32x;
1100 sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv),
1105 mutex_init(&sta32x->coeff_lock);
1106 sta32x->pdata = dev_get_platdata(dev);
1110 ret = sta32x_probe_dt(dev, sta32x);
1117 sta32x->xti_clk = devm_clk_get(dev, "xti");
1118 if (IS_ERR(sta32x->xti_clk)) {
1119 ret = PTR_ERR(sta32x->xti_clk);
1121 if (ret == -EPROBE_DEFER)
1124 sta32x->xti_clk = NULL;
1128 sta32x->gpiod_nreset = devm_gpiod_get_optional(dev, "reset",
1130 if (IS_ERR(sta32x->gpiod_nreset))
1131 return PTR_ERR(sta32x->gpiod_nreset);
1134 for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
1135 sta32x->supplies[i].supply = sta32x_supply_names[i];
1137 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(sta32x->supplies),
1140 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1144 sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap);
1145 if (IS_ERR(sta32x->regmap)) {
1146 ret = PTR_ERR(sta32x->regmap);
1147 dev_err(dev, "Failed to init regmap: %d\n", ret);
1151 i2c_set_clientdata(i2c, sta32x);
1153 ret = devm_snd_soc_register_component(dev, &sta32x_component,
1156 dev_err(dev, "Failed to register component (%d)\n", ret);
1161 static const struct i2c_device_id sta32x_i2c_id[] = {
1167 MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id);
1169 static struct i2c_driver sta32x_i2c_driver = {
1172 .of_match_table = of_match_ptr(st32x_dt_ids),
1174 .probe_new = sta32x_i2c_probe,
1175 .id_table = sta32x_i2c_id,
1178 module_i2c_driver(sta32x_i2c_driver);
1180 MODULE_DESCRIPTION("ASoC STA32X driver");
1181 MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>");
1182 MODULE_LICENSE("GPL");