1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682s.c -- RT5682I-VS ALSA SoC audio component driver
5 // Copyright 2021 Realtek Semiconductor Corp.
6 // Author: Derek Fang <derek.fang@realtek.com>
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/i2c.h>
16 #include <linux/platform_device.h>
17 #include <linux/spi/spi.h>
18 #include <linux/acpi.h>
19 #include <linux/gpio.h>
20 #include <linux/of_gpio.h>
21 #include <linux/mutex.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/jack.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 #include <sound/rt5682s.h>
34 #define DEVICE_ID 0x6749
36 static const struct rt5682s_platform_data i2s_default_platform_data = {
37 .dmic1_data_pin = RT5682S_DMIC1_DATA_GPIO2,
38 .dmic1_clk_pin = RT5682S_DMIC1_CLK_GPIO3,
39 .jd_src = RT5682S_JD1,
40 .dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
41 .dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk",
44 static const char *rt5682s_supply_names[RT5682S_NUM_SUPPLIES] = {
49 static const struct reg_sequence patch_list[] = {
50 {RT5682S_I2C_CTRL, 0x0007},
51 {RT5682S_DIG_IN_CTRL_1, 0x0000},
52 {RT5682S_CHOP_DAC_2, 0x2020},
53 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101},
54 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0},
55 {RT5682S_HP_CALIB_CTRL_9, 0x0002},
56 {RT5682S_DEPOP_1, 0x0000},
57 {RT5682S_HP_CHARGE_PUMP_2, 0x3c15},
58 {RT5682S_DAC1_DIG_VOL, 0xfefe},
59 {RT5682S_SAR_IL_CMD_2, 0xac00},
60 {RT5682S_SAR_IL_CMD_3, 0x024c},
61 {RT5682S_CBJ_CTRL_6, 0x0804},
64 static void rt5682s_apply_patch_list(struct rt5682s_priv *rt5682s,
69 ret = regmap_multi_reg_write(rt5682s->regmap, patch_list, ARRAY_SIZE(patch_list));
71 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
74 static const struct reg_default rt5682s_reg[] = {
440 static bool rt5682s_volatile_register(struct device *dev, unsigned int reg)
444 case RT5682S_CBJ_CTRL_2:
445 case RT5682S_I2S1_F_DIV_CTRL_2:
446 case RT5682S_I2S2_F_DIV_CTRL_2:
447 case RT5682S_INT_ST_1:
448 case RT5682S_GPIO_ST:
449 case RT5682S_IL_CMD_1:
450 case RT5682S_4BTN_IL_CMD_1:
451 case RT5682S_AJD1_CTRL:
452 case RT5682S_VERSION_ID...RT5682S_DEVICE_ID:
453 case RT5682S_STO_NG2_CTRL_1:
454 case RT5682S_STO_NG2_CTRL_5...RT5682S_STO_NG2_CTRL_7:
455 case RT5682S_STO1_DAC_SIL_DET:
456 case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_4:
457 case RT5682S_HP_IMP_SENS_CTRL_13:
458 case RT5682S_HP_IMP_SENS_CTRL_14:
459 case RT5682S_HP_IMP_SENS_CTRL_43...RT5682S_HP_IMP_SENS_CTRL_46:
460 case RT5682S_HP_CALIB_CTRL_1:
461 case RT5682S_HP_CALIB_CTRL_10:
462 case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
463 case RT5682S_SAR_IL_CMD_2...RT5682S_SAR_IL_CMD_5:
464 case RT5682S_SAR_IL_CMD_10:
465 case RT5682S_SAR_IL_CMD_11:
466 case RT5682S_VERSION_ID_HIDE:
467 case RT5682S_VERSION_ID_CUS:
468 case RT5682S_I2C_TRANS_CTRL:
469 case RT5682S_DMIC_FLOAT_DET:
470 case RT5682S_HA_CMP_OP_1:
471 case RT5682S_NEW_CBJ_DET_CTL_10...RT5682S_NEW_CBJ_DET_CTL_16:
472 case RT5682S_CLK_SW_TEST_1:
473 case RT5682S_CLK_SW_TEST_2:
474 case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
475 case RT5682S_PILOT_DIG_CTL_1:
482 static bool rt5682s_readable_register(struct device *dev, unsigned int reg)
486 case RT5682S_VERSION_ID:
487 case RT5682S_VENDOR_ID:
488 case RT5682S_DEVICE_ID:
489 case RT5682S_HP_CTRL_1:
490 case RT5682S_HP_CTRL_2:
491 case RT5682S_HPL_GAIN:
492 case RT5682S_HPR_GAIN:
493 case RT5682S_I2C_CTRL:
494 case RT5682S_CBJ_BST_CTRL:
495 case RT5682S_CBJ_DET_CTRL:
496 case RT5682S_CBJ_CTRL_1...RT5682S_CBJ_CTRL_8:
497 case RT5682S_DAC1_DIG_VOL:
498 case RT5682S_STO1_ADC_DIG_VOL:
499 case RT5682S_STO1_ADC_BOOST:
500 case RT5682S_HP_IMP_GAIN_1:
501 case RT5682S_HP_IMP_GAIN_2:
502 case RT5682S_SIDETONE_CTRL:
503 case RT5682S_STO1_ADC_MIXER:
504 case RT5682S_AD_DA_MIXER:
505 case RT5682S_STO1_DAC_MIXER:
506 case RT5682S_A_DAC1_MUX:
507 case RT5682S_DIG_INF2_DATA:
508 case RT5682S_REC_MIXER:
509 case RT5682S_CAL_REC:
510 case RT5682S_HP_ANA_OST_CTRL_1...RT5682S_HP_ANA_OST_CTRL_3:
511 case RT5682S_PWR_DIG_1...RT5682S_PWR_MIXER:
512 case RT5682S_MB_CTRL:
513 case RT5682S_CLK_GATE_TCON_1...RT5682S_CLK_GATE_TCON_3:
514 case RT5682S_CLK_DET...RT5682S_LPF_AD_DMIC:
515 case RT5682S_I2S1_SDP:
516 case RT5682S_I2S2_SDP:
517 case RT5682S_ADDA_CLK_1:
518 case RT5682S_ADDA_CLK_2:
519 case RT5682S_I2S1_F_DIV_CTRL_1:
520 case RT5682S_I2S1_F_DIV_CTRL_2:
521 case RT5682S_TDM_CTRL:
522 case RT5682S_TDM_ADDA_CTRL_1:
523 case RT5682S_TDM_ADDA_CTRL_2:
524 case RT5682S_DATA_SEL_CTRL_1:
525 case RT5682S_TDM_TCON_CTRL_1:
526 case RT5682S_TDM_TCON_CTRL_2:
527 case RT5682S_GLB_CLK:
528 case RT5682S_PLL_TRACK_1...RT5682S_PLL_TRACK_6:
529 case RT5682S_PLL_TRACK_11:
530 case RT5682S_DEPOP_1:
531 case RT5682S_HP_CHARGE_PUMP_1:
532 case RT5682S_HP_CHARGE_PUMP_2:
533 case RT5682S_HP_CHARGE_PUMP_3:
534 case RT5682S_MICBIAS_1...RT5682S_MICBIAS_3:
535 case RT5682S_PLL_TRACK_12...RT5682S_PLL_CTRL_7:
536 case RT5682S_RC_CLK_CTRL:
537 case RT5682S_I2S2_M_CLK_CTRL_1:
538 case RT5682S_I2S2_F_DIV_CTRL_1:
539 case RT5682S_I2S2_F_DIV_CTRL_2:
540 case RT5682S_IRQ_CTRL_1...RT5682S_IRQ_CTRL_4:
541 case RT5682S_INT_ST_1:
542 case RT5682S_GPIO_CTRL_1:
543 case RT5682S_GPIO_CTRL_2:
544 case RT5682S_GPIO_ST:
545 case RT5682S_HP_AMP_DET_CTRL_1:
546 case RT5682S_MID_HP_AMP_DET:
547 case RT5682S_LOW_HP_AMP_DET:
548 case RT5682S_DELAY_BUF_CTRL:
549 case RT5682S_SV_ZCD_1:
550 case RT5682S_SV_ZCD_2:
551 case RT5682S_IL_CMD_1...RT5682S_IL_CMD_6:
552 case RT5682S_4BTN_IL_CMD_1...RT5682S_4BTN_IL_CMD_7:
553 case RT5682S_ADC_STO1_HP_CTRL_1:
554 case RT5682S_ADC_STO1_HP_CTRL_2:
555 case RT5682S_AJD1_CTRL:
556 case RT5682S_JD_CTRL_1:
557 case RT5682S_DUMMY_1...RT5682S_DUMMY_3:
558 case RT5682S_DAC_ADC_DIG_VOL1:
559 case RT5682S_BIAS_CUR_CTRL_2...RT5682S_BIAS_CUR_CTRL_10:
560 case RT5682S_VREF_REC_OP_FB_CAP_CTRL_1:
561 case RT5682S_VREF_REC_OP_FB_CAP_CTRL_2:
562 case RT5682S_CHARGE_PUMP_1:
563 case RT5682S_DIG_IN_CTRL_1:
564 case RT5682S_PAD_DRIVING_CTRL:
565 case RT5682S_CHOP_DAC_1:
566 case RT5682S_CHOP_DAC_2:
567 case RT5682S_CHOP_ADC:
568 case RT5682S_CALIB_ADC_CTRL:
569 case RT5682S_VOL_TEST:
570 case RT5682S_SPKVDD_DET_ST:
571 case RT5682S_TEST_MODE_CTRL_1...RT5682S_TEST_MODE_CTRL_4:
572 case RT5682S_PLL_INTERNAL_1...RT5682S_PLL_INTERNAL_4:
573 case RT5682S_STO_NG2_CTRL_1...RT5682S_STO_NG2_CTRL_10:
574 case RT5682S_STO1_DAC_SIL_DET:
575 case RT5682S_SIL_PSV_CTRL1:
576 case RT5682S_SIL_PSV_CTRL2:
577 case RT5682S_SIL_PSV_CTRL3:
578 case RT5682S_SIL_PSV_CTRL4:
579 case RT5682S_SIL_PSV_CTRL5:
580 case RT5682S_HP_IMP_SENS_CTRL_1...RT5682S_HP_IMP_SENS_CTRL_46:
581 case RT5682S_HP_LOGIC_CTRL_1...RT5682S_HP_LOGIC_CTRL_3:
582 case RT5682S_HP_CALIB_CTRL_1...RT5682S_HP_CALIB_CTRL_11:
583 case RT5682S_HP_CALIB_ST_1...RT5682S_HP_CALIB_ST_11:
584 case RT5682S_SAR_IL_CMD_1...RT5682S_SAR_IL_CMD_14:
585 case RT5682S_DUMMY_4...RT5682S_DUMMY_6:
586 case RT5682S_VERSION_ID_HIDE:
587 case RT5682S_VERSION_ID_CUS:
588 case RT5682S_SCAN_CTL:
589 case RT5682S_HP_AMP_DET:
590 case RT5682S_BIAS_CUR_CTRL_11:
591 case RT5682S_BIAS_CUR_CTRL_12:
592 case RT5682S_BIAS_CUR_CTRL_13:
593 case RT5682S_BIAS_CUR_CTRL_14:
594 case RT5682S_BIAS_CUR_CTRL_15:
595 case RT5682S_BIAS_CUR_CTRL_16:
596 case RT5682S_BIAS_CUR_CTRL_17:
597 case RT5682S_BIAS_CUR_CTRL_18:
598 case RT5682S_I2C_TRANS_CTRL:
599 case RT5682S_DUMMY_7:
600 case RT5682S_DUMMY_8:
601 case RT5682S_DMIC_FLOAT_DET:
602 case RT5682S_HA_CMP_OP_1...RT5682S_HA_CMP_OP_13:
603 case RT5682S_HA_CMP_OP_14...RT5682S_HA_CMP_OP_25:
604 case RT5682S_NEW_CBJ_DET_CTL_1...RT5682S_NEW_CBJ_DET_CTL_16:
605 case RT5682S_DA_FILTER_1...RT5682S_DA_FILTER_5:
606 case RT5682S_CLK_SW_TEST_1:
607 case RT5682S_CLK_SW_TEST_2:
608 case RT5682S_CLK_SW_TEST_3...RT5682S_CLK_SW_TEST_14:
609 case RT5682S_EFUSE_MANU_WRITE_1...RT5682S_EFUSE_MANU_WRITE_6:
610 case RT5682S_EFUSE_READ_1...RT5682S_EFUSE_READ_18:
611 case RT5682S_EFUSE_TIMING_CTL_1:
612 case RT5682S_EFUSE_TIMING_CTL_2:
613 case RT5682S_PILOT_DIG_CTL_1:
614 case RT5682S_PILOT_DIG_CTL_2:
615 case RT5682S_HP_AMP_DET_CTL_1...RT5682S_HP_AMP_DET_CTL_4:
622 static void rt5682s_reset(struct rt5682s_priv *rt5682s)
624 regmap_write(rt5682s->regmap, RT5682S_RESET, 0);
627 static int rt5682s_button_detect(struct snd_soc_component *component)
631 val = snd_soc_component_read(component, RT5682S_4BTN_IL_CMD_1);
632 btn_type = val & 0xfff0;
633 snd_soc_component_write(component, RT5682S_4BTN_IL_CMD_1, val);
634 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
635 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
636 RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
647 static void rt5682s_sar_power_mode(struct snd_soc_component *component, int mode)
649 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
651 mutex_lock(&rt5682s->sar_mutex);
655 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
656 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
657 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
658 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
659 RT5682S_CTRL_MB1_REG | RT5682S_CTRL_MB2_REG);
660 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
661 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
662 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
663 RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
664 usleep_range(5000, 5500);
665 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
666 RT5682S_SAR_BUTDET_MASK, RT5682S_SAR_BUTDET_EN);
667 usleep_range(5000, 5500);
668 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_2,
669 RT5682S_SAR_ADC_PSV_MASK, RT5682S_SAR_ADC_PSV_ENTRY);
672 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
673 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
674 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
675 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
676 RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
677 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
678 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_SEL_MB1_2_AUTO);
679 usleep_range(5000, 5500);
680 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
681 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK,
682 RT5682S_SAR_BUTDET_EN | RT5682S_SAR_BUTDET_POW_NORM);
685 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
686 RT5682S_MB1_PATH_MASK | RT5682S_MB2_PATH_MASK,
687 RT5682S_CTRL_MB1_FSM | RT5682S_CTRL_MB2_FSM);
688 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
689 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
690 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
691 RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
694 dev_err(component->dev, "Invalid SAR Power mode: %d\n", mode);
698 mutex_unlock(&rt5682s->sar_mutex);
701 static void rt5682s_enable_push_button_irq(struct snd_soc_component *component)
703 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
704 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_BTN);
705 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
706 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
707 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_EN |
708 RT5682S_SAR_BUTDET_POW_NORM | RT5682S_SAR_SEL_MB1_2_AUTO);
709 snd_soc_component_write(component, RT5682S_IL_CMD_1, 0x0040);
710 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
711 RT5682S_4BTN_IL_MASK | RT5682S_4BTN_IL_RST_MASK,
712 RT5682S_4BTN_IL_EN | RT5682S_4BTN_IL_NOR);
713 snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
714 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_EN);
717 static void rt5682s_disable_push_button_irq(struct snd_soc_component *component)
719 snd_soc_component_update_bits(component, RT5682S_IRQ_CTRL_3,
720 RT5682S_IL_IRQ_MASK, RT5682S_IL_IRQ_DIS);
721 snd_soc_component_update_bits(component, RT5682S_4BTN_IL_CMD_2,
722 RT5682S_4BTN_IL_MASK, RT5682S_4BTN_IL_DIS);
723 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
724 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
725 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
726 RT5682S_SAR_BUTDET_MASK | RT5682S_SAR_BUTDET_POW_MASK |
727 RT5682S_SAR_SEL_MB1_2_CTL_MASK, RT5682S_SAR_BUTDET_DIS |
728 RT5682S_SAR_BUTDET_POW_SAV | RT5682S_SAR_SEL_MB1_2_MANU);
732 * rt5682s_headset_detect - Detect headset.
733 * @component: SoC audio component device.
734 * @jack_insert: Jack insert or not.
736 * Detect whether is headset or not when jack inserted.
738 * Returns detect status.
740 static int rt5682s_headset_detect(struct snd_soc_component *component, int jack_insert)
742 unsigned int val, count;
746 rt5682s_disable_push_button_irq(component);
747 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
748 RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
749 RT5682S_PWR_VREF1 | RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
750 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
751 RT5682S_PWR_FV1 | RT5682S_PWR_FV2, 0);
752 usleep_range(15000, 20000);
753 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
754 RT5682S_PWR_FV1 | RT5682S_PWR_FV2,
755 RT5682S_PWR_FV1 | RT5682S_PWR_FV2);
756 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
757 RT5682S_PWR_CBJ, RT5682S_PWR_CBJ);
758 snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x0365);
759 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
760 RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
761 RT5682S_OSW_L_DIS | RT5682S_OSW_R_DIS);
762 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_13,
763 RT5682S_SAR_SOUR_MASK, RT5682S_SAR_SOUR_TYPE);
764 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
765 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_EN);
766 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
767 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
768 usleep_range(45000, 50000);
769 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
770 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_HIGH);
774 usleep_range(10000, 15000);
775 val = snd_soc_component_read(component, RT5682S_CBJ_CTRL_2)
776 & RT5682S_JACK_TYPE_MASK;
778 } while (val == 0 && count < 50);
780 dev_dbg(component->dev, "%s, val=%d, count=%d\n", __func__, val, count);
785 jack_type = SND_JACK_HEADSET;
786 snd_soc_component_write(component, RT5682S_SAR_IL_CMD_3, 0x024c);
787 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
788 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_EN);
789 snd_soc_component_update_bits(component, RT5682S_SAR_IL_CMD_1,
790 RT5682S_SAR_SEL_MB1_2_MASK, val << RT5682S_SAR_SEL_MB1_2_SFT);
791 rt5682s_enable_push_button_irq(component);
792 rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
795 jack_type = SND_JACK_HEADPHONE;
798 snd_soc_component_update_bits(component, RT5682S_HP_CHARGE_PUMP_2,
799 RT5682S_OSW_L_MASK | RT5682S_OSW_R_MASK,
800 RT5682S_OSW_L_EN | RT5682S_OSW_R_EN);
801 usleep_range(35000, 40000);
803 rt5682s_sar_power_mode(component, SAR_PWR_OFF);
804 rt5682s_disable_push_button_irq(component);
805 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
806 RT5682S_TRIG_JD_MASK, RT5682S_TRIG_JD_LOW);
808 if (!snd_soc_dapm_get_pin_status(&component->dapm, "MICBIAS"))
809 snd_soc_component_update_bits(component,
810 RT5682S_PWR_ANLG_1, RT5682S_PWR_MB, 0);
811 if (!snd_soc_dapm_get_pin_status(&component->dapm, "Vref2"))
812 snd_soc_component_update_bits(component,
813 RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2, 0);
815 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_3,
817 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_1,
818 RT5682S_FAST_OFF_MASK, RT5682S_FAST_OFF_DIS);
819 snd_soc_component_update_bits(component, RT5682S_CBJ_CTRL_3,
820 RT5682S_CBJ_IN_BUF_MASK, RT5682S_CBJ_IN_BUF_DIS);
824 dev_dbg(component->dev, "jack_type = %d\n", jack_type);
829 static void rt5682s_jack_detect_handler(struct work_struct *work)
831 struct rt5682s_priv *rt5682s =
832 container_of(work, struct rt5682s_priv, jack_detect_work.work);
833 struct snd_soc_dapm_context *dapm;
836 if (!rt5682s->component || !rt5682s->component->card ||
837 !rt5682s->component->card->instantiated) {
838 /* card not yet ready, try later */
839 mod_delayed_work(system_power_efficient_wq,
840 &rt5682s->jack_detect_work, msecs_to_jiffies(15));
844 dapm = snd_soc_component_get_dapm(rt5682s->component);
846 snd_soc_dapm_mutex_lock(dapm);
847 mutex_lock(&rt5682s->calibrate_mutex);
849 val = snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL)
850 & RT5682S_JDH_RS_MASK;
853 if (rt5682s->jack_type == 0) {
854 /* jack was out, report jack type */
855 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 1);
856 rt5682s->irq_work_delay_time = 0;
857 } else if ((rt5682s->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
858 /* jack is already in, report button event */
859 rt5682s->jack_type = SND_JACK_HEADSET;
860 btn_type = rt5682s_button_detect(rt5682s->component);
862 * rt5682s can report three kinds of button behavior,
863 * one click, double click and hold. However,
864 * currently we will report button pressed/released
865 * event. So all the three button behaviors are
866 * treated as button pressed.
872 rt5682s->jack_type |= SND_JACK_BTN_0;
877 rt5682s->jack_type |= SND_JACK_BTN_1;
882 rt5682s->jack_type |= SND_JACK_BTN_2;
887 rt5682s->jack_type |= SND_JACK_BTN_3;
889 case 0x0000: /* unpressed */
892 dev_err(rt5682s->component->dev,
893 "Unexpected button code 0x%04x\n", btn_type);
899 rt5682s->jack_type = rt5682s_headset_detect(rt5682s->component, 0);
900 rt5682s->irq_work_delay_time = 50;
903 mutex_unlock(&rt5682s->calibrate_mutex);
904 snd_soc_dapm_mutex_unlock(dapm);
906 snd_soc_jack_report(rt5682s->hs_jack, rt5682s->jack_type,
907 SND_JACK_HEADSET | SND_JACK_BTN_0 | SND_JACK_BTN_1 |
908 SND_JACK_BTN_2 | SND_JACK_BTN_3);
910 if (rt5682s->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
911 SND_JACK_BTN_2 | SND_JACK_BTN_3))
912 schedule_delayed_work(&rt5682s->jd_check_work, 0);
914 cancel_delayed_work_sync(&rt5682s->jd_check_work);
917 static void rt5682s_jd_check_handler(struct work_struct *work)
919 struct rt5682s_priv *rt5682s =
920 container_of(work, struct rt5682s_priv, jd_check_work.work);
922 if (snd_soc_component_read(rt5682s->component, RT5682S_AJD1_CTRL) & RT5682S_JDH_RS_MASK) {
924 schedule_delayed_work(&rt5682s->jack_detect_work, 0);
926 schedule_delayed_work(&rt5682s->jd_check_work, 500);
930 static irqreturn_t rt5682s_irq(int irq, void *data)
932 struct rt5682s_priv *rt5682s = data;
934 mod_delayed_work(system_power_efficient_wq, &rt5682s->jack_detect_work,
935 msecs_to_jiffies(rt5682s->irq_work_delay_time));
940 static int rt5682s_set_jack_detect(struct snd_soc_component *component,
941 struct snd_soc_jack *hs_jack, void *data)
943 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
944 int btndet_delay = 16;
946 rt5682s->hs_jack = hs_jack;
949 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
950 RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
951 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
953 cancel_delayed_work_sync(&rt5682s->jack_detect_work);
958 switch (rt5682s->pdata.jd_src) {
960 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_5,
961 RT5682S_JD_FAST_OFF_SRC_MASK, RT5682S_JD_FAST_OFF_SRC_JDH);
962 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_2,
963 RT5682S_EXT_JD_SRC, RT5682S_EXT_JD_SRC_MANUAL);
964 regmap_update_bits(rt5682s->regmap, RT5682S_CBJ_CTRL_1,
965 RT5682S_EMB_JD_MASK | RT5682S_DET_TYPE |
966 RT5682S_POL_FAST_OFF_MASK | RT5682S_MIC_CAP_MASK,
967 RT5682S_EMB_JD_EN | RT5682S_DET_TYPE |
968 RT5682S_POL_FAST_OFF_HIGH | RT5682S_MIC_CAP_HS);
969 regmap_update_bits(rt5682s->regmap, RT5682S_SAR_IL_CMD_1,
970 RT5682S_SAR_POW_MASK, RT5682S_SAR_POW_EN);
971 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
972 RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_IRQ);
973 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_3,
974 RT5682S_PWR_BGLDO, RT5682S_PWR_BGLDO);
975 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_2,
976 RT5682S_PWR_JD_MASK, RT5682S_PWR_JD_ENABLE);
977 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
978 RT5682S_POW_IRQ | RT5682S_POW_JDH, RT5682S_POW_IRQ | RT5682S_POW_JDH);
979 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
980 RT5682S_JD1_EN_MASK | RT5682S_JD1_POL_MASK,
981 RT5682S_JD1_EN | RT5682S_JD1_POL_NOR);
982 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_4,
983 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
984 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
985 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_5,
986 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
987 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
988 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_6,
989 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
990 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
991 regmap_update_bits(rt5682s->regmap, RT5682S_4BTN_IL_CMD_7,
992 RT5682S_4BTN_IL_HOLD_WIN_MASK | RT5682S_4BTN_IL_CLICK_WIN_MASK,
993 (btndet_delay << RT5682S_4BTN_IL_HOLD_WIN_SFT | btndet_delay));
995 mod_delayed_work(system_power_efficient_wq,
996 &rt5682s->jack_detect_work, msecs_to_jiffies(250));
999 case RT5682S_JD_NULL:
1000 regmap_update_bits(rt5682s->regmap, RT5682S_IRQ_CTRL_2,
1001 RT5682S_JD1_EN_MASK, RT5682S_JD1_DIS);
1002 regmap_update_bits(rt5682s->regmap, RT5682S_RC_CLK_CTRL,
1003 RT5682S_POW_JDH, 0);
1007 dev_warn(component->dev, "Wrong JD source\n");
1014 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9562, 75, 0);
1015 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1016 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
1017 static const DECLARE_TLV_DB_SCALE(cbj_bst_tlv, -1200, 150, 0);
1019 static const struct snd_kcontrol_new rt5682s_snd_controls[] = {
1020 /* DAC Digital Volume */
1021 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682S_DAC1_DIG_VOL,
1022 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 127, 0, dac_vol_tlv),
1024 /* CBJ Boost Volume */
1025 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682S_REC_MIXER,
1026 RT5682S_BST_CBJ_SFT, 35, 0, cbj_bst_tlv),
1028 /* ADC Digital Volume Control */
1029 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682S_STO1_ADC_DIG_VOL,
1030 RT5682S_L_MUTE_SFT, RT5682S_R_MUTE_SFT, 1, 1),
1031 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682S_STO1_ADC_DIG_VOL,
1032 RT5682S_L_VOL_SFT + 1, RT5682S_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1034 /* ADC Boost Volume Control */
1035 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682S_STO1_ADC_BOOST,
1036 RT5682S_STO1_ADC_L_BST_SFT, RT5682S_STO1_ADC_R_BST_SFT, 3, 0, adc_bst_tlv),
1040 * rt5682s_sel_asrc_clk_src - select ASRC clock source for a set of filters
1041 * @component: SoC audio component device.
1042 * @filter_mask: mask of filters.
1043 * @clk_src: clock source
1045 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682S can
1046 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1047 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1048 * ASRC function will track i2s clock and generate a corresponding system clock
1049 * for codec. This function provides an API to select the clock source for a
1050 * set of filters specified by the mask. And the component driver will turn on
1051 * ASRC for these filters if ASRC is selected as their clock source.
1053 int rt5682s_sel_asrc_clk_src(struct snd_soc_component *component,
1054 unsigned int filter_mask, unsigned int clk_src)
1057 case RT5682S_CLK_SEL_SYS:
1058 case RT5682S_CLK_SEL_I2S1_ASRC:
1059 case RT5682S_CLK_SEL_I2S2_ASRC:
1066 if (filter_mask & RT5682S_DA_STEREO1_FILTER) {
1067 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_2,
1068 RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1071 if (filter_mask & RT5682S_AD_STEREO1_FILTER) {
1072 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_3,
1073 RT5682S_FILTER_CLK_SEL_MASK, clk_src << RT5682S_FILTER_CLK_SEL_SFT);
1076 snd_soc_component_update_bits(component, RT5682S_PLL_TRACK_11,
1077 RT5682S_ASRCIN_AUTO_CLKOUT_MASK, RT5682S_ASRCIN_AUTO_CLKOUT_EN);
1081 EXPORT_SYMBOL_GPL(rt5682s_sel_asrc_clk_src);
1083 static int rt5682s_div_sel(struct rt5682s_priv *rt5682s,
1084 int target, const int div[], int size)
1088 if (rt5682s->sysclk < target) {
1089 dev_err(rt5682s->component->dev,
1090 "sysclk rate %d is too low\n", rt5682s->sysclk);
1094 for (i = 0; i < size - 1; i++) {
1095 dev_dbg(rt5682s->component->dev, "div[%d]=%d\n", i, div[i]);
1096 if (target * div[i] == rt5682s->sysclk)
1098 if (target * div[i + 1] > rt5682s->sysclk) {
1099 dev_dbg(rt5682s->component->dev,
1100 "can't find div for sysclk %d\n", rt5682s->sysclk);
1105 if (target * div[i] < rt5682s->sysclk)
1106 dev_err(rt5682s->component->dev,
1107 "sysclk rate %d is too high\n", rt5682s->sysclk);
1112 static int get_clk_info(int sclk, int rate)
1115 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1117 if (sclk <= 0 || rate <= 0)
1121 for (i = 0; i < ARRAY_SIZE(pd); i++)
1122 if (sclk == rate * pd[i])
1129 * set_dmic_clk - Set parameter of dmic.
1132 * @kcontrol: The kcontrol of this widget.
1135 * Choose dmic clock between 1MHz and 3MHz.
1136 * It is better for clock to approximate 3MHz.
1138 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1139 struct snd_kcontrol *kcontrol, int event)
1141 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1142 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1143 int idx, dmic_clk_rate = 3072000;
1144 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1146 if (rt5682s->pdata.dmic_clk_rate)
1147 dmic_clk_rate = rt5682s->pdata.dmic_clk_rate;
1149 idx = rt5682s_div_sel(rt5682s, dmic_clk_rate, div, ARRAY_SIZE(div));
1151 snd_soc_component_update_bits(component, RT5682S_DMIC_CTRL_1,
1152 RT5682S_DMIC_CLK_MASK, idx << RT5682S_DMIC_CLK_SFT);
1157 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1158 struct snd_kcontrol *kcontrol, int event)
1160 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1161 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1162 int ref, val, reg, idx;
1163 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1164 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1166 val = snd_soc_component_read(component, RT5682S_GPIO_CTRL_1)
1167 & RT5682S_GP4_PIN_MASK;
1169 if (w->shift == RT5682S_PWR_ADC_S1F_BIT && val == RT5682S_GP4_PIN_ADCDAT2)
1170 ref = 256 * rt5682s->lrck[RT5682S_AIF2];
1172 ref = 256 * rt5682s->lrck[RT5682S_AIF1];
1174 idx = rt5682s_div_sel(rt5682s, ref, div_f, ARRAY_SIZE(div_f));
1176 if (w->shift == RT5682S_PWR_ADC_S1F_BIT)
1177 reg = RT5682S_PLL_TRACK_3;
1179 reg = RT5682S_PLL_TRACK_2;
1181 snd_soc_component_update_bits(component, reg,
1182 RT5682S_FILTER_CLK_DIV_MASK, idx << RT5682S_FILTER_CLK_DIV_SFT);
1184 /* select over sample rate */
1185 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1186 if (rt5682s->sysclk <= 12288000 * div_o[idx])
1190 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
1191 RT5682S_ADC_OSR_MASK | RT5682S_DAC_OSR_MASK,
1192 (idx << RT5682S_ADC_OSR_SFT) | (idx << RT5682S_DAC_OSR_SFT));
1197 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1198 struct snd_kcontrol *kcontrol, int event)
1200 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1201 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1202 unsigned int delay = 50, val;
1204 if (rt5682s->pdata.dmic_delay)
1205 delay = rt5682s->pdata.dmic_delay;
1208 case SND_SOC_DAPM_POST_PMU:
1209 val = (snd_soc_component_read(component, RT5682S_GLB_CLK)
1210 & RT5682S_SCLK_SRC_MASK) >> RT5682S_SCLK_SRC_SFT;
1211 if (val == RT5682S_CLK_SRC_PLL1 || val == RT5682S_CLK_SRC_PLL2)
1212 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
1213 RT5682S_PWR_VREF2 | RT5682S_PWR_MB,
1214 RT5682S_PWR_VREF2 | RT5682S_PWR_MB);
1216 /*Add delay to avoid pop noise*/
1220 case SND_SOC_DAPM_POST_PMD:
1221 if (!rt5682s->jack_type) {
1222 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1223 snd_soc_component_update_bits(component,
1224 RT5682S_PWR_ANLG_1, RT5682S_PWR_MB, 0);
1225 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1226 snd_soc_component_update_bits(component,
1227 RT5682S_PWR_ANLG_1, RT5682S_PWR_VREF2, 0);
1235 static int set_i2s_clk(struct snd_soc_dapm_widget *w,
1236 struct snd_kcontrol *kcontrol, int event)
1238 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1239 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1241 unsigned int reg, mask, sft;
1243 if (event != SND_SOC_DAPM_PRE_PMU)
1246 if (w->shift == RT5682S_PWR_I2S2_BIT) {
1248 reg = RT5682S_I2S2_M_CLK_CTRL_1;
1249 mask = RT5682S_I2S2_M_D_MASK;
1250 sft = RT5682S_I2S2_M_D_SFT;
1253 reg = RT5682S_ADDA_CLK_1;
1254 mask = RT5682S_I2S_M_D_MASK;
1255 sft = RT5682S_I2S_M_D_SFT;
1258 if (!rt5682s->master[id])
1261 pre_div = get_clk_info(rt5682s->sysclk, rt5682s->lrck[id]);
1263 dev_err(component->dev, "get pre_div failed\n");
1267 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d master\n",
1268 rt5682s->lrck[id], pre_div, id);
1269 snd_soc_component_update_bits(component, reg, mask, pre_div << sft);
1274 static int is_sys_clk_from_plla(struct snd_soc_dapm_widget *w,
1275 struct snd_soc_dapm_widget *sink)
1277 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1278 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1280 if ((rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL1) ||
1281 (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2 && rt5682s->pll_comb == USE_PLLAB))
1287 static int is_sys_clk_from_pllb(struct snd_soc_dapm_widget *w,
1288 struct snd_soc_dapm_widget *sink)
1290 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1291 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1293 if (rt5682s->sysclk_src == RT5682S_CLK_SRC_PLL2)
1299 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1300 struct snd_soc_dapm_widget *sink)
1302 unsigned int reg, sft, val;
1303 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1306 case RT5682S_ADC_STO1_ASRC_SFT:
1307 reg = RT5682S_PLL_TRACK_3;
1308 sft = RT5682S_FILTER_CLK_SEL_SFT;
1310 case RT5682S_DAC_STO1_ASRC_SFT:
1311 reg = RT5682S_PLL_TRACK_2;
1312 sft = RT5682S_FILTER_CLK_SEL_SFT;
1318 val = (snd_soc_component_read(component, reg) >> sft) & 0xf;
1320 case RT5682S_CLK_SEL_I2S1_ASRC:
1321 case RT5682S_CLK_SEL_I2S2_ASRC:
1328 static int rt5682s_hp_amp_event(struct snd_soc_dapm_widget *w,
1329 struct snd_kcontrol *kcontrol, int event)
1331 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1334 case SND_SOC_DAPM_POST_PMU:
1335 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1336 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN,
1337 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN);
1338 usleep_range(15000, 20000);
1339 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1340 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1341 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN,
1342 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1343 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN);
1344 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_11, 0x6666);
1345 snd_soc_component_write(component, RT5682S_BIAS_CUR_CTRL_12, 0xa82a);
1347 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1348 RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1349 RT5682S_HPO_SEL_IP_EN_SW, RT5682S_HPO_L_PATH_EN |
1350 RT5682S_HPO_R_PATH_EN | RT5682S_HPO_IP_EN_GATING);
1351 usleep_range(5000, 10000);
1352 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1353 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_L | RT5682S_CP_SW_SIZE_S);
1356 case SND_SOC_DAPM_POST_PMD:
1357 snd_soc_component_update_bits(component, RT5682S_HP_CTRL_2,
1358 RT5682S_HPO_L_PATH_MASK | RT5682S_HPO_R_PATH_MASK |
1359 RT5682S_HPO_SEL_IP_EN_SW, 0);
1360 snd_soc_component_update_bits(component, RT5682S_HP_AMP_DET_CTL_1,
1361 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
1362 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1363 RT5682S_LDO_PUMP_EN | RT5682S_PUMP_EN |
1364 RT5682S_CAPLESS_L_EN | RT5682S_CAPLESS_R_EN, 0);
1365 snd_soc_component_update_bits(component, RT5682S_DEPOP_1,
1366 RT5682S_OUT_HP_L_EN | RT5682S_OUT_HP_R_EN, 0);
1373 static int rt5682s_stereo1_adc_mixl_event(struct snd_soc_dapm_widget *w,
1374 struct snd_kcontrol *kcontrol, int event)
1376 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1377 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1378 unsigned int delay = 0;
1380 if (rt5682s->pdata.amic_delay)
1381 delay = rt5682s->pdata.amic_delay;
1384 case SND_SOC_DAPM_POST_PMU:
1386 snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1389 case SND_SOC_DAPM_PRE_PMD:
1390 snd_soc_component_update_bits(component, RT5682S_STO1_ADC_DIG_VOL,
1391 RT5682S_L_MUTE, RT5682S_L_MUTE);
1398 static int sar_power_event(struct snd_soc_dapm_widget *w,
1399 struct snd_kcontrol *kcontrol, int event)
1401 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1402 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
1404 if ((rt5682s->jack_type & SND_JACK_HEADSET) != SND_JACK_HEADSET)
1408 case SND_SOC_DAPM_PRE_PMU:
1409 rt5682s_sar_power_mode(component, SAR_PWR_NORMAL);
1411 case SND_SOC_DAPM_POST_PMD:
1412 rt5682s_sar_power_mode(component, SAR_PWR_SAVING);
1419 /* Interface data select */
1420 static const char * const rt5682s_data_select[] = {
1421 "L/R", "R/L", "L/L", "R/R"
1424 static SOC_ENUM_SINGLE_DECL(rt5682s_if2_adc_enum, RT5682S_DIG_INF2_DATA,
1425 RT5682S_IF2_ADC_SEL_SFT, rt5682s_data_select);
1427 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_01_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1428 RT5682S_IF1_ADC1_SEL_SFT, rt5682s_data_select);
1430 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_23_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1431 RT5682S_IF1_ADC2_SEL_SFT, rt5682s_data_select);
1433 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_45_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1434 RT5682S_IF1_ADC3_SEL_SFT, rt5682s_data_select);
1436 static SOC_ENUM_SINGLE_DECL(rt5682s_if1_67_adc_enum, RT5682S_TDM_ADDA_CTRL_1,
1437 RT5682S_IF1_ADC4_SEL_SFT, rt5682s_data_select);
1439 static const struct snd_kcontrol_new rt5682s_if2_adc_swap_mux =
1440 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682s_if2_adc_enum);
1442 static const struct snd_kcontrol_new rt5682s_if1_01_adc_swap_mux =
1443 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682s_if1_01_adc_enum);
1445 static const struct snd_kcontrol_new rt5682s_if1_23_adc_swap_mux =
1446 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682s_if1_23_adc_enum);
1448 static const struct snd_kcontrol_new rt5682s_if1_45_adc_swap_mux =
1449 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682s_if1_45_adc_enum);
1451 static const struct snd_kcontrol_new rt5682s_if1_67_adc_swap_mux =
1452 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682s_if1_67_adc_enum);
1455 static const struct snd_kcontrol_new rt5682s_sto1_adc_l_mix[] = {
1456 SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1457 RT5682S_M_STO1_ADC_L1_SFT, 1, 1),
1458 SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1459 RT5682S_M_STO1_ADC_L2_SFT, 1, 1),
1462 static const struct snd_kcontrol_new rt5682s_sto1_adc_r_mix[] = {
1463 SOC_DAPM_SINGLE("ADC1 Switch", RT5682S_STO1_ADC_MIXER,
1464 RT5682S_M_STO1_ADC_R1_SFT, 1, 1),
1465 SOC_DAPM_SINGLE("ADC2 Switch", RT5682S_STO1_ADC_MIXER,
1466 RT5682S_M_STO1_ADC_R2_SFT, 1, 1),
1469 static const struct snd_kcontrol_new rt5682s_dac_l_mix[] = {
1470 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1471 RT5682S_M_ADCMIX_L_SFT, 1, 1),
1472 SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1473 RT5682S_M_DAC1_L_SFT, 1, 1),
1476 static const struct snd_kcontrol_new rt5682s_dac_r_mix[] = {
1477 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682S_AD_DA_MIXER,
1478 RT5682S_M_ADCMIX_R_SFT, 1, 1),
1479 SOC_DAPM_SINGLE("DAC1 Switch", RT5682S_AD_DA_MIXER,
1480 RT5682S_M_DAC1_R_SFT, 1, 1),
1483 static const struct snd_kcontrol_new rt5682s_sto1_dac_l_mix[] = {
1484 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1485 RT5682S_M_DAC_L1_STO_L_SFT, 1, 1),
1486 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1487 RT5682S_M_DAC_R1_STO_L_SFT, 1, 1),
1490 static const struct snd_kcontrol_new rt5682s_sto1_dac_r_mix[] = {
1491 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682S_STO1_DAC_MIXER,
1492 RT5682S_M_DAC_L1_STO_R_SFT, 1, 1),
1493 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682S_STO1_DAC_MIXER,
1494 RT5682S_M_DAC_R1_STO_R_SFT, 1, 1),
1497 /* Analog Input Mixer */
1498 static const struct snd_kcontrol_new rt5682s_rec1_l_mix[] = {
1499 SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1500 RT5682S_M_CBJ_RM1_L_SFT, 1, 1),
1503 static const struct snd_kcontrol_new rt5682s_rec1_r_mix[] = {
1504 SOC_DAPM_SINGLE("CBJ Switch", RT5682S_REC_MIXER,
1505 RT5682S_M_CBJ_RM1_R_SFT, 1, 1),
1508 /* STO1 ADC1 Source */
1509 /* MX-26 [13] [5] */
1510 static const char * const rt5682s_sto1_adc1_src[] = {
1514 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1l_enum, RT5682S_STO1_ADC_MIXER,
1515 RT5682S_STO1_ADC1L_SRC_SFT, rt5682s_sto1_adc1_src);
1517 static const struct snd_kcontrol_new rt5682s_sto1_adc1l_mux =
1518 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1l_enum);
1520 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc1r_enum, RT5682S_STO1_ADC_MIXER,
1521 RT5682S_STO1_ADC1R_SRC_SFT, rt5682s_sto1_adc1_src);
1523 static const struct snd_kcontrol_new rt5682s_sto1_adc1r_mux =
1524 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682s_sto1_adc1r_enum);
1526 /* STO1 ADC Source */
1527 /* MX-26 [11:10] [3:2] */
1528 static const char * const rt5682s_sto1_adc_src[] = {
1532 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcl_enum, RT5682S_STO1_ADC_MIXER,
1533 RT5682S_STO1_ADCL_SRC_SFT, rt5682s_sto1_adc_src);
1535 static const struct snd_kcontrol_new rt5682s_sto1_adcl_mux =
1536 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682s_sto1_adcl_enum);
1538 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adcr_enum, RT5682S_STO1_ADC_MIXER,
1539 RT5682S_STO1_ADCR_SRC_SFT, rt5682s_sto1_adc_src);
1541 static const struct snd_kcontrol_new rt5682s_sto1_adcr_mux =
1542 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682s_sto1_adcr_enum);
1544 /* STO1 ADC2 Source */
1545 /* MX-26 [12] [4] */
1546 static const char * const rt5682s_sto1_adc2_src[] = {
1550 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2l_enum, RT5682S_STO1_ADC_MIXER,
1551 RT5682S_STO1_ADC2L_SRC_SFT, rt5682s_sto1_adc2_src);
1553 static const struct snd_kcontrol_new rt5682s_sto1_adc2l_mux =
1554 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682s_sto1_adc2l_enum);
1556 static SOC_ENUM_SINGLE_DECL(rt5682s_sto1_adc2r_enum, RT5682S_STO1_ADC_MIXER,
1557 RT5682S_STO1_ADC2R_SRC_SFT, rt5682s_sto1_adc2_src);
1559 static const struct snd_kcontrol_new rt5682s_sto1_adc2r_mux =
1560 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682s_sto1_adc2r_enum);
1562 /* MX-79 [6:4] I2S1 ADC data location */
1563 static const unsigned int rt5682s_if1_adc_slot_values[] = {
1567 static const char * const rt5682s_if1_adc_slot_src[] = {
1568 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1571 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_if1_adc_slot_enum,
1572 RT5682S_TDM_CTRL, RT5682S_TDM_ADC_LCA_SFT, RT5682S_TDM_ADC_LCA_MASK,
1573 rt5682s_if1_adc_slot_src, rt5682s_if1_adc_slot_values);
1575 static const struct snd_kcontrol_new rt5682s_if1_adc_slot_mux =
1576 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682s_if1_adc_slot_enum);
1578 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1579 /* MX-2B [4], MX-2B [0]*/
1580 static const char * const rt5682s_alg_dac1_src[] = {
1581 "Stereo1 DAC Mixer", "DAC1"
1584 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_l1_enum, RT5682S_A_DAC1_MUX,
1585 RT5682S_A_DACL1_SFT, rt5682s_alg_dac1_src);
1587 static const struct snd_kcontrol_new rt5682s_alg_dac_l1_mux =
1588 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682s_alg_dac_l1_enum);
1590 static SOC_ENUM_SINGLE_DECL(rt5682s_alg_dac_r1_enum, RT5682S_A_DAC1_MUX,
1591 RT5682S_A_DACR1_SFT, rt5682s_alg_dac1_src);
1593 static const struct snd_kcontrol_new rt5682s_alg_dac_r1_mux =
1594 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682s_alg_dac_r1_enum);
1596 static const unsigned int rt5682s_adcdat_pin_values[] = {
1600 static const char * const rt5682s_adcdat_pin_select[] = {
1601 "ADCDAT1", "ADCDAT2",
1604 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682s_adcdat_pin_enum,
1605 RT5682S_GPIO_CTRL_1, RT5682S_GP4_PIN_SFT, RT5682S_GP4_PIN_MASK,
1606 rt5682s_adcdat_pin_select, rt5682s_adcdat_pin_values);
1608 static const struct snd_kcontrol_new rt5682s_adcdat_pin_ctrl =
1609 SOC_DAPM_ENUM("ADCDAT", rt5682s_adcdat_pin_enum);
1611 static const struct snd_soc_dapm_widget rt5682s_dapm_widgets[] = {
1612 SND_SOC_DAPM_SUPPLY("LDO MB1", RT5682S_PWR_ANLG_3,
1613 RT5682S_PWR_LDO_MB1_BIT, 0, NULL, 0),
1614 SND_SOC_DAPM_SUPPLY("LDO MB2", RT5682S_PWR_ANLG_3,
1615 RT5682S_PWR_LDO_MB2_BIT, 0, NULL, 0),
1616 SND_SOC_DAPM_SUPPLY("LDO", RT5682S_PWR_ANLG_3,
1617 RT5682S_PWR_LDO_BIT, 0, NULL, 0),
1618 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1619 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1622 SND_SOC_DAPM_SUPPLY_S("PLLA_LDO", 0, RT5682S_PWR_ANLG_3,
1623 RT5682S_PWR_LDO_PLLA_BIT, 0, NULL, 0),
1624 SND_SOC_DAPM_SUPPLY_S("PLLB_LDO", 0, RT5682S_PWR_ANLG_3,
1625 RT5682S_PWR_LDO_PLLB_BIT, 0, NULL, 0),
1626 SND_SOC_DAPM_SUPPLY_S("PLLA_BIAS", 0, RT5682S_PWR_ANLG_3,
1627 RT5682S_PWR_BIAS_PLLA_BIT, 0, NULL, 0),
1628 SND_SOC_DAPM_SUPPLY_S("PLLB_BIAS", 0, RT5682S_PWR_ANLG_3,
1629 RT5682S_PWR_BIAS_PLLB_BIT, 0, NULL, 0),
1630 SND_SOC_DAPM_SUPPLY_S("PLLA", 0, RT5682S_PWR_ANLG_3,
1631 RT5682S_PWR_PLLA_BIT, 0, NULL, 0),
1632 SND_SOC_DAPM_SUPPLY_S("PLLB", 0, RT5682S_PWR_ANLG_3,
1633 RT5682S_PWR_PLLB_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1634 SND_SOC_DAPM_SUPPLY_S("PLLA_RST", 1, RT5682S_PWR_ANLG_3,
1635 RT5682S_RSTB_PLLA_BIT, 0, NULL, 0),
1636 SND_SOC_DAPM_SUPPLY_S("PLLB_RST", 1, RT5682S_PWR_ANLG_3,
1637 RT5682S_RSTB_PLLB_BIT, 0, NULL, 0),
1640 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1641 RT5682S_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1642 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682S_PLL_TRACK_1,
1643 RT5682S_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1644 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682S_PLL_TRACK_1,
1645 RT5682S_AD_ASRC_SFT, 0, NULL, 0),
1646 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682S_PLL_TRACK_1,
1647 RT5682S_DA_ASRC_SFT, 0, NULL, 0),
1648 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682S_PLL_TRACK_1,
1649 RT5682S_DMIC_ASRC_SFT, 0, NULL, 0),
1652 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682S_PWR_ANLG_2,
1653 RT5682S_PWR_MB1_BIT, 0, NULL, 0),
1654 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682S_PWR_ANLG_2,
1655 RT5682S_PWR_MB2_BIT, 0, NULL, 0),
1658 SND_SOC_DAPM_INPUT("DMIC L1"),
1659 SND_SOC_DAPM_INPUT("DMIC R1"),
1661 SND_SOC_DAPM_INPUT("IN1P"),
1663 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1664 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1665 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682S_DMIC_CTRL_1, RT5682S_DMIC_1_EN_SFT, 0,
1666 set_dmic_power, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1669 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
1672 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682s_rec1_l_mix,
1673 ARRAY_SIZE(rt5682s_rec1_l_mix)),
1674 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5682s_rec1_r_mix,
1675 ARRAY_SIZE(rt5682s_rec1_r_mix)),
1676 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682S_CAL_REC,
1677 RT5682S_PWR_RM1_L_BIT, 0, NULL, 0),
1678 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5682S_CAL_REC,
1679 RT5682S_PWR_RM1_R_BIT, 0, NULL, 0),
1682 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1683 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1685 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682S_PWR_DIG_1,
1686 RT5682S_PWR_ADC_L1_BIT, 0, NULL, 0),
1687 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682S_PWR_DIG_1,
1688 RT5682S_PWR_ADC_R1_BIT, 0, NULL, 0),
1689 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682S_CHOP_ADC,
1690 RT5682S_CKGEN_ADC1_SFT, 0, NULL, 0),
1693 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1694 &rt5682s_sto1_adc1l_mux),
1695 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1696 &rt5682s_sto1_adc1r_mux),
1697 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1698 &rt5682s_sto1_adc2l_mux),
1699 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1700 &rt5682s_sto1_adc2r_mux),
1701 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1702 &rt5682s_sto1_adcl_mux),
1703 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1704 &rt5682s_sto1_adcr_mux),
1705 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1706 &rt5682s_if1_adc_slot_mux),
1709 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682S_PWR_DIG_2,
1710 RT5682S_PWR_ADC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1711 SND_SOC_DAPM_MIXER_E("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1712 rt5682s_sto1_adc_l_mix, ARRAY_SIZE(rt5682s_sto1_adc_l_mix),
1713 rt5682s_stereo1_adc_mixl_event,
1714 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1715 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682S_STO1_ADC_DIG_VOL,
1716 RT5682S_R_MUTE_SFT, 1, rt5682s_sto1_adc_r_mix,
1717 ARRAY_SIZE(rt5682s_sto1_adc_r_mix)),
1720 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1722 /* Digital Interface */
1723 SND_SOC_DAPM_SUPPLY("I2S1", RT5682S_PWR_DIG_1, RT5682S_PWR_I2S1_BIT,
1724 0, set_i2s_clk, SND_SOC_DAPM_PRE_PMU),
1725 SND_SOC_DAPM_SUPPLY("I2S2", RT5682S_PWR_DIG_1, RT5682S_PWR_I2S2_BIT,
1726 0, set_i2s_clk, SND_SOC_DAPM_PRE_PMU),
1727 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1728 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1730 /* Digital Interface Select */
1731 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1732 &rt5682s_if1_01_adc_swap_mux),
1733 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1734 &rt5682s_if1_23_adc_swap_mux),
1735 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1736 &rt5682s_if1_45_adc_swap_mux),
1737 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1738 &rt5682s_if1_67_adc_swap_mux),
1739 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1740 &rt5682s_if2_adc_swap_mux),
1742 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0, &rt5682s_adcdat_pin_ctrl),
1744 /* Audio Interface */
1745 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, RT5682S_I2S1_SDP,
1746 RT5682S_SEL_ADCDAT_SFT, 1),
1747 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, RT5682S_I2S2_SDP,
1748 RT5682S_I2S2_PIN_CFG_SFT, 1),
1749 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1752 /* DAC mixer before sound effect */
1753 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1754 rt5682s_dac_l_mix, ARRAY_SIZE(rt5682s_dac_l_mix)),
1755 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1756 rt5682s_dac_r_mix, ARRAY_SIZE(rt5682s_dac_r_mix)),
1758 /* DAC channel Mux */
1759 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_l1_mux),
1760 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0, &rt5682s_alg_dac_r1_mux),
1763 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682S_PWR_DIG_2,
1764 RT5682S_PWR_DAC_S1F_BIT, 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1765 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1766 rt5682s_sto1_dac_l_mix, ARRAY_SIZE(rt5682s_sto1_dac_l_mix)),
1767 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1768 rt5682s_sto1_dac_r_mix, ARRAY_SIZE(rt5682s_sto1_dac_r_mix)),
1771 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_L1_BIT, 0),
1772 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682S_PWR_DIG_1, RT5682S_PWR_DAC_R1_BIT, 0),
1775 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682s_hp_amp_event,
1776 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
1779 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682S_CLK_DET,
1780 RT5682S_SYS_CLK_DET_SFT, 0, NULL, 0),
1781 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682S_CLK_DET,
1782 RT5682S_PLL1_CLK_DET_SFT, 0, NULL, 0),
1783 SND_SOC_DAPM_SUPPLY("MCLK0 DET PWR", RT5682S_PWR_ANLG_2,
1784 RT5682S_PWR_MCLK0_WD_BIT, 0, NULL, 0),
1787 SND_SOC_DAPM_SUPPLY("SAR", SND_SOC_NOPM, 0, 0, sar_power_event,
1788 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1791 SND_SOC_DAPM_OUTPUT("HPOL"),
1792 SND_SOC_DAPM_OUTPUT("HPOR"),
1795 static const struct snd_soc_dapm_route rt5682s_dapm_routes[] = {
1797 {"ADC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1798 {"ADC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1799 {"DAC Stereo1 Filter", NULL, "PLLA", is_sys_clk_from_plla},
1800 {"DAC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1801 {"PLLA", NULL, "PLLA_LDO"},
1802 {"PLLA", NULL, "PLLA_BIAS"},
1803 {"PLLA", NULL, "PLLA_RST"},
1804 {"PLLB", NULL, "PLLB_LDO"},
1805 {"PLLB", NULL, "PLLB_BIAS"},
1806 {"PLLB", NULL, "PLLB_RST"},
1809 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1810 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1811 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1812 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1813 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1814 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1816 {"CLKDET SYS", NULL, "MCLK0 DET PWR"},
1818 {"BST1 CBJ", NULL, "IN1P"},
1819 {"BST1 CBJ", NULL, "SAR"},
1821 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1822 {"RECMIX1L", NULL, "RECMIX1L Power"},
1823 {"RECMIX1R", "CBJ Switch", "BST1 CBJ"},
1824 {"RECMIX1R", NULL, "RECMIX1R Power"},
1826 {"ADC1 L", NULL, "RECMIX1L"},
1827 {"ADC1 L", NULL, "ADC1 L Power"},
1828 {"ADC1 L", NULL, "ADC1 clock"},
1829 {"ADC1 R", NULL, "RECMIX1R"},
1830 {"ADC1 R", NULL, "ADC1 R Power"},
1831 {"ADC1 R", NULL, "ADC1 clock"},
1833 {"DMIC L1", NULL, "DMIC CLK"},
1834 {"DMIC L1", NULL, "DMIC1 Power"},
1835 {"DMIC R1", NULL, "DMIC CLK"},
1836 {"DMIC R1", NULL, "DMIC1 Power"},
1837 {"DMIC CLK", NULL, "DMIC ASRC"},
1839 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1840 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1841 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1842 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1844 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1845 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1846 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1847 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1849 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1850 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1851 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1852 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1854 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1855 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1856 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1858 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1859 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1860 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1862 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1863 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1865 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1866 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1867 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1868 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1869 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1870 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1871 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1872 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1873 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1874 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1875 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1876 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1877 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1878 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1879 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1880 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1882 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1883 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1884 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1885 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1886 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1887 {"AIF1TX", NULL, "I2S1"},
1888 {"AIF1TX", NULL, "ADCDAT Mux"},
1889 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1890 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1891 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1892 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1893 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1894 {"AIF2TX", NULL, "ADCDAT Mux"},
1896 {"IF1 DAC1 L", NULL, "AIF1RX"},
1897 {"IF1 DAC1 L", NULL, "I2S1"},
1898 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1899 {"IF1 DAC1 R", NULL, "AIF1RX"},
1900 {"IF1 DAC1 R", NULL, "I2S1"},
1901 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1903 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1904 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1905 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1906 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1908 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1909 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1911 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1912 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1914 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1915 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1916 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1917 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1919 {"DAC L1", NULL, "DAC L1 Source"},
1920 {"DAC R1", NULL, "DAC R1 Source"},
1922 {"HP Amp", NULL, "DAC L1"},
1923 {"HP Amp", NULL, "DAC R1"},
1924 {"HP Amp", NULL, "CLKDET SYS"},
1925 {"HP Amp", NULL, "SAR"},
1927 {"HPOL", NULL, "HP Amp"},
1928 {"HPOR", NULL, "HP Amp"},
1931 static int rt5682s_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1932 unsigned int rx_mask, int slots, int slot_width)
1934 struct snd_soc_component *component = dai->component;
1935 unsigned int cl, val = 0;
1937 if (tx_mask || rx_mask)
1938 snd_soc_component_update_bits(component,
1939 RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, RT5682S_TDM_EN);
1941 snd_soc_component_update_bits(component,
1942 RT5682S_TDM_ADDA_CTRL_2, RT5682S_TDM_EN, 0);
1946 val |= RT5682S_TDM_TX_CH_4;
1947 val |= RT5682S_TDM_RX_CH_4;
1950 val |= RT5682S_TDM_TX_CH_6;
1951 val |= RT5682S_TDM_RX_CH_6;
1954 val |= RT5682S_TDM_TX_CH_8;
1955 val |= RT5682S_TDM_RX_CH_8;
1963 snd_soc_component_update_bits(component, RT5682S_TDM_CTRL,
1964 RT5682S_TDM_TX_CH_MASK | RT5682S_TDM_RX_CH_MASK, val);
1966 switch (slot_width) {
1968 if (tx_mask || rx_mask)
1970 cl = RT5682S_I2S1_TX_CHL_8 | RT5682S_I2S1_RX_CHL_8;
1973 val = RT5682S_TDM_CL_16;
1974 cl = RT5682S_I2S1_TX_CHL_16 | RT5682S_I2S1_RX_CHL_16;
1977 val = RT5682S_TDM_CL_20;
1978 cl = RT5682S_I2S1_TX_CHL_20 | RT5682S_I2S1_RX_CHL_20;
1981 val = RT5682S_TDM_CL_24;
1982 cl = RT5682S_I2S1_TX_CHL_24 | RT5682S_I2S1_RX_CHL_24;
1985 val = RT5682S_TDM_CL_32;
1986 cl = RT5682S_I2S1_TX_CHL_32 | RT5682S_I2S1_RX_CHL_32;
1992 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
1993 RT5682S_TDM_CL_MASK, val);
1994 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
1995 RT5682S_I2S1_TX_CHL_MASK | RT5682S_I2S1_RX_CHL_MASK, cl);
2000 static int rt5682s_hw_params(struct snd_pcm_substream *substream,
2001 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2003 struct snd_soc_component *component = dai->component;
2004 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2005 unsigned int len_1 = 0, len_2 = 0;
2008 rt5682s->lrck[dai->id] = params_rate(params);
2010 frame_size = snd_soc_params_to_frame_size(params);
2011 if (frame_size < 0) {
2012 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2016 switch (params_width(params)) {
2020 len_1 |= RT5682S_I2S1_DL_20;
2021 len_2 |= RT5682S_I2S2_DL_20;
2024 len_1 |= RT5682S_I2S1_DL_24;
2025 len_2 |= RT5682S_I2S2_DL_24;
2028 len_1 |= RT5682S_I2S1_DL_32;
2029 len_2 |= RT5682S_I2S2_DL_24;
2032 len_1 |= RT5682S_I2S2_DL_8;
2033 len_2 |= RT5682S_I2S2_DL_8;
2041 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2042 RT5682S_I2S1_DL_MASK, len_1);
2043 if (params_channels(params) == 1) /* mono mode */
2044 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2045 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_EN);
2047 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2048 RT5682S_I2S1_MONO_MASK, RT5682S_I2S1_MONO_DIS);
2051 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2052 RT5682S_I2S2_DL_MASK, len_2);
2053 if (params_channels(params) == 1) /* mono mode */
2054 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2055 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_EN);
2057 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2058 RT5682S_I2S2_MONO_MASK, RT5682S_I2S2_MONO_DIS);
2061 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2068 static int rt5682s_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2070 struct snd_soc_component *component = dai->component;
2071 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2072 unsigned int reg_val = 0, tdm_ctrl = 0;
2074 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2075 case SND_SOC_DAIFMT_CBM_CFM:
2076 rt5682s->master[dai->id] = 1;
2078 case SND_SOC_DAIFMT_CBS_CFS:
2079 rt5682s->master[dai->id] = 0;
2085 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2086 case SND_SOC_DAIFMT_NB_NF:
2088 case SND_SOC_DAIFMT_IB_NF:
2089 reg_val |= RT5682S_I2S_BP_INV;
2090 tdm_ctrl |= RT5682S_TDM_S_BP_INV;
2092 case SND_SOC_DAIFMT_NB_IF:
2093 if (dai->id == RT5682S_AIF1)
2094 tdm_ctrl |= RT5682S_TDM_S_LP_INV | RT5682S_TDM_M_BP_INV;
2098 case SND_SOC_DAIFMT_IB_IF:
2099 if (dai->id == RT5682S_AIF1)
2100 tdm_ctrl |= RT5682S_TDM_S_BP_INV | RT5682S_TDM_S_LP_INV |
2101 RT5682S_TDM_M_BP_INV | RT5682S_TDM_M_LP_INV;
2109 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2110 case SND_SOC_DAIFMT_I2S:
2112 case SND_SOC_DAIFMT_LEFT_J:
2113 reg_val |= RT5682S_I2S_DF_LEFT;
2114 tdm_ctrl |= RT5682S_TDM_DF_LEFT;
2116 case SND_SOC_DAIFMT_DSP_A:
2117 reg_val |= RT5682S_I2S_DF_PCM_A;
2118 tdm_ctrl |= RT5682S_TDM_DF_PCM_A;
2120 case SND_SOC_DAIFMT_DSP_B:
2121 reg_val |= RT5682S_I2S_DF_PCM_B;
2122 tdm_ctrl |= RT5682S_TDM_DF_PCM_B;
2130 snd_soc_component_update_bits(component, RT5682S_I2S1_SDP,
2131 RT5682S_I2S_DF_MASK, reg_val);
2132 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2133 RT5682S_TDM_MS_MASK | RT5682S_TDM_S_BP_MASK |
2134 RT5682S_TDM_DF_MASK | RT5682S_TDM_M_BP_MASK |
2135 RT5682S_TDM_M_LP_MASK | RT5682S_TDM_S_LP_MASK,
2136 tdm_ctrl | rt5682s->master[dai->id]);
2139 if (rt5682s->master[dai->id] == 0)
2140 reg_val |= RT5682S_I2S2_MS_S;
2141 snd_soc_component_update_bits(component, RT5682S_I2S2_SDP,
2142 RT5682S_I2S2_MS_MASK | RT5682S_I2S_BP_MASK |
2143 RT5682S_I2S_DF_MASK, reg_val);
2146 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2152 static int rt5682s_set_component_sysclk(struct snd_soc_component *component,
2153 int clk_id, int source, unsigned int freq, int dir)
2155 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2156 unsigned int src = 0;
2158 if (freq == rt5682s->sysclk && clk_id == rt5682s->sysclk_src)
2162 case RT5682S_SCLK_S_MCLK:
2163 src = RT5682S_CLK_SRC_MCLK;
2165 case RT5682S_SCLK_S_PLL1:
2166 src = RT5682S_CLK_SRC_PLL1;
2168 case RT5682S_SCLK_S_PLL2:
2169 src = RT5682S_CLK_SRC_PLL2;
2171 case RT5682S_SCLK_S_RCCLK:
2172 src = RT5682S_CLK_SRC_RCCLK;
2175 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2179 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2180 RT5682S_SCLK_SRC_MASK, src << RT5682S_SCLK_SRC_SFT);
2181 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_1,
2182 RT5682S_I2S_M_CLK_SRC_MASK, src << RT5682S_I2S_M_CLK_SRC_SFT);
2183 snd_soc_component_update_bits(component, RT5682S_I2S2_M_CLK_CTRL_1,
2184 RT5682S_I2S2_M_CLK_SRC_MASK, src << RT5682S_I2S2_M_CLK_SRC_SFT);
2186 rt5682s->sysclk = freq;
2187 rt5682s->sysclk_src = clk_id;
2189 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2195 static const struct pll_calc_map plla_table[] = {
2196 {2048000, 24576000, 0, 46, 2, true, false, false, false},
2197 {256000, 24576000, 0, 382, 2, true, false, false, false},
2198 {512000, 24576000, 0, 190, 2, true, false, false, false},
2199 {4096000, 24576000, 0, 22, 2, true, false, false, false},
2200 {1024000, 24576000, 0, 94, 2, true, false, false, false},
2201 {11289600, 22579200, 1, 22, 2, false, false, false, false},
2202 {1411200, 22579200, 0, 62, 2, true, false, false, false},
2203 {2822400, 22579200, 0, 30, 2, true, false, false, false},
2204 {12288000, 24576000, 1, 22, 2, false, false, false, false},
2205 {1536000, 24576000, 0, 62, 2, true, false, false, false},
2206 {3072000, 24576000, 0, 30, 2, true, false, false, false},
2207 {24576000, 49152000, 4, 22, 0, false, false, false, false},
2208 {3072000, 49152000, 0, 30, 0, true, false, false, false},
2209 {6144000, 49152000, 0, 30, 0, false, false, false, false},
2210 {49152000, 98304000, 10, 22, 0, false, true, false, false},
2211 {6144000, 98304000, 0, 30, 0, false, true, false, false},
2212 {12288000, 98304000, 1, 22, 0, false, true, false, false},
2213 {48000000, 3840000, 10, 22, 23, false, false, false, false},
2214 {24000000, 3840000, 4, 22, 23, false, false, false, false},
2215 {19200000, 3840000, 3, 23, 23, false, false, false, false},
2216 {38400000, 3840000, 8, 23, 23, false, false, false, false},
2219 static const struct pll_calc_map pllb_table[] = {
2220 {48000000, 24576000, 8, 6, 3, false, false, false, false},
2221 {48000000, 22579200, 23, 12, 3, false, false, false, true},
2222 {24000000, 24576000, 3, 6, 3, false, false, false, false},
2223 {24000000, 22579200, 23, 26, 3, false, false, false, true},
2224 {19200000, 24576000, 2, 6, 3, false, false, false, false},
2225 {19200000, 22579200, 3, 5, 3, false, false, false, true},
2226 {38400000, 24576000, 6, 6, 3, false, false, false, false},
2227 {38400000, 22579200, 8, 5, 3, false, false, false, true},
2228 {3840000, 49152000, 0, 6, 0, true, false, false, false},
2231 static int find_pll_inter_combination(unsigned int f_in, unsigned int f_out,
2232 struct pll_calc_map *a, struct pll_calc_map *b)
2236 /* Look at PLLA table */
2237 for (i = 0; i < ARRAY_SIZE(plla_table); i++) {
2238 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == f_out) {
2239 memcpy(a, plla_table + i, sizeof(*a));
2244 /* Look at PLLB table */
2245 for (i = 0; i < ARRAY_SIZE(pllb_table); i++) {
2246 if (pllb_table[i].freq_in == f_in && pllb_table[i].freq_out == f_out) {
2247 memcpy(b, pllb_table + i, sizeof(*b));
2252 /* Find a combination of PLLA & PLLB */
2253 for (i = ARRAY_SIZE(plla_table) - 1; i >= 0; i--) {
2254 if (plla_table[i].freq_in == f_in && plla_table[i].freq_out == 3840000) {
2255 for (j = ARRAY_SIZE(pllb_table) - 1; j >= 0; j--) {
2256 if (pllb_table[j].freq_in == 3840000 &&
2257 pllb_table[j].freq_out == f_out) {
2258 memcpy(a, plla_table + i, sizeof(*a));
2259 memcpy(b, pllb_table + j, sizeof(*b));
2269 static int rt5682s_set_component_pll(struct snd_soc_component *component,
2270 int pll_id, int source, unsigned int freq_in,
2271 unsigned int freq_out)
2273 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2274 struct pll_calc_map a_map, b_map;
2276 if (source == rt5682s->pll_src[pll_id] && freq_in == rt5682s->pll_in[pll_id] &&
2277 freq_out == rt5682s->pll_out[pll_id])
2280 if (!freq_in || !freq_out) {
2281 dev_dbg(component->dev, "PLL disabled\n");
2282 rt5682s->pll_in[pll_id] = 0;
2283 rt5682s->pll_out[pll_id] = 0;
2284 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2285 RT5682S_SCLK_SRC_MASK, RT5682S_CLK_SRC_MCLK << RT5682S_SCLK_SRC_SFT);
2290 case RT5682S_PLL_S_MCLK:
2291 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2292 RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_MCLK);
2294 case RT5682S_PLL_S_BCLK1:
2295 snd_soc_component_update_bits(component, RT5682S_GLB_CLK,
2296 RT5682S_PLL_SRC_MASK, RT5682S_PLL_SRC_BCLK1);
2299 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2303 rt5682s->pll_comb = find_pll_inter_combination(freq_in, freq_out,
2306 if ((pll_id == RT5682S_PLL1 && rt5682s->pll_comb == USE_PLLA) ||
2307 (pll_id == RT5682S_PLL2 && (rt5682s->pll_comb == USE_PLLB ||
2308 rt5682s->pll_comb == USE_PLLAB))) {
2309 dev_dbg(component->dev,
2310 "Supported freq conversion for PLL%d:(%d->%d): %d\n",
2311 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2313 dev_err(component->dev,
2314 "Unsupported freq conversion for PLL%d:(%d->%d): %d\n",
2315 pll_id + 1, freq_in, freq_out, rt5682s->pll_comb);
2319 if (rt5682s->pll_comb == USE_PLLA || rt5682s->pll_comb == USE_PLLAB) {
2320 dev_dbg(component->dev,
2321 "PLLA: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d\n",
2322 a_map.freq_in, a_map.freq_out, a_map.m_bp, a_map.k_bp,
2323 (a_map.m_bp ? 0 : a_map.m), a_map.n, (a_map.k_bp ? 0 : a_map.k));
2324 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_1,
2325 RT5682S_PLLA_N_MASK, a_map.n);
2326 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_2,
2327 RT5682S_PLLA_M_MASK | RT5682S_PLLA_K_MASK,
2328 a_map.m << RT5682S_PLLA_M_SFT | a_map.k);
2329 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2330 RT5682S_PLLA_M_BP_MASK | RT5682S_PLLA_K_BP_MASK,
2331 a_map.m_bp << RT5682S_PLLA_M_BP_SFT |
2332 a_map.k_bp << RT5682S_PLLA_K_BP_SFT);
2335 if (rt5682s->pll_comb == USE_PLLB || rt5682s->pll_comb == USE_PLLAB) {
2336 dev_dbg(component->dev,
2337 "PLLB: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d byp_ps=%d sel_ps=%d\n",
2338 b_map.freq_in, b_map.freq_out, b_map.m_bp, b_map.k_bp,
2339 (b_map.m_bp ? 0 : b_map.m), b_map.n, (b_map.k_bp ? 0 : b_map.k),
2340 b_map.byp_ps, b_map.sel_ps);
2341 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_3,
2342 RT5682S_PLLB_N_MASK, b_map.n);
2343 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_4,
2344 RT5682S_PLLB_M_MASK | RT5682S_PLLB_K_MASK,
2345 b_map.m << RT5682S_PLLB_M_SFT | b_map.k);
2346 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_6,
2347 RT5682S_PLLB_SEL_PS_MASK | RT5682S_PLLB_BYP_PS_MASK |
2348 RT5682S_PLLB_M_BP_MASK | RT5682S_PLLB_K_BP_MASK,
2349 b_map.sel_ps << RT5682S_PLLB_SEL_PS_SFT |
2350 b_map.byp_ps << RT5682S_PLLB_BYP_PS_SFT |
2351 b_map.m_bp << RT5682S_PLLB_M_BP_SFT |
2352 b_map.k_bp << RT5682S_PLLB_K_BP_SFT);
2355 if (rt5682s->pll_comb == USE_PLLB)
2356 snd_soc_component_update_bits(component, RT5682S_PLL_CTRL_7,
2357 RT5682S_PLLB_SRC_MASK, RT5682S_PLLB_SRC_DFIN);
2359 rt5682s->pll_in[pll_id] = freq_in;
2360 rt5682s->pll_out[pll_id] = freq_out;
2361 rt5682s->pll_src[pll_id] = source;
2366 static int rt5682s_set_bclk1_ratio(struct snd_soc_dai *dai,
2369 struct snd_soc_component *component = dai->component;
2370 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2372 rt5682s->bclk[dai->id] = ratio;
2376 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2377 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_256);
2380 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2381 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_128);
2384 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2385 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_64);
2388 snd_soc_component_update_bits(component, RT5682S_TDM_TCON_CTRL_1,
2389 RT5682S_TDM_BCLK_MS1_MASK, RT5682S_TDM_BCLK_MS1_32);
2392 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2399 static int rt5682s_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2401 struct snd_soc_component *component = dai->component;
2402 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2404 rt5682s->bclk[dai->id] = ratio;
2408 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2409 RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_64);
2412 snd_soc_component_update_bits(component, RT5682S_ADDA_CLK_2,
2413 RT5682S_I2S2_BCLK_MS2_MASK, RT5682S_I2S2_BCLK_MS2_32);
2416 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2423 static int rt5682s_set_bias_level(struct snd_soc_component *component,
2424 enum snd_soc_bias_level level)
2426 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2429 case SND_SOC_BIAS_PREPARE:
2430 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2431 RT5682S_PWR_LDO, RT5682S_PWR_LDO);
2433 case SND_SOC_BIAS_STANDBY:
2434 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2435 RT5682S_DIG_GATE_CTRL, RT5682S_DIG_GATE_CTRL);
2437 case SND_SOC_BIAS_OFF:
2438 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_1,
2439 RT5682S_DIG_GATE_CTRL | RT5682S_PWR_LDO, 0);
2441 case SND_SOC_BIAS_ON:
2448 #ifdef CONFIG_COMMON_CLK
2449 #define CLK_PLL2_FIN 48000000
2450 #define CLK_48 48000
2451 #define CLK_44 44100
2453 static bool rt5682s_clk_check(struct rt5682s_priv *rt5682s)
2455 if (!rt5682s->master[RT5682S_AIF1]) {
2456 dev_dbg(rt5682s->component->dev, "dai clk fmt not set correctly\n");
2462 static int rt5682s_wclk_prepare(struct clk_hw *hw)
2464 struct rt5682s_priv *rt5682s =
2465 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2466 struct snd_soc_component *component = rt5682s->component;
2467 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2469 if (!rt5682s_clk_check(rt5682s))
2472 snd_soc_dapm_mutex_lock(dapm);
2474 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2475 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2476 RT5682S_PWR_MB, RT5682S_PWR_MB);
2478 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2479 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2480 RT5682S_PWR_VREF2 | RT5682S_PWR_FV2, RT5682S_PWR_VREF2);
2481 usleep_range(15000, 20000);
2482 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2483 RT5682S_PWR_FV2, RT5682S_PWR_FV2);
2485 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2486 /* Only need to power PLLB due to the rate set restriction */
2487 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLLB");
2488 snd_soc_dapm_sync_unlocked(dapm);
2490 snd_soc_dapm_mutex_unlock(dapm);
2495 static void rt5682s_wclk_unprepare(struct clk_hw *hw)
2497 struct rt5682s_priv *rt5682s =
2498 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2499 struct snd_soc_component *component = rt5682s->component;
2500 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2502 if (!rt5682s_clk_check(rt5682s))
2505 snd_soc_dapm_mutex_lock(dapm);
2507 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2508 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2509 if (!rt5682s->jack_type)
2510 snd_soc_component_update_bits(component, RT5682S_PWR_ANLG_1,
2511 RT5682S_PWR_VREF2 | RT5682S_PWR_FV2 | RT5682S_PWR_MB, 0);
2513 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2514 snd_soc_dapm_disable_pin_unlocked(dapm, "PLLB");
2515 snd_soc_dapm_sync_unlocked(dapm);
2517 snd_soc_dapm_mutex_unlock(dapm);
2520 static unsigned long rt5682s_wclk_recalc_rate(struct clk_hw *hw,
2521 unsigned long parent_rate)
2523 struct rt5682s_priv *rt5682s =
2524 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2525 struct snd_soc_component *component = rt5682s->component;
2526 const char * const clk_name = clk_hw_get_name(hw);
2528 if (!rt5682s_clk_check(rt5682s))
2531 * Only accept to set wclk rate to 44.1k or 48kHz.
2533 if (rt5682s->lrck[RT5682S_AIF1] != CLK_48 &&
2534 rt5682s->lrck[RT5682S_AIF1] != CLK_44) {
2535 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2536 __func__, clk_name, CLK_44, CLK_48);
2540 return rt5682s->lrck[RT5682S_AIF1];
2543 static long rt5682s_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2544 unsigned long *parent_rate)
2546 struct rt5682s_priv *rt5682s =
2547 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2548 struct snd_soc_component *component = rt5682s->component;
2549 const char * const clk_name = clk_hw_get_name(hw);
2551 if (!rt5682s_clk_check(rt5682s))
2554 * Only accept to set wclk rate to 44.1k or 48kHz.
2555 * It will force to 48kHz if not both.
2557 if (rate != CLK_48 && rate != CLK_44) {
2558 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2559 __func__, clk_name, CLK_44, CLK_48);
2566 static int rt5682s_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2567 unsigned long parent_rate)
2569 struct rt5682s_priv *rt5682s =
2570 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_WCLK_IDX]);
2571 struct snd_soc_component *component = rt5682s->component;
2572 struct clk *parent_clk;
2573 const char * const clk_name = clk_hw_get_name(hw);
2574 unsigned int clk_pll2_fout;
2576 if (!rt5682s_clk_check(rt5682s))
2580 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2581 * it is fixed or set to 48MHz before setting wclk rate. It's a
2582 * temporary limitation. Only accept 48MHz clk as the clk provider.
2584 * It will set the codec anyway by assuming mclk is 48MHz.
2586 parent_clk = clk_get_parent(hw->clk);
2588 dev_warn(component->dev,
2589 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2592 if (parent_rate != CLK_PLL2_FIN)
2593 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2594 clk_name, CLK_PLL2_FIN);
2597 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2600 clk_pll2_fout = rate * 512;
2601 rt5682s_set_component_pll(component, RT5682S_PLL2, RT5682S_PLL_S_MCLK,
2602 CLK_PLL2_FIN, clk_pll2_fout);
2604 rt5682s_set_component_sysclk(component, RT5682S_SCLK_S_PLL2, 0,
2605 clk_pll2_fout, SND_SOC_CLOCK_IN);
2607 rt5682s->lrck[RT5682S_AIF1] = rate;
2612 static unsigned long rt5682s_bclk_recalc_rate(struct clk_hw *hw,
2613 unsigned long parent_rate)
2615 struct rt5682s_priv *rt5682s =
2616 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2617 struct snd_soc_component *component = rt5682s->component;
2618 unsigned int bclks_per_wclk;
2620 bclks_per_wclk = snd_soc_component_read(component, RT5682S_TDM_TCON_CTRL_1);
2622 switch (bclks_per_wclk & RT5682S_TDM_BCLK_MS1_MASK) {
2623 case RT5682S_TDM_BCLK_MS1_256:
2624 return parent_rate * 256;
2625 case RT5682S_TDM_BCLK_MS1_128:
2626 return parent_rate * 128;
2627 case RT5682S_TDM_BCLK_MS1_64:
2628 return parent_rate * 64;
2629 case RT5682S_TDM_BCLK_MS1_32:
2630 return parent_rate * 32;
2636 static unsigned long rt5682s_bclk_get_factor(unsigned long rate,
2637 unsigned long parent_rate)
2639 unsigned long factor;
2641 factor = rate / parent_rate;
2644 else if (factor < 128)
2646 else if (factor < 256)
2652 static long rt5682s_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2653 unsigned long *parent_rate)
2655 struct rt5682s_priv *rt5682s =
2656 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2657 unsigned long factor;
2659 if (!*parent_rate || !rt5682s_clk_check(rt5682s))
2663 * BCLK rates are set as a multiplier of WCLK in HW.
2664 * We don't allow changing the parent WCLK. We just do
2665 * some rounding down based on the parent WCLK rate
2666 * and find the appropriate multiplier of BCLK to
2667 * get the rounded down BCLK value.
2669 factor = rt5682s_bclk_get_factor(rate, *parent_rate);
2671 return *parent_rate * factor;
2674 static int rt5682s_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2675 unsigned long parent_rate)
2677 struct rt5682s_priv *rt5682s =
2678 container_of(hw, struct rt5682s_priv, dai_clks_hw[RT5682S_DAI_BCLK_IDX]);
2679 struct snd_soc_component *component = rt5682s->component;
2680 struct snd_soc_dai *dai;
2681 unsigned long factor;
2683 if (!rt5682s_clk_check(rt5682s))
2686 factor = rt5682s_bclk_get_factor(rate, parent_rate);
2688 for_each_component_dais(component, dai)
2689 if (dai->id == RT5682S_AIF1)
2692 dev_err(component->dev, "dai %d not found in component\n",
2697 return rt5682s_set_bclk1_ratio(dai, factor);
2700 static const struct clk_ops rt5682s_dai_clk_ops[RT5682S_DAI_NUM_CLKS] = {
2701 [RT5682S_DAI_WCLK_IDX] = {
2702 .prepare = rt5682s_wclk_prepare,
2703 .unprepare = rt5682s_wclk_unprepare,
2704 .recalc_rate = rt5682s_wclk_recalc_rate,
2705 .round_rate = rt5682s_wclk_round_rate,
2706 .set_rate = rt5682s_wclk_set_rate,
2708 [RT5682S_DAI_BCLK_IDX] = {
2709 .recalc_rate = rt5682s_bclk_recalc_rate,
2710 .round_rate = rt5682s_bclk_round_rate,
2711 .set_rate = rt5682s_bclk_set_rate,
2715 static int rt5682s_register_dai_clks(struct snd_soc_component *component)
2717 struct device *dev = component->dev;
2718 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2719 struct rt5682s_platform_data *pdata = &rt5682s->pdata;
2720 struct clk_hw *dai_clk_hw;
2723 for (i = 0; i < RT5682S_DAI_NUM_CLKS; ++i) {
2724 struct clk_init_data init = { };
2725 struct clk_parent_data parent_data;
2726 const struct clk_hw *parent;
2728 dai_clk_hw = &rt5682s->dai_clks_hw[i];
2731 case RT5682S_DAI_WCLK_IDX:
2732 /* Make MCLK the parent of WCLK */
2733 if (rt5682s->mclk) {
2734 parent_data = (struct clk_parent_data){
2737 init.parent_data = &parent_data;
2738 init.num_parents = 1;
2741 case RT5682S_DAI_BCLK_IDX:
2742 /* Make WCLK the parent of BCLK */
2743 parent = &rt5682s->dai_clks_hw[RT5682S_DAI_WCLK_IDX];
2744 init.parent_hws = &parent;
2745 init.num_parents = 1;
2748 dev_err(dev, "Invalid clock index\n");
2752 init.name = pdata->dai_clk_names[i];
2753 init.ops = &rt5682s_dai_clk_ops[i];
2754 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2755 dai_clk_hw->init = &init;
2757 ret = devm_clk_hw_register(dev, dai_clk_hw);
2759 dev_warn(dev, "Failed to register %s: %d\n", init.name, ret);
2764 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, dai_clk_hw);
2766 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2767 init.name, dev_name(dev));
2776 static int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2778 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2781 /* Check if MCLK provided */
2782 rt5682s->mclk = devm_clk_get(component->dev, "mclk");
2783 if (IS_ERR(rt5682s->mclk)) {
2784 if (PTR_ERR(rt5682s->mclk) != -ENOENT) {
2785 ret = PTR_ERR(rt5682s->mclk);
2788 rt5682s->mclk = NULL;
2791 /* Register CCF DAI clock control */
2792 ret = rt5682s_register_dai_clks(component);
2796 /* Initial setup for CCF */
2797 rt5682s->lrck[RT5682S_AIF1] = CLK_48;
2802 static inline int rt5682s_dai_probe_clks(struct snd_soc_component *component)
2806 #endif /* CONFIG_COMMON_CLK */
2808 static int rt5682s_probe(struct snd_soc_component *component)
2810 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2811 struct snd_soc_dapm_context *dapm = &component->dapm;
2814 rt5682s->component = component;
2816 ret = rt5682s_dai_probe_clks(component);
2820 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2821 snd_soc_dapm_disable_pin(dapm, "Vref2");
2822 snd_soc_dapm_sync(dapm);
2826 static void rt5682s_remove(struct snd_soc_component *component)
2828 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2830 rt5682s_reset(rt5682s);
2834 static int rt5682s_suspend(struct snd_soc_component *component)
2836 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2838 cancel_delayed_work_sync(&rt5682s->jack_detect_work);
2839 cancel_delayed_work_sync(&rt5682s->jd_check_work);
2841 if (rt5682s->hs_jack)
2842 rt5682s->jack_type = rt5682s_headset_detect(component, 0);
2844 regcache_cache_only(rt5682s->regmap, true);
2845 regcache_mark_dirty(rt5682s->regmap);
2850 static int rt5682s_resume(struct snd_soc_component *component)
2852 struct rt5682s_priv *rt5682s = snd_soc_component_get_drvdata(component);
2854 regcache_cache_only(rt5682s->regmap, false);
2855 regcache_sync(rt5682s->regmap);
2857 if (rt5682s->hs_jack) {
2858 mod_delayed_work(system_power_efficient_wq,
2859 &rt5682s->jack_detect_work, msecs_to_jiffies(0));
2865 #define rt5682s_suspend NULL
2866 #define rt5682s_resume NULL
2869 static const struct snd_soc_dai_ops rt5682s_aif1_dai_ops = {
2870 .hw_params = rt5682s_hw_params,
2871 .set_fmt = rt5682s_set_dai_fmt,
2872 .set_tdm_slot = rt5682s_set_tdm_slot,
2873 .set_bclk_ratio = rt5682s_set_bclk1_ratio,
2876 static const struct snd_soc_dai_ops rt5682s_aif2_dai_ops = {
2877 .hw_params = rt5682s_hw_params,
2878 .set_fmt = rt5682s_set_dai_fmt,
2879 .set_bclk_ratio = rt5682s_set_bclk2_ratio,
2882 static const struct snd_soc_component_driver rt5682s_soc_component_dev = {
2883 .probe = rt5682s_probe,
2884 .remove = rt5682s_remove,
2885 .suspend = rt5682s_suspend,
2886 .resume = rt5682s_resume,
2887 .set_bias_level = rt5682s_set_bias_level,
2888 .controls = rt5682s_snd_controls,
2889 .num_controls = ARRAY_SIZE(rt5682s_snd_controls),
2890 .dapm_widgets = rt5682s_dapm_widgets,
2891 .num_dapm_widgets = ARRAY_SIZE(rt5682s_dapm_widgets),
2892 .dapm_routes = rt5682s_dapm_routes,
2893 .num_dapm_routes = ARRAY_SIZE(rt5682s_dapm_routes),
2894 .set_sysclk = rt5682s_set_component_sysclk,
2895 .set_pll = rt5682s_set_component_pll,
2896 .set_jack = rt5682s_set_jack_detect,
2897 .use_pmdown_time = 1,
2899 .non_legacy_dai_naming = 1,
2902 static int rt5682s_parse_dt(struct rt5682s_priv *rt5682s, struct device *dev)
2904 device_property_read_u32(dev, "realtek,dmic1-data-pin",
2905 &rt5682s->pdata.dmic1_data_pin);
2906 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2907 &rt5682s->pdata.dmic1_clk_pin);
2908 device_property_read_u32(dev, "realtek,jd-src",
2909 &rt5682s->pdata.jd_src);
2910 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2911 &rt5682s->pdata.dmic_clk_rate);
2912 device_property_read_u32(dev, "realtek,dmic-delay-ms",
2913 &rt5682s->pdata.dmic_delay);
2914 device_property_read_u32(dev, "realtek,amic-delay-ms",
2915 &rt5682s->pdata.amic_delay);
2917 rt5682s->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2918 "realtek,ldo1-en-gpios", 0);
2920 if (device_property_read_string_array(dev, "clock-output-names",
2921 rt5682s->pdata.dai_clk_names,
2922 RT5682S_DAI_NUM_CLKS) < 0)
2923 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
2924 rt5682s->pdata.dai_clk_names[RT5682S_DAI_WCLK_IDX],
2925 rt5682s->pdata.dai_clk_names[RT5682S_DAI_BCLK_IDX]);
2927 rt5682s->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
2928 "realtek,dmic-clk-driving-high");
2933 static void rt5682s_calibrate(struct rt5682s_priv *rt5682s)
2935 unsigned int count, value;
2937 mutex_lock(&rt5682s->calibrate_mutex);
2939 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xaa80);
2940 usleep_range(15000, 20000);
2941 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0xfa80);
2942 regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x01c0);
2943 regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0380);
2944 regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x8000);
2945 regmap_write(rt5682s->regmap, RT5682S_ADDA_CLK_1, 0x1001);
2946 regmap_write(rt5682s->regmap, RT5682S_CHOP_DAC_2, 0x3030);
2947 regmap_write(rt5682s->regmap, RT5682S_CHOP_ADC, 0xb000);
2948 regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0x686c);
2949 regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5151);
2950 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0321);
2951 regmap_write(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2, 0x0004);
2952 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0x7c00);
2953 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_1, 0xfc00);
2955 for (count = 0; count < 60; count++) {
2956 regmap_read(rt5682s->regmap, RT5682S_HP_CALIB_ST_1, &value);
2957 if (!(value & 0x8000))
2960 usleep_range(10000, 10005);
2964 dev_err(rt5682s->component->dev, "HP Calibration Failure\n");
2966 /* restore settings */
2967 regmap_write(rt5682s->regmap, RT5682S_MICBIAS_2, 0x0180);
2968 regmap_write(rt5682s->regmap, RT5682S_CAL_REC, 0x5858);
2969 regmap_write(rt5682s->regmap, RT5682S_STO1_ADC_MIXER, 0xc0c4);
2970 regmap_write(rt5682s->regmap, RT5682S_HP_CALIB_CTRL_2, 0x0320);
2971 regmap_write(rt5682s->regmap, RT5682S_PWR_DIG_1, 0x00c0);
2972 regmap_write(rt5682s->regmap, RT5682S_PWR_ANLG_1, 0x0800);
2973 regmap_write(rt5682s->regmap, RT5682S_GLB_CLK, 0x0000);
2975 mutex_unlock(&rt5682s->calibrate_mutex);
2978 static const struct regmap_config rt5682s_regmap = {
2981 .max_register = RT5682S_MAX_REG,
2982 .volatile_reg = rt5682s_volatile_register,
2983 .readable_reg = rt5682s_readable_register,
2984 .cache_type = REGCACHE_RBTREE,
2985 .reg_defaults = rt5682s_reg,
2986 .num_reg_defaults = ARRAY_SIZE(rt5682s_reg),
2987 .use_single_read = true,
2988 .use_single_write = true,
2991 static struct snd_soc_dai_driver rt5682s_dai[] = {
2993 .name = "rt5682s-aif1",
2996 .stream_name = "AIF1 Playback",
2999 .rates = RT5682S_STEREO_RATES,
3000 .formats = RT5682S_FORMATS,
3003 .stream_name = "AIF1 Capture",
3006 .rates = RT5682S_STEREO_RATES,
3007 .formats = RT5682S_FORMATS,
3009 .ops = &rt5682s_aif1_dai_ops,
3012 .name = "rt5682s-aif2",
3015 .stream_name = "AIF2 Capture",
3018 .rates = RT5682S_STEREO_RATES,
3019 .formats = RT5682S_FORMATS,
3021 .ops = &rt5682s_aif2_dai_ops,
3025 static void rt5682s_i2c_disable_regulators(void *data)
3027 struct rt5682s_priv *rt5682s = data;
3029 regulator_bulk_disable(ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies);
3032 static int rt5682s_i2c_probe(struct i2c_client *i2c,
3033 const struct i2c_device_id *id)
3035 struct rt5682s_platform_data *pdata = dev_get_platdata(&i2c->dev);
3036 struct rt5682s_priv *rt5682s;
3040 rt5682s = devm_kzalloc(&i2c->dev, sizeof(struct rt5682s_priv), GFP_KERNEL);
3044 i2c_set_clientdata(i2c, rt5682s);
3046 rt5682s->pdata = i2s_default_platform_data;
3049 rt5682s->pdata = *pdata;
3051 rt5682s_parse_dt(rt5682s, &i2c->dev);
3053 rt5682s->regmap = devm_regmap_init_i2c(i2c, &rt5682s_regmap);
3054 if (IS_ERR(rt5682s->regmap)) {
3055 ret = PTR_ERR(rt5682s->regmap);
3056 dev_err(&i2c->dev, "Failed to allocate register map: %d\n", ret);
3060 for (i = 0; i < ARRAY_SIZE(rt5682s->supplies); i++)
3061 rt5682s->supplies[i].supply = rt5682s_supply_names[i];
3063 ret = devm_regulator_bulk_get(&i2c->dev,
3064 ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies);
3066 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3070 ret = devm_add_action_or_reset(&i2c->dev, rt5682s_i2c_disable_regulators, rt5682s);
3074 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682s->supplies), rt5682s->supplies);
3076 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3080 if (gpio_is_valid(rt5682s->pdata.ldo1_en)) {
3081 if (devm_gpio_request_one(&i2c->dev, rt5682s->pdata.ldo1_en,
3082 GPIOF_OUT_INIT_HIGH, "rt5682s"))
3083 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
3086 /* Sleep for 50 ms minimum */
3087 usleep_range(50000, 55000);
3089 regmap_read(rt5682s->regmap, RT5682S_DEVICE_ID, &val);
3090 if (val != DEVICE_ID) {
3091 dev_err(&i2c->dev, "Device with ID register %x is not rt5682s\n", val);
3095 rt5682s_reset(rt5682s);
3096 rt5682s_apply_patch_list(rt5682s, &i2c->dev);
3098 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_DIG_2,
3099 RT5682S_DLDO_I_LIMIT_MASK, RT5682S_DLDO_I_LIMIT_DIS);
3100 usleep_range(20000, 25000);
3102 mutex_init(&rt5682s->calibrate_mutex);
3103 mutex_init(&rt5682s->sar_mutex);
3104 rt5682s_calibrate(rt5682s);
3106 regmap_update_bits(rt5682s->regmap, RT5682S_MICBIAS_2,
3107 RT5682S_PWR_CLK25M_MASK | RT5682S_PWR_CLK1M_MASK,
3108 RT5682S_PWR_CLK25M_PD | RT5682S_PWR_CLK1M_PU);
3109 regmap_update_bits(rt5682s->regmap, RT5682S_PWR_ANLG_1,
3110 RT5682S_PWR_BG, RT5682S_PWR_BG);
3111 regmap_update_bits(rt5682s->regmap, RT5682S_HP_LOGIC_CTRL_2,
3112 RT5682S_HP_SIG_SRC_MASK, RT5682S_HP_SIG_SRC_1BIT_CTL);
3113 regmap_update_bits(rt5682s->regmap, RT5682S_HP_CHARGE_PUMP_2,
3114 RT5682S_PM_HP_MASK, RT5682S_PM_HP_HV);
3115 regmap_update_bits(rt5682s->regmap, RT5682S_HP_AMP_DET_CTL_1,
3116 RT5682S_CP_SW_SIZE_MASK, RT5682S_CP_SW_SIZE_M);
3119 switch (rt5682s->pdata.dmic1_data_pin) {
3120 case RT5682S_DMIC1_DATA_NULL:
3122 case RT5682S_DMIC1_DATA_GPIO2: /* share with LRCK2 */
3123 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3124 RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO2);
3125 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3126 RT5682S_GP2_PIN_MASK, RT5682S_GP2_PIN_DMIC_SDA);
3128 case RT5682S_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
3129 regmap_update_bits(rt5682s->regmap, RT5682S_DMIC_CTRL_1,
3130 RT5682S_DMIC_1_DP_MASK, RT5682S_DMIC_1_DP_GPIO5);
3131 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3132 RT5682S_GP5_PIN_MASK, RT5682S_GP5_PIN_DMIC_SDA);
3135 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
3140 switch (rt5682s->pdata.dmic1_clk_pin) {
3141 case RT5682S_DMIC1_CLK_NULL:
3143 case RT5682S_DMIC1_CLK_GPIO1: /* share with IRQ */
3144 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3145 RT5682S_GP1_PIN_MASK, RT5682S_GP1_PIN_DMIC_CLK);
3147 case RT5682S_DMIC1_CLK_GPIO3: /* share with BCLK2 */
3148 regmap_update_bits(rt5682s->regmap, RT5682S_GPIO_CTRL_1,
3149 RT5682S_GP3_PIN_MASK, RT5682S_GP3_PIN_DMIC_CLK);
3150 if (rt5682s->pdata.dmic_clk_driving_high)
3151 regmap_update_bits(rt5682s->regmap, RT5682S_PAD_DRIVING_CTRL,
3152 RT5682S_PAD_DRV_GP3_MASK, RT5682S_PAD_DRV_GP3_HIGH);
3155 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
3159 INIT_DELAYED_WORK(&rt5682s->jack_detect_work, rt5682s_jack_detect_handler);
3160 INIT_DELAYED_WORK(&rt5682s->jd_check_work, rt5682s_jd_check_handler);
3163 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, rt5682s_irq,
3164 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
3165 "rt5682s", rt5682s);
3167 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
3170 return devm_snd_soc_register_component(&i2c->dev, &rt5682s_soc_component_dev,
3171 rt5682s_dai, ARRAY_SIZE(rt5682s_dai));
3174 static void rt5682s_i2c_shutdown(struct i2c_client *client)
3176 struct rt5682s_priv *rt5682s = i2c_get_clientdata(client);
3178 disable_irq(client->irq);
3179 cancel_delayed_work_sync(&rt5682s->jack_detect_work);
3180 cancel_delayed_work_sync(&rt5682s->jd_check_work);
3182 rt5682s_reset(rt5682s);
3185 static int rt5682s_i2c_remove(struct i2c_client *client)
3187 rt5682s_i2c_shutdown(client);
3192 static const struct of_device_id rt5682s_of_match[] = {
3193 {.compatible = "realtek,rt5682s"},
3196 MODULE_DEVICE_TABLE(of, rt5682s_of_match);
3198 static const struct acpi_device_id rt5682s_acpi_match[] = {
3202 MODULE_DEVICE_TABLE(acpi, rt5682s_acpi_match);
3204 static const struct i2c_device_id rt5682s_i2c_id[] = {
3208 MODULE_DEVICE_TABLE(i2c, rt5682s_i2c_id);
3210 static struct i2c_driver rt5682s_i2c_driver = {
3213 .of_match_table = rt5682s_of_match,
3214 .acpi_match_table = rt5682s_acpi_match,
3215 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3217 .probe = rt5682s_i2c_probe,
3218 .remove = rt5682s_i2c_remove,
3219 .shutdown = rt5682s_i2c_shutdown,
3220 .id_table = rt5682s_i2c_id,
3222 module_i2c_driver(rt5682s_i2c_driver);
3224 MODULE_DESCRIPTION("ASoC RT5682I-VS driver");
3225 MODULE_AUTHOR("Derek Fang <derek.fang@realtek.com>");
3226 MODULE_LICENSE("GPL v2");