sound/soc/codecs/rt5682.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * rt5682.c  --  RT5682 ALSA SoC audio component driver
   4  *
   5  * Copyright 2018 Realtek Semiconductor Corp.
   6  * Author: Bard Liao <bardliao@realtek.com>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/pm.h>
  14 #include <linux/i2c.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/acpi.h>
  18 #include <linux/gpio.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/mutex.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/jack.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29 #include <sound/tlv.h>
  30 #include <sound/rt5682.h>
  31
  32 #include "rl6231.h"
  33 #include "rt5682.h"
  34
  35 #define RT5682_NUM_SUPPLIES 3
  36
  37 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
  38         "AVDD",
  39         "MICVDD",
  40         "VBAT",
  41 };
  42
  43 static const struct rt5682_platform_data i2s_default_platform_data = {
  44         .dmic1_data_pin = RT5682_DMIC1_DATA_GPIO2,
  45         .dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3,
  46         .jd_src = RT5682_JD1,
  47         .btndet_delay = 16,
  48 };
  49
  50 struct rt5682_priv {
  51         struct snd_soc_component *component;
  52         struct rt5682_platform_data pdata;
  53         struct regmap *regmap;
  54         struct snd_soc_jack *hs_jack;
  55         struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
  56         struct delayed_work jack_detect_work;
  57         struct delayed_work jd_check_work;
  58         struct mutex calibrate_mutex;
  59
  60         int sysclk;
  61         int sysclk_src;
  62         int lrck[RT5682_AIFS];
  63         int bclk[RT5682_AIFS];
  64         int master[RT5682_AIFS];
  65
  66         int pll_src;
  67         int pll_in;
  68         int pll_out;
  69
  70         int jack_type;
  71 };
  72
  73 static const struct reg_sequence patch_list[] = {
  74         {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
  75         {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
  76 };
  77
  78 static const struct reg_default rt5682_reg[] = {
  79         {0x0002, 0x8080},
  80         {0x0003, 0x8000},
  81         {0x0005, 0x0000},
  82         {0x0006, 0x0000},
  83         {0x0008, 0x800f},
  84         {0x000b, 0x0000},
  85         {0x0010, 0x4040},
  86         {0x0011, 0x0000},
  87         {0x0012, 0x1404},
  88         {0x0013, 0x1000},
  89         {0x0014, 0xa00a},
  90         {0x0015, 0x0404},
  91         {0x0016, 0x0404},
  92         {0x0019, 0xafaf},
  93         {0x001c, 0x2f2f},
  94         {0x001f, 0x0000},
  95         {0x0022, 0x5757},
  96         {0x0023, 0x0039},
  97         {0x0024, 0x000b},
  98         {0x0026, 0xc0c4},
  99         {0x0029, 0x8080},
 100         {0x002a, 0xa0a0},
 101         {0x002b, 0x0300},
 102         {0x0030, 0x0000},
 103         {0x003c, 0x0080},
 104         {0x0044, 0x0c0c},
 105         {0x0049, 0x0000},
 106         {0x0061, 0x0000},
 107         {0x0062, 0x0000},
 108         {0x0063, 0x003f},
 109         {0x0064, 0x0000},
 110         {0x0065, 0x0000},
 111         {0x0066, 0x0030},
 112         {0x0067, 0x0000},
 113         {0x006b, 0x0000},
 114         {0x006c, 0x0000},
 115         {0x006d, 0x2200},
 116         {0x006e, 0x0a10},
 117         {0x0070, 0x8000},
 118         {0x0071, 0x8000},
 119         {0x0073, 0x0000},
 120         {0x0074, 0x0000},
 121         {0x0075, 0x0002},
 122         {0x0076, 0x0001},
 123         {0x0079, 0x0000},
 124         {0x007a, 0x0000},
 125         {0x007b, 0x0000},
 126         {0x007c, 0x0100},
 127         {0x007e, 0x0000},
 128         {0x0080, 0x0000},
 129         {0x0081, 0x0000},
 130         {0x0082, 0x0000},
 131         {0x0083, 0x0000},
 132         {0x0084, 0x0000},
 133         {0x0085, 0x0000},
 134         {0x0086, 0x0005},
 135         {0x0087, 0x0000},
 136         {0x0088, 0x0000},
 137         {0x008c, 0x0003},
 138         {0x008d, 0x0000},
 139         {0x008e, 0x0060},
 140         {0x008f, 0x1000},
 141         {0x0091, 0x0c26},
 142         {0x0092, 0x0073},
 143         {0x0093, 0x0000},
 144         {0x0094, 0x0080},
 145         {0x0098, 0x0000},
 146         {0x009a, 0x0000},
 147         {0x009b, 0x0000},
 148         {0x009c, 0x0000},
 149         {0x009d, 0x0000},
 150         {0x009e, 0x100c},
 151         {0x009f, 0x0000},
 152         {0x00a0, 0x0000},
 153         {0x00a3, 0x0002},
 154         {0x00a4, 0x0001},
 155         {0x00ae, 0x2040},
 156         {0x00af, 0x0000},
 157         {0x00b6, 0x0000},
 158         {0x00b7, 0x0000},
 159         {0x00b8, 0x0000},
 160         {0x00b9, 0x0002},
 161         {0x00be, 0x0000},
 162         {0x00c0, 0x0160},
 163         {0x00c1, 0x82a0},
 164         {0x00c2, 0x0000},
 165         {0x00d0, 0x0000},
 166         {0x00d1, 0x2244},
 167         {0x00d2, 0x3300},
 168         {0x00d3, 0x2200},
 169         {0x00d4, 0x0000},
 170         {0x00d9, 0x0009},
 171         {0x00da, 0x0000},
 172         {0x00db, 0x0000},
 173         {0x00dc, 0x00c0},
 174         {0x00dd, 0x2220},
 175         {0x00de, 0x3131},
 176         {0x00df, 0x3131},
 177         {0x00e0, 0x3131},
 178         {0x00e2, 0x0000},
 179         {0x00e3, 0x4000},
 180         {0x00e4, 0x0aa0},
 181         {0x00e5, 0x3131},
 182         {0x00e6, 0x3131},
 183         {0x00e7, 0x3131},
 184         {0x00e8, 0x3131},
 185         {0x00ea, 0xb320},
 186         {0x00eb, 0x0000},
 187         {0x00f0, 0x0000},
 188         {0x00f1, 0x00d0},
 189         {0x00f2, 0x00d0},
 190         {0x00f6, 0x0000},
 191         {0x00fa, 0x0000},
 192         {0x00fb, 0x0000},
 193         {0x00fc, 0x0000},
 194         {0x00fd, 0x0000},
 195         {0x00fe, 0x10ec},
 196         {0x00ff, 0x6530},
 197         {0x0100, 0xa0a0},
 198         {0x010b, 0x0000},
 199         {0x010c, 0xae00},
 200         {0x010d, 0xaaa0},
 201         {0x010e, 0x8aa2},
 202         {0x010f, 0x02a2},
 203         {0x0110, 0xc000},
 204         {0x0111, 0x04a2},
 205         {0x0112, 0x2800},
 206         {0x0113, 0x0000},
 207         {0x0117, 0x0100},
 208         {0x0125, 0x0410},
 209         {0x0132, 0x6026},
 210         {0x0136, 0x5555},
 211         {0x0138, 0x3700},
 212         {0x013a, 0x2000},
 213         {0x013b, 0x2000},
 214         {0x013c, 0x2005},
 215         {0x013f, 0x0000},
 216         {0x0142, 0x0000},
 217         {0x0145, 0x0002},
 218         {0x0146, 0x0000},
 219         {0x0147, 0x0000},
 220         {0x0148, 0x0000},
 221         {0x0149, 0x0000},
 222         {0x0150, 0x79a1},
 223         {0x0151, 0x0000},
 224         {0x0160, 0x4ec0},
 225         {0x0161, 0x0080},
 226         {0x0162, 0x0200},
 227         {0x0163, 0x0800},
 228         {0x0164, 0x0000},
 229         {0x0165, 0x0000},
 230         {0x0166, 0x0000},
 231         {0x0167, 0x000f},
 232         {0x0168, 0x000f},
 233         {0x0169, 0x0021},
 234         {0x0190, 0x413d},
 235         {0x0194, 0x0000},
 236         {0x0195, 0x0000},
 237         {0x0197, 0x0022},
 238         {0x0198, 0x0000},
 239         {0x0199, 0x0000},
 240         {0x01af, 0x0000},
 241         {0x01b0, 0x0400},
 242         {0x01b1, 0x0000},
 243         {0x01b2, 0x0000},
 244         {0x01b3, 0x0000},
 245         {0x01b4, 0x0000},
 246         {0x01b5, 0x0000},
 247         {0x01b6, 0x01c3},
 248         {0x01b7, 0x02a0},
 249         {0x01b8, 0x03e9},
 250         {0x01b9, 0x1389},
 251         {0x01ba, 0xc351},
 252         {0x01bb, 0x0009},
 253         {0x01bc, 0x0018},
 254         {0x01bd, 0x002a},
 255         {0x01be, 0x004c},
 256         {0x01bf, 0x0097},
 257         {0x01c0, 0x433d},
 258         {0x01c2, 0x0000},
 259         {0x01c3, 0x0000},
 260         {0x01c4, 0x0000},
 261         {0x01c5, 0x0000},
 262         {0x01c6, 0x0000},
 263         {0x01c7, 0x0000},
 264         {0x01c8, 0x40af},
 265         {0x01c9, 0x0702},
 266         {0x01ca, 0x0000},
 267         {0x01cb, 0x0000},
 268         {0x01cc, 0x5757},
 269         {0x01cd, 0x5757},
 270         {0x01ce, 0x5757},
 271         {0x01cf, 0x5757},
 272         {0x01d0, 0x5757},
 273         {0x01d1, 0x5757},
 274         {0x01d2, 0x5757},
 275         {0x01d3, 0x5757},
 276         {0x01d4, 0x5757},
 277         {0x01d5, 0x5757},
 278         {0x01d6, 0x0000},
 279         {0x01d7, 0x0008},
 280         {0x01d8, 0x0029},
 281         {0x01d9, 0x3333},
 282         {0x01da, 0x0000},
 283         {0x01db, 0x0004},
 284         {0x01dc, 0x0000},
 285         {0x01de, 0x7c00},
 286         {0x01df, 0x0320},
 287         {0x01e0, 0x06a1},
 288         {0x01e1, 0x0000},
 289         {0x01e2, 0x0000},
 290         {0x01e3, 0x0000},
 291         {0x01e4, 0x0000},
 292         {0x01e6, 0x0001},
 293         {0x01e7, 0x0000},
 294         {0x01e8, 0x0000},
 295         {0x01ea, 0x0000},
 296         {0x01eb, 0x0000},
 297         {0x01ec, 0x0000},
 298         {0x01ed, 0x0000},
 299         {0x01ee, 0x0000},
 300         {0x01ef, 0x0000},
 301         {0x01f0, 0x0000},
 302         {0x01f1, 0x0000},
 303         {0x01f2, 0x0000},
 304         {0x01f3, 0x0000},
 305         {0x01f4, 0x0000},
 306         {0x0210, 0x6297},
 307         {0x0211, 0xa005},
 308         {0x0212, 0x824c},
 309         {0x0213, 0xf7ff},
 310         {0x0214, 0xf24c},
 311         {0x0215, 0x0102},
 312         {0x0216, 0x00a3},
 313         {0x0217, 0x0048},
 314         {0x0218, 0xa2c0},
 315         {0x0219, 0x0400},
 316         {0x021a, 0x00c8},
 317         {0x021b, 0x00c0},
 318         {0x021c, 0x0000},
 319         {0x0250, 0x4500},
 320         {0x0251, 0x40b3},
 321         {0x0252, 0x0000},
 322         {0x0253, 0x0000},
 323         {0x0254, 0x0000},
 324         {0x0255, 0x0000},
 325         {0x0256, 0x0000},
 326         {0x0257, 0x0000},
 327         {0x0258, 0x0000},
 328         {0x0259, 0x0000},
 329         {0x025a, 0x0005},
 330         {0x0270, 0x0000},
 331         {0x02ff, 0x0110},
 332         {0x0300, 0x001f},
 333         {0x0301, 0x032c},
 334         {0x0302, 0x5f21},
 335         {0x0303, 0x4000},
 336         {0x0304, 0x4000},
 337         {0x0305, 0x06d5},
 338         {0x0306, 0x8000},
 339         {0x0307, 0x0700},
 340         {0x0310, 0x4560},
 341         {0x0311, 0xa4a8},
 342         {0x0312, 0x7418},
 343         {0x0313, 0x0000},
 344         {0x0314, 0x0006},
 345         {0x0315, 0xffff},
 346         {0x0316, 0xc400},
 347         {0x0317, 0x0000},
 348         {0x03c0, 0x7e00},
 349         {0x03c1, 0x8000},
 350         {0x03c2, 0x8000},
 351         {0x03c3, 0x8000},
 352         {0x03c4, 0x8000},
 353         {0x03c5, 0x8000},
 354         {0x03c6, 0x8000},
 355         {0x03c7, 0x8000},
 356         {0x03c8, 0x8000},
 357         {0x03c9, 0x8000},
 358         {0x03ca, 0x8000},
 359         {0x03cb, 0x8000},
 360         {0x03cc, 0x8000},
 361         {0x03d0, 0x0000},
 362         {0x03d1, 0x0000},
 363         {0x03d2, 0x0000},
 364         {0x03d3, 0x0000},
 365         {0x03d4, 0x2000},
 366         {0x03d5, 0x2000},
 367         {0x03d6, 0x0000},
 368         {0x03d7, 0x0000},
 369         {0x03d8, 0x2000},
 370         {0x03d9, 0x2000},
 371         {0x03da, 0x2000},
 372         {0x03db, 0x2000},
 373         {0x03dc, 0x0000},
 374         {0x03dd, 0x0000},
 375         {0x03de, 0x0000},
 376         {0x03df, 0x2000},
 377         {0x03e0, 0x0000},
 378         {0x03e1, 0x0000},
 379         {0x03e2, 0x0000},
 380         {0x03e3, 0x0000},
 381         {0x03e4, 0x0000},
 382         {0x03e5, 0x0000},
 383         {0x03e6, 0x0000},
 384         {0x03e7, 0x0000},
 385         {0x03e8, 0x0000},
 386         {0x03e9, 0x0000},
 387         {0x03ea, 0x0000},
 388         {0x03eb, 0x0000},
 389         {0x03ec, 0x0000},
 390         {0x03ed, 0x0000},
 391         {0x03ee, 0x0000},
 392         {0x03ef, 0x0000},
 393         {0x03f0, 0x0800},
 394         {0x03f1, 0x0800},
 395         {0x03f2, 0x0800},
 396         {0x03f3, 0x0800},
 397 };
 398
 399 static bool rt5682_volatile_register(struct device *dev, unsigned int reg)
 400 {
 401         switch (reg) {
 402         case RT5682_RESET:
 403         case RT5682_CBJ_CTRL_2:
 404         case RT5682_INT_ST_1:
 405         case RT5682_4BTN_IL_CMD_1:
 406         case RT5682_AJD1_CTRL:
 407         case RT5682_HP_CALIB_CTRL_1:
 408         case RT5682_DEVICE_ID:
 409         case RT5682_I2C_MODE:
 410         case RT5682_HP_CALIB_CTRL_10:
 411         case RT5682_EFUSE_CTRL_2:
 412         case RT5682_JD_TOP_VC_VTRL:
 413         case RT5682_HP_IMP_SENS_CTRL_19:
 414         case RT5682_IL_CMD_1:
 415         case RT5682_SAR_IL_CMD_2:
 416         case RT5682_SAR_IL_CMD_4:
 417         case RT5682_SAR_IL_CMD_10:
 418         case RT5682_SAR_IL_CMD_11:
 419         case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
 420         case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
 421                 return true;
 422         default:
 423                 return false;
 424         }
 425 }
 426
 427 static bool rt5682_readable_register(struct device *dev, unsigned int reg)
 428 {
 429         switch (reg) {
 430         case RT5682_RESET:
 431         case RT5682_VERSION_ID:
 432         case RT5682_VENDOR_ID:
 433         case RT5682_DEVICE_ID:
 434         case RT5682_HP_CTRL_1:
 435         case RT5682_HP_CTRL_2:
 436         case RT5682_HPL_GAIN:
 437         case RT5682_HPR_GAIN:
 438         case RT5682_I2C_CTRL:
 439         case RT5682_CBJ_BST_CTRL:
 440         case RT5682_CBJ_CTRL_1:
 441         case RT5682_CBJ_CTRL_2:
 442         case RT5682_CBJ_CTRL_3:
 443         case RT5682_CBJ_CTRL_4:
 444         case RT5682_CBJ_CTRL_5:
 445         case RT5682_CBJ_CTRL_6:
 446         case RT5682_CBJ_CTRL_7:
 447         case RT5682_DAC1_DIG_VOL:
 448         case RT5682_STO1_ADC_DIG_VOL:
 449         case RT5682_STO1_ADC_BOOST:
 450         case RT5682_HP_IMP_GAIN_1:
 451         case RT5682_HP_IMP_GAIN_2:
 452         case RT5682_SIDETONE_CTRL:
 453         case RT5682_STO1_ADC_MIXER:
 454         case RT5682_AD_DA_MIXER:
 455         case RT5682_STO1_DAC_MIXER:
 456         case RT5682_A_DAC1_MUX:
 457         case RT5682_DIG_INF2_DATA:
 458         case RT5682_REC_MIXER:
 459         case RT5682_CAL_REC:
 460         case RT5682_ALC_BACK_GAIN:
 461         case RT5682_PWR_DIG_1:
 462         case RT5682_PWR_DIG_2:
 463         case RT5682_PWR_ANLG_1:
 464         case RT5682_PWR_ANLG_2:
 465         case RT5682_PWR_ANLG_3:
 466         case RT5682_PWR_MIXER:
 467         case RT5682_PWR_VOL:
 468         case RT5682_CLK_DET:
 469         case RT5682_RESET_LPF_CTRL:
 470         case RT5682_RESET_HPF_CTRL:
 471         case RT5682_DMIC_CTRL_1:
 472         case RT5682_I2S1_SDP:
 473         case RT5682_I2S2_SDP:
 474         case RT5682_ADDA_CLK_1:
 475         case RT5682_ADDA_CLK_2:
 476         case RT5682_I2S1_F_DIV_CTRL_1:
 477         case RT5682_I2S1_F_DIV_CTRL_2:
 478         case RT5682_TDM_CTRL:
 479         case RT5682_TDM_ADDA_CTRL_1:
 480         case RT5682_TDM_ADDA_CTRL_2:
 481         case RT5682_DATA_SEL_CTRL_1:
 482         case RT5682_TDM_TCON_CTRL:
 483         case RT5682_GLB_CLK:
 484         case RT5682_PLL_CTRL_1:
 485         case RT5682_PLL_CTRL_2:
 486         case RT5682_PLL_TRACK_1:
 487         case RT5682_PLL_TRACK_2:
 488         case RT5682_PLL_TRACK_3:
 489         case RT5682_PLL_TRACK_4:
 490         case RT5682_PLL_TRACK_5:
 491         case RT5682_PLL_TRACK_6:
 492         case RT5682_PLL_TRACK_11:
 493         case RT5682_SDW_REF_CLK:
 494         case RT5682_DEPOP_1:
 495         case RT5682_DEPOP_2:
 496         case RT5682_HP_CHARGE_PUMP_1:
 497         case RT5682_HP_CHARGE_PUMP_2:
 498         case RT5682_MICBIAS_1:
 499         case RT5682_MICBIAS_2:
 500         case RT5682_PLL_TRACK_12:
 501         case RT5682_PLL_TRACK_14:
 502         case RT5682_PLL2_CTRL_1:
 503         case RT5682_PLL2_CTRL_2:
 504         case RT5682_PLL2_CTRL_3:
 505         case RT5682_PLL2_CTRL_4:
 506         case RT5682_RC_CLK_CTRL:
 507         case RT5682_I2S_M_CLK_CTRL_1:
 508         case RT5682_I2S2_F_DIV_CTRL_1:
 509         case RT5682_I2S2_F_DIV_CTRL_2:
 510         case RT5682_EQ_CTRL_1:
 511         case RT5682_EQ_CTRL_2:
 512         case RT5682_IRQ_CTRL_1:
 513         case RT5682_IRQ_CTRL_2:
 514         case RT5682_IRQ_CTRL_3:
 515         case RT5682_IRQ_CTRL_4:
 516         case RT5682_INT_ST_1:
 517         case RT5682_GPIO_CTRL_1:
 518         case RT5682_GPIO_CTRL_2:
 519         case RT5682_GPIO_CTRL_3:
 520         case RT5682_HP_AMP_DET_CTRL_1:
 521         case RT5682_HP_AMP_DET_CTRL_2:
 522         case RT5682_MID_HP_AMP_DET:
 523         case RT5682_LOW_HP_AMP_DET:
 524         case RT5682_DELAY_BUF_CTRL:
 525         case RT5682_SV_ZCD_1:
 526         case RT5682_SV_ZCD_2:
 527         case RT5682_IL_CMD_1:
 528         case RT5682_IL_CMD_2:
 529         case RT5682_IL_CMD_3:
 530         case RT5682_IL_CMD_4:
 531         case RT5682_IL_CMD_5:
 532         case RT5682_IL_CMD_6:
 533         case RT5682_4BTN_IL_CMD_1:
 534         case RT5682_4BTN_IL_CMD_2:
 535         case RT5682_4BTN_IL_CMD_3:
 536         case RT5682_4BTN_IL_CMD_4:
 537         case RT5682_4BTN_IL_CMD_5:
 538         case RT5682_4BTN_IL_CMD_6:
 539         case RT5682_4BTN_IL_CMD_7:
 540         case RT5682_ADC_STO1_HP_CTRL_1:
 541         case RT5682_ADC_STO1_HP_CTRL_2:
 542         case RT5682_AJD1_CTRL:
 543         case RT5682_JD1_THD:
 544         case RT5682_JD2_THD:
 545         case RT5682_JD_CTRL_1:
 546         case RT5682_DUMMY_1:
 547         case RT5682_DUMMY_2:
 548         case RT5682_DUMMY_3:
 549         case RT5682_DAC_ADC_DIG_VOL1:
 550         case RT5682_BIAS_CUR_CTRL_2:
 551         case RT5682_BIAS_CUR_CTRL_3:
 552         case RT5682_BIAS_CUR_CTRL_4:
 553         case RT5682_BIAS_CUR_CTRL_5:
 554         case RT5682_BIAS_CUR_CTRL_6:
 555         case RT5682_BIAS_CUR_CTRL_7:
 556         case RT5682_BIAS_CUR_CTRL_8:
 557         case RT5682_BIAS_CUR_CTRL_9:
 558         case RT5682_BIAS_CUR_CTRL_10:
 559         case RT5682_VREF_REC_OP_FB_CAP_CTRL:
 560         case RT5682_CHARGE_PUMP_1:
 561         case RT5682_DIG_IN_CTRL_1:
 562         case RT5682_PAD_DRIVING_CTRL:
 563         case RT5682_SOFT_RAMP_DEPOP:
 564         case RT5682_CHOP_DAC:
 565         case RT5682_CHOP_ADC:
 566         case RT5682_CALIB_ADC_CTRL:
 567         case RT5682_VOL_TEST:
 568         case RT5682_SPKVDD_DET_STA:
 569         case RT5682_TEST_MODE_CTRL_1:
 570         case RT5682_TEST_MODE_CTRL_2:
 571         case RT5682_TEST_MODE_CTRL_3:
 572         case RT5682_TEST_MODE_CTRL_4:
 573         case RT5682_TEST_MODE_CTRL_5:
 574         case RT5682_PLL1_INTERNAL:
 575         case RT5682_PLL2_INTERNAL:
 576         case RT5682_STO_NG2_CTRL_1:
 577         case RT5682_STO_NG2_CTRL_2:
 578         case RT5682_STO_NG2_CTRL_3:
 579         case RT5682_STO_NG2_CTRL_4:
 580         case RT5682_STO_NG2_CTRL_5:
 581         case RT5682_STO_NG2_CTRL_6:
 582         case RT5682_STO_NG2_CTRL_7:
 583         case RT5682_STO_NG2_CTRL_8:
 584         case RT5682_STO_NG2_CTRL_9:
 585         case RT5682_STO_NG2_CTRL_10:
 586         case RT5682_STO1_DAC_SIL_DET:
 587         case RT5682_SIL_PSV_CTRL1:
 588         case RT5682_SIL_PSV_CTRL2:
 589         case RT5682_SIL_PSV_CTRL3:
 590         case RT5682_SIL_PSV_CTRL4:
 591         case RT5682_SIL_PSV_CTRL5:
 592         case RT5682_HP_IMP_SENS_CTRL_01:
 593         case RT5682_HP_IMP_SENS_CTRL_02:
 594         case RT5682_HP_IMP_SENS_CTRL_03:
 595         case RT5682_HP_IMP_SENS_CTRL_04:
 596         case RT5682_HP_IMP_SENS_CTRL_05:
 597         case RT5682_HP_IMP_SENS_CTRL_06:
 598         case RT5682_HP_IMP_SENS_CTRL_07:
 599         case RT5682_HP_IMP_SENS_CTRL_08:
 600         case RT5682_HP_IMP_SENS_CTRL_09:
 601         case RT5682_HP_IMP_SENS_CTRL_10:
 602         case RT5682_HP_IMP_SENS_CTRL_11:
 603         case RT5682_HP_IMP_SENS_CTRL_12:
 604         case RT5682_HP_IMP_SENS_CTRL_13:
 605         case RT5682_HP_IMP_SENS_CTRL_14:
 606         case RT5682_HP_IMP_SENS_CTRL_15:
 607         case RT5682_HP_IMP_SENS_CTRL_16:
 608         case RT5682_HP_IMP_SENS_CTRL_17:
 609         case RT5682_HP_IMP_SENS_CTRL_18:
 610         case RT5682_HP_IMP_SENS_CTRL_19:
 611         case RT5682_HP_IMP_SENS_CTRL_20:
 612         case RT5682_HP_IMP_SENS_CTRL_21:
 613         case RT5682_HP_IMP_SENS_CTRL_22:
 614         case RT5682_HP_IMP_SENS_CTRL_23:
 615         case RT5682_HP_IMP_SENS_CTRL_24:
 616         case RT5682_HP_IMP_SENS_CTRL_25:
 617         case RT5682_HP_IMP_SENS_CTRL_26:
 618         case RT5682_HP_IMP_SENS_CTRL_27:
 619         case RT5682_HP_IMP_SENS_CTRL_28:
 620         case RT5682_HP_IMP_SENS_CTRL_29:
 621         case RT5682_HP_IMP_SENS_CTRL_30:
 622         case RT5682_HP_IMP_SENS_CTRL_31:
 623         case RT5682_HP_IMP_SENS_CTRL_32:
 624         case RT5682_HP_IMP_SENS_CTRL_33:
 625         case RT5682_HP_IMP_SENS_CTRL_34:
 626         case RT5682_HP_IMP_SENS_CTRL_35:
 627         case RT5682_HP_IMP_SENS_CTRL_36:
 628         case RT5682_HP_IMP_SENS_CTRL_37:
 629         case RT5682_HP_IMP_SENS_CTRL_38:
 630         case RT5682_HP_IMP_SENS_CTRL_39:
 631         case RT5682_HP_IMP_SENS_CTRL_40:
 632         case RT5682_HP_IMP_SENS_CTRL_41:
 633         case RT5682_HP_IMP_SENS_CTRL_42:
 634         case RT5682_HP_IMP_SENS_CTRL_43:
 635         case RT5682_HP_LOGIC_CTRL_1:
 636         case RT5682_HP_LOGIC_CTRL_2:
 637         case RT5682_HP_LOGIC_CTRL_3:
 638         case RT5682_HP_CALIB_CTRL_1:
 639         case RT5682_HP_CALIB_CTRL_2:
 640         case RT5682_HP_CALIB_CTRL_3:
 641         case RT5682_HP_CALIB_CTRL_4:
 642         case RT5682_HP_CALIB_CTRL_5:
 643         case RT5682_HP_CALIB_CTRL_6:
 644         case RT5682_HP_CALIB_CTRL_7:
 645         case RT5682_HP_CALIB_CTRL_9:
 646         case RT5682_HP_CALIB_CTRL_10:
 647         case RT5682_HP_CALIB_CTRL_11:
 648         case RT5682_HP_CALIB_STA_1:
 649         case RT5682_HP_CALIB_STA_2:
 650         case RT5682_HP_CALIB_STA_3:
 651         case RT5682_HP_CALIB_STA_4:
 652         case RT5682_HP_CALIB_STA_5:
 653         case RT5682_HP_CALIB_STA_6:
 654         case RT5682_HP_CALIB_STA_7:
 655         case RT5682_HP_CALIB_STA_8:
 656         case RT5682_HP_CALIB_STA_9:
 657         case RT5682_HP_CALIB_STA_10:
 658         case RT5682_HP_CALIB_STA_11:
 659         case RT5682_SAR_IL_CMD_1:
 660         case RT5682_SAR_IL_CMD_2:
 661         case RT5682_SAR_IL_CMD_3:
 662         case RT5682_SAR_IL_CMD_4:
 663         case RT5682_SAR_IL_CMD_5:
 664         case RT5682_SAR_IL_CMD_6:
 665         case RT5682_SAR_IL_CMD_7:
 666         case RT5682_SAR_IL_CMD_8:
 667         case RT5682_SAR_IL_CMD_9:
 668         case RT5682_SAR_IL_CMD_10:
 669         case RT5682_SAR_IL_CMD_11:
 670         case RT5682_SAR_IL_CMD_12:
 671         case RT5682_SAR_IL_CMD_13:
 672         case RT5682_EFUSE_CTRL_1:
 673         case RT5682_EFUSE_CTRL_2:
 674         case RT5682_EFUSE_CTRL_3:
 675         case RT5682_EFUSE_CTRL_4:
 676         case RT5682_EFUSE_CTRL_5:
 677         case RT5682_EFUSE_CTRL_6:
 678         case RT5682_EFUSE_CTRL_7:
 679         case RT5682_EFUSE_CTRL_8:
 680         case RT5682_EFUSE_CTRL_9:
 681         case RT5682_EFUSE_CTRL_10:
 682         case RT5682_EFUSE_CTRL_11:
 683         case RT5682_JD_TOP_VC_VTRL:
 684         case RT5682_DRC1_CTRL_0:
 685         case RT5682_DRC1_CTRL_1:
 686         case RT5682_DRC1_CTRL_2:
 687         case RT5682_DRC1_CTRL_3:
 688         case RT5682_DRC1_CTRL_4:
 689         case RT5682_DRC1_CTRL_5:
 690         case RT5682_DRC1_CTRL_6:
 691         case RT5682_DRC1_HARD_LMT_CTRL_1:
 692         case RT5682_DRC1_HARD_LMT_CTRL_2:
 693         case RT5682_DRC1_PRIV_1:
 694         case RT5682_DRC1_PRIV_2:
 695         case RT5682_DRC1_PRIV_3:
 696         case RT5682_DRC1_PRIV_4:
 697         case RT5682_DRC1_PRIV_5:
 698         case RT5682_DRC1_PRIV_6:
 699         case RT5682_DRC1_PRIV_7:
 700         case RT5682_DRC1_PRIV_8:
 701         case RT5682_EQ_AUTO_RCV_CTRL1:
 702         case RT5682_EQ_AUTO_RCV_CTRL2:
 703         case RT5682_EQ_AUTO_RCV_CTRL3:
 704         case RT5682_EQ_AUTO_RCV_CTRL4:
 705         case RT5682_EQ_AUTO_RCV_CTRL5:
 706         case RT5682_EQ_AUTO_RCV_CTRL6:
 707         case RT5682_EQ_AUTO_RCV_CTRL7:
 708         case RT5682_EQ_AUTO_RCV_CTRL8:
 709         case RT5682_EQ_AUTO_RCV_CTRL9:
 710         case RT5682_EQ_AUTO_RCV_CTRL10:
 711         case RT5682_EQ_AUTO_RCV_CTRL11:
 712         case RT5682_EQ_AUTO_RCV_CTRL12:
 713         case RT5682_EQ_AUTO_RCV_CTRL13:
 714         case RT5682_ADC_L_EQ_LPF1_A1:
 715         case RT5682_R_EQ_LPF1_A1:
 716         case RT5682_L_EQ_LPF1_H0:
 717         case RT5682_R_EQ_LPF1_H0:
 718         case RT5682_L_EQ_BPF1_A1:
 719         case RT5682_R_EQ_BPF1_A1:
 720         case RT5682_L_EQ_BPF1_A2:
 721         case RT5682_R_EQ_BPF1_A2:
 722         case RT5682_L_EQ_BPF1_H0:
 723         case RT5682_R_EQ_BPF1_H0:
 724         case RT5682_L_EQ_BPF2_A1:
 725         case RT5682_R_EQ_BPF2_A1:
 726         case RT5682_L_EQ_BPF2_A2:
 727         case RT5682_R_EQ_BPF2_A2:
 728         case RT5682_L_EQ_BPF2_H0:
 729         case RT5682_R_EQ_BPF2_H0:
 730         case RT5682_L_EQ_BPF3_A1:
 731         case RT5682_R_EQ_BPF3_A1:
 732         case RT5682_L_EQ_BPF3_A2:
 733         case RT5682_R_EQ_BPF3_A2:
 734         case RT5682_L_EQ_BPF3_H0:
 735         case RT5682_R_EQ_BPF3_H0:
 736         case RT5682_L_EQ_BPF4_A1:
 737         case RT5682_R_EQ_BPF4_A1:
 738         case RT5682_L_EQ_BPF4_A2:
 739         case RT5682_R_EQ_BPF4_A2:
 740         case RT5682_L_EQ_BPF4_H0:
 741         case RT5682_R_EQ_BPF4_H0:
 742         case RT5682_L_EQ_HPF1_A1:
 743         case RT5682_R_EQ_HPF1_A1:
 744         case RT5682_L_EQ_HPF1_H0:
 745         case RT5682_R_EQ_HPF1_H0:
 746         case RT5682_L_EQ_PRE_VOL:
 747         case RT5682_R_EQ_PRE_VOL:
 748         case RT5682_L_EQ_POST_VOL:
 749         case RT5682_R_EQ_POST_VOL:
 750         case RT5682_I2C_MODE:
 751                 return true;
 752         default:
 753                 return false;
 754         }
 755 }
 756
 757 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
 758 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 759 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
 760
 761 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
 762 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 763         0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
 764         1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
 765         2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
 766         3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
 767         6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
 768         7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
 769         8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
 770 );
 771
 772 /* Interface data select */
 773 static const char * const rt5682_data_select[] = {
 774         "L/R", "R/L", "L/L", "R/R"
 775 };
 776
 777 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
 778         RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
 779
 780 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
 781         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
 782
 783 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
 784         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
 785
 786 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
 787         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
 788
 789 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
 790         RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
 791
 792 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
 793         SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
 794
 795 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
 796         SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
 797
 798 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
 799         SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
 800
 801 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
 802         SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
 803
 804 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
 805         SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
 806
 807 static void rt5682_reset(struct regmap *regmap)
 808 {
 809         regmap_write(regmap, RT5682_RESET, 0);
 810         regmap_write(regmap, RT5682_I2C_MODE, 1);
 811 }
 812 /**
 813  * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
 814  * @component: SoC audio component device.
 815  * @filter_mask: mask of filters.
 816  * @clk_src: clock source
 817  *
 818  * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
 819  * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
 820  * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
 821  * ASRC function will track i2s clock and generate a corresponding system clock
 822  * for codec. This function provides an API to select the clock source for a
 823  * set of filters specified by the mask. And the component driver will turn on
 824  * ASRC for these filters if ASRC is selected as their clock source.
 825  */
 826 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
 827                 unsigned int filter_mask, unsigned int clk_src)
 828 {
 829
 830         switch (clk_src) {
 831         case RT5682_CLK_SEL_SYS:
 832         case RT5682_CLK_SEL_I2S1_ASRC:
 833         case RT5682_CLK_SEL_I2S2_ASRC:
 834                 break;
 835
 836         default:
 837                 return -EINVAL;
 838         }
 839
 840         if (filter_mask & RT5682_DA_STEREO1_FILTER) {
 841                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
 842                         RT5682_FILTER_CLK_SEL_MASK,
 843                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 844         }
 845
 846         if (filter_mask & RT5682_AD_STEREO1_FILTER) {
 847                 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
 848                         RT5682_FILTER_CLK_SEL_MASK,
 849                         clk_src << RT5682_FILTER_CLK_SEL_SFT);
 850         }
 851
 852         return 0;
 853 }
 854 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
 855
 856 static int rt5682_button_detect(struct snd_soc_component *component)
 857 {
 858         int btn_type, val;
 859
 860         val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
 861         btn_type = val & 0xfff0;
 862         snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
 863         pr_debug("%s btn_type=%x\n", __func__, btn_type);
 864         snd_soc_component_update_bits(component,
 865                 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
 866
 867         return btn_type;
 868 }
 869
 870 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
 871                 bool enable)
 872 {
 873         if (enable) {
 874                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 875                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
 876                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 877                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
 878                 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
 879                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 880                         RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
 881                         RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
 882                 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
 883                         RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN);
 884         } else {
 885                 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
 886                         RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
 887                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
 888                         RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
 889                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 890                         RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
 891                 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
 892                         RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
 893                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
 894                         RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
 895         }
 896 }
 897
 898 /**
 899  * rt5682_headset_detect - Detect headset.
 900  * @component: SoC audio component device.
 901  * @jack_insert: Jack insert or not.
 902  *
 903  * Detect whether is headset or not when jack inserted.
 904  *
 905  * Returns detect status.
 906  */
 907 static int rt5682_headset_detect(struct snd_soc_component *component,
 908                 int jack_insert)
 909 {
 910         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 911         unsigned int val, count;
 912
 913         if (jack_insert) {
 914
 915                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
 916                         RT5682_PWR_VREF2 | RT5682_PWR_MB,
 917                         RT5682_PWR_VREF2 | RT5682_PWR_MB);
 918                 snd_soc_component_update_bits(component,
 919                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
 920                 usleep_range(15000, 20000);
 921                 snd_soc_component_update_bits(component,
 922                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
 923                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 924                         RT5682_PWR_CBJ, RT5682_PWR_CBJ);
 925
 926                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 927                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
 928
 929                 count = 0;
 930                 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
 931                         & RT5682_JACK_TYPE_MASK;
 932                 while (val == 0 && count < 50) {
 933                         usleep_range(10000, 15000);
 934                         val = snd_soc_component_read32(component,
 935                                 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
 936                         count++;
 937                 }
 938
 939                 switch (val) {
 940                 case 0x1:
 941                 case 0x2:
 942                         rt5682->jack_type = SND_JACK_HEADSET;
 943                         rt5682_enable_push_button_irq(component, true);
 944                         break;
 945                 default:
 946                         rt5682->jack_type = SND_JACK_HEADPHONE;
 947                 }
 948
 949         } else {
 950                 rt5682_enable_push_button_irq(component, false);
 951                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
 952                         RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
 953                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
 954                         RT5682_PWR_VREF2 | RT5682_PWR_MB, 0);
 955                 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
 956                         RT5682_PWR_CBJ, 0);
 957
 958                 rt5682->jack_type = 0;
 959         }
 960
 961         dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
 962         return rt5682->jack_type;
 963 }
 964
 965 static irqreturn_t rt5682_irq(int irq, void *data)
 966 {
 967         struct rt5682_priv *rt5682 = data;
 968
 969         mod_delayed_work(system_power_efficient_wq,
 970                         &rt5682->jack_detect_work, msecs_to_jiffies(250));
 971
 972         return IRQ_HANDLED;
 973 }
 974
 975 static void rt5682_jd_check_handler(struct work_struct *work)
 976 {
 977         struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
 978                 jd_check_work.work);
 979
 980         if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
 981                 & RT5682_JDH_RS_MASK) {
 982                 /* jack out */
 983                 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
 984
 985                 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
 986                                 SND_JACK_HEADSET |
 987                                 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
 988                                 SND_JACK_BTN_2 | SND_JACK_BTN_3);
 989         } else {
 990                 schedule_delayed_work(&rt5682->jd_check_work, 500);
 991         }
 992 }
 993
 994 static int rt5682_set_jack_detect(struct snd_soc_component *component,
 995         struct snd_soc_jack *hs_jack, void *data)
 996 {
 997         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
 998
 999         rt5682->hs_jack = hs_jack;
1000
1001         if (!hs_jack) {
1002                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1003                                    RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1004                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1005                                    RT5682_POW_JDH | RT5682_POW_JDL, 0);
1006                 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1007                 return 0;
1008         }
1009
1010         switch (rt5682->pdata.jd_src) {
1011         case RT5682_JD1:
1012                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2,
1013                         RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
1014                 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042);
1015                 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3,
1016                         RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
1017                 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
1018                         RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
1019                 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1020                         RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1021                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1022                                 RT5682_POW_IRQ | RT5682_POW_JDH |
1023                                 RT5682_POW_ANA, RT5682_POW_IRQ |
1024                                 RT5682_POW_JDH | RT5682_POW_ANA);
1025                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1026                         RT5682_PWR_JDH | RT5682_PWR_JDL,
1027                         RT5682_PWR_JDH | RT5682_PWR_JDL);
1028                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1029                         RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1030                         RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1031                 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1032                         0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1033                         rt5682->pdata.btndet_delay));
1034                 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1035                         0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1036                         rt5682->pdata.btndet_delay));
1037                 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1038                         0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1039                         rt5682->pdata.btndet_delay));
1040                 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1041                         0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1042                         rt5682->pdata.btndet_delay));
1043                 mod_delayed_work(system_power_efficient_wq,
1044                            &rt5682->jack_detect_work, msecs_to_jiffies(250));
1045                 break;
1046
1047         case RT5682_JD_NULL:
1048                 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1049                         RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1050                 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1051                                 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1052                 break;
1053
1054         default:
1055                 dev_warn(component->dev, "Wrong JD source\n");
1056                 break;
1057         }
1058
1059         return 0;
1060 }
1061
1062 static void rt5682_jack_detect_handler(struct work_struct *work)
1063 {
1064         struct rt5682_priv *rt5682 =
1065                 container_of(work, struct rt5682_priv, jack_detect_work.work);
1066         int val, btn_type;
1067
1068         while (!rt5682->component)
1069                 usleep_range(10000, 15000);
1070
1071         while (!rt5682->component->card->instantiated)
1072                 usleep_range(10000, 15000);
1073
1074         mutex_lock(&rt5682->calibrate_mutex);
1075
1076         val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1077                 & RT5682_JDH_RS_MASK;
1078         if (!val) {
1079                 /* jack in */
1080                 if (rt5682->jack_type == 0) {
1081                         /* jack was out, report jack type */
1082                         rt5682->jack_type =
1083                                 rt5682_headset_detect(rt5682->component, 1);
1084                 } else {
1085                         /* jack is already in, report button event */
1086                         rt5682->jack_type = SND_JACK_HEADSET;
1087                         btn_type = rt5682_button_detect(rt5682->component);
1088                         /**
1089                          * rt5682 can report three kinds of button behavior,
1090                          * one click, double click and hold. However,
1091                          * currently we will report button pressed/released
1092                          * event. So all the three button behaviors are
1093                          * treated as button pressed.
1094                          */
1095                         switch (btn_type) {
1096                         case 0x8000:
1097                         case 0x4000:
1098                         case 0x2000:
1099                                 rt5682->jack_type |= SND_JACK_BTN_0;
1100                                 break;
1101                         case 0x1000:
1102                         case 0x0800:
1103                         case 0x0400:
1104                                 rt5682->jack_type |= SND_JACK_BTN_1;
1105                                 break;
1106                         case 0x0200:
1107                         case 0x0100:
1108                         case 0x0080:
1109                                 rt5682->jack_type |= SND_JACK_BTN_2;
1110                                 break;
1111                         case 0x0040:
1112                         case 0x0020:
1113                         case 0x0010:
1114                                 rt5682->jack_type |= SND_JACK_BTN_3;
1115                                 break;
1116                         case 0x0000: /* unpressed */
1117                                 break;
1118                         default:
1119                                 btn_type = 0;
1120                                 dev_err(rt5682->component->dev,
1121                                         "Unexpected button code 0x%04x\n",
1122                                         btn_type);
1123                                 break;
1124                         }
1125                 }
1126         } else {
1127                 /* jack out */
1128                 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1129         }
1130
1131         snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1132                         SND_JACK_HEADSET |
1133                             SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1134                             SND_JACK_BTN_2 | SND_JACK_BTN_3);
1135
1136         if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1137                 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1138                 schedule_delayed_work(&rt5682->jd_check_work, 0);
1139         else
1140                 cancel_delayed_work_sync(&rt5682->jd_check_work);
1141
1142         mutex_unlock(&rt5682->calibrate_mutex);
1143 }
1144
1145 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1146         /* DAC Digital Volume */
1147         SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1148                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv),
1149
1150         /* IN Boost Volume */
1151         SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1152                 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1153
1154         /* ADC Digital Volume Control */
1155         SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1156                 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1157         SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1158                 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1159
1160         /* ADC Boost Volume Control */
1161         SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1162                 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1163                 3, 0, adc_bst_tlv),
1164 };
1165
1166
1167 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1168                           int target, const int div[], int size)
1169 {
1170         int i;
1171
1172         if (rt5682->sysclk < target) {
1173                 pr_err("sysclk rate %d is too low\n",
1174                         rt5682->sysclk);
1175                 return 0;
1176         }
1177
1178         for (i = 0; i < size - 1; i++) {
1179                 pr_info("div[%d]=%d\n", i, div[i]);
1180                 if (target * div[i] == rt5682->sysclk)
1181                         return i;
1182                 if (target * div[i + 1] > rt5682->sysclk) {
1183                         pr_err("can't find div for sysclk %d\n",
1184                                 rt5682->sysclk);
1185                         return i;
1186                 }
1187         }
1188
1189         if (target * div[i] < rt5682->sysclk)
1190                 pr_err("sysclk rate %d is too high\n",
1191                         rt5682->sysclk);
1192
1193         return size - 1;
1194
1195 }
1196
1197 /**
1198  * set_dmic_clk - Set parameter of dmic.
1199  *
1200  * @w: DAPM widget.
1201  * @kcontrol: The kcontrol of this widget.
1202  * @event: Event id.
1203  *
1204  * Choose dmic clock between 1MHz and 3MHz.
1205  * It is better for clock to approximate 3MHz.
1206  */
1207 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1208         struct snd_kcontrol *kcontrol, int event)
1209 {
1210         struct snd_soc_component *component =
1211                 snd_soc_dapm_to_component(w->dapm);
1212         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1213         int idx = -EINVAL;
1214         static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1215
1216         idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
1217
1218         snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1219                 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1220
1221         return 0;
1222 }
1223
1224 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1225         struct snd_kcontrol *kcontrol, int event)
1226 {
1227         struct snd_soc_component *component =
1228                 snd_soc_dapm_to_component(w->dapm);
1229         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1230         int ref, val, reg, idx = -EINVAL;
1231         static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1232         static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1233
1234         val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1235                 RT5682_GP4_PIN_MASK;
1236         if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1237                 val == RT5682_GP4_PIN_ADCDAT2)
1238                 ref = 256 * rt5682->lrck[RT5682_AIF2];
1239         else
1240                 ref = 256 * rt5682->lrck[RT5682_AIF1];
1241
1242         idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1243
1244         if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1245                 reg = RT5682_PLL_TRACK_3;
1246         else
1247                 reg = RT5682_PLL_TRACK_2;
1248
1249         snd_soc_component_update_bits(component, reg,
1250                 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1251
1252         /* select over sample rate */
1253         for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1254                 if (rt5682->sysclk <= 12288000 * div_o[idx])
1255                         break;
1256         }
1257
1258         snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1259                 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1260                 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1261
1262         return 0;
1263 }
1264
1265 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1266                          struct snd_soc_dapm_widget *sink)
1267 {
1268         unsigned int val;
1269         struct snd_soc_component *component =
1270                 snd_soc_dapm_to_component(w->dapm);
1271
1272         val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1273         val &= RT5682_SCLK_SRC_MASK;
1274         if (val == RT5682_SCLK_SRC_PLL1)
1275                 return 1;
1276         else
1277                 return 0;
1278 }
1279
1280 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1281                          struct snd_soc_dapm_widget *sink)
1282 {
1283         unsigned int reg, shift, val;
1284         struct snd_soc_component *component =
1285                 snd_soc_dapm_to_component(w->dapm);
1286
1287         switch (w->shift) {
1288         case RT5682_ADC_STO1_ASRC_SFT:
1289                 reg = RT5682_PLL_TRACK_3;
1290                 shift = RT5682_FILTER_CLK_SEL_SFT;
1291                 break;
1292         case RT5682_DAC_STO1_ASRC_SFT:
1293                 reg = RT5682_PLL_TRACK_2;
1294                 shift = RT5682_FILTER_CLK_SEL_SFT;
1295                 break;
1296         default:
1297                 return 0;
1298         }
1299
1300         val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1301         switch (val) {
1302         case RT5682_CLK_SEL_I2S1_ASRC:
1303         case RT5682_CLK_SEL_I2S2_ASRC:
1304                 return 1;
1305         default:
1306                 return 0;
1307         }
1308
1309 }
1310
1311 /* Digital Mixer */
1312 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1313         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1314                         RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1315         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1316                         RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1317 };
1318
1319 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1320         SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1321                         RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1322         SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1323                         RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1324 };
1325
1326 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1327         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1328                         RT5682_M_ADCMIX_L_SFT, 1, 1),
1329         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1330                         RT5682_M_DAC1_L_SFT, 1, 1),
1331 };
1332
1333 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1334         SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1335                         RT5682_M_ADCMIX_R_SFT, 1, 1),
1336         SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1337                         RT5682_M_DAC1_R_SFT, 1, 1),
1338 };
1339
1340 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1341         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1342                         RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1343         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1344                         RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1345 };
1346
1347 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1348         SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1349                         RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1350         SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1351                         RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1352 };
1353
1354 /* Analog Input Mixer */
1355 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1356         SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1357                         RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1358 };
1359
1360 /* STO1 ADC1 Source */
1361 /* MX-26 [13] [5] */
1362 static const char * const rt5682_sto1_adc1_src[] = {
1363         "DAC MIX", "ADC"
1364 };
1365
1366 static SOC_ENUM_SINGLE_DECL(
1367         rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1368         RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1369
1370 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1371         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1372
1373 static SOC_ENUM_SINGLE_DECL(
1374         rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1375         RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1376
1377 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1378         SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1379
1380 /* STO1 ADC Source */
1381 /* MX-26 [11:10] [3:2] */
1382 static const char * const rt5682_sto1_adc_src[] = {
1383         "ADC1 L", "ADC1 R"
1384 };
1385
1386 static SOC_ENUM_SINGLE_DECL(
1387         rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1388         RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1389
1390 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1391         SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1392
1393 static SOC_ENUM_SINGLE_DECL(
1394         rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1395         RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1396
1397 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1398         SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1399
1400 /* STO1 ADC2 Source */
1401 /* MX-26 [12] [4] */
1402 static const char * const rt5682_sto1_adc2_src[] = {
1403         "DAC MIX", "DMIC"
1404 };
1405
1406 static SOC_ENUM_SINGLE_DECL(
1407         rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1408         RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1409
1410 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1411         SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1412
1413 static SOC_ENUM_SINGLE_DECL(
1414         rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1415         RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1416
1417 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1418         SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1419
1420 /* MX-79 [6:4] I2S1 ADC data location */
1421 static const unsigned int rt5682_if1_adc_slot_values[] = {
1422         0,
1423         2,
1424         4,
1425         6,
1426 };
1427
1428 static const char * const rt5682_if1_adc_slot_src[] = {
1429         "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1430 };
1431
1432 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1433         RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1434         rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1435
1436 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1437         SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1438
1439 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1440 /* MX-2B [4], MX-2B [0]*/
1441 static const char * const rt5682_alg_dac1_src[] = {
1442         "Stereo1 DAC Mixer", "DAC1"
1443 };
1444
1445 static SOC_ENUM_SINGLE_DECL(
1446         rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1447         RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1448
1449 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1450         SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1451
1452 static SOC_ENUM_SINGLE_DECL(
1453         rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1454         RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1455
1456 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1457         SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1458
1459 /* Out Switch */
1460 static const struct snd_kcontrol_new hpol_switch =
1461         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1462                                         RT5682_L_MUTE_SFT, 1, 1);
1463 static const struct snd_kcontrol_new hpor_switch =
1464         SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1465                                         RT5682_R_MUTE_SFT, 1, 1);
1466
1467 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1468         struct snd_kcontrol *kcontrol, int event)
1469 {
1470         struct snd_soc_component *component =
1471                 snd_soc_dapm_to_component(w->dapm);
1472
1473         switch (event) {
1474         case SND_SOC_DAPM_PRE_PMU:
1475                 snd_soc_component_write(component,
1476                         RT5682_HP_LOGIC_CTRL_2, 0x0012);
1477                 snd_soc_component_write(component,
1478                         RT5682_HP_CTRL_2, 0x6000);
1479                 snd_soc_component_update_bits(component,
1480                         RT5682_DEPOP_1, 0x60, 0x60);
1481                 snd_soc_component_update_bits(component,
1482                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1483                 break;
1484
1485         case SND_SOC_DAPM_POST_PMD:
1486                 snd_soc_component_update_bits(component,
1487                         RT5682_DEPOP_1, 0x60, 0x0);
1488                 snd_soc_component_write(component,
1489                         RT5682_HP_CTRL_2, 0x0000);
1490                 snd_soc_component_update_bits(component,
1491                         RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1492                 break;
1493
1494         default:
1495                 return 0;
1496         }
1497
1498         return 0;
1499
1500 }
1501
1502 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1503         struct snd_kcontrol *kcontrol, int event)
1504 {
1505         switch (event) {
1506         case SND_SOC_DAPM_POST_PMU:
1507                 /*Add delay to avoid pop noise*/
1508                 msleep(150);
1509                 break;
1510
1511         default:
1512                 return 0;
1513         }
1514
1515         return 0;
1516 }
1517
1518 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1519         struct snd_kcontrol *kcontrol, int event)
1520 {
1521         struct snd_soc_component *component =
1522                 snd_soc_dapm_to_component(w->dapm);
1523
1524         switch (event) {
1525         case SND_SOC_DAPM_PRE_PMU:
1526                 switch (w->shift) {
1527                 case RT5682_PWR_VREF1_BIT:
1528                         snd_soc_component_update_bits(component,
1529                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1530                         break;
1531
1532                 case RT5682_PWR_VREF2_BIT:
1533                         snd_soc_component_update_bits(component,
1534                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1535                         break;
1536
1537                 default:
1538                         break;
1539                 }
1540                 break;
1541
1542         case SND_SOC_DAPM_POST_PMU:
1543                 usleep_range(15000, 20000);
1544                 switch (w->shift) {
1545                 case RT5682_PWR_VREF1_BIT:
1546                         snd_soc_component_update_bits(component,
1547                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1548                                 RT5682_PWR_FV1);
1549                         break;
1550
1551                 case RT5682_PWR_VREF2_BIT:
1552                         snd_soc_component_update_bits(component,
1553                                 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1554                                 RT5682_PWR_FV2);
1555                         break;
1556
1557                 default:
1558                         break;
1559                 }
1560                 break;
1561
1562         default:
1563                 return 0;
1564         }
1565
1566         return 0;
1567 }
1568
1569 static const unsigned int rt5682_adcdat_pin_values[] = {
1570         1,
1571         3,
1572 };
1573
1574 static const char * const rt5682_adcdat_pin_select[] = {
1575         "ADCDAT1",
1576         "ADCDAT2",
1577 };
1578
1579 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1580         RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1581         rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1582
1583 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1584         SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1585
1586 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1587         SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1588                 0, NULL, 0),
1589         SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1590                 0, NULL, 0),
1591         SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1592                 0, NULL, 0),
1593         SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1594                 0, NULL, 0),
1595         SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1596                 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1597
1598         /* ASRC */
1599         SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1600                 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1601         SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1602                 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1603         SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1604                 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1605         SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1606                 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1607         SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1608                 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1609
1610         /* Input Side */
1611         SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1612                 0, NULL, 0),
1613         SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1614                 0, NULL, 0),
1615
1616         /* Input Lines */
1617         SND_SOC_DAPM_INPUT("DMIC L1"),
1618         SND_SOC_DAPM_INPUT("DMIC R1"),
1619
1620         SND_SOC_DAPM_INPUT("IN1P"),
1621
1622         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1623                 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1624         SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1625                 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1626
1627         /* Boost */
1628         SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1629                 0, 0, NULL, 0),
1630
1631         /* REC Mixer */
1632         SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1633                 ARRAY_SIZE(rt5682_rec1_l_mix)),
1634         SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1635                 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1636
1637         /* ADCs */
1638         SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1639         SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1640
1641         SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1642                 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1643         SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1644                 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1645         SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1646                 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1647
1648         /* ADC Mux */
1649         SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1650                 &rt5682_sto1_adc1l_mux),
1651         SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1652                 &rt5682_sto1_adc1r_mux),
1653         SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1654                 &rt5682_sto1_adc2l_mux),
1655         SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1656                 &rt5682_sto1_adc2r_mux),
1657         SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1658                 &rt5682_sto1_adcl_mux),
1659         SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1660                 &rt5682_sto1_adcr_mux),
1661         SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1662                 &rt5682_if1_adc_slot_mux),
1663
1664         /* ADC Mixer */
1665         SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1666                 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1667                 SND_SOC_DAPM_PRE_PMU),
1668         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1669                 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1670                 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1671         SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1672                 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1673                 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1674         SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1675                 14, 1, NULL, 0),
1676
1677         /* ADC PGA */
1678         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1679
1680         /* Digital Interface */
1681         SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1682                 0, NULL, 0),
1683         SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1684                 0, NULL, 0),
1685         SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1686         SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1687         SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1688
1689         /* Digital Interface Select */
1690         SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1691                         &rt5682_if1_01_adc_swap_mux),
1692         SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1693                         &rt5682_if1_23_adc_swap_mux),
1694         SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1695                         &rt5682_if1_45_adc_swap_mux),
1696         SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1697                         &rt5682_if1_67_adc_swap_mux),
1698         SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1699                         &rt5682_if2_adc_swap_mux),
1700
1701         SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1702                         &rt5682_adcdat_pin_ctrl),
1703
1704         /* Audio Interface */
1705         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1706                 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1707         SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1708                 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1709         SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1710
1711         /* Output Side */
1712         /* DAC mixer before sound effect  */
1713         SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1714                 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1715         SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1716                 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1717
1718         /* DAC channel Mux */
1719         SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1720                 &rt5682_alg_dac_l1_mux),
1721         SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1722                 &rt5682_alg_dac_r1_mux),
1723
1724         /* DAC Mixer */
1725         SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1726                 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1727                 SND_SOC_DAPM_PRE_PMU),
1728         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1729                 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1730         SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1731                 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1732
1733         /* DACs */
1734         SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1735                 RT5682_PWR_DAC_L1_BIT, 0),
1736         SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1737                 RT5682_PWR_DAC_R1_BIT, 0),
1738         SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1739                 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1740
1741         /* HPO */
1742         SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1743                 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1744
1745         SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1746                 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1747         SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1748                 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1749         SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1750                 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1751         SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1752                 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1753
1754         SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1755                 &hpol_switch),
1756         SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1757                 &hpor_switch),
1758
1759         /* CLK DET */
1760         SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1761                 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1762         SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1763                 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1764         SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1765                 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1766         SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1767                 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1768
1769         /* Output Lines */
1770         SND_SOC_DAPM_OUTPUT("HPOL"),
1771         SND_SOC_DAPM_OUTPUT("HPOR"),
1772
1773 };
1774
1775 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1776         /*PLL*/
1777         {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1778         {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1779
1780         /*ASRC*/
1781         {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1782         {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1783         {"ADC STO1 ASRC", NULL, "AD ASRC"},
1784         {"ADC STO1 ASRC", NULL, "DA ASRC"},
1785         {"ADC STO1 ASRC", NULL, "CLKDET"},
1786         {"DAC STO1 ASRC", NULL, "AD ASRC"},
1787         {"DAC STO1 ASRC", NULL, "DA ASRC"},
1788         {"DAC STO1 ASRC", NULL, "CLKDET"},
1789
1790         /*Vref*/
1791         {"MICBIAS1", NULL, "Vref1"},
1792         {"MICBIAS2", NULL, "Vref1"},
1793
1794         {"CLKDET SYS", NULL, "CLKDET"},
1795
1796         {"IN1P", NULL, "LDO2"},
1797
1798         {"BST1 CBJ", NULL, "IN1P"},
1799
1800         {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1801         {"RECMIX1L", NULL, "RECMIX1L Power"},
1802
1803         {"ADC1 L", NULL, "RECMIX1L"},
1804         {"ADC1 L", NULL, "ADC1 L Power"},
1805         {"ADC1 L", NULL, "ADC1 clock"},
1806
1807         {"DMIC L1", NULL, "DMIC CLK"},
1808         {"DMIC L1", NULL, "DMIC1 Power"},
1809         {"DMIC R1", NULL, "DMIC CLK"},
1810         {"DMIC R1", NULL, "DMIC1 Power"},
1811         {"DMIC CLK", NULL, "DMIC ASRC"},
1812
1813         {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1814         {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1815         {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1816         {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1817
1818         {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1819         {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1820         {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1821         {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1822
1823         {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1824         {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1825         {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1826         {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1827
1828         {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1829         {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1830         {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1831
1832         {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1833         {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1834         {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1835
1836         {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1837
1838         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1839         {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1840
1841         {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1842         {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1843         {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1844         {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1845         {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1846         {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1847         {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1848         {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1849         {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1850         {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1851         {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1852         {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1853         {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1854         {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1855         {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1856         {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1857
1858         {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1859         {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1860         {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1861         {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1862         {"IF1_ADC Mux", NULL, "I2S1"},
1863         {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1864         {"AIF1TX", NULL, "ADCDAT Mux"},
1865         {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1866         {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1867         {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1868         {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1869         {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1870         {"AIF2TX", NULL, "ADCDAT Mux"},
1871
1872         {"IF1 DAC1 L", NULL, "AIF1RX"},
1873         {"IF1 DAC1 L", NULL, "I2S1"},
1874         {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1875         {"IF1 DAC1 R", NULL, "AIF1RX"},
1876         {"IF1 DAC1 R", NULL, "I2S1"},
1877         {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1878
1879         {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1880         {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1881         {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1882         {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1883
1884         {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1885         {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1886
1887         {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1888         {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1889
1890         {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1891         {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1892         {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1893         {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1894
1895         {"DAC L1", NULL, "DAC L1 Source"},
1896         {"DAC R1", NULL, "DAC R1 Source"},
1897
1898         {"DAC L1", NULL, "DAC 1 Clock"},
1899         {"DAC R1", NULL, "DAC 1 Clock"},
1900
1901         {"HP Amp", NULL, "DAC L1"},
1902         {"HP Amp", NULL, "DAC R1"},
1903         {"HP Amp", NULL, "HP Amp L"},
1904         {"HP Amp", NULL, "HP Amp R"},
1905         {"HP Amp", NULL, "Capless"},
1906         {"HP Amp", NULL, "Charge Pump"},
1907         {"HP Amp", NULL, "CLKDET SYS"},
1908         {"HP Amp", NULL, "Vref1"},
1909         {"HPOL Playback", "Switch", "HP Amp"},
1910         {"HPOR Playback", "Switch", "HP Amp"},
1911         {"HPOL", NULL, "HPOL Playback"},
1912         {"HPOR", NULL, "HPOR Playback"},
1913 };
1914
1915 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1916                         unsigned int rx_mask, int slots, int slot_width)
1917 {
1918         struct snd_soc_component *component = dai->component;
1919         unsigned int cl, val = 0;
1920
1921         if (tx_mask || rx_mask)
1922                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1923                         RT5682_TDM_EN, RT5682_TDM_EN);
1924         else
1925                 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1926                         RT5682_TDM_EN, 0);
1927
1928         switch (slots) {
1929         case 4:
1930                 val |= RT5682_TDM_TX_CH_4;
1931                 val |= RT5682_TDM_RX_CH_4;
1932                 break;
1933         case 6:
1934                 val |= RT5682_TDM_TX_CH_6;
1935                 val |= RT5682_TDM_RX_CH_6;
1936                 break;
1937         case 8:
1938                 val |= RT5682_TDM_TX_CH_8;
1939                 val |= RT5682_TDM_RX_CH_8;
1940                 break;
1941         case 2:
1942                 break;
1943         default:
1944                 return -EINVAL;
1945         }
1946
1947         snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
1948                 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
1949
1950         switch (slot_width) {
1951         case 8:
1952                 if (tx_mask || rx_mask)
1953                         return -EINVAL;
1954                 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
1955                 break;
1956         case 16:
1957                 val = RT5682_TDM_CL_16;
1958                 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
1959                 break;
1960         case 20:
1961                 val = RT5682_TDM_CL_20;
1962                 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
1963                 break;
1964         case 24:
1965                 val = RT5682_TDM_CL_24;
1966                 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
1967                 break;
1968         case 32:
1969                 val = RT5682_TDM_CL_32;
1970                 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
1971                 break;
1972         default:
1973                 return -EINVAL;
1974         }
1975
1976         snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
1977                 RT5682_TDM_CL_MASK, val);
1978         snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
1979                 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
1980
1981         return 0;
1982 }
1983
1984
1985 static int rt5682_hw_params(struct snd_pcm_substream *substream,
1986         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1987 {
1988         struct snd_soc_component *component = dai->component;
1989         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1990         unsigned int len_1 = 0, len_2 = 0;
1991         int pre_div, frame_size;
1992
1993         rt5682->lrck[dai->id] = params_rate(params);
1994         pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
1995
1996         frame_size = snd_soc_params_to_frame_size(params);
1997         if (frame_size < 0) {
1998                 dev_err(component->dev, "Unsupported frame size: %d\n",
1999                         frame_size);
2000                 return -EINVAL;
2001         }
2002
2003         dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2004                                 rt5682->lrck[dai->id], pre_div, dai->id);
2005
2006         switch (params_width(params)) {
2007         case 16:
2008                 break;
2009         case 20:
2010                 len_1 |= RT5682_I2S1_DL_20;
2011                 len_2 |= RT5682_I2S2_DL_20;
2012                 break;
2013         case 24:
2014                 len_1 |= RT5682_I2S1_DL_24;
2015                 len_2 |= RT5682_I2S2_DL_24;
2016                 break;
2017         case 32:
2018                 len_1 |= RT5682_I2S1_DL_32;
2019                 len_2 |= RT5682_I2S2_DL_24;
2020                 break;
2021         case 8:
2022                 len_1 |= RT5682_I2S2_DL_8;
2023                 len_2 |= RT5682_I2S2_DL_8;
2024                 break;
2025         default:
2026                 return -EINVAL;
2027         }
2028
2029         switch (dai->id) {
2030         case RT5682_AIF1:
2031                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2032                         RT5682_I2S1_DL_MASK, len_1);
2033                 if (rt5682->master[RT5682_AIF1]) {
2034                         snd_soc_component_update_bits(component,
2035                                 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK,
2036                                 pre_div << RT5682_I2S_M_DIV_SFT);
2037                 }
2038                 if (params_channels(params) == 1) /* mono mode */
2039                         snd_soc_component_update_bits(component,
2040                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2041                                 RT5682_I2S1_MONO_EN);
2042                 else
2043                         snd_soc_component_update_bits(component,
2044                                 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2045                                 RT5682_I2S1_MONO_DIS);
2046                 break;
2047         case RT5682_AIF2:
2048                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2049                         RT5682_I2S2_DL_MASK, len_2);
2050                 if (rt5682->master[RT5682_AIF2]) {
2051                         snd_soc_component_update_bits(component,
2052                                 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2053                                 pre_div << RT5682_I2S2_M_PD_SFT);
2054                 }
2055                 if (params_channels(params) == 1) /* mono mode */
2056                         snd_soc_component_update_bits(component,
2057                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2058                                 RT5682_I2S2_MONO_EN);
2059                 else
2060                         snd_soc_component_update_bits(component,
2061                                 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2062                                 RT5682_I2S2_MONO_DIS);
2063                 break;
2064         default:
2065                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2066                 return -EINVAL;
2067         }
2068
2069         return 0;
2070 }
2071
2072 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2073 {
2074         struct snd_soc_component *component = dai->component;
2075         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2076         unsigned int reg_val = 0, tdm_ctrl = 0;
2077
2078         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2079         case SND_SOC_DAIFMT_CBM_CFM:
2080                 rt5682->master[dai->id] = 1;
2081                 break;
2082         case SND_SOC_DAIFMT_CBS_CFS:
2083                 rt5682->master[dai->id] = 0;
2084                 break;
2085         default:
2086                 return -EINVAL;
2087         }
2088
2089         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2090         case SND_SOC_DAIFMT_NB_NF:
2091                 break;
2092         case SND_SOC_DAIFMT_IB_NF:
2093                 reg_val |= RT5682_I2S_BP_INV;
2094                 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2095                 break;
2096         case SND_SOC_DAIFMT_NB_IF:
2097                 if (dai->id == RT5682_AIF1)
2098                         tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2099                 else
2100                         return -EINVAL;
2101                 break;
2102         case SND_SOC_DAIFMT_IB_IF:
2103                 if (dai->id == RT5682_AIF1)
2104                         tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2105                                     RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2106                 else
2107                         return -EINVAL;
2108                 break;
2109         default:
2110                 return -EINVAL;
2111         }
2112
2113         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2114         case SND_SOC_DAIFMT_I2S:
2115                 break;
2116         case SND_SOC_DAIFMT_LEFT_J:
2117                 reg_val |= RT5682_I2S_DF_LEFT;
2118                 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2119                 break;
2120         case SND_SOC_DAIFMT_DSP_A:
2121                 reg_val |= RT5682_I2S_DF_PCM_A;
2122                 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2123                 break;
2124         case SND_SOC_DAIFMT_DSP_B:
2125                 reg_val |= RT5682_I2S_DF_PCM_B;
2126                 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2127                 break;
2128         default:
2129                 return -EINVAL;
2130         }
2131
2132         switch (dai->id) {
2133         case RT5682_AIF1:
2134                 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2135                         RT5682_I2S_DF_MASK, reg_val);
2136                 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2137                         RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2138                         RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2139                         RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2140                         tdm_ctrl | rt5682->master[dai->id]);
2141                 break;
2142         case RT5682_AIF2:
2143                 if (rt5682->master[dai->id] == 0)
2144                         reg_val |= RT5682_I2S2_MS_S;
2145                 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2146                         RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2147                         RT5682_I2S_DF_MASK, reg_val);
2148                 break;
2149         default:
2150                 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2151                 return -EINVAL;
2152         }
2153         return 0;
2154 }
2155
2156 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2157                 int clk_id, int source, unsigned int freq, int dir)
2158 {
2159         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2160         unsigned int reg_val = 0, src = 0;
2161
2162         if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2163                 return 0;
2164
2165         switch (clk_id) {
2166         case RT5682_SCLK_S_MCLK:
2167                 reg_val |= RT5682_SCLK_SRC_MCLK;
2168                 src = RT5682_CLK_SRC_MCLK;
2169                 break;
2170         case RT5682_SCLK_S_PLL1:
2171                 reg_val |= RT5682_SCLK_SRC_PLL1;
2172                 src = RT5682_CLK_SRC_PLL1;
2173                 break;
2174         case RT5682_SCLK_S_PLL2:
2175                 reg_val |= RT5682_SCLK_SRC_PLL2;
2176                 src = RT5682_CLK_SRC_PLL2;
2177                 break;
2178         case RT5682_SCLK_S_RCCLK:
2179                 reg_val |= RT5682_SCLK_SRC_RCCLK;
2180                 src = RT5682_CLK_SRC_RCCLK;
2181                 break;
2182         default:
2183                 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2184                 return -EINVAL;
2185         }
2186         snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2187                 RT5682_SCLK_SRC_MASK, reg_val);
2188
2189         if (rt5682->master[RT5682_AIF2]) {
2190                 snd_soc_component_update_bits(component,
2191                         RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2192                         src << RT5682_I2S2_SRC_SFT);
2193         }
2194
2195         rt5682->sysclk = freq;
2196         rt5682->sysclk_src = clk_id;
2197
2198         dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2199                 freq, clk_id);
2200
2201         return 0;
2202 }
2203
2204 static int rt5682_set_component_pll(struct snd_soc_component *component,
2205                 int pll_id, int source, unsigned int freq_in,
2206                 unsigned int freq_out)
2207 {
2208         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2209         struct rl6231_pll_code pll_code;
2210         int ret;
2211
2212         if (source == rt5682->pll_src && freq_in == rt5682->pll_in &&
2213             freq_out == rt5682->pll_out)
2214                 return 0;
2215
2216         if (!freq_in || !freq_out) {
2217                 dev_dbg(component->dev, "PLL disabled\n");
2218
2219                 rt5682->pll_in = 0;
2220                 rt5682->pll_out = 0;
2221                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2222                         RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2223                 return 0;
2224         }
2225
2226         switch (source) {
2227         case RT5682_PLL1_S_MCLK:
2228                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2229                         RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK);
2230                 break;
2231         case RT5682_PLL1_S_BCLK1:
2232                 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2233                                 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1);
2234                 break;
2235         default:
2236                 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2237                 return -EINVAL;
2238         }
2239
2240         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2241         if (ret < 0) {
2242                 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2243                 return ret;
2244         }
2245
2246         dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2247                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2248                 pll_code.n_code, pll_code.k_code);
2249
2250         snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2251                 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2252         snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2253                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2254                 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2255
2256         rt5682->pll_in = freq_in;
2257         rt5682->pll_out = freq_out;
2258         rt5682->pll_src = source;
2259
2260         return 0;
2261 }
2262
2263 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2264 {
2265         struct snd_soc_component *component = dai->component;
2266         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2267
2268         rt5682->bclk[dai->id] = ratio;
2269
2270         switch (ratio) {
2271         case 64:
2272                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2273                         RT5682_I2S2_BCLK_MS2_MASK,
2274                         RT5682_I2S2_BCLK_MS2_64);
2275                 break;
2276         case 32:
2277                 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2278                         RT5682_I2S2_BCLK_MS2_MASK,
2279                         RT5682_I2S2_BCLK_MS2_32);
2280                 break;
2281         default:
2282                 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2283                 return -EINVAL;
2284         }
2285
2286         return 0;
2287 }
2288
2289 static int rt5682_set_bias_level(struct snd_soc_component *component,
2290                         enum snd_soc_bias_level level)
2291 {
2292         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2293
2294         switch (level) {
2295         case SND_SOC_BIAS_PREPARE:
2296                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2297                         RT5682_PWR_BG, RT5682_PWR_BG);
2298                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2299                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2300                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2301                 break;
2302
2303         case SND_SOC_BIAS_STANDBY:
2304                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2305                         RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2306                 break;
2307         case SND_SOC_BIAS_OFF:
2308                 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2309                         RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2310                 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2311                         RT5682_PWR_BG, 0);
2312                 break;
2313
2314         default:
2315                 break;
2316         }
2317
2318         return 0;
2319 }
2320
2321 static int rt5682_probe(struct snd_soc_component *component)
2322 {
2323         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2324
2325         rt5682->component = component;
2326
2327         return 0;
2328 }
2329
2330 static void rt5682_remove(struct snd_soc_component *component)
2331 {
2332         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2333
2334         rt5682_reset(rt5682->regmap);
2335 }
2336
2337 #ifdef CONFIG_PM
2338 static int rt5682_suspend(struct snd_soc_component *component)
2339 {
2340         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2341
2342         regcache_cache_only(rt5682->regmap, true);
2343         regcache_mark_dirty(rt5682->regmap);
2344         return 0;
2345 }
2346
2347 static int rt5682_resume(struct snd_soc_component *component)
2348 {
2349         struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2350
2351         regcache_cache_only(rt5682->regmap, false);
2352         regcache_sync(rt5682->regmap);
2353
2354         rt5682_irq(0, rt5682);
2355
2356         return 0;
2357 }
2358 #else
2359 #define rt5682_suspend NULL
2360 #define rt5682_resume NULL
2361 #endif
2362
2363 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2364 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2365                 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2366
2367 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2368         .hw_params = rt5682_hw_params,
2369         .set_fmt = rt5682_set_dai_fmt,
2370         .set_tdm_slot = rt5682_set_tdm_slot,
2371 };
2372
2373 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2374         .hw_params = rt5682_hw_params,
2375         .set_fmt = rt5682_set_dai_fmt,
2376         .set_bclk_ratio = rt5682_set_bclk_ratio,
2377 };
2378
2379 static struct snd_soc_dai_driver rt5682_dai[] = {
2380         {
2381                 .name = "rt5682-aif1",
2382                 .id = RT5682_AIF1,
2383                 .playback = {
2384                         .stream_name = "AIF1 Playback",
2385                         .channels_min = 1,
2386                         .channels_max = 2,
2387                         .rates = RT5682_STEREO_RATES,
2388                         .formats = RT5682_FORMATS,
2389                 },
2390                 .capture = {
2391                         .stream_name = "AIF1 Capture",
2392                         .channels_min = 1,
2393                         .channels_max = 2,
2394                         .rates = RT5682_STEREO_RATES,
2395                         .formats = RT5682_FORMATS,
2396                 },
2397                 .ops = &rt5682_aif1_dai_ops,
2398         },
2399         {
2400                 .name = "rt5682-aif2",
2401                 .id = RT5682_AIF2,
2402                 .capture = {
2403                         .stream_name = "AIF2 Capture",
2404                         .channels_min = 1,
2405                         .channels_max = 2,
2406                         .rates = RT5682_STEREO_RATES,
2407                         .formats = RT5682_FORMATS,
2408                 },
2409                 .ops = &rt5682_aif2_dai_ops,
2410         },
2411 };
2412
2413 static const struct snd_soc_component_driver soc_component_dev_rt5682 = {
2414         .probe = rt5682_probe,
2415         .remove = rt5682_remove,
2416         .suspend = rt5682_suspend,
2417         .resume = rt5682_resume,
2418         .set_bias_level = rt5682_set_bias_level,
2419         .controls = rt5682_snd_controls,
2420         .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2421         .dapm_widgets = rt5682_dapm_widgets,
2422         .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2423         .dapm_routes = rt5682_dapm_routes,
2424         .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2425         .set_sysclk = rt5682_set_component_sysclk,
2426         .set_pll = rt5682_set_component_pll,
2427         .set_jack = rt5682_set_jack_detect,
2428         .use_pmdown_time        = 1,
2429         .endianness             = 1,
2430         .non_legacy_dai_naming  = 1,
2431 };
2432
2433 static const struct regmap_config rt5682_regmap = {
2434         .reg_bits = 16,
2435         .val_bits = 16,
2436         .max_register = RT5682_I2C_MODE,
2437         .volatile_reg = rt5682_volatile_register,
2438         .readable_reg = rt5682_readable_register,
2439         .cache_type = REGCACHE_RBTREE,
2440         .reg_defaults = rt5682_reg,
2441         .num_reg_defaults = ARRAY_SIZE(rt5682_reg),
2442         .use_single_read = true,
2443         .use_single_write = true,
2444 };
2445
2446 static const struct i2c_device_id rt5682_i2c_id[] = {
2447         {"rt5682", 0},
2448         {}
2449 };
2450 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
2451
2452 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2453 {
2454
2455         device_property_read_u32(dev, "realtek,dmic1-data-pin",
2456                 &rt5682->pdata.dmic1_data_pin);
2457         device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2458                 &rt5682->pdata.dmic1_clk_pin);
2459         device_property_read_u32(dev, "realtek,jd-src",
2460                 &rt5682->pdata.jd_src);
2461         device_property_read_u32(dev, "realtek,btndet-delay",
2462                 &rt5682->pdata.btndet_delay);
2463
2464         rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2465                 "realtek,ldo1-en-gpios", 0);
2466
2467         return 0;
2468 }
2469
2470 static void rt5682_calibrate(struct rt5682_priv *rt5682)
2471 {
2472         int value, count;
2473
2474         mutex_lock(&rt5682->calibrate_mutex);
2475
2476         rt5682_reset(rt5682->regmap);
2477         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
2478         usleep_range(15000, 20000);
2479         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
2480         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
2481         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
2482         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
2483         regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
2484         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
2485         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
2486         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
2487         regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
2488         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
2489         regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
2490         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2491         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
2492         regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
2493         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2494
2495         regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
2496
2497         for (count = 0; count < 60; count++) {
2498                 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
2499                 if (!(value & 0x8000))
2500                         break;
2501
2502                 usleep_range(10000, 10005);
2503         }
2504
2505         if (count >= 60)
2506                 pr_err("HP Calibration Failure\n");
2507
2508         /* restore settings */
2509         regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af);
2510         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
2511         regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
2512         regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
2513         regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
2514         regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
2515         regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
2516
2517         mutex_unlock(&rt5682->calibrate_mutex);
2518
2519 }
2520
2521 static int rt5682_i2c_probe(struct i2c_client *i2c,
2522                     const struct i2c_device_id *id)
2523 {
2524         struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
2525         struct rt5682_priv *rt5682;
2526         int i, ret;
2527         unsigned int val;
2528
2529         rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
2530                 GFP_KERNEL);
2531
2532         if (rt5682 == NULL)
2533                 return -ENOMEM;
2534
2535         i2c_set_clientdata(i2c, rt5682);
2536
2537         rt5682->pdata = i2s_default_platform_data;
2538
2539         if (pdata)
2540                 rt5682->pdata = *pdata;
2541         else
2542                 rt5682_parse_dt(rt5682, &i2c->dev);
2543
2544         rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
2545         if (IS_ERR(rt5682->regmap)) {
2546                 ret = PTR_ERR(rt5682->regmap);
2547                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2548                         ret);
2549                 return ret;
2550         }
2551
2552         for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
2553                 rt5682->supplies[i].supply = rt5682_supply_names[i];
2554
2555         ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
2556                                       rt5682->supplies);
2557         if (ret != 0) {
2558                 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2559                 return ret;
2560         }
2561
2562         ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
2563                                     rt5682->supplies);
2564         if (ret != 0) {
2565                 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2566                 return ret;
2567         }
2568
2569         if (gpio_is_valid(rt5682->pdata.ldo1_en)) {
2570                 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en,
2571                                           GPIOF_OUT_INIT_HIGH, "rt5682"))
2572                         dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2573         }
2574
2575         /* Sleep for 300 ms miniumum */
2576         usleep_range(300000, 350000);
2577
2578         regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
2579         usleep_range(10000, 15000);
2580
2581         regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
2582         if (val != DEVICE_ID) {
2583                 pr_err("Device with ID register %x is not rt5682\n", val);
2584                 return -ENODEV;
2585         }
2586
2587         rt5682_reset(rt5682->regmap);
2588
2589         mutex_init(&rt5682->calibrate_mutex);
2590         rt5682_calibrate(rt5682);
2591
2592         ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
2593                                     ARRAY_SIZE(patch_list));
2594         if (ret != 0)
2595                 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2596
2597         regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
2598
2599         /* DMIC pin*/
2600         if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
2601                 switch (rt5682->pdata.dmic1_data_pin) {
2602                 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */
2603                         regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2604                                 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
2605                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2606                                 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
2607                         break;
2608
2609                 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
2610                         regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2611                                 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
2612                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2613                                 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
2614                         break;
2615
2616                 default:
2617                         dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
2618                         break;
2619                 }
2620
2621                 switch (rt5682->pdata.dmic1_clk_pin) {
2622                 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */
2623                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2624                                 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
2625                         break;
2626
2627                 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */
2628                         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2629                                 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
2630                         break;
2631
2632                 default:
2633                         dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
2634                         break;
2635                 }
2636         }
2637
2638         regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2639                         RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
2640                         RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
2641         regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2642         regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2643                         RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
2644                         RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
2645         regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2646         regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
2647                         RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
2648         regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
2649                         RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
2650         regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1,
2651                         RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
2652
2653         INIT_DELAYED_WORK(&rt5682->jack_detect_work,
2654                                 rt5682_jack_detect_handler);
2655         INIT_DELAYED_WORK(&rt5682->jd_check_work,
2656                                 rt5682_jd_check_handler);
2657
2658
2659         if (i2c->irq) {
2660                 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2661                         rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2662                         | IRQF_ONESHOT, "rt5682", rt5682);
2663                 if (ret)
2664                         dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2665
2666         }
2667
2668         return devm_snd_soc_register_component(&i2c->dev,
2669                                         &soc_component_dev_rt5682,
2670                                         rt5682_dai, ARRAY_SIZE(rt5682_dai));
2671 }
2672
2673 static void rt5682_i2c_shutdown(struct i2c_client *client)
2674 {
2675         struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
2676
2677         rt5682_reset(rt5682->regmap);
2678 }
2679
2680 #ifdef CONFIG_OF
2681 static const struct of_device_id rt5682_of_match[] = {
2682         {.compatible = "realtek,rt5682i"},
2683         {},
2684 };
2685 MODULE_DEVICE_TABLE(of, rt5682_of_match);
2686 #endif
2687
2688 #ifdef CONFIG_ACPI
2689 static const struct acpi_device_id rt5682_acpi_match[] = {
2690         {"10EC5682", 0,},
2691         {},
2692 };
2693 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
2694 #endif
2695
2696 static struct i2c_driver rt5682_i2c_driver = {
2697         .driver = {
2698                 .name = "rt5682",
2699                 .of_match_table = of_match_ptr(rt5682_of_match),
2700                 .acpi_match_table = ACPI_PTR(rt5682_acpi_match),
2701         },
2702         .probe = rt5682_i2c_probe,
2703         .shutdown = rt5682_i2c_shutdown,
2704         .id_table = rt5682_i2c_id,
2705 };
2706 module_i2c_driver(rt5682_i2c_driver);
2707
2708 MODULE_DESCRIPTION("ASoC RT5682 driver");
2709 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2710 MODULE_LICENSE("GPL v2");