2 * rt5682.c -- RT5682 ALSA SoC audio component driver
4 * Copyright 2018 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/acpi.h>
21 #include <linux/gpio.h>
22 #include <linux/of_gpio.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/mutex.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/jack.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <sound/rt5682.h>
38 #define RT5682_NUM_SUPPLIES 3
40 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
46 static const struct rt5682_platform_data i2s_default_platform_data = {
47 .dmic1_data_pin = RT5682_DMIC1_DATA_GPIO2,
48 .dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3,
53 struct snd_soc_component *component;
54 struct rt5682_platform_data pdata;
55 struct regmap *regmap;
56 struct snd_soc_jack *hs_jack;
57 struct regulator_bulk_data supplies[RT5682_NUM_SUPPLIES];
58 struct delayed_work jack_detect_work;
59 struct delayed_work jd_check_work;
60 struct mutex calibrate_mutex;
64 int lrck[RT5682_AIFS];
65 int bclk[RT5682_AIFS];
66 int master[RT5682_AIFS];
75 static const struct reg_sequence patch_list[] = {
76 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
77 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
80 static const struct reg_default rt5682_reg[] = {
401 static bool rt5682_volatile_register(struct device *dev, unsigned int reg)
405 case RT5682_CBJ_CTRL_2:
406 case RT5682_INT_ST_1:
407 case RT5682_4BTN_IL_CMD_1:
408 case RT5682_AJD1_CTRL:
409 case RT5682_HP_CALIB_CTRL_1:
410 case RT5682_DEVICE_ID:
411 case RT5682_I2C_MODE:
412 case RT5682_HP_CALIB_CTRL_10:
413 case RT5682_EFUSE_CTRL_2:
414 case RT5682_JD_TOP_VC_VTRL:
415 case RT5682_HP_IMP_SENS_CTRL_19:
416 case RT5682_IL_CMD_1:
417 case RT5682_SAR_IL_CMD_2:
418 case RT5682_SAR_IL_CMD_4:
419 case RT5682_SAR_IL_CMD_10:
420 case RT5682_SAR_IL_CMD_11:
421 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
422 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
429 static bool rt5682_readable_register(struct device *dev, unsigned int reg)
433 case RT5682_VERSION_ID:
434 case RT5682_VENDOR_ID:
435 case RT5682_DEVICE_ID:
436 case RT5682_HP_CTRL_1:
437 case RT5682_HP_CTRL_2:
438 case RT5682_HPL_GAIN:
439 case RT5682_HPR_GAIN:
440 case RT5682_I2C_CTRL:
441 case RT5682_CBJ_BST_CTRL:
442 case RT5682_CBJ_CTRL_1:
443 case RT5682_CBJ_CTRL_2:
444 case RT5682_CBJ_CTRL_3:
445 case RT5682_CBJ_CTRL_4:
446 case RT5682_CBJ_CTRL_5:
447 case RT5682_CBJ_CTRL_6:
448 case RT5682_CBJ_CTRL_7:
449 case RT5682_DAC1_DIG_VOL:
450 case RT5682_STO1_ADC_DIG_VOL:
451 case RT5682_STO1_ADC_BOOST:
452 case RT5682_HP_IMP_GAIN_1:
453 case RT5682_HP_IMP_GAIN_2:
454 case RT5682_SIDETONE_CTRL:
455 case RT5682_STO1_ADC_MIXER:
456 case RT5682_AD_DA_MIXER:
457 case RT5682_STO1_DAC_MIXER:
458 case RT5682_A_DAC1_MUX:
459 case RT5682_DIG_INF2_DATA:
460 case RT5682_REC_MIXER:
462 case RT5682_ALC_BACK_GAIN:
463 case RT5682_PWR_DIG_1:
464 case RT5682_PWR_DIG_2:
465 case RT5682_PWR_ANLG_1:
466 case RT5682_PWR_ANLG_2:
467 case RT5682_PWR_ANLG_3:
468 case RT5682_PWR_MIXER:
471 case RT5682_RESET_LPF_CTRL:
472 case RT5682_RESET_HPF_CTRL:
473 case RT5682_DMIC_CTRL_1:
474 case RT5682_I2S1_SDP:
475 case RT5682_I2S2_SDP:
476 case RT5682_ADDA_CLK_1:
477 case RT5682_ADDA_CLK_2:
478 case RT5682_I2S1_F_DIV_CTRL_1:
479 case RT5682_I2S1_F_DIV_CTRL_2:
480 case RT5682_TDM_CTRL:
481 case RT5682_TDM_ADDA_CTRL_1:
482 case RT5682_TDM_ADDA_CTRL_2:
483 case RT5682_DATA_SEL_CTRL_1:
484 case RT5682_TDM_TCON_CTRL:
486 case RT5682_PLL_CTRL_1:
487 case RT5682_PLL_CTRL_2:
488 case RT5682_PLL_TRACK_1:
489 case RT5682_PLL_TRACK_2:
490 case RT5682_PLL_TRACK_3:
491 case RT5682_PLL_TRACK_4:
492 case RT5682_PLL_TRACK_5:
493 case RT5682_PLL_TRACK_6:
494 case RT5682_PLL_TRACK_11:
495 case RT5682_SDW_REF_CLK:
498 case RT5682_HP_CHARGE_PUMP_1:
499 case RT5682_HP_CHARGE_PUMP_2:
500 case RT5682_MICBIAS_1:
501 case RT5682_MICBIAS_2:
502 case RT5682_PLL_TRACK_12:
503 case RT5682_PLL_TRACK_14:
504 case RT5682_PLL2_CTRL_1:
505 case RT5682_PLL2_CTRL_2:
506 case RT5682_PLL2_CTRL_3:
507 case RT5682_PLL2_CTRL_4:
508 case RT5682_RC_CLK_CTRL:
509 case RT5682_I2S_M_CLK_CTRL_1:
510 case RT5682_I2S2_F_DIV_CTRL_1:
511 case RT5682_I2S2_F_DIV_CTRL_2:
512 case RT5682_EQ_CTRL_1:
513 case RT5682_EQ_CTRL_2:
514 case RT5682_IRQ_CTRL_1:
515 case RT5682_IRQ_CTRL_2:
516 case RT5682_IRQ_CTRL_3:
517 case RT5682_IRQ_CTRL_4:
518 case RT5682_INT_ST_1:
519 case RT5682_GPIO_CTRL_1:
520 case RT5682_GPIO_CTRL_2:
521 case RT5682_GPIO_CTRL_3:
522 case RT5682_HP_AMP_DET_CTRL_1:
523 case RT5682_HP_AMP_DET_CTRL_2:
524 case RT5682_MID_HP_AMP_DET:
525 case RT5682_LOW_HP_AMP_DET:
526 case RT5682_DELAY_BUF_CTRL:
527 case RT5682_SV_ZCD_1:
528 case RT5682_SV_ZCD_2:
529 case RT5682_IL_CMD_1:
530 case RT5682_IL_CMD_2:
531 case RT5682_IL_CMD_3:
532 case RT5682_IL_CMD_4:
533 case RT5682_IL_CMD_5:
534 case RT5682_IL_CMD_6:
535 case RT5682_4BTN_IL_CMD_1:
536 case RT5682_4BTN_IL_CMD_2:
537 case RT5682_4BTN_IL_CMD_3:
538 case RT5682_4BTN_IL_CMD_4:
539 case RT5682_4BTN_IL_CMD_5:
540 case RT5682_4BTN_IL_CMD_6:
541 case RT5682_4BTN_IL_CMD_7:
542 case RT5682_ADC_STO1_HP_CTRL_1:
543 case RT5682_ADC_STO1_HP_CTRL_2:
544 case RT5682_AJD1_CTRL:
547 case RT5682_JD_CTRL_1:
551 case RT5682_DAC_ADC_DIG_VOL1:
552 case RT5682_BIAS_CUR_CTRL_2:
553 case RT5682_BIAS_CUR_CTRL_3:
554 case RT5682_BIAS_CUR_CTRL_4:
555 case RT5682_BIAS_CUR_CTRL_5:
556 case RT5682_BIAS_CUR_CTRL_6:
557 case RT5682_BIAS_CUR_CTRL_7:
558 case RT5682_BIAS_CUR_CTRL_8:
559 case RT5682_BIAS_CUR_CTRL_9:
560 case RT5682_BIAS_CUR_CTRL_10:
561 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
562 case RT5682_CHARGE_PUMP_1:
563 case RT5682_DIG_IN_CTRL_1:
564 case RT5682_PAD_DRIVING_CTRL:
565 case RT5682_SOFT_RAMP_DEPOP:
566 case RT5682_CHOP_DAC:
567 case RT5682_CHOP_ADC:
568 case RT5682_CALIB_ADC_CTRL:
569 case RT5682_VOL_TEST:
570 case RT5682_SPKVDD_DET_STA:
571 case RT5682_TEST_MODE_CTRL_1:
572 case RT5682_TEST_MODE_CTRL_2:
573 case RT5682_TEST_MODE_CTRL_3:
574 case RT5682_TEST_MODE_CTRL_4:
575 case RT5682_TEST_MODE_CTRL_5:
576 case RT5682_PLL1_INTERNAL:
577 case RT5682_PLL2_INTERNAL:
578 case RT5682_STO_NG2_CTRL_1:
579 case RT5682_STO_NG2_CTRL_2:
580 case RT5682_STO_NG2_CTRL_3:
581 case RT5682_STO_NG2_CTRL_4:
582 case RT5682_STO_NG2_CTRL_5:
583 case RT5682_STO_NG2_CTRL_6:
584 case RT5682_STO_NG2_CTRL_7:
585 case RT5682_STO_NG2_CTRL_8:
586 case RT5682_STO_NG2_CTRL_9:
587 case RT5682_STO_NG2_CTRL_10:
588 case RT5682_STO1_DAC_SIL_DET:
589 case RT5682_SIL_PSV_CTRL1:
590 case RT5682_SIL_PSV_CTRL2:
591 case RT5682_SIL_PSV_CTRL3:
592 case RT5682_SIL_PSV_CTRL4:
593 case RT5682_SIL_PSV_CTRL5:
594 case RT5682_HP_IMP_SENS_CTRL_01:
595 case RT5682_HP_IMP_SENS_CTRL_02:
596 case RT5682_HP_IMP_SENS_CTRL_03:
597 case RT5682_HP_IMP_SENS_CTRL_04:
598 case RT5682_HP_IMP_SENS_CTRL_05:
599 case RT5682_HP_IMP_SENS_CTRL_06:
600 case RT5682_HP_IMP_SENS_CTRL_07:
601 case RT5682_HP_IMP_SENS_CTRL_08:
602 case RT5682_HP_IMP_SENS_CTRL_09:
603 case RT5682_HP_IMP_SENS_CTRL_10:
604 case RT5682_HP_IMP_SENS_CTRL_11:
605 case RT5682_HP_IMP_SENS_CTRL_12:
606 case RT5682_HP_IMP_SENS_CTRL_13:
607 case RT5682_HP_IMP_SENS_CTRL_14:
608 case RT5682_HP_IMP_SENS_CTRL_15:
609 case RT5682_HP_IMP_SENS_CTRL_16:
610 case RT5682_HP_IMP_SENS_CTRL_17:
611 case RT5682_HP_IMP_SENS_CTRL_18:
612 case RT5682_HP_IMP_SENS_CTRL_19:
613 case RT5682_HP_IMP_SENS_CTRL_20:
614 case RT5682_HP_IMP_SENS_CTRL_21:
615 case RT5682_HP_IMP_SENS_CTRL_22:
616 case RT5682_HP_IMP_SENS_CTRL_23:
617 case RT5682_HP_IMP_SENS_CTRL_24:
618 case RT5682_HP_IMP_SENS_CTRL_25:
619 case RT5682_HP_IMP_SENS_CTRL_26:
620 case RT5682_HP_IMP_SENS_CTRL_27:
621 case RT5682_HP_IMP_SENS_CTRL_28:
622 case RT5682_HP_IMP_SENS_CTRL_29:
623 case RT5682_HP_IMP_SENS_CTRL_30:
624 case RT5682_HP_IMP_SENS_CTRL_31:
625 case RT5682_HP_IMP_SENS_CTRL_32:
626 case RT5682_HP_IMP_SENS_CTRL_33:
627 case RT5682_HP_IMP_SENS_CTRL_34:
628 case RT5682_HP_IMP_SENS_CTRL_35:
629 case RT5682_HP_IMP_SENS_CTRL_36:
630 case RT5682_HP_IMP_SENS_CTRL_37:
631 case RT5682_HP_IMP_SENS_CTRL_38:
632 case RT5682_HP_IMP_SENS_CTRL_39:
633 case RT5682_HP_IMP_SENS_CTRL_40:
634 case RT5682_HP_IMP_SENS_CTRL_41:
635 case RT5682_HP_IMP_SENS_CTRL_42:
636 case RT5682_HP_IMP_SENS_CTRL_43:
637 case RT5682_HP_LOGIC_CTRL_1:
638 case RT5682_HP_LOGIC_CTRL_2:
639 case RT5682_HP_LOGIC_CTRL_3:
640 case RT5682_HP_CALIB_CTRL_1:
641 case RT5682_HP_CALIB_CTRL_2:
642 case RT5682_HP_CALIB_CTRL_3:
643 case RT5682_HP_CALIB_CTRL_4:
644 case RT5682_HP_CALIB_CTRL_5:
645 case RT5682_HP_CALIB_CTRL_6:
646 case RT5682_HP_CALIB_CTRL_7:
647 case RT5682_HP_CALIB_CTRL_9:
648 case RT5682_HP_CALIB_CTRL_10:
649 case RT5682_HP_CALIB_CTRL_11:
650 case RT5682_HP_CALIB_STA_1:
651 case RT5682_HP_CALIB_STA_2:
652 case RT5682_HP_CALIB_STA_3:
653 case RT5682_HP_CALIB_STA_4:
654 case RT5682_HP_CALIB_STA_5:
655 case RT5682_HP_CALIB_STA_6:
656 case RT5682_HP_CALIB_STA_7:
657 case RT5682_HP_CALIB_STA_8:
658 case RT5682_HP_CALIB_STA_9:
659 case RT5682_HP_CALIB_STA_10:
660 case RT5682_HP_CALIB_STA_11:
661 case RT5682_SAR_IL_CMD_1:
662 case RT5682_SAR_IL_CMD_2:
663 case RT5682_SAR_IL_CMD_3:
664 case RT5682_SAR_IL_CMD_4:
665 case RT5682_SAR_IL_CMD_5:
666 case RT5682_SAR_IL_CMD_6:
667 case RT5682_SAR_IL_CMD_7:
668 case RT5682_SAR_IL_CMD_8:
669 case RT5682_SAR_IL_CMD_9:
670 case RT5682_SAR_IL_CMD_10:
671 case RT5682_SAR_IL_CMD_11:
672 case RT5682_SAR_IL_CMD_12:
673 case RT5682_SAR_IL_CMD_13:
674 case RT5682_EFUSE_CTRL_1:
675 case RT5682_EFUSE_CTRL_2:
676 case RT5682_EFUSE_CTRL_3:
677 case RT5682_EFUSE_CTRL_4:
678 case RT5682_EFUSE_CTRL_5:
679 case RT5682_EFUSE_CTRL_6:
680 case RT5682_EFUSE_CTRL_7:
681 case RT5682_EFUSE_CTRL_8:
682 case RT5682_EFUSE_CTRL_9:
683 case RT5682_EFUSE_CTRL_10:
684 case RT5682_EFUSE_CTRL_11:
685 case RT5682_JD_TOP_VC_VTRL:
686 case RT5682_DRC1_CTRL_0:
687 case RT5682_DRC1_CTRL_1:
688 case RT5682_DRC1_CTRL_2:
689 case RT5682_DRC1_CTRL_3:
690 case RT5682_DRC1_CTRL_4:
691 case RT5682_DRC1_CTRL_5:
692 case RT5682_DRC1_CTRL_6:
693 case RT5682_DRC1_HARD_LMT_CTRL_1:
694 case RT5682_DRC1_HARD_LMT_CTRL_2:
695 case RT5682_DRC1_PRIV_1:
696 case RT5682_DRC1_PRIV_2:
697 case RT5682_DRC1_PRIV_3:
698 case RT5682_DRC1_PRIV_4:
699 case RT5682_DRC1_PRIV_5:
700 case RT5682_DRC1_PRIV_6:
701 case RT5682_DRC1_PRIV_7:
702 case RT5682_DRC1_PRIV_8:
703 case RT5682_EQ_AUTO_RCV_CTRL1:
704 case RT5682_EQ_AUTO_RCV_CTRL2:
705 case RT5682_EQ_AUTO_RCV_CTRL3:
706 case RT5682_EQ_AUTO_RCV_CTRL4:
707 case RT5682_EQ_AUTO_RCV_CTRL5:
708 case RT5682_EQ_AUTO_RCV_CTRL6:
709 case RT5682_EQ_AUTO_RCV_CTRL7:
710 case RT5682_EQ_AUTO_RCV_CTRL8:
711 case RT5682_EQ_AUTO_RCV_CTRL9:
712 case RT5682_EQ_AUTO_RCV_CTRL10:
713 case RT5682_EQ_AUTO_RCV_CTRL11:
714 case RT5682_EQ_AUTO_RCV_CTRL12:
715 case RT5682_EQ_AUTO_RCV_CTRL13:
716 case RT5682_ADC_L_EQ_LPF1_A1:
717 case RT5682_R_EQ_LPF1_A1:
718 case RT5682_L_EQ_LPF1_H0:
719 case RT5682_R_EQ_LPF1_H0:
720 case RT5682_L_EQ_BPF1_A1:
721 case RT5682_R_EQ_BPF1_A1:
722 case RT5682_L_EQ_BPF1_A2:
723 case RT5682_R_EQ_BPF1_A2:
724 case RT5682_L_EQ_BPF1_H0:
725 case RT5682_R_EQ_BPF1_H0:
726 case RT5682_L_EQ_BPF2_A1:
727 case RT5682_R_EQ_BPF2_A1:
728 case RT5682_L_EQ_BPF2_A2:
729 case RT5682_R_EQ_BPF2_A2:
730 case RT5682_L_EQ_BPF2_H0:
731 case RT5682_R_EQ_BPF2_H0:
732 case RT5682_L_EQ_BPF3_A1:
733 case RT5682_R_EQ_BPF3_A1:
734 case RT5682_L_EQ_BPF3_A2:
735 case RT5682_R_EQ_BPF3_A2:
736 case RT5682_L_EQ_BPF3_H0:
737 case RT5682_R_EQ_BPF3_H0:
738 case RT5682_L_EQ_BPF4_A1:
739 case RT5682_R_EQ_BPF4_A1:
740 case RT5682_L_EQ_BPF4_A2:
741 case RT5682_R_EQ_BPF4_A2:
742 case RT5682_L_EQ_BPF4_H0:
743 case RT5682_R_EQ_BPF4_H0:
744 case RT5682_L_EQ_HPF1_A1:
745 case RT5682_R_EQ_HPF1_A1:
746 case RT5682_L_EQ_HPF1_H0:
747 case RT5682_R_EQ_HPF1_H0:
748 case RT5682_L_EQ_PRE_VOL:
749 case RT5682_R_EQ_PRE_VOL:
750 case RT5682_L_EQ_POST_VOL:
751 case RT5682_R_EQ_POST_VOL:
752 case RT5682_I2C_MODE:
759 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
760 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
761 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
763 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
764 static const DECLARE_TLV_DB_RANGE(bst_tlv,
765 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
766 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
767 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
768 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
769 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
770 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
771 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
774 /* Interface data select */
775 static const char * const rt5682_data_select[] = {
776 "L/R", "R/L", "L/L", "R/R"
779 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
780 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
782 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
783 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
785 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
786 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
788 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
789 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
791 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
792 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
794 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
795 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
797 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
798 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
800 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
801 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
803 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
804 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
806 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
807 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
809 static void rt5682_reset(struct regmap *regmap)
811 regmap_write(regmap, RT5682_RESET, 0);
812 regmap_write(regmap, RT5682_I2C_MODE, 1);
815 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
816 * @component: SoC audio component device.
817 * @filter_mask: mask of filters.
818 * @clk_src: clock source
820 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
821 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
822 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
823 * ASRC function will track i2s clock and generate a corresponding system clock
824 * for codec. This function provides an API to select the clock source for a
825 * set of filters specified by the mask. And the component driver will turn on
826 * ASRC for these filters if ASRC is selected as their clock source.
828 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
829 unsigned int filter_mask, unsigned int clk_src)
833 case RT5682_CLK_SEL_SYS:
834 case RT5682_CLK_SEL_I2S1_ASRC:
835 case RT5682_CLK_SEL_I2S2_ASRC:
842 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
843 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
844 RT5682_FILTER_CLK_SEL_MASK,
845 clk_src << RT5682_FILTER_CLK_SEL_SFT);
848 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
849 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
850 RT5682_FILTER_CLK_SEL_MASK,
851 clk_src << RT5682_FILTER_CLK_SEL_SFT);
856 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
858 static int rt5682_button_detect(struct snd_soc_component *component)
862 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
863 btn_type = val & 0xfff0;
864 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
865 pr_debug("%s btn_type=%x\n", __func__, btn_type);
866 snd_soc_component_update_bits(component,
867 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
872 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
876 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
877 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
878 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
879 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
880 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
881 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
882 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
883 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
884 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
885 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_EN);
887 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
888 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
889 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
890 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
891 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
892 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
893 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
894 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
895 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
896 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
901 * rt5682_headset_detect - Detect headset.
902 * @component: SoC audio component device.
903 * @jack_insert: Jack insert or not.
905 * Detect whether is headset or not when jack inserted.
907 * Returns detect status.
909 static int rt5682_headset_detect(struct snd_soc_component *component,
912 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
913 unsigned int val, count;
917 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
918 RT5682_PWR_VREF2 | RT5682_PWR_MB,
919 RT5682_PWR_VREF2 | RT5682_PWR_MB);
920 snd_soc_component_update_bits(component,
921 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
922 usleep_range(15000, 20000);
923 snd_soc_component_update_bits(component,
924 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
925 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
926 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
928 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
929 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
932 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
933 & RT5682_JACK_TYPE_MASK;
934 while (val == 0 && count < 50) {
935 usleep_range(10000, 15000);
936 val = snd_soc_component_read32(component,
937 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
944 rt5682->jack_type = SND_JACK_HEADSET;
945 rt5682_enable_push_button_irq(component, true);
948 rt5682->jack_type = SND_JACK_HEADPHONE;
952 rt5682_enable_push_button_irq(component, false);
953 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
954 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
955 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
956 RT5682_PWR_VREF2 | RT5682_PWR_MB, 0);
957 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
960 rt5682->jack_type = 0;
963 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
964 return rt5682->jack_type;
967 static irqreturn_t rt5682_irq(int irq, void *data)
969 struct rt5682_priv *rt5682 = data;
971 mod_delayed_work(system_power_efficient_wq,
972 &rt5682->jack_detect_work, msecs_to_jiffies(250));
977 static void rt5682_jd_check_handler(struct work_struct *work)
979 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
982 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
983 & RT5682_JDH_RS_MASK) {
985 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
987 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
989 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
990 SND_JACK_BTN_2 | SND_JACK_BTN_3);
992 schedule_delayed_work(&rt5682->jd_check_work, 500);
996 static int rt5682_set_jack_detect(struct snd_soc_component *component,
997 struct snd_soc_jack *hs_jack, void *data)
999 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1001 switch (rt5682->pdata.jd_src) {
1003 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_2,
1004 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
1005 snd_soc_component_write(component, RT5682_CBJ_CTRL_1, 0xd042);
1006 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_3,
1007 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
1008 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
1009 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
1010 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1011 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1012 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1013 RT5682_POW_IRQ | RT5682_POW_JDH |
1014 RT5682_POW_ANA, RT5682_POW_IRQ |
1015 RT5682_POW_JDH | RT5682_POW_ANA);
1016 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1017 RT5682_PWR_JDH | RT5682_PWR_JDL,
1018 RT5682_PWR_JDH | RT5682_PWR_JDL);
1019 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1020 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1021 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1022 mod_delayed_work(system_power_efficient_wq,
1023 &rt5682->jack_detect_work, msecs_to_jiffies(250));
1026 case RT5682_JD_NULL:
1027 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1028 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1029 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1030 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1034 dev_warn(component->dev, "Wrong JD source\n");
1038 rt5682->hs_jack = hs_jack;
1043 static void rt5682_jack_detect_handler(struct work_struct *work)
1045 struct rt5682_priv *rt5682 =
1046 container_of(work, struct rt5682_priv, jack_detect_work.work);
1049 while (!rt5682->component)
1050 usleep_range(10000, 15000);
1052 while (!rt5682->component->card->instantiated)
1053 usleep_range(10000, 15000);
1055 mutex_lock(&rt5682->calibrate_mutex);
1057 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1058 & RT5682_JDH_RS_MASK;
1061 if (rt5682->jack_type == 0) {
1062 /* jack was out, report jack type */
1064 rt5682_headset_detect(rt5682->component, 1);
1066 /* jack is already in, report button event */
1067 rt5682->jack_type = SND_JACK_HEADSET;
1068 btn_type = rt5682_button_detect(rt5682->component);
1070 * rt5682 can report three kinds of button behavior,
1071 * one click, double click and hold. However,
1072 * currently we will report button pressed/released
1073 * event. So all the three button behaviors are
1074 * treated as button pressed.
1080 rt5682->jack_type |= SND_JACK_BTN_0;
1085 rt5682->jack_type |= SND_JACK_BTN_1;
1090 rt5682->jack_type |= SND_JACK_BTN_2;
1095 rt5682->jack_type |= SND_JACK_BTN_3;
1097 case 0x0000: /* unpressed */
1101 dev_err(rt5682->component->dev,
1102 "Unexpected button code 0x%04x\n",
1109 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1112 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1114 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1115 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1117 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1118 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1119 schedule_delayed_work(&rt5682->jd_check_work, 0);
1121 cancel_delayed_work_sync(&rt5682->jd_check_work);
1123 mutex_unlock(&rt5682->calibrate_mutex);
1126 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1127 /* DAC Digital Volume */
1128 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1129 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 86, 0, dac_vol_tlv),
1131 /* IN Boost Volume */
1132 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1133 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1135 /* ADC Digital Volume Control */
1136 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1137 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1138 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1139 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1141 /* ADC Boost Volume Control */
1142 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1143 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1148 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1149 int target, const int div[], int size)
1153 if (rt5682->sysclk < target) {
1154 pr_err("sysclk rate %d is too low\n",
1159 for (i = 0; i < size - 1; i++) {
1160 pr_info("div[%d]=%d\n", i, div[i]);
1161 if (target * div[i] == rt5682->sysclk)
1163 if (target * div[i + 1] > rt5682->sysclk) {
1164 pr_err("can't find div for sysclk %d\n",
1170 if (target * div[i] < rt5682->sysclk)
1171 pr_err("sysclk rate %d is too high\n",
1179 * set_dmic_clk - Set parameter of dmic.
1182 * @kcontrol: The kcontrol of this widget.
1185 * Choose dmic clock between 1MHz and 3MHz.
1186 * It is better for clock to approximate 3MHz.
1188 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1189 struct snd_kcontrol *kcontrol, int event)
1191 struct snd_soc_component *component =
1192 snd_soc_dapm_to_component(w->dapm);
1193 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1195 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1197 idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
1199 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1200 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1205 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1206 struct snd_kcontrol *kcontrol, int event)
1208 struct snd_soc_component *component =
1209 snd_soc_dapm_to_component(w->dapm);
1210 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1211 int ref, val, reg, idx = -EINVAL;
1212 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1213 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1215 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1216 RT5682_GP4_PIN_MASK;
1217 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1218 val == RT5682_GP4_PIN_ADCDAT2)
1219 ref = 256 * rt5682->lrck[RT5682_AIF2];
1221 ref = 256 * rt5682->lrck[RT5682_AIF1];
1223 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1225 if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1226 reg = RT5682_PLL_TRACK_3;
1228 reg = RT5682_PLL_TRACK_2;
1230 snd_soc_component_update_bits(component, reg,
1231 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1233 /* select over sample rate */
1234 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1235 if (rt5682->sysclk <= 12288000 * div_o[idx])
1239 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1240 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1241 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1246 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1247 struct snd_soc_dapm_widget *sink)
1250 struct snd_soc_component *component =
1251 snd_soc_dapm_to_component(w->dapm);
1253 val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1254 val &= RT5682_SCLK_SRC_MASK;
1255 if (val == RT5682_SCLK_SRC_PLL1)
1261 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1262 struct snd_soc_dapm_widget *sink)
1264 unsigned int reg, shift, val;
1265 struct snd_soc_component *component =
1266 snd_soc_dapm_to_component(w->dapm);
1269 case RT5682_ADC_STO1_ASRC_SFT:
1270 reg = RT5682_PLL_TRACK_3;
1271 shift = RT5682_FILTER_CLK_SEL_SFT;
1273 case RT5682_DAC_STO1_ASRC_SFT:
1274 reg = RT5682_PLL_TRACK_2;
1275 shift = RT5682_FILTER_CLK_SEL_SFT;
1281 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1283 case RT5682_CLK_SEL_I2S1_ASRC:
1284 case RT5682_CLK_SEL_I2S2_ASRC:
1293 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1294 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1295 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1296 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1297 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1300 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1301 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1302 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1303 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1304 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1307 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1308 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1309 RT5682_M_ADCMIX_L_SFT, 1, 1),
1310 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1311 RT5682_M_DAC1_L_SFT, 1, 1),
1314 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1315 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1316 RT5682_M_ADCMIX_R_SFT, 1, 1),
1317 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1318 RT5682_M_DAC1_R_SFT, 1, 1),
1321 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1322 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1323 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1324 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1325 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1328 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1329 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1330 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1331 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1332 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1335 /* Analog Input Mixer */
1336 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1337 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1338 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1341 /* STO1 ADC1 Source */
1342 /* MX-26 [13] [5] */
1343 static const char * const rt5682_sto1_adc1_src[] = {
1347 static SOC_ENUM_SINGLE_DECL(
1348 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1349 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1351 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1352 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1354 static SOC_ENUM_SINGLE_DECL(
1355 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1356 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1358 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1359 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1361 /* STO1 ADC Source */
1362 /* MX-26 [11:10] [3:2] */
1363 static const char * const rt5682_sto1_adc_src[] = {
1367 static SOC_ENUM_SINGLE_DECL(
1368 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1369 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1371 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1372 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1374 static SOC_ENUM_SINGLE_DECL(
1375 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1376 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1378 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1379 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1381 /* STO1 ADC2 Source */
1382 /* MX-26 [12] [4] */
1383 static const char * const rt5682_sto1_adc2_src[] = {
1387 static SOC_ENUM_SINGLE_DECL(
1388 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1389 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1391 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1392 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1394 static SOC_ENUM_SINGLE_DECL(
1395 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1396 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1398 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1399 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1401 /* MX-79 [6:4] I2S1 ADC data location */
1402 static const unsigned int rt5682_if1_adc_slot_values[] = {
1409 static const char * const rt5682_if1_adc_slot_src[] = {
1410 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1413 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1414 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1415 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1417 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1418 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1420 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1421 /* MX-2B [4], MX-2B [0]*/
1422 static const char * const rt5682_alg_dac1_src[] = {
1423 "Stereo1 DAC Mixer", "DAC1"
1426 static SOC_ENUM_SINGLE_DECL(
1427 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1428 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1430 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1431 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1433 static SOC_ENUM_SINGLE_DECL(
1434 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1435 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1437 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1438 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1441 static const struct snd_kcontrol_new hpol_switch =
1442 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1443 RT5682_L_MUTE_SFT, 1, 1);
1444 static const struct snd_kcontrol_new hpor_switch =
1445 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1446 RT5682_R_MUTE_SFT, 1, 1);
1448 static int rt5682_charge_pump_event(struct snd_soc_dapm_widget *w,
1449 struct snd_kcontrol *kcontrol, int event)
1451 struct snd_soc_component *component =
1452 snd_soc_dapm_to_component(w->dapm);
1455 case SND_SOC_DAPM_PRE_PMU:
1456 snd_soc_component_update_bits(component,
1457 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
1459 case SND_SOC_DAPM_POST_PMD:
1460 snd_soc_component_update_bits(component,
1461 RT5682_HP_CHARGE_PUMP_1, RT5682_PM_HP_MASK, RT5682_PM_HP_LV);
1470 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1471 struct snd_kcontrol *kcontrol, int event)
1473 struct snd_soc_component *component =
1474 snd_soc_dapm_to_component(w->dapm);
1477 case SND_SOC_DAPM_PRE_PMU:
1478 snd_soc_component_write(component,
1479 RT5682_HP_LOGIC_CTRL_2, 0x0012);
1480 snd_soc_component_write(component,
1481 RT5682_HP_CTRL_2, 0x6000);
1482 snd_soc_component_update_bits(component,
1483 RT5682_DEPOP_1, 0x60, 0x60);
1484 snd_soc_component_update_bits(component,
1485 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1488 case SND_SOC_DAPM_POST_PMD:
1489 snd_soc_component_update_bits(component,
1490 RT5682_DEPOP_1, 0x60, 0x0);
1491 snd_soc_component_write(component,
1492 RT5682_HP_CTRL_2, 0x0000);
1493 snd_soc_component_update_bits(component,
1494 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1505 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1506 struct snd_kcontrol *kcontrol, int event)
1509 case SND_SOC_DAPM_POST_PMU:
1510 /*Add delay to avoid pop noise*/
1521 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1522 struct snd_kcontrol *kcontrol, int event)
1524 struct snd_soc_component *component =
1525 snd_soc_dapm_to_component(w->dapm);
1528 case SND_SOC_DAPM_PRE_PMU:
1530 case RT5682_PWR_VREF1_BIT:
1531 snd_soc_component_update_bits(component,
1532 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1535 case RT5682_PWR_VREF2_BIT:
1536 snd_soc_component_update_bits(component,
1537 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1545 case SND_SOC_DAPM_POST_PMU:
1546 usleep_range(15000, 20000);
1548 case RT5682_PWR_VREF1_BIT:
1549 snd_soc_component_update_bits(component,
1550 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1554 case RT5682_PWR_VREF2_BIT:
1555 snd_soc_component_update_bits(component,
1556 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1572 static const unsigned int rt5682_adcdat_pin_values[] = {
1577 static const char * const rt5682_adcdat_pin_select[] = {
1582 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1583 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1584 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1586 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1587 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1589 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1590 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1592 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1594 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1596 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1598 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1599 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1602 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1603 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1604 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1605 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1606 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1607 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1608 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1609 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1610 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1611 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1614 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1616 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1620 SND_SOC_DAPM_INPUT("DMIC L1"),
1621 SND_SOC_DAPM_INPUT("DMIC R1"),
1623 SND_SOC_DAPM_INPUT("IN1P"),
1625 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1626 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1627 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1628 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1631 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1635 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1636 ARRAY_SIZE(rt5682_rec1_l_mix)),
1637 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1638 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1641 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1642 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1644 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1645 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1646 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1647 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1648 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1649 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1652 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1653 &rt5682_sto1_adc1l_mux),
1654 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1655 &rt5682_sto1_adc1r_mux),
1656 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1657 &rt5682_sto1_adc2l_mux),
1658 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1659 &rt5682_sto1_adc2r_mux),
1660 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1661 &rt5682_sto1_adcl_mux),
1662 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1663 &rt5682_sto1_adcr_mux),
1664 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1665 &rt5682_if1_adc_slot_mux),
1668 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1669 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1670 SND_SOC_DAPM_PRE_PMU),
1671 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1672 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1673 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1674 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1675 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1676 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1677 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1681 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1683 /* Digital Interface */
1684 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1686 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1688 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1689 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1690 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1692 /* Digital Interface Select */
1693 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1694 &rt5682_if1_01_adc_swap_mux),
1695 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1696 &rt5682_if1_23_adc_swap_mux),
1697 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1698 &rt5682_if1_45_adc_swap_mux),
1699 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1700 &rt5682_if1_67_adc_swap_mux),
1701 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1702 &rt5682_if2_adc_swap_mux),
1704 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1705 &rt5682_adcdat_pin_ctrl),
1707 /* Audio Interface */
1708 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1709 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1710 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1711 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1712 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1715 /* DAC mixer before sound effect */
1716 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1717 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1718 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1719 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1721 /* DAC channel Mux */
1722 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1723 &rt5682_alg_dac_l1_mux),
1724 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1725 &rt5682_alg_dac_r1_mux),
1728 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1729 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1730 SND_SOC_DAPM_PRE_PMU),
1731 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1732 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1733 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1734 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1737 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1738 RT5682_PWR_DAC_L1_BIT, 0),
1739 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1740 RT5682_PWR_DAC_R1_BIT, 0),
1741 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1742 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1745 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1746 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1748 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1749 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1750 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1751 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1752 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1753 RT5682_PUMP_EN_SFT, 0, rt5682_charge_pump_event,
1754 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1755 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1756 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1758 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1760 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1764 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1765 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1766 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1767 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1768 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1769 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1770 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1771 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1774 SND_SOC_DAPM_OUTPUT("HPOL"),
1775 SND_SOC_DAPM_OUTPUT("HPOR"),
1779 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1781 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1782 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1785 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1786 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1787 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1788 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1789 {"ADC STO1 ASRC", NULL, "CLKDET"},
1790 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1791 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1792 {"DAC STO1 ASRC", NULL, "CLKDET"},
1795 {"MICBIAS1", NULL, "Vref1"},
1796 {"MICBIAS2", NULL, "Vref1"},
1798 {"CLKDET SYS", NULL, "CLKDET"},
1800 {"IN1P", NULL, "LDO2"},
1802 {"BST1 CBJ", NULL, "IN1P"},
1804 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1805 {"RECMIX1L", NULL, "RECMIX1L Power"},
1807 {"ADC1 L", NULL, "RECMIX1L"},
1808 {"ADC1 L", NULL, "ADC1 L Power"},
1809 {"ADC1 L", NULL, "ADC1 clock"},
1811 {"DMIC L1", NULL, "DMIC CLK"},
1812 {"DMIC L1", NULL, "DMIC1 Power"},
1813 {"DMIC R1", NULL, "DMIC CLK"},
1814 {"DMIC R1", NULL, "DMIC1 Power"},
1815 {"DMIC CLK", NULL, "DMIC ASRC"},
1817 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1818 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1819 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1820 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1822 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1823 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1824 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1825 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1827 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1828 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1829 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1830 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1832 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1833 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1834 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1836 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1837 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1838 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1840 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1842 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1843 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1845 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1846 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1847 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1848 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1849 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1850 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1851 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1852 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1853 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1854 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1855 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1856 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1857 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1858 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1859 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1860 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1862 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1863 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1864 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1865 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1866 {"IF1_ADC Mux", NULL, "I2S1"},
1867 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1868 {"AIF1TX", NULL, "ADCDAT Mux"},
1869 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1870 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1871 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1872 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1873 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1874 {"AIF2TX", NULL, "ADCDAT Mux"},
1876 {"IF1 DAC1 L", NULL, "AIF1RX"},
1877 {"IF1 DAC1 L", NULL, "I2S1"},
1878 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1879 {"IF1 DAC1 R", NULL, "AIF1RX"},
1880 {"IF1 DAC1 R", NULL, "I2S1"},
1881 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1883 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1884 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1885 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1886 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1888 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1889 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1891 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1892 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1894 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1895 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1896 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1897 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1899 {"DAC L1", NULL, "DAC L1 Source"},
1900 {"DAC R1", NULL, "DAC R1 Source"},
1902 {"DAC L1", NULL, "DAC 1 Clock"},
1903 {"DAC R1", NULL, "DAC 1 Clock"},
1905 {"HP Amp", NULL, "DAC L1"},
1906 {"HP Amp", NULL, "DAC R1"},
1907 {"HP Amp", NULL, "HP Amp L"},
1908 {"HP Amp", NULL, "HP Amp R"},
1909 {"HP Amp", NULL, "Capless"},
1910 {"HP Amp", NULL, "Charge Pump"},
1911 {"HP Amp", NULL, "CLKDET SYS"},
1912 {"HP Amp", NULL, "Vref1"},
1913 {"HPOL Playback", "Switch", "HP Amp"},
1914 {"HPOR Playback", "Switch", "HP Amp"},
1915 {"HPOL", NULL, "HPOL Playback"},
1916 {"HPOR", NULL, "HPOR Playback"},
1919 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1920 unsigned int rx_mask, int slots, int slot_width)
1922 struct snd_soc_component *component = dai->component;
1923 unsigned int cl, val = 0;
1925 if (tx_mask || rx_mask)
1926 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1927 RT5682_TDM_EN, RT5682_TDM_EN);
1929 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1934 val |= RT5682_TDM_TX_CH_4;
1935 val |= RT5682_TDM_RX_CH_4;
1938 val |= RT5682_TDM_TX_CH_6;
1939 val |= RT5682_TDM_RX_CH_6;
1942 val |= RT5682_TDM_TX_CH_8;
1943 val |= RT5682_TDM_RX_CH_8;
1951 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
1952 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
1954 switch (slot_width) {
1956 if (tx_mask || rx_mask)
1958 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
1961 val = RT5682_TDM_CL_16;
1962 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
1965 val = RT5682_TDM_CL_20;
1966 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
1969 val = RT5682_TDM_CL_24;
1970 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
1973 val = RT5682_TDM_CL_32;
1974 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
1980 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
1981 RT5682_TDM_CL_MASK, val);
1982 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
1983 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
1989 static int rt5682_hw_params(struct snd_pcm_substream *substream,
1990 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1992 struct snd_soc_component *component = dai->component;
1993 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1994 unsigned int len_1 = 0, len_2 = 0;
1995 int pre_div, frame_size;
1997 rt5682->lrck[dai->id] = params_rate(params);
1998 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2000 frame_size = snd_soc_params_to_frame_size(params);
2001 if (frame_size < 0) {
2002 dev_err(component->dev, "Unsupported frame size: %d\n",
2007 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2008 rt5682->lrck[dai->id], pre_div, dai->id);
2010 switch (params_width(params)) {
2014 len_1 |= RT5682_I2S1_DL_20;
2015 len_2 |= RT5682_I2S2_DL_20;
2018 len_1 |= RT5682_I2S1_DL_24;
2019 len_2 |= RT5682_I2S2_DL_24;
2022 len_1 |= RT5682_I2S1_DL_32;
2023 len_2 |= RT5682_I2S2_DL_24;
2026 len_1 |= RT5682_I2S2_DL_8;
2027 len_2 |= RT5682_I2S2_DL_8;
2035 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2036 RT5682_I2S1_DL_MASK, len_1);
2037 if (rt5682->master[RT5682_AIF1]) {
2038 snd_soc_component_update_bits(component,
2039 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK,
2040 pre_div << RT5682_I2S_M_DIV_SFT);
2042 if (params_channels(params) == 1) /* mono mode */
2043 snd_soc_component_update_bits(component,
2044 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2045 RT5682_I2S1_MONO_EN);
2047 snd_soc_component_update_bits(component,
2048 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2049 RT5682_I2S1_MONO_DIS);
2052 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2053 RT5682_I2S2_DL_MASK, len_2);
2054 if (rt5682->master[RT5682_AIF2]) {
2055 snd_soc_component_update_bits(component,
2056 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2057 pre_div << RT5682_I2S2_M_PD_SFT);
2059 if (params_channels(params) == 1) /* mono mode */
2060 snd_soc_component_update_bits(component,
2061 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2062 RT5682_I2S2_MONO_EN);
2064 snd_soc_component_update_bits(component,
2065 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2066 RT5682_I2S2_MONO_DIS);
2069 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2076 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2078 struct snd_soc_component *component = dai->component;
2079 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2080 unsigned int reg_val = 0, tdm_ctrl = 0;
2082 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2083 case SND_SOC_DAIFMT_CBM_CFM:
2084 rt5682->master[dai->id] = 1;
2086 case SND_SOC_DAIFMT_CBS_CFS:
2087 rt5682->master[dai->id] = 0;
2093 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2094 case SND_SOC_DAIFMT_NB_NF:
2096 case SND_SOC_DAIFMT_IB_NF:
2097 reg_val |= RT5682_I2S_BP_INV;
2098 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2100 case SND_SOC_DAIFMT_NB_IF:
2101 if (dai->id == RT5682_AIF1)
2102 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2106 case SND_SOC_DAIFMT_IB_IF:
2107 if (dai->id == RT5682_AIF1)
2108 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2109 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2117 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2118 case SND_SOC_DAIFMT_I2S:
2120 case SND_SOC_DAIFMT_LEFT_J:
2121 reg_val |= RT5682_I2S_DF_LEFT;
2122 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2124 case SND_SOC_DAIFMT_DSP_A:
2125 reg_val |= RT5682_I2S_DF_PCM_A;
2126 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2128 case SND_SOC_DAIFMT_DSP_B:
2129 reg_val |= RT5682_I2S_DF_PCM_B;
2130 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2138 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2139 RT5682_I2S_DF_MASK, reg_val);
2140 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2141 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2142 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2143 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2144 tdm_ctrl | rt5682->master[dai->id]);
2147 if (rt5682->master[dai->id] == 0)
2148 reg_val |= RT5682_I2S2_MS_S;
2149 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2150 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2151 RT5682_I2S_DF_MASK, reg_val);
2154 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2160 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2161 int clk_id, int source, unsigned int freq, int dir)
2163 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2164 unsigned int reg_val = 0, src = 0;
2166 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2170 case RT5682_SCLK_S_MCLK:
2171 reg_val |= RT5682_SCLK_SRC_MCLK;
2172 src = RT5682_CLK_SRC_MCLK;
2174 case RT5682_SCLK_S_PLL1:
2175 reg_val |= RT5682_SCLK_SRC_PLL1;
2176 src = RT5682_CLK_SRC_PLL1;
2178 case RT5682_SCLK_S_PLL2:
2179 reg_val |= RT5682_SCLK_SRC_PLL2;
2180 src = RT5682_CLK_SRC_PLL2;
2182 case RT5682_SCLK_S_RCCLK:
2183 reg_val |= RT5682_SCLK_SRC_RCCLK;
2184 src = RT5682_CLK_SRC_RCCLK;
2187 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2190 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2191 RT5682_SCLK_SRC_MASK, reg_val);
2193 if (rt5682->master[RT5682_AIF2]) {
2194 snd_soc_component_update_bits(component,
2195 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2196 src << RT5682_I2S2_SRC_SFT);
2199 rt5682->sysclk = freq;
2200 rt5682->sysclk_src = clk_id;
2202 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2208 static int rt5682_set_component_pll(struct snd_soc_component *component,
2209 int pll_id, int source, unsigned int freq_in,
2210 unsigned int freq_out)
2212 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2213 struct rl6231_pll_code pll_code;
2216 if (source == rt5682->pll_src && freq_in == rt5682->pll_in &&
2217 freq_out == rt5682->pll_out)
2220 if (!freq_in || !freq_out) {
2221 dev_dbg(component->dev, "PLL disabled\n");
2224 rt5682->pll_out = 0;
2225 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2226 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2231 case RT5682_PLL1_S_MCLK:
2232 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2233 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_MCLK);
2235 case RT5682_PLL1_S_BCLK1:
2236 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2237 RT5682_PLL1_SRC_MASK, RT5682_PLL1_SRC_BCLK1);
2240 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2244 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2246 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2250 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2251 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2252 pll_code.n_code, pll_code.k_code);
2254 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2255 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2256 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2257 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2258 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2260 rt5682->pll_in = freq_in;
2261 rt5682->pll_out = freq_out;
2262 rt5682->pll_src = source;
2267 static int rt5682_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2269 struct snd_soc_component *component = dai->component;
2270 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2272 rt5682->bclk[dai->id] = ratio;
2276 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2277 RT5682_I2S2_BCLK_MS2_MASK,
2278 RT5682_I2S2_BCLK_MS2_64);
2281 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2282 RT5682_I2S2_BCLK_MS2_MASK,
2283 RT5682_I2S2_BCLK_MS2_32);
2286 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2293 static int rt5682_set_bias_level(struct snd_soc_component *component,
2294 enum snd_soc_bias_level level)
2296 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2299 case SND_SOC_BIAS_PREPARE:
2300 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2301 RT5682_PWR_BG, RT5682_PWR_BG);
2302 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2303 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2304 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2307 case SND_SOC_BIAS_STANDBY:
2308 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2309 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2311 case SND_SOC_BIAS_OFF:
2312 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2313 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2314 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2325 static int rt5682_probe(struct snd_soc_component *component)
2327 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2329 rt5682->component = component;
2334 static void rt5682_remove(struct snd_soc_component *component)
2336 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2338 rt5682_reset(rt5682->regmap);
2342 static int rt5682_suspend(struct snd_soc_component *component)
2344 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2346 regcache_cache_only(rt5682->regmap, true);
2347 regcache_mark_dirty(rt5682->regmap);
2351 static int rt5682_resume(struct snd_soc_component *component)
2353 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2355 regcache_cache_only(rt5682->regmap, false);
2356 regcache_sync(rt5682->regmap);
2358 rt5682_irq(0, rt5682);
2363 #define rt5682_suspend NULL
2364 #define rt5682_resume NULL
2367 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2368 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2369 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2371 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2372 .hw_params = rt5682_hw_params,
2373 .set_fmt = rt5682_set_dai_fmt,
2374 .set_tdm_slot = rt5682_set_tdm_slot,
2377 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2378 .hw_params = rt5682_hw_params,
2379 .set_fmt = rt5682_set_dai_fmt,
2380 .set_bclk_ratio = rt5682_set_bclk_ratio,
2383 static struct snd_soc_dai_driver rt5682_dai[] = {
2385 .name = "rt5682-aif1",
2388 .stream_name = "AIF1 Playback",
2391 .rates = RT5682_STEREO_RATES,
2392 .formats = RT5682_FORMATS,
2395 .stream_name = "AIF1 Capture",
2398 .rates = RT5682_STEREO_RATES,
2399 .formats = RT5682_FORMATS,
2401 .ops = &rt5682_aif1_dai_ops,
2404 .name = "rt5682-aif2",
2407 .stream_name = "AIF2 Capture",
2410 .rates = RT5682_STEREO_RATES,
2411 .formats = RT5682_FORMATS,
2413 .ops = &rt5682_aif2_dai_ops,
2417 static const struct snd_soc_component_driver soc_component_dev_rt5682 = {
2418 .probe = rt5682_probe,
2419 .remove = rt5682_remove,
2420 .suspend = rt5682_suspend,
2421 .resume = rt5682_resume,
2422 .set_bias_level = rt5682_set_bias_level,
2423 .controls = rt5682_snd_controls,
2424 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2425 .dapm_widgets = rt5682_dapm_widgets,
2426 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2427 .dapm_routes = rt5682_dapm_routes,
2428 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2429 .set_sysclk = rt5682_set_component_sysclk,
2430 .set_pll = rt5682_set_component_pll,
2431 .set_jack = rt5682_set_jack_detect,
2432 .use_pmdown_time = 1,
2434 .non_legacy_dai_naming = 1,
2437 static const struct regmap_config rt5682_regmap = {
2440 .max_register = RT5682_I2C_MODE,
2441 .volatile_reg = rt5682_volatile_register,
2442 .readable_reg = rt5682_readable_register,
2443 .cache_type = REGCACHE_RBTREE,
2444 .reg_defaults = rt5682_reg,
2445 .num_reg_defaults = ARRAY_SIZE(rt5682_reg),
2446 .use_single_read = true,
2447 .use_single_write = true,
2450 static const struct i2c_device_id rt5682_i2c_id[] = {
2454 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
2456 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2459 device_property_read_u32(dev, "realtek,dmic1-data-pin",
2460 &rt5682->pdata.dmic1_data_pin);
2461 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2462 &rt5682->pdata.dmic1_clk_pin);
2463 device_property_read_u32(dev, "realtek,jd-src",
2464 &rt5682->pdata.jd_src);
2466 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2467 "realtek,ldo1-en-gpios", 0);
2472 static void rt5682_calibrate(struct rt5682_priv *rt5682)
2476 mutex_lock(&rt5682->calibrate_mutex);
2478 rt5682_reset(rt5682->regmap);
2479 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
2480 usleep_range(15000, 20000);
2481 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
2482 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
2483 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
2484 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
2485 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
2486 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
2487 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
2488 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
2489 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
2490 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
2491 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
2492 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2493 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
2494 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
2495 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
2497 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
2499 for (count = 0; count < 60; count++) {
2500 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
2501 if (!(value & 0x8000))
2504 usleep_range(10000, 10005);
2508 pr_err("HP Calibration Failure\n");
2510 /* restore settings */
2511 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af);
2512 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
2513 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
2514 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
2515 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
2516 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
2517 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
2519 mutex_unlock(&rt5682->calibrate_mutex);
2523 static int rt5682_i2c_probe(struct i2c_client *i2c,
2524 const struct i2c_device_id *id)
2526 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
2527 struct rt5682_priv *rt5682;
2531 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
2537 i2c_set_clientdata(i2c, rt5682);
2539 rt5682->pdata = i2s_default_platform_data;
2542 rt5682->pdata = *pdata;
2544 rt5682_parse_dt(rt5682, &i2c->dev);
2546 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
2547 if (IS_ERR(rt5682->regmap)) {
2548 ret = PTR_ERR(rt5682->regmap);
2549 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2554 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
2555 rt5682->supplies[i].supply = rt5682_supply_names[i];
2557 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
2560 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2564 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
2567 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2571 if (gpio_is_valid(rt5682->pdata.ldo1_en)) {
2572 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en,
2573 GPIOF_OUT_INIT_HIGH, "rt5682"))
2574 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2577 /* Sleep for 300 ms miniumum */
2578 usleep_range(300000, 350000);
2580 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
2581 usleep_range(10000, 15000);
2583 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
2584 if (val != DEVICE_ID) {
2585 pr_err("Device with ID register %x is not rt5682\n", val);
2589 rt5682_reset(rt5682->regmap);
2591 rt5682_calibrate(rt5682);
2593 ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
2594 ARRAY_SIZE(patch_list));
2596 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2598 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
2601 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
2602 switch (rt5682->pdata.dmic1_data_pin) {
2603 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */
2604 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2605 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
2606 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2607 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
2610 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
2611 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
2612 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
2613 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2614 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
2618 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
2622 switch (rt5682->pdata.dmic1_clk_pin) {
2623 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */
2624 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2625 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
2628 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */
2629 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2630 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
2634 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
2639 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2640 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
2641 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
2642 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
2643 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
2644 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
2645 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
2646 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
2647 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
2648 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
2649 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
2650 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
2652 INIT_DELAYED_WORK(&rt5682->jack_detect_work,
2653 rt5682_jack_detect_handler);
2654 INIT_DELAYED_WORK(&rt5682->jd_check_work,
2655 rt5682_jd_check_handler);
2657 mutex_init(&rt5682->calibrate_mutex);
2660 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2661 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2662 | IRQF_ONESHOT, "rt5682", rt5682);
2664 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2668 return snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5682,
2669 rt5682_dai, ARRAY_SIZE(rt5682_dai));
2672 static int rt5682_i2c_remove(struct i2c_client *i2c)
2674 snd_soc_unregister_component(&i2c->dev);
2679 static void rt5682_i2c_shutdown(struct i2c_client *client)
2681 struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
2683 rt5682_reset(rt5682->regmap);
2687 static const struct of_device_id rt5682_of_match[] = {
2688 {.compatible = "realtek,rt5682i"},
2691 MODULE_DEVICE_TABLE(of, rt5682_of_match);
2695 static const struct acpi_device_id rt5682_acpi_match[] = {
2699 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
2702 static struct i2c_driver rt5682_i2c_driver = {
2705 .of_match_table = of_match_ptr(rt5682_of_match),
2706 .acpi_match_table = ACPI_PTR(rt5682_acpi_match),
2708 .probe = rt5682_i2c_probe,
2709 .remove = rt5682_i2c_remove,
2710 .shutdown = rt5682_i2c_shutdown,
2711 .id_table = rt5682_i2c_id,
2713 module_i2c_driver(rt5682_i2c_driver);
2715 MODULE_DESCRIPTION("ASoC RT5682 driver");
2716 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2717 MODULE_LICENSE("GPL v2");
projects / linux-2.6-microblaze.git / blob