1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5682.c -- RT5682 ALSA SoC audio component driver
5 * Copyright 2018 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/i2c.h>
16 #include <linux/platform_device.h>
17 #include <linux/spi/spi.h>
18 #include <linux/acpi.h>
19 #include <linux/gpio.h>
20 #include <linux/of_gpio.h>
21 #include <linux/mutex.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/jack.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 #include <sound/rt5682.h>
34 #include "rt5682-sdw.h"
36 static const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
42 static const struct rt5682_platform_data i2s_default_platform_data = {
43 .dmic1_data_pin = RT5682_DMIC1_DATA_GPIO2,
44 .dmic1_clk_pin = RT5682_DMIC1_CLK_GPIO3,
47 .dai_clk_names[RT5682_DAI_WCLK_IDX] = "rt5682-dai-wclk",
48 .dai_clk_names[RT5682_DAI_BCLK_IDX] = "rt5682-dai-bclk",
51 static const struct reg_sequence patch_list[] = {
52 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
53 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
54 {RT5682_I2C_CTRL, 0x000f},
55 {RT5682_PLL2_INTERNAL, 0x8266},
58 static const struct reg_default rt5682_reg[] = {
379 static bool rt5682_volatile_register(struct device *dev, unsigned int reg)
383 case RT5682_CBJ_CTRL_2:
384 case RT5682_INT_ST_1:
385 case RT5682_4BTN_IL_CMD_1:
386 case RT5682_AJD1_CTRL:
387 case RT5682_HP_CALIB_CTRL_1:
388 case RT5682_DEVICE_ID:
389 case RT5682_I2C_MODE:
390 case RT5682_HP_CALIB_CTRL_10:
391 case RT5682_EFUSE_CTRL_2:
392 case RT5682_JD_TOP_VC_VTRL:
393 case RT5682_HP_IMP_SENS_CTRL_19:
394 case RT5682_IL_CMD_1:
395 case RT5682_SAR_IL_CMD_2:
396 case RT5682_SAR_IL_CMD_4:
397 case RT5682_SAR_IL_CMD_10:
398 case RT5682_SAR_IL_CMD_11:
399 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
400 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
407 static bool rt5682_readable_register(struct device *dev, unsigned int reg)
411 case RT5682_VERSION_ID:
412 case RT5682_VENDOR_ID:
413 case RT5682_DEVICE_ID:
414 case RT5682_HP_CTRL_1:
415 case RT5682_HP_CTRL_2:
416 case RT5682_HPL_GAIN:
417 case RT5682_HPR_GAIN:
418 case RT5682_I2C_CTRL:
419 case RT5682_CBJ_BST_CTRL:
420 case RT5682_CBJ_CTRL_1:
421 case RT5682_CBJ_CTRL_2:
422 case RT5682_CBJ_CTRL_3:
423 case RT5682_CBJ_CTRL_4:
424 case RT5682_CBJ_CTRL_5:
425 case RT5682_CBJ_CTRL_6:
426 case RT5682_CBJ_CTRL_7:
427 case RT5682_DAC1_DIG_VOL:
428 case RT5682_STO1_ADC_DIG_VOL:
429 case RT5682_STO1_ADC_BOOST:
430 case RT5682_HP_IMP_GAIN_1:
431 case RT5682_HP_IMP_GAIN_2:
432 case RT5682_SIDETONE_CTRL:
433 case RT5682_STO1_ADC_MIXER:
434 case RT5682_AD_DA_MIXER:
435 case RT5682_STO1_DAC_MIXER:
436 case RT5682_A_DAC1_MUX:
437 case RT5682_DIG_INF2_DATA:
438 case RT5682_REC_MIXER:
440 case RT5682_ALC_BACK_GAIN:
441 case RT5682_PWR_DIG_1:
442 case RT5682_PWR_DIG_2:
443 case RT5682_PWR_ANLG_1:
444 case RT5682_PWR_ANLG_2:
445 case RT5682_PWR_ANLG_3:
446 case RT5682_PWR_MIXER:
449 case RT5682_RESET_LPF_CTRL:
450 case RT5682_RESET_HPF_CTRL:
451 case RT5682_DMIC_CTRL_1:
452 case RT5682_I2S1_SDP:
453 case RT5682_I2S2_SDP:
454 case RT5682_ADDA_CLK_1:
455 case RT5682_ADDA_CLK_2:
456 case RT5682_I2S1_F_DIV_CTRL_1:
457 case RT5682_I2S1_F_DIV_CTRL_2:
458 case RT5682_TDM_CTRL:
459 case RT5682_TDM_ADDA_CTRL_1:
460 case RT5682_TDM_ADDA_CTRL_2:
461 case RT5682_DATA_SEL_CTRL_1:
462 case RT5682_TDM_TCON_CTRL:
464 case RT5682_PLL_CTRL_1:
465 case RT5682_PLL_CTRL_2:
466 case RT5682_PLL_TRACK_1:
467 case RT5682_PLL_TRACK_2:
468 case RT5682_PLL_TRACK_3:
469 case RT5682_PLL_TRACK_4:
470 case RT5682_PLL_TRACK_5:
471 case RT5682_PLL_TRACK_6:
472 case RT5682_PLL_TRACK_11:
473 case RT5682_SDW_REF_CLK:
476 case RT5682_HP_CHARGE_PUMP_1:
477 case RT5682_HP_CHARGE_PUMP_2:
478 case RT5682_MICBIAS_1:
479 case RT5682_MICBIAS_2:
480 case RT5682_PLL_TRACK_12:
481 case RT5682_PLL_TRACK_14:
482 case RT5682_PLL2_CTRL_1:
483 case RT5682_PLL2_CTRL_2:
484 case RT5682_PLL2_CTRL_3:
485 case RT5682_PLL2_CTRL_4:
486 case RT5682_RC_CLK_CTRL:
487 case RT5682_I2S_M_CLK_CTRL_1:
488 case RT5682_I2S2_F_DIV_CTRL_1:
489 case RT5682_I2S2_F_DIV_CTRL_2:
490 case RT5682_EQ_CTRL_1:
491 case RT5682_EQ_CTRL_2:
492 case RT5682_IRQ_CTRL_1:
493 case RT5682_IRQ_CTRL_2:
494 case RT5682_IRQ_CTRL_3:
495 case RT5682_IRQ_CTRL_4:
496 case RT5682_INT_ST_1:
497 case RT5682_GPIO_CTRL_1:
498 case RT5682_GPIO_CTRL_2:
499 case RT5682_GPIO_CTRL_3:
500 case RT5682_HP_AMP_DET_CTRL_1:
501 case RT5682_HP_AMP_DET_CTRL_2:
502 case RT5682_MID_HP_AMP_DET:
503 case RT5682_LOW_HP_AMP_DET:
504 case RT5682_DELAY_BUF_CTRL:
505 case RT5682_SV_ZCD_1:
506 case RT5682_SV_ZCD_2:
507 case RT5682_IL_CMD_1:
508 case RT5682_IL_CMD_2:
509 case RT5682_IL_CMD_3:
510 case RT5682_IL_CMD_4:
511 case RT5682_IL_CMD_5:
512 case RT5682_IL_CMD_6:
513 case RT5682_4BTN_IL_CMD_1:
514 case RT5682_4BTN_IL_CMD_2:
515 case RT5682_4BTN_IL_CMD_3:
516 case RT5682_4BTN_IL_CMD_4:
517 case RT5682_4BTN_IL_CMD_5:
518 case RT5682_4BTN_IL_CMD_6:
519 case RT5682_4BTN_IL_CMD_7:
520 case RT5682_ADC_STO1_HP_CTRL_1:
521 case RT5682_ADC_STO1_HP_CTRL_2:
522 case RT5682_AJD1_CTRL:
525 case RT5682_JD_CTRL_1:
529 case RT5682_DAC_ADC_DIG_VOL1:
530 case RT5682_BIAS_CUR_CTRL_2:
531 case RT5682_BIAS_CUR_CTRL_3:
532 case RT5682_BIAS_CUR_CTRL_4:
533 case RT5682_BIAS_CUR_CTRL_5:
534 case RT5682_BIAS_CUR_CTRL_6:
535 case RT5682_BIAS_CUR_CTRL_7:
536 case RT5682_BIAS_CUR_CTRL_8:
537 case RT5682_BIAS_CUR_CTRL_9:
538 case RT5682_BIAS_CUR_CTRL_10:
539 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
540 case RT5682_CHARGE_PUMP_1:
541 case RT5682_DIG_IN_CTRL_1:
542 case RT5682_PAD_DRIVING_CTRL:
543 case RT5682_SOFT_RAMP_DEPOP:
544 case RT5682_CHOP_DAC:
545 case RT5682_CHOP_ADC:
546 case RT5682_CALIB_ADC_CTRL:
547 case RT5682_VOL_TEST:
548 case RT5682_SPKVDD_DET_STA:
549 case RT5682_TEST_MODE_CTRL_1:
550 case RT5682_TEST_MODE_CTRL_2:
551 case RT5682_TEST_MODE_CTRL_3:
552 case RT5682_TEST_MODE_CTRL_4:
553 case RT5682_TEST_MODE_CTRL_5:
554 case RT5682_PLL1_INTERNAL:
555 case RT5682_PLL2_INTERNAL:
556 case RT5682_STO_NG2_CTRL_1:
557 case RT5682_STO_NG2_CTRL_2:
558 case RT5682_STO_NG2_CTRL_3:
559 case RT5682_STO_NG2_CTRL_4:
560 case RT5682_STO_NG2_CTRL_5:
561 case RT5682_STO_NG2_CTRL_6:
562 case RT5682_STO_NG2_CTRL_7:
563 case RT5682_STO_NG2_CTRL_8:
564 case RT5682_STO_NG2_CTRL_9:
565 case RT5682_STO_NG2_CTRL_10:
566 case RT5682_STO1_DAC_SIL_DET:
567 case RT5682_SIL_PSV_CTRL1:
568 case RT5682_SIL_PSV_CTRL2:
569 case RT5682_SIL_PSV_CTRL3:
570 case RT5682_SIL_PSV_CTRL4:
571 case RT5682_SIL_PSV_CTRL5:
572 case RT5682_HP_IMP_SENS_CTRL_01:
573 case RT5682_HP_IMP_SENS_CTRL_02:
574 case RT5682_HP_IMP_SENS_CTRL_03:
575 case RT5682_HP_IMP_SENS_CTRL_04:
576 case RT5682_HP_IMP_SENS_CTRL_05:
577 case RT5682_HP_IMP_SENS_CTRL_06:
578 case RT5682_HP_IMP_SENS_CTRL_07:
579 case RT5682_HP_IMP_SENS_CTRL_08:
580 case RT5682_HP_IMP_SENS_CTRL_09:
581 case RT5682_HP_IMP_SENS_CTRL_10:
582 case RT5682_HP_IMP_SENS_CTRL_11:
583 case RT5682_HP_IMP_SENS_CTRL_12:
584 case RT5682_HP_IMP_SENS_CTRL_13:
585 case RT5682_HP_IMP_SENS_CTRL_14:
586 case RT5682_HP_IMP_SENS_CTRL_15:
587 case RT5682_HP_IMP_SENS_CTRL_16:
588 case RT5682_HP_IMP_SENS_CTRL_17:
589 case RT5682_HP_IMP_SENS_CTRL_18:
590 case RT5682_HP_IMP_SENS_CTRL_19:
591 case RT5682_HP_IMP_SENS_CTRL_20:
592 case RT5682_HP_IMP_SENS_CTRL_21:
593 case RT5682_HP_IMP_SENS_CTRL_22:
594 case RT5682_HP_IMP_SENS_CTRL_23:
595 case RT5682_HP_IMP_SENS_CTRL_24:
596 case RT5682_HP_IMP_SENS_CTRL_25:
597 case RT5682_HP_IMP_SENS_CTRL_26:
598 case RT5682_HP_IMP_SENS_CTRL_27:
599 case RT5682_HP_IMP_SENS_CTRL_28:
600 case RT5682_HP_IMP_SENS_CTRL_29:
601 case RT5682_HP_IMP_SENS_CTRL_30:
602 case RT5682_HP_IMP_SENS_CTRL_31:
603 case RT5682_HP_IMP_SENS_CTRL_32:
604 case RT5682_HP_IMP_SENS_CTRL_33:
605 case RT5682_HP_IMP_SENS_CTRL_34:
606 case RT5682_HP_IMP_SENS_CTRL_35:
607 case RT5682_HP_IMP_SENS_CTRL_36:
608 case RT5682_HP_IMP_SENS_CTRL_37:
609 case RT5682_HP_IMP_SENS_CTRL_38:
610 case RT5682_HP_IMP_SENS_CTRL_39:
611 case RT5682_HP_IMP_SENS_CTRL_40:
612 case RT5682_HP_IMP_SENS_CTRL_41:
613 case RT5682_HP_IMP_SENS_CTRL_42:
614 case RT5682_HP_IMP_SENS_CTRL_43:
615 case RT5682_HP_LOGIC_CTRL_1:
616 case RT5682_HP_LOGIC_CTRL_2:
617 case RT5682_HP_LOGIC_CTRL_3:
618 case RT5682_HP_CALIB_CTRL_1:
619 case RT5682_HP_CALIB_CTRL_2:
620 case RT5682_HP_CALIB_CTRL_3:
621 case RT5682_HP_CALIB_CTRL_4:
622 case RT5682_HP_CALIB_CTRL_5:
623 case RT5682_HP_CALIB_CTRL_6:
624 case RT5682_HP_CALIB_CTRL_7:
625 case RT5682_HP_CALIB_CTRL_9:
626 case RT5682_HP_CALIB_CTRL_10:
627 case RT5682_HP_CALIB_CTRL_11:
628 case RT5682_HP_CALIB_STA_1:
629 case RT5682_HP_CALIB_STA_2:
630 case RT5682_HP_CALIB_STA_3:
631 case RT5682_HP_CALIB_STA_4:
632 case RT5682_HP_CALIB_STA_5:
633 case RT5682_HP_CALIB_STA_6:
634 case RT5682_HP_CALIB_STA_7:
635 case RT5682_HP_CALIB_STA_8:
636 case RT5682_HP_CALIB_STA_9:
637 case RT5682_HP_CALIB_STA_10:
638 case RT5682_HP_CALIB_STA_11:
639 case RT5682_SAR_IL_CMD_1:
640 case RT5682_SAR_IL_CMD_2:
641 case RT5682_SAR_IL_CMD_3:
642 case RT5682_SAR_IL_CMD_4:
643 case RT5682_SAR_IL_CMD_5:
644 case RT5682_SAR_IL_CMD_6:
645 case RT5682_SAR_IL_CMD_7:
646 case RT5682_SAR_IL_CMD_8:
647 case RT5682_SAR_IL_CMD_9:
648 case RT5682_SAR_IL_CMD_10:
649 case RT5682_SAR_IL_CMD_11:
650 case RT5682_SAR_IL_CMD_12:
651 case RT5682_SAR_IL_CMD_13:
652 case RT5682_EFUSE_CTRL_1:
653 case RT5682_EFUSE_CTRL_2:
654 case RT5682_EFUSE_CTRL_3:
655 case RT5682_EFUSE_CTRL_4:
656 case RT5682_EFUSE_CTRL_5:
657 case RT5682_EFUSE_CTRL_6:
658 case RT5682_EFUSE_CTRL_7:
659 case RT5682_EFUSE_CTRL_8:
660 case RT5682_EFUSE_CTRL_9:
661 case RT5682_EFUSE_CTRL_10:
662 case RT5682_EFUSE_CTRL_11:
663 case RT5682_JD_TOP_VC_VTRL:
664 case RT5682_DRC1_CTRL_0:
665 case RT5682_DRC1_CTRL_1:
666 case RT5682_DRC1_CTRL_2:
667 case RT5682_DRC1_CTRL_3:
668 case RT5682_DRC1_CTRL_4:
669 case RT5682_DRC1_CTRL_5:
670 case RT5682_DRC1_CTRL_6:
671 case RT5682_DRC1_HARD_LMT_CTRL_1:
672 case RT5682_DRC1_HARD_LMT_CTRL_2:
673 case RT5682_DRC1_PRIV_1:
674 case RT5682_DRC1_PRIV_2:
675 case RT5682_DRC1_PRIV_3:
676 case RT5682_DRC1_PRIV_4:
677 case RT5682_DRC1_PRIV_5:
678 case RT5682_DRC1_PRIV_6:
679 case RT5682_DRC1_PRIV_7:
680 case RT5682_DRC1_PRIV_8:
681 case RT5682_EQ_AUTO_RCV_CTRL1:
682 case RT5682_EQ_AUTO_RCV_CTRL2:
683 case RT5682_EQ_AUTO_RCV_CTRL3:
684 case RT5682_EQ_AUTO_RCV_CTRL4:
685 case RT5682_EQ_AUTO_RCV_CTRL5:
686 case RT5682_EQ_AUTO_RCV_CTRL6:
687 case RT5682_EQ_AUTO_RCV_CTRL7:
688 case RT5682_EQ_AUTO_RCV_CTRL8:
689 case RT5682_EQ_AUTO_RCV_CTRL9:
690 case RT5682_EQ_AUTO_RCV_CTRL10:
691 case RT5682_EQ_AUTO_RCV_CTRL11:
692 case RT5682_EQ_AUTO_RCV_CTRL12:
693 case RT5682_EQ_AUTO_RCV_CTRL13:
694 case RT5682_ADC_L_EQ_LPF1_A1:
695 case RT5682_R_EQ_LPF1_A1:
696 case RT5682_L_EQ_LPF1_H0:
697 case RT5682_R_EQ_LPF1_H0:
698 case RT5682_L_EQ_BPF1_A1:
699 case RT5682_R_EQ_BPF1_A1:
700 case RT5682_L_EQ_BPF1_A2:
701 case RT5682_R_EQ_BPF1_A2:
702 case RT5682_L_EQ_BPF1_H0:
703 case RT5682_R_EQ_BPF1_H0:
704 case RT5682_L_EQ_BPF2_A1:
705 case RT5682_R_EQ_BPF2_A1:
706 case RT5682_L_EQ_BPF2_A2:
707 case RT5682_R_EQ_BPF2_A2:
708 case RT5682_L_EQ_BPF2_H0:
709 case RT5682_R_EQ_BPF2_H0:
710 case RT5682_L_EQ_BPF3_A1:
711 case RT5682_R_EQ_BPF3_A1:
712 case RT5682_L_EQ_BPF3_A2:
713 case RT5682_R_EQ_BPF3_A2:
714 case RT5682_L_EQ_BPF3_H0:
715 case RT5682_R_EQ_BPF3_H0:
716 case RT5682_L_EQ_BPF4_A1:
717 case RT5682_R_EQ_BPF4_A1:
718 case RT5682_L_EQ_BPF4_A2:
719 case RT5682_R_EQ_BPF4_A2:
720 case RT5682_L_EQ_BPF4_H0:
721 case RT5682_R_EQ_BPF4_H0:
722 case RT5682_L_EQ_HPF1_A1:
723 case RT5682_R_EQ_HPF1_A1:
724 case RT5682_L_EQ_HPF1_H0:
725 case RT5682_R_EQ_HPF1_H0:
726 case RT5682_L_EQ_PRE_VOL:
727 case RT5682_R_EQ_PRE_VOL:
728 case RT5682_L_EQ_POST_VOL:
729 case RT5682_R_EQ_POST_VOL:
730 case RT5682_I2C_MODE:
737 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
738 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
739 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
741 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
742 static const DECLARE_TLV_DB_RANGE(bst_tlv,
743 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
744 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
745 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
746 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
747 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
748 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
749 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
752 /* Interface data select */
753 static const char * const rt5682_data_select[] = {
754 "L/R", "R/L", "L/L", "R/R"
757 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
758 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
760 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
761 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
763 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
764 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
766 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
767 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
769 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
770 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
772 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
773 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
775 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
776 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
778 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
779 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
781 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
782 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
784 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
785 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
787 static const char * const rt5682_dac_select[] = {
791 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
792 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
794 static const struct snd_kcontrol_new rt5682_dac_l_mux =
795 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
797 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
798 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
800 static const struct snd_kcontrol_new rt5682_dac_r_mux =
801 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
803 static void rt5682_reset(struct rt5682_priv *rt5682)
805 regmap_write(rt5682->regmap, RT5682_RESET, 0);
807 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
810 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
811 * @component: SoC audio component device.
812 * @filter_mask: mask of filters.
813 * @clk_src: clock source
815 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
816 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
817 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
818 * ASRC function will track i2s clock and generate a corresponding system clock
819 * for codec. This function provides an API to select the clock source for a
820 * set of filters specified by the mask. And the component driver will turn on
821 * ASRC for these filters if ASRC is selected as their clock source.
823 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
824 unsigned int filter_mask, unsigned int clk_src)
828 case RT5682_CLK_SEL_SYS:
829 case RT5682_CLK_SEL_I2S1_ASRC:
830 case RT5682_CLK_SEL_I2S2_ASRC:
837 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
838 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
839 RT5682_FILTER_CLK_SEL_MASK,
840 clk_src << RT5682_FILTER_CLK_SEL_SFT);
843 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
844 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
845 RT5682_FILTER_CLK_SEL_MASK,
846 clk_src << RT5682_FILTER_CLK_SEL_SFT);
851 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
853 static int rt5682_button_detect(struct snd_soc_component *component)
857 val = snd_soc_component_read32(component, RT5682_4BTN_IL_CMD_1);
858 btn_type = val & 0xfff0;
859 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
860 pr_debug("%s btn_type=%x\n", __func__, btn_type);
861 snd_soc_component_update_bits(component,
862 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
867 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
870 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
873 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
874 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
875 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
876 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
877 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
878 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
879 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
880 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
882 snd_soc_component_update_bits(component,
884 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
885 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
887 snd_soc_component_update_bits(component,
888 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
891 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
892 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
893 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
894 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
895 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
896 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
897 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
898 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
899 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
900 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
905 * rt5682_headset_detect - Detect headset.
906 * @component: SoC audio component device.
907 * @jack_insert: Jack insert or not.
909 * Detect whether is headset or not when jack inserted.
911 * Returns detect status.
913 static int rt5682_headset_detect(struct snd_soc_component *component,
916 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
917 struct snd_soc_dapm_context *dapm = &component->dapm;
918 unsigned int val, count;
922 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
923 RT5682_PWR_VREF2 | RT5682_PWR_MB,
924 RT5682_PWR_VREF2 | RT5682_PWR_MB);
925 snd_soc_component_update_bits(component,
926 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
927 usleep_range(15000, 20000);
928 snd_soc_component_update_bits(component,
929 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
930 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
931 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
933 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
934 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
937 val = snd_soc_component_read32(component, RT5682_CBJ_CTRL_2)
938 & RT5682_JACK_TYPE_MASK;
939 while (val == 0 && count < 50) {
940 usleep_range(10000, 15000);
941 val = snd_soc_component_read32(component,
942 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
949 rt5682->jack_type = SND_JACK_HEADSET;
950 rt5682_enable_push_button_irq(component, true);
953 rt5682->jack_type = SND_JACK_HEADPHONE;
957 rt5682_enable_push_button_irq(component, false);
958 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
959 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
960 if (snd_soc_dapm_get_pin_status(dapm, "MICBIAS"))
961 snd_soc_component_update_bits(component,
962 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
964 snd_soc_component_update_bits(component,
966 RT5682_PWR_VREF2 | RT5682_PWR_MB, 0);
967 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
970 rt5682->jack_type = 0;
973 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
974 return rt5682->jack_type;
977 static irqreturn_t rt5682_irq(int irq, void *data)
979 struct rt5682_priv *rt5682 = data;
981 mod_delayed_work(system_power_efficient_wq,
982 &rt5682->jack_detect_work, msecs_to_jiffies(250));
987 static void rt5682_jd_check_handler(struct work_struct *work)
989 struct rt5682_priv *rt5682 = container_of(work, struct rt5682_priv,
992 if (snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
993 & RT5682_JDH_RS_MASK) {
995 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
997 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
999 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1000 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1002 schedule_delayed_work(&rt5682->jd_check_work, 500);
1006 static int rt5682_set_jack_detect(struct snd_soc_component *component,
1007 struct snd_soc_jack *hs_jack, void *data)
1009 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1011 rt5682->hs_jack = hs_jack;
1013 if (!rt5682->is_sdw) {
1015 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1016 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1017 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1018 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1019 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1023 switch (rt5682->pdata.jd_src) {
1025 snd_soc_component_update_bits(component,
1026 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1027 RT5682_EXT_JD_SRC_MANUAL);
1028 snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1030 snd_soc_component_update_bits(component,
1031 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1032 RT5682_CBJ_IN_BUF_EN);
1033 snd_soc_component_update_bits(component,
1034 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1036 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1037 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1038 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1039 RT5682_POW_IRQ | RT5682_POW_JDH |
1040 RT5682_POW_ANA, RT5682_POW_IRQ |
1041 RT5682_POW_JDH | RT5682_POW_ANA);
1042 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1043 RT5682_PWR_JDH | RT5682_PWR_JDL,
1044 RT5682_PWR_JDH | RT5682_PWR_JDL);
1045 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1046 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1047 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1048 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1049 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1050 rt5682->pdata.btndet_delay));
1051 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1052 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1053 rt5682->pdata.btndet_delay));
1054 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1055 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1056 rt5682->pdata.btndet_delay));
1057 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1058 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1059 rt5682->pdata.btndet_delay));
1060 mod_delayed_work(system_power_efficient_wq,
1061 &rt5682->jack_detect_work,
1062 msecs_to_jiffies(250));
1065 case RT5682_JD_NULL:
1066 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1067 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1068 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1069 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1073 dev_warn(component->dev, "Wrong JD source\n");
1081 static void rt5682_jack_detect_handler(struct work_struct *work)
1083 struct rt5682_priv *rt5682 =
1084 container_of(work, struct rt5682_priv, jack_detect_work.work);
1087 while (!rt5682->component)
1088 usleep_range(10000, 15000);
1090 while (!rt5682->component->card->instantiated)
1091 usleep_range(10000, 15000);
1093 mutex_lock(&rt5682->calibrate_mutex);
1095 val = snd_soc_component_read32(rt5682->component, RT5682_AJD1_CTRL)
1096 & RT5682_JDH_RS_MASK;
1099 if (rt5682->jack_type == 0) {
1100 /* jack was out, report jack type */
1102 rt5682_headset_detect(rt5682->component, 1);
1104 /* jack is already in, report button event */
1105 rt5682->jack_type = SND_JACK_HEADSET;
1106 btn_type = rt5682_button_detect(rt5682->component);
1108 * rt5682 can report three kinds of button behavior,
1109 * one click, double click and hold. However,
1110 * currently we will report button pressed/released
1111 * event. So all the three button behaviors are
1112 * treated as button pressed.
1118 rt5682->jack_type |= SND_JACK_BTN_0;
1123 rt5682->jack_type |= SND_JACK_BTN_1;
1128 rt5682->jack_type |= SND_JACK_BTN_2;
1133 rt5682->jack_type |= SND_JACK_BTN_3;
1135 case 0x0000: /* unpressed */
1139 dev_err(rt5682->component->dev,
1140 "Unexpected button code 0x%04x\n",
1147 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1150 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1152 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1153 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1155 if (!rt5682->is_sdw) {
1156 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1157 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1158 schedule_delayed_work(&rt5682->jd_check_work, 0);
1160 cancel_delayed_work_sync(&rt5682->jd_check_work);
1163 mutex_unlock(&rt5682->calibrate_mutex);
1166 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1167 /* DAC Digital Volume */
1168 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1169 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1171 /* IN Boost Volume */
1172 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1173 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1175 /* ADC Digital Volume Control */
1176 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1177 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1178 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1179 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1181 /* ADC Boost Volume Control */
1182 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1183 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1188 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1189 int target, const int div[], int size)
1193 if (rt5682->sysclk < target) {
1194 pr_err("sysclk rate %d is too low\n",
1199 for (i = 0; i < size - 1; i++) {
1200 pr_info("div[%d]=%d\n", i, div[i]);
1201 if (target * div[i] == rt5682->sysclk)
1203 if (target * div[i + 1] > rt5682->sysclk) {
1204 pr_err("can't find div for sysclk %d\n",
1210 if (target * div[i] < rt5682->sysclk)
1211 pr_err("sysclk rate %d is too high\n",
1219 * set_dmic_clk - Set parameter of dmic.
1222 * @kcontrol: The kcontrol of this widget.
1225 * Choose dmic clock between 1MHz and 3MHz.
1226 * It is better for clock to approximate 3MHz.
1228 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1229 struct snd_kcontrol *kcontrol, int event)
1231 struct snd_soc_component *component =
1232 snd_soc_dapm_to_component(w->dapm);
1233 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1235 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1237 idx = rt5682_div_sel(rt5682, 1500000, div, ARRAY_SIZE(div));
1239 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1240 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1245 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1246 struct snd_kcontrol *kcontrol, int event)
1248 struct snd_soc_component *component =
1249 snd_soc_dapm_to_component(w->dapm);
1250 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1251 int ref, val, reg, idx = -EINVAL;
1252 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1253 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1258 val = snd_soc_component_read32(component, RT5682_GPIO_CTRL_1) &
1259 RT5682_GP4_PIN_MASK;
1260 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1261 val == RT5682_GP4_PIN_ADCDAT2)
1262 ref = 256 * rt5682->lrck[RT5682_AIF2];
1264 ref = 256 * rt5682->lrck[RT5682_AIF1];
1266 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1268 if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1269 reg = RT5682_PLL_TRACK_3;
1271 reg = RT5682_PLL_TRACK_2;
1273 snd_soc_component_update_bits(component, reg,
1274 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1276 /* select over sample rate */
1277 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1278 if (rt5682->sysclk <= 12288000 * div_o[idx])
1282 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1283 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1284 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1289 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1290 struct snd_soc_dapm_widget *sink)
1293 struct snd_soc_component *component =
1294 snd_soc_dapm_to_component(w->dapm);
1296 val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1297 val &= RT5682_SCLK_SRC_MASK;
1298 if (val == RT5682_SCLK_SRC_PLL1)
1304 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1305 struct snd_soc_dapm_widget *sink)
1308 struct snd_soc_component *component =
1309 snd_soc_dapm_to_component(w->dapm);
1311 val = snd_soc_component_read32(component, RT5682_GLB_CLK);
1312 val &= RT5682_SCLK_SRC_MASK;
1313 if (val == RT5682_SCLK_SRC_PLL2)
1319 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1320 struct snd_soc_dapm_widget *sink)
1322 unsigned int reg, shift, val;
1323 struct snd_soc_component *component =
1324 snd_soc_dapm_to_component(w->dapm);
1327 case RT5682_ADC_STO1_ASRC_SFT:
1328 reg = RT5682_PLL_TRACK_3;
1329 shift = RT5682_FILTER_CLK_SEL_SFT;
1331 case RT5682_DAC_STO1_ASRC_SFT:
1332 reg = RT5682_PLL_TRACK_2;
1333 shift = RT5682_FILTER_CLK_SEL_SFT;
1339 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1341 case RT5682_CLK_SEL_I2S1_ASRC:
1342 case RT5682_CLK_SEL_I2S2_ASRC:
1351 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1352 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1353 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1354 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1355 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1358 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1359 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1360 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1361 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1362 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1365 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1366 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1367 RT5682_M_ADCMIX_L_SFT, 1, 1),
1368 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1369 RT5682_M_DAC1_L_SFT, 1, 1),
1372 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1373 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1374 RT5682_M_ADCMIX_R_SFT, 1, 1),
1375 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1376 RT5682_M_DAC1_R_SFT, 1, 1),
1379 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1380 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1381 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1382 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1383 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1386 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1387 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1388 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1389 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1390 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1393 /* Analog Input Mixer */
1394 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1395 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1396 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1399 /* STO1 ADC1 Source */
1400 /* MX-26 [13] [5] */
1401 static const char * const rt5682_sto1_adc1_src[] = {
1405 static SOC_ENUM_SINGLE_DECL(
1406 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1407 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1409 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1410 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1412 static SOC_ENUM_SINGLE_DECL(
1413 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1414 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1416 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1417 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1419 /* STO1 ADC Source */
1420 /* MX-26 [11:10] [3:2] */
1421 static const char * const rt5682_sto1_adc_src[] = {
1425 static SOC_ENUM_SINGLE_DECL(
1426 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1427 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1429 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1430 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1432 static SOC_ENUM_SINGLE_DECL(
1433 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1434 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1436 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1437 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1439 /* STO1 ADC2 Source */
1440 /* MX-26 [12] [4] */
1441 static const char * const rt5682_sto1_adc2_src[] = {
1445 static SOC_ENUM_SINGLE_DECL(
1446 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1447 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1449 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1450 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1452 static SOC_ENUM_SINGLE_DECL(
1453 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1454 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1456 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1457 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1459 /* MX-79 [6:4] I2S1 ADC data location */
1460 static const unsigned int rt5682_if1_adc_slot_values[] = {
1467 static const char * const rt5682_if1_adc_slot_src[] = {
1468 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1471 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1472 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1473 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1475 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1476 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1478 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1479 /* MX-2B [4], MX-2B [0]*/
1480 static const char * const rt5682_alg_dac1_src[] = {
1481 "Stereo1 DAC Mixer", "DAC1"
1484 static SOC_ENUM_SINGLE_DECL(
1485 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1486 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1488 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1489 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1491 static SOC_ENUM_SINGLE_DECL(
1492 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1493 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1495 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1496 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1499 static const struct snd_kcontrol_new hpol_switch =
1500 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1501 RT5682_L_MUTE_SFT, 1, 1);
1502 static const struct snd_kcontrol_new hpor_switch =
1503 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1504 RT5682_R_MUTE_SFT, 1, 1);
1506 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1507 struct snd_kcontrol *kcontrol, int event)
1509 struct snd_soc_component *component =
1510 snd_soc_dapm_to_component(w->dapm);
1513 case SND_SOC_DAPM_PRE_PMU:
1514 snd_soc_component_write(component,
1515 RT5682_HP_LOGIC_CTRL_2, 0x0012);
1516 snd_soc_component_write(component,
1517 RT5682_HP_CTRL_2, 0x6000);
1518 snd_soc_component_update_bits(component,
1519 RT5682_DEPOP_1, 0x60, 0x60);
1520 snd_soc_component_update_bits(component,
1521 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1524 case SND_SOC_DAPM_POST_PMD:
1525 snd_soc_component_update_bits(component,
1526 RT5682_DEPOP_1, 0x60, 0x0);
1527 snd_soc_component_write(component,
1528 RT5682_HP_CTRL_2, 0x0000);
1529 snd_soc_component_update_bits(component,
1530 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1541 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1542 struct snd_kcontrol *kcontrol, int event)
1545 case SND_SOC_DAPM_POST_PMU:
1546 /*Add delay to avoid pop noise*/
1557 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1558 struct snd_kcontrol *kcontrol, int event)
1560 struct snd_soc_component *component =
1561 snd_soc_dapm_to_component(w->dapm);
1564 case SND_SOC_DAPM_PRE_PMU:
1566 case RT5682_PWR_VREF1_BIT:
1567 snd_soc_component_update_bits(component,
1568 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1571 case RT5682_PWR_VREF2_BIT:
1572 snd_soc_component_update_bits(component,
1573 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1581 case SND_SOC_DAPM_POST_PMU:
1582 usleep_range(15000, 20000);
1584 case RT5682_PWR_VREF1_BIT:
1585 snd_soc_component_update_bits(component,
1586 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1590 case RT5682_PWR_VREF2_BIT:
1591 snd_soc_component_update_bits(component,
1592 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1608 static const unsigned int rt5682_adcdat_pin_values[] = {
1613 static const char * const rt5682_adcdat_pin_select[] = {
1618 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1619 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1620 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1622 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1623 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1625 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1626 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1628 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1630 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1632 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1633 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1634 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1635 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1636 SND_SOC_DAPM_SUPPLY("Vref2", RT5682_PWR_ANLG_1, RT5682_PWR_VREF2_BIT, 0,
1638 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1641 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1642 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1643 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1644 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1645 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1646 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1647 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1648 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1649 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1650 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1653 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1655 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1659 SND_SOC_DAPM_INPUT("DMIC L1"),
1660 SND_SOC_DAPM_INPUT("DMIC R1"),
1662 SND_SOC_DAPM_INPUT("IN1P"),
1664 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1665 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1666 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1667 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1670 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1674 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1675 ARRAY_SIZE(rt5682_rec1_l_mix)),
1676 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1677 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1680 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1681 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1683 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1684 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1685 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1686 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1687 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1688 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1691 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1692 &rt5682_sto1_adc1l_mux),
1693 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1694 &rt5682_sto1_adc1r_mux),
1695 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1696 &rt5682_sto1_adc2l_mux),
1697 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1698 &rt5682_sto1_adc2r_mux),
1699 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1700 &rt5682_sto1_adcl_mux),
1701 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1702 &rt5682_sto1_adcr_mux),
1703 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1704 &rt5682_if1_adc_slot_mux),
1707 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1708 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1709 SND_SOC_DAPM_PRE_PMU),
1710 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1711 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1712 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1713 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1714 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1715 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1716 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1720 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1722 /* Digital Interface */
1723 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1725 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1727 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1728 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1729 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1730 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1731 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1733 /* Digital Interface Select */
1734 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1735 &rt5682_if1_01_adc_swap_mux),
1736 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1737 &rt5682_if1_23_adc_swap_mux),
1738 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1739 &rt5682_if1_45_adc_swap_mux),
1740 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1741 &rt5682_if1_67_adc_swap_mux),
1742 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1743 &rt5682_if2_adc_swap_mux),
1745 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1746 &rt5682_adcdat_pin_ctrl),
1748 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1750 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1753 /* Audio Interface */
1754 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1755 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1756 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1757 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1758 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1759 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1760 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1763 /* DAC mixer before sound effect */
1764 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1765 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1766 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1767 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1769 /* DAC channel Mux */
1770 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1771 &rt5682_alg_dac_l1_mux),
1772 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1773 &rt5682_alg_dac_r1_mux),
1776 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1777 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1778 SND_SOC_DAPM_PRE_PMU),
1779 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1780 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1781 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1782 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1785 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1786 RT5682_PWR_DAC_L1_BIT, 0),
1787 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1788 RT5682_PWR_DAC_R1_BIT, 0),
1789 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1790 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1793 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1794 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1796 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1797 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1798 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1799 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1800 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1801 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1802 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1803 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1805 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1807 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1811 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1812 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1813 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1814 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1815 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1816 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1817 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1818 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1821 SND_SOC_DAPM_OUTPUT("HPOL"),
1822 SND_SOC_DAPM_OUTPUT("HPOR"),
1826 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1828 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1829 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1830 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1831 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1832 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1833 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1836 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1837 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1838 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1839 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1840 {"ADC STO1 ASRC", NULL, "CLKDET"},
1841 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1842 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1843 {"DAC STO1 ASRC", NULL, "CLKDET"},
1846 {"MICBIAS1", NULL, "Vref1"},
1847 {"MICBIAS2", NULL, "Vref1"},
1849 {"CLKDET SYS", NULL, "CLKDET"},
1851 {"IN1P", NULL, "LDO2"},
1853 {"BST1 CBJ", NULL, "IN1P"},
1855 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1856 {"RECMIX1L", NULL, "RECMIX1L Power"},
1858 {"ADC1 L", NULL, "RECMIX1L"},
1859 {"ADC1 L", NULL, "ADC1 L Power"},
1860 {"ADC1 L", NULL, "ADC1 clock"},
1862 {"DMIC L1", NULL, "DMIC CLK"},
1863 {"DMIC L1", NULL, "DMIC1 Power"},
1864 {"DMIC R1", NULL, "DMIC CLK"},
1865 {"DMIC R1", NULL, "DMIC1 Power"},
1866 {"DMIC CLK", NULL, "DMIC ASRC"},
1868 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1869 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1870 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1871 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1873 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1874 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1875 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1876 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1878 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1879 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1880 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1881 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1883 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1884 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1885 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1887 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1888 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1889 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1891 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1893 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1894 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1896 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1897 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1898 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1899 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1900 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1901 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1902 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1903 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1904 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1905 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1906 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1907 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1908 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1909 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1910 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1911 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1913 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1914 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1915 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1916 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1917 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1918 {"AIF1TX", NULL, "I2S1"},
1919 {"AIF1TX", NULL, "ADCDAT Mux"},
1920 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1921 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1922 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1923 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1924 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1925 {"AIF2TX", NULL, "ADCDAT Mux"},
1927 {"SDWTX", NULL, "PLL2B"},
1928 {"SDWTX", NULL, "PLL2F"},
1929 {"SDWTX", NULL, "ADCDAT Mux"},
1931 {"IF1 DAC1 L", NULL, "AIF1RX"},
1932 {"IF1 DAC1 L", NULL, "I2S1"},
1933 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1934 {"IF1 DAC1 R", NULL, "AIF1RX"},
1935 {"IF1 DAC1 R", NULL, "I2S1"},
1936 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1938 {"SOUND DAC L", NULL, "SDWRX"},
1939 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
1940 {"SOUND DAC L", NULL, "PLL2B"},
1941 {"SOUND DAC L", NULL, "PLL2F"},
1942 {"SOUND DAC R", NULL, "SDWRX"},
1943 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
1944 {"SOUND DAC R", NULL, "PLL2B"},
1945 {"SOUND DAC R", NULL, "PLL2F"},
1947 {"DAC L Mux", "IF1", "IF1 DAC1 L"},
1948 {"DAC L Mux", "SOUND", "SOUND DAC L"},
1949 {"DAC R Mux", "IF1", "IF1 DAC1 R"},
1950 {"DAC R Mux", "SOUND", "SOUND DAC R"},
1952 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1953 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
1954 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1955 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
1957 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1958 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1960 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1961 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1963 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1964 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1965 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1966 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1968 {"DAC L1", NULL, "DAC L1 Source"},
1969 {"DAC R1", NULL, "DAC R1 Source"},
1971 {"DAC L1", NULL, "DAC 1 Clock"},
1972 {"DAC R1", NULL, "DAC 1 Clock"},
1974 {"HP Amp", NULL, "DAC L1"},
1975 {"HP Amp", NULL, "DAC R1"},
1976 {"HP Amp", NULL, "HP Amp L"},
1977 {"HP Amp", NULL, "HP Amp R"},
1978 {"HP Amp", NULL, "Capless"},
1979 {"HP Amp", NULL, "Charge Pump"},
1980 {"HP Amp", NULL, "CLKDET SYS"},
1981 {"HP Amp", NULL, "Vref1"},
1982 {"HPOL Playback", "Switch", "HP Amp"},
1983 {"HPOR Playback", "Switch", "HP Amp"},
1984 {"HPOL", NULL, "HPOL Playback"},
1985 {"HPOR", NULL, "HPOR Playback"},
1988 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1989 unsigned int rx_mask, int slots, int slot_width)
1991 struct snd_soc_component *component = dai->component;
1992 unsigned int cl, val = 0;
1994 if (tx_mask || rx_mask)
1995 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1996 RT5682_TDM_EN, RT5682_TDM_EN);
1998 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2003 val |= RT5682_TDM_TX_CH_4;
2004 val |= RT5682_TDM_RX_CH_4;
2007 val |= RT5682_TDM_TX_CH_6;
2008 val |= RT5682_TDM_RX_CH_6;
2011 val |= RT5682_TDM_TX_CH_8;
2012 val |= RT5682_TDM_RX_CH_8;
2020 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2021 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2023 switch (slot_width) {
2025 if (tx_mask || rx_mask)
2027 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2030 val = RT5682_TDM_CL_16;
2031 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2034 val = RT5682_TDM_CL_20;
2035 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2038 val = RT5682_TDM_CL_24;
2039 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2042 val = RT5682_TDM_CL_32;
2043 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2049 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2050 RT5682_TDM_CL_MASK, val);
2051 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2052 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2058 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2059 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2061 struct snd_soc_component *component = dai->component;
2062 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2063 unsigned int len_1 = 0, len_2 = 0;
2064 int pre_div, frame_size;
2066 rt5682->lrck[dai->id] = params_rate(params);
2067 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2069 frame_size = snd_soc_params_to_frame_size(params);
2070 if (frame_size < 0) {
2071 dev_err(component->dev, "Unsupported frame size: %d\n",
2076 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2077 rt5682->lrck[dai->id], pre_div, dai->id);
2079 switch (params_width(params)) {
2083 len_1 |= RT5682_I2S1_DL_20;
2084 len_2 |= RT5682_I2S2_DL_20;
2087 len_1 |= RT5682_I2S1_DL_24;
2088 len_2 |= RT5682_I2S2_DL_24;
2091 len_1 |= RT5682_I2S1_DL_32;
2092 len_2 |= RT5682_I2S2_DL_24;
2095 len_1 |= RT5682_I2S2_DL_8;
2096 len_2 |= RT5682_I2S2_DL_8;
2104 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2105 RT5682_I2S1_DL_MASK, len_1);
2106 if (rt5682->master[RT5682_AIF1]) {
2107 snd_soc_component_update_bits(component,
2108 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2109 RT5682_I2S_CLK_SRC_MASK,
2110 pre_div << RT5682_I2S_M_DIV_SFT |
2111 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2113 if (params_channels(params) == 1) /* mono mode */
2114 snd_soc_component_update_bits(component,
2115 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2116 RT5682_I2S1_MONO_EN);
2118 snd_soc_component_update_bits(component,
2119 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2120 RT5682_I2S1_MONO_DIS);
2123 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2124 RT5682_I2S2_DL_MASK, len_2);
2125 if (rt5682->master[RT5682_AIF2]) {
2126 snd_soc_component_update_bits(component,
2127 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2128 pre_div << RT5682_I2S2_M_PD_SFT);
2130 if (params_channels(params) == 1) /* mono mode */
2131 snd_soc_component_update_bits(component,
2132 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2133 RT5682_I2S2_MONO_EN);
2135 snd_soc_component_update_bits(component,
2136 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2137 RT5682_I2S2_MONO_DIS);
2140 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2147 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2149 struct snd_soc_component *component = dai->component;
2150 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2151 unsigned int reg_val = 0, tdm_ctrl = 0;
2153 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2154 case SND_SOC_DAIFMT_CBM_CFM:
2155 rt5682->master[dai->id] = 1;
2157 case SND_SOC_DAIFMT_CBS_CFS:
2158 rt5682->master[dai->id] = 0;
2164 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2165 case SND_SOC_DAIFMT_NB_NF:
2167 case SND_SOC_DAIFMT_IB_NF:
2168 reg_val |= RT5682_I2S_BP_INV;
2169 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2171 case SND_SOC_DAIFMT_NB_IF:
2172 if (dai->id == RT5682_AIF1)
2173 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2177 case SND_SOC_DAIFMT_IB_IF:
2178 if (dai->id == RT5682_AIF1)
2179 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2180 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2188 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2189 case SND_SOC_DAIFMT_I2S:
2191 case SND_SOC_DAIFMT_LEFT_J:
2192 reg_val |= RT5682_I2S_DF_LEFT;
2193 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2195 case SND_SOC_DAIFMT_DSP_A:
2196 reg_val |= RT5682_I2S_DF_PCM_A;
2197 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2199 case SND_SOC_DAIFMT_DSP_B:
2200 reg_val |= RT5682_I2S_DF_PCM_B;
2201 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2209 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2210 RT5682_I2S_DF_MASK, reg_val);
2211 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2212 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2213 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2214 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2215 tdm_ctrl | rt5682->master[dai->id]);
2218 if (rt5682->master[dai->id] == 0)
2219 reg_val |= RT5682_I2S2_MS_S;
2220 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2221 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2222 RT5682_I2S_DF_MASK, reg_val);
2225 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2231 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2232 int clk_id, int source, unsigned int freq, int dir)
2234 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2235 unsigned int reg_val = 0, src = 0;
2237 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2241 case RT5682_SCLK_S_MCLK:
2242 reg_val |= RT5682_SCLK_SRC_MCLK;
2243 src = RT5682_CLK_SRC_MCLK;
2245 case RT5682_SCLK_S_PLL1:
2246 reg_val |= RT5682_SCLK_SRC_PLL1;
2247 src = RT5682_CLK_SRC_PLL1;
2249 case RT5682_SCLK_S_PLL2:
2250 reg_val |= RT5682_SCLK_SRC_PLL2;
2251 src = RT5682_CLK_SRC_PLL2;
2253 case RT5682_SCLK_S_RCCLK:
2254 reg_val |= RT5682_SCLK_SRC_RCCLK;
2255 src = RT5682_CLK_SRC_RCCLK;
2258 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2261 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2262 RT5682_SCLK_SRC_MASK, reg_val);
2264 if (rt5682->master[RT5682_AIF2]) {
2265 snd_soc_component_update_bits(component,
2266 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2267 src << RT5682_I2S2_SRC_SFT);
2270 rt5682->sysclk = freq;
2271 rt5682->sysclk_src = clk_id;
2273 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2279 static int rt5682_set_component_pll(struct snd_soc_component *component,
2280 int pll_id, int source, unsigned int freq_in,
2281 unsigned int freq_out)
2283 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2284 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2285 unsigned int pll2_fout1;
2288 if (source == rt5682->pll_src[pll_id] &&
2289 freq_in == rt5682->pll_in[pll_id] &&
2290 freq_out == rt5682->pll_out[pll_id])
2293 if (!freq_in || !freq_out) {
2294 dev_dbg(component->dev, "PLL disabled\n");
2296 rt5682->pll_in[pll_id] = 0;
2297 rt5682->pll_out[pll_id] = 0;
2298 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2299 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2303 if (pll_id == RT5682_PLL2) {
2305 case RT5682_PLL2_S_MCLK:
2306 snd_soc_component_update_bits(component,
2307 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2308 RT5682_PLL2_SRC_MCLK);
2311 dev_err(component->dev, "Unknown PLL2 Source %d\n",
2317 * PLL2 concatenates 2 PLL units.
2318 * We suggest the Fout of the front PLL is 3.84MHz.
2320 pll2_fout1 = 3840000;
2321 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2323 dev_err(component->dev, "Unsupport input clock %d\n",
2327 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2328 freq_in, pll2_fout1,
2330 (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2331 pll2f_code.n_code, pll2f_code.k_code);
2333 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2335 dev_err(component->dev, "Unsupport input clock %d\n",
2339 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2340 pll2_fout1, freq_out,
2342 (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2343 pll2b_code.n_code, pll2b_code.k_code);
2345 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2346 pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2347 pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2349 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2350 pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2352 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2353 pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2354 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2355 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2356 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2357 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2361 case RT5682_PLL1_S_MCLK:
2362 snd_soc_component_update_bits(component,
2363 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2364 RT5682_PLL1_SRC_MCLK);
2366 case RT5682_PLL1_S_BCLK1:
2367 snd_soc_component_update_bits(component,
2368 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2369 RT5682_PLL1_SRC_BCLK1);
2372 dev_err(component->dev, "Unknown PLL1 Source %d\n",
2377 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2379 dev_err(component->dev, "Unsupport input clock %d\n",
2384 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2385 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2386 pll_code.n_code, pll_code.k_code);
2388 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2389 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2390 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2391 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2392 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2395 rt5682->pll_in[pll_id] = freq_in;
2396 rt5682->pll_out[pll_id] = freq_out;
2397 rt5682->pll_src[pll_id] = source;
2402 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2404 struct snd_soc_component *component = dai->component;
2405 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2407 rt5682->bclk[dai->id] = ratio;
2411 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2412 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2415 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2416 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2419 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2420 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2423 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2424 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2427 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2434 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2436 struct snd_soc_component *component = dai->component;
2437 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2439 rt5682->bclk[dai->id] = ratio;
2443 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2444 RT5682_I2S2_BCLK_MS2_MASK,
2445 RT5682_I2S2_BCLK_MS2_64);
2448 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2449 RT5682_I2S2_BCLK_MS2_MASK,
2450 RT5682_I2S2_BCLK_MS2_32);
2453 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2460 static int rt5682_set_bias_level(struct snd_soc_component *component,
2461 enum snd_soc_bias_level level)
2463 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2466 case SND_SOC_BIAS_PREPARE:
2467 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2468 RT5682_PWR_BG, RT5682_PWR_BG);
2469 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2470 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2471 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2474 case SND_SOC_BIAS_STANDBY:
2475 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2476 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2478 case SND_SOC_BIAS_OFF:
2479 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2480 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2481 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2492 #ifdef CONFIG_COMMON_CLK
2493 #define CLK_PLL2_FIN 48000000
2494 #define CLK_PLL2_FOUT 24576000
2495 #define CLK_48 48000
2497 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2499 if (!rt5682->master[RT5682_AIF1]) {
2500 dev_err(rt5682->component->dev, "sysclk/dai not set correctly\n");
2506 static int rt5682_wclk_prepare(struct clk_hw *hw)
2508 struct rt5682_priv *rt5682 =
2509 container_of(hw, struct rt5682_priv,
2510 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2511 struct snd_soc_component *component = rt5682->component;
2512 struct snd_soc_dapm_context *dapm =
2513 snd_soc_component_get_dapm(component);
2515 if (!rt5682_clk_check(rt5682))
2518 snd_soc_dapm_mutex_lock(dapm);
2520 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2521 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2522 RT5682_PWR_MB, RT5682_PWR_MB);
2523 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2524 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2525 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2526 snd_soc_dapm_sync_unlocked(dapm);
2528 snd_soc_dapm_mutex_unlock(dapm);
2533 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2535 struct rt5682_priv *rt5682 =
2536 container_of(hw, struct rt5682_priv,
2537 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2538 struct snd_soc_component *component = rt5682->component;
2539 struct snd_soc_dapm_context *dapm =
2540 snd_soc_component_get_dapm(component);
2542 if (!rt5682_clk_check(rt5682))
2545 snd_soc_dapm_mutex_lock(dapm);
2547 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2548 if (!rt5682->jack_type)
2549 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2551 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2552 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2553 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2554 snd_soc_dapm_sync_unlocked(dapm);
2556 snd_soc_dapm_mutex_unlock(dapm);
2559 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2560 unsigned long parent_rate)
2562 struct rt5682_priv *rt5682 =
2563 container_of(hw, struct rt5682_priv,
2564 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2566 if (!rt5682_clk_check(rt5682))
2569 * Only accept to set wclk rate to 48kHz temporarily.
2574 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2575 unsigned long *parent_rate)
2577 struct rt5682_priv *rt5682 =
2578 container_of(hw, struct rt5682_priv,
2579 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2581 if (!rt5682_clk_check(rt5682))
2584 * Only accept to set wclk rate to 48kHz temporarily.
2589 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2590 unsigned long parent_rate)
2592 struct rt5682_priv *rt5682 =
2593 container_of(hw, struct rt5682_priv,
2594 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2595 struct snd_soc_component *component = rt5682->component;
2596 struct clk *parent_clk;
2597 const char * const clk_name = __clk_get_name(hw->clk);
2600 if (!rt5682_clk_check(rt5682))
2604 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2605 * it is fixed or set to 48MHz before setting wclk rate. It's a
2606 * temporary limitation. Only accept 48MHz clk as the clk provider.
2608 * It will set the codec anyway by assuming mclk is 48MHz.
2610 parent_clk = clk_get_parent(hw->clk);
2612 dev_warn(component->dev,
2613 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2616 if (parent_rate != CLK_PLL2_FIN)
2617 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2618 clk_name, CLK_PLL2_FIN);
2621 * It's a temporary limitation. Only accept to set wclk rate to 48kHz.
2622 * It will force wclk to 48kHz even it's not.
2624 if (rate != CLK_48) {
2625 dev_warn(component->dev, "clk %s only support %d Hz output\n",
2631 * To achieve the rate conversion from 48MHz to 48kHz, PLL2 is needed.
2633 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2634 CLK_PLL2_FIN, CLK_PLL2_FOUT);
2636 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2637 CLK_PLL2_FOUT, SND_SOC_CLOCK_IN);
2639 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2641 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2642 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2643 pre_div << RT5682_I2S_M_DIV_SFT |
2644 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2649 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2650 unsigned long parent_rate)
2652 struct rt5682_priv *rt5682 =
2653 container_of(hw, struct rt5682_priv,
2654 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2655 struct snd_soc_component *component = rt5682->component;
2656 unsigned int bclks_per_wclk;
2658 snd_soc_component_read(component, RT5682_TDM_TCON_CTRL,
2661 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2662 case RT5682_TDM_BCLK_MS1_256:
2663 return parent_rate * 256;
2664 case RT5682_TDM_BCLK_MS1_128:
2665 return parent_rate * 128;
2666 case RT5682_TDM_BCLK_MS1_64:
2667 return parent_rate * 64;
2668 case RT5682_TDM_BCLK_MS1_32:
2669 return parent_rate * 32;
2675 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2676 unsigned long parent_rate)
2678 unsigned long factor;
2680 factor = rate / parent_rate;
2683 else if (factor < 128)
2685 else if (factor < 256)
2691 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2692 unsigned long *parent_rate)
2694 struct rt5682_priv *rt5682 =
2695 container_of(hw, struct rt5682_priv,
2696 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2697 unsigned long factor;
2699 if (!*parent_rate || !rt5682_clk_check(rt5682))
2703 * BCLK rates are set as a multiplier of WCLK in HW.
2704 * We don't allow changing the parent WCLK. We just do
2705 * some rounding down based on the parent WCLK rate
2706 * and find the appropriate multiplier of BCLK to
2707 * get the rounded down BCLK value.
2709 factor = rt5682_bclk_get_factor(rate, *parent_rate);
2711 return *parent_rate * factor;
2714 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2715 unsigned long parent_rate)
2717 struct rt5682_priv *rt5682 =
2718 container_of(hw, struct rt5682_priv,
2719 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2720 struct snd_soc_component *component = rt5682->component;
2721 struct snd_soc_dai *dai = NULL;
2722 unsigned long factor;
2724 if (!rt5682_clk_check(rt5682))
2727 factor = rt5682_bclk_get_factor(rate, parent_rate);
2729 for_each_component_dais(component, dai)
2730 if (dai->id == RT5682_AIF1)
2733 dev_err(component->dev, "dai %d not found in component\n",
2738 return rt5682_set_bclk1_ratio(dai, factor);
2741 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2742 [RT5682_DAI_WCLK_IDX] = {
2743 .prepare = rt5682_wclk_prepare,
2744 .unprepare = rt5682_wclk_unprepare,
2745 .recalc_rate = rt5682_wclk_recalc_rate,
2746 .round_rate = rt5682_wclk_round_rate,
2747 .set_rate = rt5682_wclk_set_rate,
2749 [RT5682_DAI_BCLK_IDX] = {
2750 .recalc_rate = rt5682_bclk_recalc_rate,
2751 .round_rate = rt5682_bclk_round_rate,
2752 .set_rate = rt5682_bclk_set_rate,
2756 static int rt5682_register_dai_clks(struct snd_soc_component *component)
2758 struct device *dev = component->dev;
2759 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2760 struct rt5682_platform_data *pdata = &rt5682->pdata;
2761 struct clk_init_data init;
2762 struct clk *dai_clk;
2763 struct clk_lookup *dai_clk_lookup;
2764 struct clk_hw *dai_clk_hw;
2765 const char *parent_name;
2768 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2769 dai_clk_hw = &rt5682->dai_clks_hw[i];
2772 case RT5682_DAI_WCLK_IDX:
2773 /* Make MCLK the parent of WCLK */
2775 parent_name = __clk_get_name(rt5682->mclk);
2776 init.parent_names = &parent_name;
2777 init.num_parents = 1;
2779 init.parent_names = NULL;
2780 init.num_parents = 0;
2783 case RT5682_DAI_BCLK_IDX:
2784 /* Make WCLK the parent of BCLK */
2785 parent_name = __clk_get_name(
2786 rt5682->dai_clks[RT5682_DAI_WCLK_IDX]);
2787 init.parent_names = &parent_name;
2788 init.num_parents = 1;
2791 dev_err(dev, "Invalid clock index\n");
2796 init.name = pdata->dai_clk_names[i];
2797 init.ops = &rt5682_dai_clk_ops[i];
2798 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2799 dai_clk_hw->init = &init;
2801 dai_clk = devm_clk_register(dev, dai_clk_hw);
2802 if (IS_ERR(dai_clk)) {
2803 dev_warn(dev, "Failed to register %s: %ld\n",
2804 init.name, PTR_ERR(dai_clk));
2805 ret = PTR_ERR(dai_clk);
2808 rt5682->dai_clks[i] = dai_clk;
2811 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2814 dai_clk_lookup = clkdev_create(dai_clk, init.name,
2815 "%s", dev_name(dev));
2816 if (!dai_clk_lookup) {
2820 rt5682->dai_clks_lookup[i] = dai_clk_lookup;
2829 if (rt5682->dai_clks_lookup[i])
2830 clkdev_drop(rt5682->dai_clks_lookup[i]);
2835 #endif /* CONFIG_COMMON_CLK */
2837 static int rt5682_probe(struct snd_soc_component *component)
2839 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2840 struct sdw_slave *slave;
2843 #ifdef CONFIG_COMMON_CLK
2846 rt5682->component = component;
2848 #ifdef CONFIG_COMMON_CLK
2849 /* Check if MCLK provided */
2850 rt5682->mclk = devm_clk_get(component->dev, "mclk");
2851 if (IS_ERR(rt5682->mclk)) {
2852 if (PTR_ERR(rt5682->mclk) != -ENOENT) {
2853 ret = PTR_ERR(rt5682->mclk);
2856 rt5682->mclk = NULL;
2859 /* Register CCF DAI clock control */
2860 ret = rt5682_register_dai_clks(component);
2864 /* Initial setup for CCF */
2865 rt5682->lrck[RT5682_AIF1] = CLK_48;
2868 if (rt5682->is_sdw) {
2869 slave = rt5682->slave;
2870 time = wait_for_completion_timeout(
2871 &slave->initialization_complete,
2872 msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2874 dev_err(&slave->dev, "Initialization not complete, timed out\n");
2882 static void rt5682_remove(struct snd_soc_component *component)
2884 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2886 #ifdef CONFIG_COMMON_CLK
2889 for (i = RT5682_DAI_NUM_CLKS - 1; i >= 0; --i) {
2890 if (rt5682->dai_clks_lookup[i])
2891 clkdev_drop(rt5682->dai_clks_lookup[i]);
2895 rt5682_reset(rt5682);
2899 static int rt5682_suspend(struct snd_soc_component *component)
2901 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2903 regcache_cache_only(rt5682->regmap, true);
2904 regcache_mark_dirty(rt5682->regmap);
2908 static int rt5682_resume(struct snd_soc_component *component)
2910 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2912 regcache_cache_only(rt5682->regmap, false);
2913 regcache_sync(rt5682->regmap);
2915 rt5682_irq(0, rt5682);
2920 #define rt5682_suspend NULL
2921 #define rt5682_resume NULL
2924 #define RT5682_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2925 #define RT5682_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2926 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2928 static const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2929 .hw_params = rt5682_hw_params,
2930 .set_fmt = rt5682_set_dai_fmt,
2931 .set_tdm_slot = rt5682_set_tdm_slot,
2932 .set_bclk_ratio = rt5682_set_bclk1_ratio,
2935 static const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2936 .hw_params = rt5682_hw_params,
2937 .set_fmt = rt5682_set_dai_fmt,
2938 .set_bclk_ratio = rt5682_set_bclk2_ratio,
2941 #if IS_ENABLED(CONFIG_SND_SOC_RT5682_SDW)
2942 struct sdw_stream_data {
2943 struct sdw_stream_runtime *sdw_stream;
2946 static int rt5682_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
2949 struct sdw_stream_data *stream;
2951 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
2955 stream->sdw_stream = (struct sdw_stream_runtime *)sdw_stream;
2957 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
2958 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
2959 dai->playback_dma_data = stream;
2961 dai->capture_dma_data = stream;
2966 static void rt5682_sdw_shutdown(struct snd_pcm_substream *substream,
2967 struct snd_soc_dai *dai)
2969 struct sdw_stream_data *stream;
2971 stream = snd_soc_dai_get_dma_data(dai, substream);
2972 snd_soc_dai_set_dma_data(dai, substream, NULL);
2976 static int rt5682_sdw_hw_params(struct snd_pcm_substream *substream,
2977 struct snd_pcm_hw_params *params,
2978 struct snd_soc_dai *dai)
2980 struct snd_soc_component *component = dai->component;
2981 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2982 struct sdw_stream_config stream_config;
2983 struct sdw_port_config port_config;
2984 enum sdw_data_direction direction;
2985 struct sdw_stream_data *stream;
2986 int retval, port, num_channels;
2987 unsigned int val_p = 0, val_c = 0, osr_p = 0, osr_c = 0;
2989 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
2990 stream = snd_soc_dai_get_dma_data(dai, substream);
2998 /* SoundWire specific configuration */
2999 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3000 direction = SDW_DATA_DIR_RX;
3003 direction = SDW_DATA_DIR_TX;
3007 stream_config.frame_rate = params_rate(params);
3008 stream_config.ch_count = params_channels(params);
3009 stream_config.bps = snd_pcm_format_width(params_format(params));
3010 stream_config.direction = direction;
3012 num_channels = params_channels(params);
3013 port_config.ch_mask = (1 << (num_channels)) - 1;
3014 port_config.num = port;
3016 retval = sdw_stream_add_slave(rt5682->slave, &stream_config,
3017 &port_config, 1, stream->sdw_stream);
3019 dev_err(dai->dev, "Unable to configure port\n");
3023 switch (params_rate(params)) {
3025 val_p = RT5682_SDW_REF_1_48K;
3026 val_c = RT5682_SDW_REF_2_48K;
3029 val_p = RT5682_SDW_REF_1_96K;
3030 val_c = RT5682_SDW_REF_2_96K;
3033 val_p = RT5682_SDW_REF_1_192K;
3034 val_c = RT5682_SDW_REF_2_192K;
3037 val_p = RT5682_SDW_REF_1_32K;
3038 val_c = RT5682_SDW_REF_2_32K;
3041 val_p = RT5682_SDW_REF_1_24K;
3042 val_c = RT5682_SDW_REF_2_24K;
3045 val_p = RT5682_SDW_REF_1_16K;
3046 val_c = RT5682_SDW_REF_2_16K;
3049 val_p = RT5682_SDW_REF_1_12K;
3050 val_c = RT5682_SDW_REF_2_12K;
3053 val_p = RT5682_SDW_REF_1_8K;
3054 val_c = RT5682_SDW_REF_2_8K;
3057 val_p = RT5682_SDW_REF_1_44K;
3058 val_c = RT5682_SDW_REF_2_44K;
3061 val_p = RT5682_SDW_REF_1_88K;
3062 val_c = RT5682_SDW_REF_2_88K;
3065 val_p = RT5682_SDW_REF_1_176K;
3066 val_c = RT5682_SDW_REF_2_176K;
3069 val_p = RT5682_SDW_REF_1_22K;
3070 val_c = RT5682_SDW_REF_2_22K;
3073 val_p = RT5682_SDW_REF_1_11K;
3074 val_c = RT5682_SDW_REF_2_11K;
3080 if (params_rate(params) <= 48000) {
3081 osr_p = RT5682_DAC_OSR_D_8;
3082 osr_c = RT5682_ADC_OSR_D_8;
3083 } else if (params_rate(params) <= 96000) {
3084 osr_p = RT5682_DAC_OSR_D_4;
3085 osr_c = RT5682_ADC_OSR_D_4;
3087 osr_p = RT5682_DAC_OSR_D_2;
3088 osr_c = RT5682_ADC_OSR_D_2;
3091 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3092 regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
3093 RT5682_SDW_REF_1_MASK, val_p);
3094 regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
3095 RT5682_DAC_OSR_MASK, osr_p);
3097 regmap_update_bits(rt5682->regmap, RT5682_SDW_REF_CLK,
3098 RT5682_SDW_REF_2_MASK, val_c);
3099 regmap_update_bits(rt5682->regmap, RT5682_ADDA_CLK_1,
3100 RT5682_ADC_OSR_MASK, osr_c);
3106 static int rt5682_sdw_hw_free(struct snd_pcm_substream *substream,
3107 struct snd_soc_dai *dai)
3109 struct snd_soc_component *component = dai->component;
3110 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
3111 struct sdw_stream_data *stream =
3112 snd_soc_dai_get_dma_data(dai, substream);
3117 sdw_stream_remove_slave(rt5682->slave, stream->sdw_stream);
3121 static struct snd_soc_dai_ops rt5682_sdw_ops = {
3122 .hw_params = rt5682_sdw_hw_params,
3123 .hw_free = rt5682_sdw_hw_free,
3124 .set_sdw_stream = rt5682_set_sdw_stream,
3125 .shutdown = rt5682_sdw_shutdown,
3129 static struct snd_soc_dai_driver rt5682_dai[] = {
3131 .name = "rt5682-aif1",
3134 .stream_name = "AIF1 Playback",
3137 .rates = RT5682_STEREO_RATES,
3138 .formats = RT5682_FORMATS,
3141 .stream_name = "AIF1 Capture",
3144 .rates = RT5682_STEREO_RATES,
3145 .formats = RT5682_FORMATS,
3147 .ops = &rt5682_aif1_dai_ops,
3150 .name = "rt5682-aif2",
3153 .stream_name = "AIF2 Capture",
3156 .rates = RT5682_STEREO_RATES,
3157 .formats = RT5682_FORMATS,
3159 .ops = &rt5682_aif2_dai_ops,
3161 #if IS_ENABLED(CONFIG_SND_SOC_RT5682_SDW)
3163 .name = "rt5682-sdw",
3166 .stream_name = "SDW Playback",
3169 .rates = RT5682_STEREO_RATES,
3170 .formats = RT5682_FORMATS,
3173 .stream_name = "SDW Capture",
3176 .rates = RT5682_STEREO_RATES,
3177 .formats = RT5682_FORMATS,
3179 .ops = &rt5682_sdw_ops,
3184 static const struct snd_soc_component_driver soc_component_dev_rt5682 = {
3185 .probe = rt5682_probe,
3186 .remove = rt5682_remove,
3187 .suspend = rt5682_suspend,
3188 .resume = rt5682_resume,
3189 .set_bias_level = rt5682_set_bias_level,
3190 .controls = rt5682_snd_controls,
3191 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
3192 .dapm_widgets = rt5682_dapm_widgets,
3193 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
3194 .dapm_routes = rt5682_dapm_routes,
3195 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
3196 .set_sysclk = rt5682_set_component_sysclk,
3197 .set_pll = rt5682_set_component_pll,
3198 .set_jack = rt5682_set_jack_detect,
3199 .use_pmdown_time = 1,
3201 .non_legacy_dai_naming = 1,
3204 static const struct regmap_config rt5682_regmap = {
3207 .max_register = RT5682_I2C_MODE,
3208 .volatile_reg = rt5682_volatile_register,
3209 .readable_reg = rt5682_readable_register,
3210 .cache_type = REGCACHE_RBTREE,
3211 .reg_defaults = rt5682_reg,
3212 .num_reg_defaults = ARRAY_SIZE(rt5682_reg),
3213 .use_single_read = true,
3214 .use_single_write = true,
3217 static const struct i2c_device_id rt5682_i2c_id[] = {
3221 MODULE_DEVICE_TABLE(i2c, rt5682_i2c_id);
3223 static int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
3226 device_property_read_u32(dev, "realtek,dmic1-data-pin",
3227 &rt5682->pdata.dmic1_data_pin);
3228 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
3229 &rt5682->pdata.dmic1_clk_pin);
3230 device_property_read_u32(dev, "realtek,jd-src",
3231 &rt5682->pdata.jd_src);
3232 device_property_read_u32(dev, "realtek,btndet-delay",
3233 &rt5682->pdata.btndet_delay);
3235 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
3236 "realtek,ldo1-en-gpios", 0);
3238 if (device_property_read_string_array(dev, "clock-output-names",
3239 rt5682->pdata.dai_clk_names,
3240 RT5682_DAI_NUM_CLKS) < 0)
3241 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3242 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3243 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3248 static void rt5682_calibrate(struct rt5682_priv *rt5682)
3252 mutex_lock(&rt5682->calibrate_mutex);
3254 rt5682_reset(rt5682);
3255 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3256 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3257 usleep_range(15000, 20000);
3258 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3259 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3260 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3261 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3262 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3263 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3264 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3265 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3266 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3267 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3268 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3269 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3270 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3271 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3272 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3274 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3276 for (count = 0; count < 60; count++) {
3277 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3278 if (!(value & 0x8000))
3281 usleep_range(10000, 10005);
3285 pr_err("HP Calibration Failure\n");
3287 /* restore settings */
3288 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x02af);
3289 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3290 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3291 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3292 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3293 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3294 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3296 mutex_unlock(&rt5682->calibrate_mutex);
3300 #if IS_ENABLED(CONFIG_SND_SOC_RT5682_SDW)
3301 static int rt5682_sdw_read(void *context, unsigned int reg, unsigned int *val)
3303 struct device *dev = context;
3304 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
3305 unsigned int data_l, data_h;
3307 regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 0);
3308 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
3309 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
3310 regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_H, &data_h);
3311 regmap_read(rt5682->sdw_regmap, RT5682_SDW_DATA_L, &data_l);
3313 *val = (data_h << 8) | data_l;
3315 dev_vdbg(dev, "[%s] %04x => %04x\n", __func__, reg, *val);
3320 static int rt5682_sdw_write(void *context, unsigned int reg, unsigned int val)
3322 struct device *dev = context;
3323 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
3325 regmap_write(rt5682->sdw_regmap, RT5682_SDW_CMD, 1);
3326 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_H, (reg >> 8) & 0xff);
3327 regmap_write(rt5682->sdw_regmap, RT5682_SDW_ADDR_L, (reg & 0xff));
3328 regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_H, (val >> 8) & 0xff);
3329 regmap_write(rt5682->sdw_regmap, RT5682_SDW_DATA_L, (val & 0xff));
3331 dev_vdbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
3336 static const struct regmap_config rt5682_sdw_regmap = {
3339 .max_register = RT5682_I2C_MODE,
3340 .volatile_reg = rt5682_volatile_register,
3341 .readable_reg = rt5682_readable_register,
3342 .cache_type = REGCACHE_RBTREE,
3343 .reg_defaults = rt5682_reg,
3344 .num_reg_defaults = ARRAY_SIZE(rt5682_reg),
3345 .use_single_read = true,
3346 .use_single_write = true,
3347 .reg_read = rt5682_sdw_read,
3348 .reg_write = rt5682_sdw_write,
3351 int rt5682_sdw_init(struct device *dev, struct regmap *regmap,
3352 struct sdw_slave *slave)
3354 struct rt5682_priv *rt5682;
3357 rt5682 = devm_kzalloc(dev, sizeof(*rt5682), GFP_KERNEL);
3361 dev_set_drvdata(dev, rt5682);
3362 rt5682->slave = slave;
3363 rt5682->sdw_regmap = regmap;
3364 rt5682->is_sdw = true;
3366 rt5682->regmap = devm_regmap_init(dev, NULL, dev, &rt5682_sdw_regmap);
3367 if (IS_ERR(rt5682->regmap)) {
3368 ret = PTR_ERR(rt5682->regmap);
3369 dev_err(dev, "Failed to allocate register map: %d\n",
3375 * Mark hw_init to false
3376 * HW init will be performed when device reports present
3378 rt5682->hw_init = false;
3379 rt5682->first_hw_init = false;
3381 mutex_init(&rt5682->calibrate_mutex);
3382 INIT_DELAYED_WORK(&rt5682->jack_detect_work,
3383 rt5682_jack_detect_handler);
3385 ret = devm_snd_soc_register_component(dev, &soc_component_dev_rt5682,
3386 rt5682_dai, ARRAY_SIZE(rt5682_dai));
3388 dev_dbg(&slave->dev, "%s\n", __func__);
3392 EXPORT_SYMBOL_GPL(rt5682_sdw_init);
3394 int rt5682_io_init(struct device *dev, struct sdw_slave *slave)
3396 struct rt5682_priv *rt5682 = dev_get_drvdata(dev);
3400 if (rt5682->hw_init)
3403 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
3404 if (val != DEVICE_ID) {
3405 pr_err("Device with ID register %x is not rt5682\n", val);
3410 * PM runtime is only enabled when a Slave reports as Attached
3412 if (!rt5682->first_hw_init) {
3413 /* set autosuspend parameters */
3414 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
3415 pm_runtime_use_autosuspend(&slave->dev);
3417 /* update count of parent 'active' children */
3418 pm_runtime_set_active(&slave->dev);
3420 /* make sure the device does not suspend immediately */
3421 pm_runtime_mark_last_busy(&slave->dev);
3423 pm_runtime_enable(&slave->dev);
3426 pm_runtime_get_noresume(&slave->dev);
3428 rt5682_reset(rt5682);
3430 if (rt5682->first_hw_init) {
3431 regcache_cache_only(rt5682->regmap, false);
3432 regcache_cache_bypass(rt5682->regmap, true);
3435 rt5682_calibrate(rt5682);
3437 if (rt5682->first_hw_init) {
3438 regcache_cache_bypass(rt5682->regmap, false);
3439 regcache_mark_dirty(rt5682->regmap);
3440 regcache_sync(rt5682->regmap);
3442 /* volatile registers */
3443 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
3444 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
3449 ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
3450 ARRAY_SIZE(patch_list));
3452 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
3454 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
3456 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
3457 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
3458 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
3459 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
3460 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
3461 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
3462 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
3463 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
3464 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
3465 regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1,
3466 RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
3469 regmap_write(rt5682->regmap, RT5682_PLL2_INTERNAL, 0xa266);
3470 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_1, 0x1700);
3471 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_2, 0x0006);
3472 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_3, 0x2600);
3473 regmap_write(rt5682->regmap, RT5682_PLL2_CTRL_4, 0x0c8f);
3474 regmap_write(rt5682->regmap, RT5682_PLL_TRACK_2, 0x3000);
3475 regmap_write(rt5682->regmap, RT5682_PLL_TRACK_3, 0x4000);
3476 regmap_update_bits(rt5682->regmap, RT5682_GLB_CLK,
3477 RT5682_SCLK_SRC_MASK | RT5682_PLL2_SRC_MASK,
3478 RT5682_SCLK_SRC_PLL2 | RT5682_PLL2_SRC_SDW);
3480 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_2,
3481 RT5682_EXT_JD_SRC, RT5682_EXT_JD_SRC_MANUAL);
3482 regmap_write(rt5682->regmap, RT5682_CBJ_CTRL_1, 0xd042);
3483 regmap_update_bits(rt5682->regmap, RT5682_CBJ_CTRL_3,
3484 RT5682_CBJ_IN_BUF_EN, RT5682_CBJ_IN_BUF_EN);
3485 regmap_update_bits(rt5682->regmap, RT5682_SAR_IL_CMD_1,
3486 RT5682_SAR_POW_MASK, RT5682_SAR_POW_EN);
3487 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
3488 RT5682_POW_IRQ | RT5682_POW_JDH |
3489 RT5682_POW_ANA, RT5682_POW_IRQ |
3490 RT5682_POW_JDH | RT5682_POW_ANA);
3491 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
3492 RT5682_PWR_JDH, RT5682_PWR_JDH);
3493 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
3494 RT5682_JD1_EN_MASK | RT5682_JD1_IRQ_MASK,
3495 RT5682_JD1_EN | RT5682_JD1_IRQ_PUL);
3498 mod_delayed_work(system_power_efficient_wq,
3499 &rt5682->jack_detect_work, msecs_to_jiffies(250));
3501 /* Mark Slave initialization complete */
3502 rt5682->hw_init = true;
3503 rt5682->first_hw_init = true;
3505 pm_runtime_mark_last_busy(&slave->dev);
3506 pm_runtime_put_autosuspend(&slave->dev);
3508 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
3512 EXPORT_SYMBOL_GPL(rt5682_io_init);
3515 static int rt5682_i2c_probe(struct i2c_client *i2c,
3516 const struct i2c_device_id *id)
3518 struct rt5682_platform_data *pdata = dev_get_platdata(&i2c->dev);
3519 struct rt5682_priv *rt5682;
3523 rt5682 = devm_kzalloc(&i2c->dev, sizeof(struct rt5682_priv),
3529 i2c_set_clientdata(i2c, rt5682);
3531 rt5682->pdata = i2s_default_platform_data;
3534 rt5682->pdata = *pdata;
3536 rt5682_parse_dt(rt5682, &i2c->dev);
3538 rt5682->regmap = devm_regmap_init_i2c(i2c, &rt5682_regmap);
3539 if (IS_ERR(rt5682->regmap)) {
3540 ret = PTR_ERR(rt5682->regmap);
3541 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3546 for (i = 0; i < ARRAY_SIZE(rt5682->supplies); i++)
3547 rt5682->supplies[i].supply = rt5682_supply_names[i];
3549 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5682->supplies),
3552 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3556 ret = regulator_bulk_enable(ARRAY_SIZE(rt5682->supplies),
3559 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3563 if (gpio_is_valid(rt5682->pdata.ldo1_en)) {
3564 if (devm_gpio_request_one(&i2c->dev, rt5682->pdata.ldo1_en,
3565 GPIOF_OUT_INIT_HIGH, "rt5682"))
3566 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
3569 /* Sleep for 300 ms miniumum */
3570 usleep_range(300000, 350000);
3572 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 0x1);
3573 usleep_range(10000, 15000);
3575 regmap_read(rt5682->regmap, RT5682_DEVICE_ID, &val);
3576 if (val != DEVICE_ID) {
3577 pr_err("Device with ID register %x is not rt5682\n", val);
3581 rt5682_reset(rt5682);
3583 mutex_init(&rt5682->calibrate_mutex);
3584 rt5682_calibrate(rt5682);
3586 ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
3587 ARRAY_SIZE(patch_list));
3589 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3591 regmap_write(rt5682->regmap, RT5682_DEPOP_1, 0x0000);
3594 if (rt5682->pdata.dmic1_data_pin != RT5682_DMIC1_NULL) {
3595 switch (rt5682->pdata.dmic1_data_pin) {
3596 case RT5682_DMIC1_DATA_GPIO2: /* share with LRCK2 */
3597 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
3598 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO2);
3599 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
3600 RT5682_GP2_PIN_MASK, RT5682_GP2_PIN_DMIC_SDA);
3603 case RT5682_DMIC1_DATA_GPIO5: /* share with DACDAT1 */
3604 regmap_update_bits(rt5682->regmap, RT5682_DMIC_CTRL_1,
3605 RT5682_DMIC_1_DP_MASK, RT5682_DMIC_1_DP_GPIO5);
3606 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
3607 RT5682_GP5_PIN_MASK, RT5682_GP5_PIN_DMIC_SDA);
3611 dev_warn(&i2c->dev, "invalid DMIC_DAT pin\n");
3615 switch (rt5682->pdata.dmic1_clk_pin) {
3616 case RT5682_DMIC1_CLK_GPIO1: /* share with IRQ */
3617 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
3618 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_DMIC_CLK);
3621 case RT5682_DMIC1_CLK_GPIO3: /* share with BCLK2 */
3622 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
3623 RT5682_GP3_PIN_MASK, RT5682_GP3_PIN_DMIC_CLK);
3627 dev_warn(&i2c->dev, "invalid DMIC_CLK pin\n");
3632 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
3633 RT5682_LDO1_DVO_MASK | RT5682_HP_DRIVER_MASK,
3634 RT5682_LDO1_DVO_12 | RT5682_HP_DRIVER_5X);
3635 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0380);
3636 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
3637 RT5682_GP4_PIN_MASK | RT5682_GP5_PIN_MASK,
3638 RT5682_GP4_PIN_ADCDAT1 | RT5682_GP5_PIN_DACDAT1);
3639 regmap_write(rt5682->regmap, RT5682_TEST_MODE_CTRL_1, 0x0000);
3640 regmap_update_bits(rt5682->regmap, RT5682_BIAS_CUR_CTRL_8,
3641 RT5682_HPA_CP_BIAS_CTRL_MASK, RT5682_HPA_CP_BIAS_3UA);
3642 regmap_update_bits(rt5682->regmap, RT5682_CHARGE_PUMP_1,
3643 RT5682_CP_CLK_HP_MASK, RT5682_CP_CLK_HP_300KHZ);
3644 regmap_update_bits(rt5682->regmap, RT5682_HP_CHARGE_PUMP_1,
3645 RT5682_PM_HP_MASK, RT5682_PM_HP_HV);
3647 INIT_DELAYED_WORK(&rt5682->jack_detect_work,
3648 rt5682_jack_detect_handler);
3649 INIT_DELAYED_WORK(&rt5682->jd_check_work,
3650 rt5682_jd_check_handler);
3654 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
3655 rt5682_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
3656 | IRQF_ONESHOT, "rt5682", rt5682);
3658 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
3662 return devm_snd_soc_register_component(&i2c->dev,
3663 &soc_component_dev_rt5682,
3664 rt5682_dai, ARRAY_SIZE(rt5682_dai));
3667 static void rt5682_i2c_shutdown(struct i2c_client *client)
3669 struct rt5682_priv *rt5682 = i2c_get_clientdata(client);
3671 rt5682_reset(rt5682);
3675 static const struct of_device_id rt5682_of_match[] = {
3676 {.compatible = "realtek,rt5682i"},
3679 MODULE_DEVICE_TABLE(of, rt5682_of_match);
3683 static const struct acpi_device_id rt5682_acpi_match[] = {
3687 MODULE_DEVICE_TABLE(acpi, rt5682_acpi_match);
3690 static struct i2c_driver rt5682_i2c_driver = {
3693 .of_match_table = of_match_ptr(rt5682_of_match),
3694 .acpi_match_table = ACPI_PTR(rt5682_acpi_match),
3696 .probe = rt5682_i2c_probe,
3697 .shutdown = rt5682_i2c_shutdown,
3698 .id_table = rt5682_i2c_id,
3700 module_i2c_driver(rt5682_i2c_driver);
3702 MODULE_DESCRIPTION("ASoC RT5682 driver");
3703 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3704 MODULE_LICENSE("GPL v2");