2 * rt5668.h -- RT5668/RT5658 ALSA SoC audio driver
4 * Copyright 2018 Realtek Microelectronics
5 * Author: Bard Liao <bardliao@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
15 #include <sound/rt5668.h>
17 #define DEVICE_ID 0x6530
20 #define RT5668_RESET 0x0000
21 #define RT5668_VERSION_ID 0x00fd
22 #define RT5668_VENDOR_ID 0x00fe
23 #define RT5668_DEVICE_ID 0x00ff
25 #define RT5668_HP_CTRL_1 0x0002
26 #define RT5668_HP_CTRL_2 0x0003
27 #define RT5668_HPL_GAIN 0x0005
28 #define RT5668_HPR_GAIN 0x0006
30 #define RT5668_I2C_CTRL 0x0008
33 #define RT5668_CBJ_BST_CTRL 0x000b
34 #define RT5668_CBJ_CTRL_1 0x0010
35 #define RT5668_CBJ_CTRL_2 0x0011
36 #define RT5668_CBJ_CTRL_3 0x0012
37 #define RT5668_CBJ_CTRL_4 0x0013
38 #define RT5668_CBJ_CTRL_5 0x0014
39 #define RT5668_CBJ_CTRL_6 0x0015
40 #define RT5668_CBJ_CTRL_7 0x0016
41 /* I/O - ADC/DAC/DMIC */
42 #define RT5668_DAC1_DIG_VOL 0x0019
43 #define RT5668_STO1_ADC_DIG_VOL 0x001c
44 #define RT5668_STO1_ADC_BOOST 0x001f
45 #define RT5668_HP_IMP_GAIN_1 0x0022
46 #define RT5668_HP_IMP_GAIN_2 0x0023
48 #define RT5668_SIDETONE_CTRL 0x0024
49 #define RT5668_STO1_ADC_MIXER 0x0026
50 #define RT5668_AD_DA_MIXER 0x0029
51 #define RT5668_STO1_DAC_MIXER 0x002a
52 #define RT5668_A_DAC1_MUX 0x002b
53 #define RT5668_DIG_INF2_DATA 0x0030
55 #define RT5668_REC_MIXER 0x003c
56 #define RT5668_CAL_REC 0x0044
57 #define RT5668_ALC_BACK_GAIN 0x0049
59 #define RT5668_PWR_DIG_1 0x0061
60 #define RT5668_PWR_DIG_2 0x0062
61 #define RT5668_PWR_ANLG_1 0x0063
62 #define RT5668_PWR_ANLG_2 0x0064
63 #define RT5668_PWR_ANLG_3 0x0065
64 #define RT5668_PWR_MIXER 0x0066
65 #define RT5668_PWR_VOL 0x0067
67 #define RT5668_CLK_DET 0x006b
68 /* Filter Auto Reset */
69 #define RT5668_RESET_LPF_CTRL 0x006c
70 #define RT5668_RESET_HPF_CTRL 0x006d
72 #define RT5668_DMIC_CTRL_1 0x006e
73 /* Format - ADC/DAC */
74 #define RT5668_I2S1_SDP 0x0070
75 #define RT5668_I2S2_SDP 0x0071
76 #define RT5668_ADDA_CLK_1 0x0073
77 #define RT5668_ADDA_CLK_2 0x0074
78 #define RT5668_I2S1_F_DIV_CTRL_1 0x0075
79 #define RT5668_I2S1_F_DIV_CTRL_2 0x0076
80 /* Format - TDM Control */
81 #define RT5668_TDM_CTRL 0x0079
82 #define RT5668_TDM_ADDA_CTRL_1 0x007a
83 #define RT5668_TDM_ADDA_CTRL_2 0x007b
84 #define RT5668_DATA_SEL_CTRL_1 0x007c
85 #define RT5668_TDM_TCON_CTRL 0x007e
86 /* Function - Analog */
87 #define RT5668_GLB_CLK 0x0080
88 #define RT5668_PLL_CTRL_1 0x0081
89 #define RT5668_PLL_CTRL_2 0x0082
90 #define RT5668_PLL_TRACK_1 0x0083
91 #define RT5668_PLL_TRACK_2 0x0084
92 #define RT5668_PLL_TRACK_3 0x0085
93 #define RT5668_PLL_TRACK_4 0x0086
94 #define RT5668_PLL_TRACK_5 0x0087
95 #define RT5668_PLL_TRACK_6 0x0088
96 #define RT5668_PLL_TRACK_11 0x008c
97 #define RT5668_SDW_REF_CLK 0x008d
98 #define RT5668_DEPOP_1 0x008e
99 #define RT5668_DEPOP_2 0x008f
100 #define RT5668_HP_CHARGE_PUMP_1 0x0091
101 #define RT5668_HP_CHARGE_PUMP_2 0x0092
102 #define RT5668_MICBIAS_1 0x0093
103 #define RT5668_MICBIAS_2 0x0094
104 #define RT5668_PLL_TRACK_12 0x0098
105 #define RT5668_PLL_TRACK_14 0x009a
106 #define RT5668_PLL2_CTRL_1 0x009b
107 #define RT5668_PLL2_CTRL_2 0x009c
108 #define RT5668_PLL2_CTRL_3 0x009d
109 #define RT5668_PLL2_CTRL_4 0x009e
110 #define RT5668_RC_CLK_CTRL 0x009f
111 #define RT5668_I2S_M_CLK_CTRL_1 0x00a0
112 #define RT5668_I2S2_F_DIV_CTRL_1 0x00a3
113 #define RT5668_I2S2_F_DIV_CTRL_2 0x00a4
114 /* Function - Digital */
115 #define RT5668_EQ_CTRL_1 0x00ae
116 #define RT5668_EQ_CTRL_2 0x00af
117 #define RT5668_IRQ_CTRL_1 0x00b6
118 #define RT5668_IRQ_CTRL_2 0x00b7
119 #define RT5668_IRQ_CTRL_3 0x00b8
120 #define RT5668_IRQ_CTRL_4 0x00b9
121 #define RT5668_INT_ST_1 0x00be
122 #define RT5668_GPIO_CTRL_1 0x00c0
123 #define RT5668_GPIO_CTRL_2 0x00c1
124 #define RT5668_GPIO_CTRL_3 0x00c2
125 #define RT5668_HP_AMP_DET_CTRL_1 0x00d0
126 #define RT5668_HP_AMP_DET_CTRL_2 0x00d1
127 #define RT5668_MID_HP_AMP_DET 0x00d2
128 #define RT5668_LOW_HP_AMP_DET 0x00d3
129 #define RT5668_DELAY_BUF_CTRL 0x00d4
130 #define RT5668_SV_ZCD_1 0x00d9
131 #define RT5668_SV_ZCD_2 0x00da
132 #define RT5668_IL_CMD_1 0x00db
133 #define RT5668_IL_CMD_2 0x00dc
134 #define RT5668_IL_CMD_3 0x00dd
135 #define RT5668_IL_CMD_4 0x00de
136 #define RT5668_IL_CMD_5 0x00df
137 #define RT5668_IL_CMD_6 0x00e0
138 #define RT5668_4BTN_IL_CMD_1 0x00e2
139 #define RT5668_4BTN_IL_CMD_2 0x00e3
140 #define RT5668_4BTN_IL_CMD_3 0x00e4
141 #define RT5668_4BTN_IL_CMD_4 0x00e5
142 #define RT5668_4BTN_IL_CMD_5 0x00e6
143 #define RT5668_4BTN_IL_CMD_6 0x00e7
144 #define RT5668_4BTN_IL_CMD_7 0x00e8
146 #define RT5668_ADC_STO1_HP_CTRL_1 0x00ea
147 #define RT5668_ADC_STO1_HP_CTRL_2 0x00eb
148 #define RT5668_AJD1_CTRL 0x00f0
149 #define RT5668_JD1_THD 0x00f1
150 #define RT5668_JD2_THD 0x00f2
151 #define RT5668_JD_CTRL_1 0x00f6
152 /* General Control */
153 #define RT5668_DUMMY_1 0x00fa
154 #define RT5668_DUMMY_2 0x00fb
155 #define RT5668_DUMMY_3 0x00fc
157 #define RT5668_DAC_ADC_DIG_VOL1 0x0100
158 #define RT5668_BIAS_CUR_CTRL_2 0x010b
159 #define RT5668_BIAS_CUR_CTRL_3 0x010c
160 #define RT5668_BIAS_CUR_CTRL_4 0x010d
161 #define RT5668_BIAS_CUR_CTRL_5 0x010e
162 #define RT5668_BIAS_CUR_CTRL_6 0x010f
163 #define RT5668_BIAS_CUR_CTRL_7 0x0110
164 #define RT5668_BIAS_CUR_CTRL_8 0x0111
165 #define RT5668_BIAS_CUR_CTRL_9 0x0112
166 #define RT5668_BIAS_CUR_CTRL_10 0x0113
167 #define RT5668_VREF_REC_OP_FB_CAP_CTRL 0x0117
168 #define RT5668_CHARGE_PUMP_1 0x0125
169 #define RT5668_DIG_IN_CTRL_1 0x0132
170 #define RT5668_PAD_DRIVING_CTRL 0x0136
171 #define RT5668_SOFT_RAMP_DEPOP 0x0138
172 #define RT5668_CHOP_DAC 0x013a
173 #define RT5668_CHOP_ADC 0x013b
174 #define RT5668_CALIB_ADC_CTRL 0x013c
175 #define RT5668_VOL_TEST 0x013f
176 #define RT5668_SPKVDD_DET_STA 0x0142
177 #define RT5668_TEST_MODE_CTRL_1 0x0145
178 #define RT5668_TEST_MODE_CTRL_2 0x0146
179 #define RT5668_TEST_MODE_CTRL_3 0x0147
180 #define RT5668_TEST_MODE_CTRL_4 0x0148
181 #define RT5668_TEST_MODE_CTRL_5 0x0149
182 #define RT5668_PLL1_INTERNAL 0x0150
183 #define RT5668_PLL2_INTERNAL 0x0151
184 #define RT5668_STO_NG2_CTRL_1 0x0160
185 #define RT5668_STO_NG2_CTRL_2 0x0161
186 #define RT5668_STO_NG2_CTRL_3 0x0162
187 #define RT5668_STO_NG2_CTRL_4 0x0163
188 #define RT5668_STO_NG2_CTRL_5 0x0164
189 #define RT5668_STO_NG2_CTRL_6 0x0165
190 #define RT5668_STO_NG2_CTRL_7 0x0166
191 #define RT5668_STO_NG2_CTRL_8 0x0167
192 #define RT5668_STO_NG2_CTRL_9 0x0168
193 #define RT5668_STO_NG2_CTRL_10 0x0169
194 #define RT5668_STO1_DAC_SIL_DET 0x0190
195 #define RT5668_SIL_PSV_CTRL1 0x0194
196 #define RT5668_SIL_PSV_CTRL2 0x0195
197 #define RT5668_SIL_PSV_CTRL3 0x0197
198 #define RT5668_SIL_PSV_CTRL4 0x0198
199 #define RT5668_SIL_PSV_CTRL5 0x0199
200 #define RT5668_HP_IMP_SENS_CTRL_01 0x01af
201 #define RT5668_HP_IMP_SENS_CTRL_02 0x01b0
202 #define RT5668_HP_IMP_SENS_CTRL_03 0x01b1
203 #define RT5668_HP_IMP_SENS_CTRL_04 0x01b2
204 #define RT5668_HP_IMP_SENS_CTRL_05 0x01b3
205 #define RT5668_HP_IMP_SENS_CTRL_06 0x01b4
206 #define RT5668_HP_IMP_SENS_CTRL_07 0x01b5
207 #define RT5668_HP_IMP_SENS_CTRL_08 0x01b6
208 #define RT5668_HP_IMP_SENS_CTRL_09 0x01b7
209 #define RT5668_HP_IMP_SENS_CTRL_10 0x01b8
210 #define RT5668_HP_IMP_SENS_CTRL_11 0x01b9
211 #define RT5668_HP_IMP_SENS_CTRL_12 0x01ba
212 #define RT5668_HP_IMP_SENS_CTRL_13 0x01bb
213 #define RT5668_HP_IMP_SENS_CTRL_14 0x01bc
214 #define RT5668_HP_IMP_SENS_CTRL_15 0x01bd
215 #define RT5668_HP_IMP_SENS_CTRL_16 0x01be
216 #define RT5668_HP_IMP_SENS_CTRL_17 0x01bf
217 #define RT5668_HP_IMP_SENS_CTRL_18 0x01c0
218 #define RT5668_HP_IMP_SENS_CTRL_19 0x01c1
219 #define RT5668_HP_IMP_SENS_CTRL_20 0x01c2
220 #define RT5668_HP_IMP_SENS_CTRL_21 0x01c3
221 #define RT5668_HP_IMP_SENS_CTRL_22 0x01c4
222 #define RT5668_HP_IMP_SENS_CTRL_23 0x01c5
223 #define RT5668_HP_IMP_SENS_CTRL_24 0x01c6
224 #define RT5668_HP_IMP_SENS_CTRL_25 0x01c7
225 #define RT5668_HP_IMP_SENS_CTRL_26 0x01c8
226 #define RT5668_HP_IMP_SENS_CTRL_27 0x01c9
227 #define RT5668_HP_IMP_SENS_CTRL_28 0x01ca
228 #define RT5668_HP_IMP_SENS_CTRL_29 0x01cb
229 #define RT5668_HP_IMP_SENS_CTRL_30 0x01cc
230 #define RT5668_HP_IMP_SENS_CTRL_31 0x01cd
231 #define RT5668_HP_IMP_SENS_CTRL_32 0x01ce
232 #define RT5668_HP_IMP_SENS_CTRL_33 0x01cf
233 #define RT5668_HP_IMP_SENS_CTRL_34 0x01d0
234 #define RT5668_HP_IMP_SENS_CTRL_35 0x01d1
235 #define RT5668_HP_IMP_SENS_CTRL_36 0x01d2
236 #define RT5668_HP_IMP_SENS_CTRL_37 0x01d3
237 #define RT5668_HP_IMP_SENS_CTRL_38 0x01d4
238 #define RT5668_HP_IMP_SENS_CTRL_39 0x01d5
239 #define RT5668_HP_IMP_SENS_CTRL_40 0x01d6
240 #define RT5668_HP_IMP_SENS_CTRL_41 0x01d7
241 #define RT5668_HP_IMP_SENS_CTRL_42 0x01d8
242 #define RT5668_HP_IMP_SENS_CTRL_43 0x01d9
243 #define RT5668_HP_LOGIC_CTRL_1 0x01da
244 #define RT5668_HP_LOGIC_CTRL_2 0x01db
245 #define RT5668_HP_LOGIC_CTRL_3 0x01dc
246 #define RT5668_HP_CALIB_CTRL_1 0x01de
247 #define RT5668_HP_CALIB_CTRL_2 0x01df
248 #define RT5668_HP_CALIB_CTRL_3 0x01e0
249 #define RT5668_HP_CALIB_CTRL_4 0x01e1
250 #define RT5668_HP_CALIB_CTRL_5 0x01e2
251 #define RT5668_HP_CALIB_CTRL_6 0x01e3
252 #define RT5668_HP_CALIB_CTRL_7 0x01e4
253 #define RT5668_HP_CALIB_CTRL_9 0x01e6
254 #define RT5668_HP_CALIB_CTRL_10 0x01e7
255 #define RT5668_HP_CALIB_CTRL_11 0x01e8
256 #define RT5668_HP_CALIB_STA_1 0x01ea
257 #define RT5668_HP_CALIB_STA_2 0x01eb
258 #define RT5668_HP_CALIB_STA_3 0x01ec
259 #define RT5668_HP_CALIB_STA_4 0x01ed
260 #define RT5668_HP_CALIB_STA_5 0x01ee
261 #define RT5668_HP_CALIB_STA_6 0x01ef
262 #define RT5668_HP_CALIB_STA_7 0x01f0
263 #define RT5668_HP_CALIB_STA_8 0x01f1
264 #define RT5668_HP_CALIB_STA_9 0x01f2
265 #define RT5668_HP_CALIB_STA_10 0x01f3
266 #define RT5668_HP_CALIB_STA_11 0x01f4
267 #define RT5668_SAR_IL_CMD_1 0x0210
268 #define RT5668_SAR_IL_CMD_2 0x0211
269 #define RT5668_SAR_IL_CMD_3 0x0212
270 #define RT5668_SAR_IL_CMD_4 0x0213
271 #define RT5668_SAR_IL_CMD_5 0x0214
272 #define RT5668_SAR_IL_CMD_6 0x0215
273 #define RT5668_SAR_IL_CMD_7 0x0216
274 #define RT5668_SAR_IL_CMD_8 0x0217
275 #define RT5668_SAR_IL_CMD_9 0x0218
276 #define RT5668_SAR_IL_CMD_10 0x0219
277 #define RT5668_SAR_IL_CMD_11 0x021a
278 #define RT5668_SAR_IL_CMD_12 0x021b
279 #define RT5668_SAR_IL_CMD_13 0x021c
280 #define RT5668_EFUSE_CTRL_1 0x0250
281 #define RT5668_EFUSE_CTRL_2 0x0251
282 #define RT5668_EFUSE_CTRL_3 0x0252
283 #define RT5668_EFUSE_CTRL_4 0x0253
284 #define RT5668_EFUSE_CTRL_5 0x0254
285 #define RT5668_EFUSE_CTRL_6 0x0255
286 #define RT5668_EFUSE_CTRL_7 0x0256
287 #define RT5668_EFUSE_CTRL_8 0x0257
288 #define RT5668_EFUSE_CTRL_9 0x0258
289 #define RT5668_EFUSE_CTRL_10 0x0259
290 #define RT5668_EFUSE_CTRL_11 0x025a
291 #define RT5668_JD_TOP_VC_VTRL 0x0270
292 #define RT5668_DRC1_CTRL_0 0x02ff
293 #define RT5668_DRC1_CTRL_1 0x0300
294 #define RT5668_DRC1_CTRL_2 0x0301
295 #define RT5668_DRC1_CTRL_3 0x0302
296 #define RT5668_DRC1_CTRL_4 0x0303
297 #define RT5668_DRC1_CTRL_5 0x0304
298 #define RT5668_DRC1_CTRL_6 0x0305
299 #define RT5668_DRC1_HARD_LMT_CTRL_1 0x0306
300 #define RT5668_DRC1_HARD_LMT_CTRL_2 0x0307
301 #define RT5668_DRC1_PRIV_1 0x0310
302 #define RT5668_DRC1_PRIV_2 0x0311
303 #define RT5668_DRC1_PRIV_3 0x0312
304 #define RT5668_DRC1_PRIV_4 0x0313
305 #define RT5668_DRC1_PRIV_5 0x0314
306 #define RT5668_DRC1_PRIV_6 0x0315
307 #define RT5668_DRC1_PRIV_7 0x0316
308 #define RT5668_DRC1_PRIV_8 0x0317
309 #define RT5668_EQ_AUTO_RCV_CTRL1 0x03c0
310 #define RT5668_EQ_AUTO_RCV_CTRL2 0x03c1
311 #define RT5668_EQ_AUTO_RCV_CTRL3 0x03c2
312 #define RT5668_EQ_AUTO_RCV_CTRL4 0x03c3
313 #define RT5668_EQ_AUTO_RCV_CTRL5 0x03c4
314 #define RT5668_EQ_AUTO_RCV_CTRL6 0x03c5
315 #define RT5668_EQ_AUTO_RCV_CTRL7 0x03c6
316 #define RT5668_EQ_AUTO_RCV_CTRL8 0x03c7
317 #define RT5668_EQ_AUTO_RCV_CTRL9 0x03c8
318 #define RT5668_EQ_AUTO_RCV_CTRL10 0x03c9
319 #define RT5668_EQ_AUTO_RCV_CTRL11 0x03ca
320 #define RT5668_EQ_AUTO_RCV_CTRL12 0x03cb
321 #define RT5668_EQ_AUTO_RCV_CTRL13 0x03cc
322 #define RT5668_ADC_L_EQ_LPF1_A1 0x03d0
323 #define RT5668_R_EQ_LPF1_A1 0x03d1
324 #define RT5668_L_EQ_LPF1_H0 0x03d2
325 #define RT5668_R_EQ_LPF1_H0 0x03d3
326 #define RT5668_L_EQ_BPF1_A1 0x03d4
327 #define RT5668_R_EQ_BPF1_A1 0x03d5
328 #define RT5668_L_EQ_BPF1_A2 0x03d6
329 #define RT5668_R_EQ_BPF1_A2 0x03d7
330 #define RT5668_L_EQ_BPF1_H0 0x03d8
331 #define RT5668_R_EQ_BPF1_H0 0x03d9
332 #define RT5668_L_EQ_BPF2_A1 0x03da
333 #define RT5668_R_EQ_BPF2_A1 0x03db
334 #define RT5668_L_EQ_BPF2_A2 0x03dc
335 #define RT5668_R_EQ_BPF2_A2 0x03dd
336 #define RT5668_L_EQ_BPF2_H0 0x03de
337 #define RT5668_R_EQ_BPF2_H0 0x03df
338 #define RT5668_L_EQ_BPF3_A1 0x03e0
339 #define RT5668_R_EQ_BPF3_A1 0x03e1
340 #define RT5668_L_EQ_BPF3_A2 0x03e2
341 #define RT5668_R_EQ_BPF3_A2 0x03e3
342 #define RT5668_L_EQ_BPF3_H0 0x03e4
343 #define RT5668_R_EQ_BPF3_H0 0x03e5
344 #define RT5668_L_EQ_BPF4_A1 0x03e6
345 #define RT5668_R_EQ_BPF4_A1 0x03e7
346 #define RT5668_L_EQ_BPF4_A2 0x03e8
347 #define RT5668_R_EQ_BPF4_A2 0x03e9
348 #define RT5668_L_EQ_BPF4_H0 0x03ea
349 #define RT5668_R_EQ_BPF4_H0 0x03eb
350 #define RT5668_L_EQ_HPF1_A1 0x03ec
351 #define RT5668_R_EQ_HPF1_A1 0x03ed
352 #define RT5668_L_EQ_HPF1_H0 0x03ee
353 #define RT5668_R_EQ_HPF1_H0 0x03ef
354 #define RT5668_L_EQ_PRE_VOL 0x03f0
355 #define RT5668_R_EQ_PRE_VOL 0x03f1
356 #define RT5668_L_EQ_POST_VOL 0x03f2
357 #define RT5668_R_EQ_POST_VOL 0x03f3
358 #define RT5668_I2C_MODE 0xffff
361 /* global definition */
362 #define RT5668_L_MUTE (0x1 << 15)
363 #define RT5668_L_MUTE_SFT 15
364 #define RT5668_VOL_L_MUTE (0x1 << 14)
365 #define RT5668_VOL_L_SFT 14
366 #define RT5668_R_MUTE (0x1 << 7)
367 #define RT5668_R_MUTE_SFT 7
368 #define RT5668_VOL_R_MUTE (0x1 << 6)
369 #define RT5668_VOL_R_SFT 6
370 #define RT5668_L_VOL_MASK (0x3f << 8)
371 #define RT5668_L_VOL_SFT 8
372 #define RT5668_R_VOL_MASK (0x3f)
373 #define RT5668_R_VOL_SFT 0
375 /*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
376 #define RT5668_G_HP (0xf << 8)
377 #define RT5668_G_HP_SFT 8
378 #define RT5668_G_STO_DA_DMIX (0xf)
379 #define RT5668_G_STO_DA_SFT 0
381 /* CBJ Control (0x000b) */
382 #define RT5668_BST_CBJ_MASK (0xf << 8)
383 #define RT5668_BST_CBJ_SFT 8
385 /* Embeeded Jack and Type Detection Control 1 (0x0010) */
386 #define RT5668_EMB_JD_EN (0x1 << 15)
387 #define RT5668_EMB_JD_EN_SFT 15
388 #define RT5668_EMB_JD_RST (0x1 << 14)
389 #define RT5668_JD_MODE (0x1 << 13)
390 #define RT5668_JD_MODE_SFT 13
391 #define RT5668_DET_TYPE (0x1 << 12)
392 #define RT5668_DET_TYPE_SFT 12
393 #define RT5668_POLA_EXT_JD_MASK (0x1 << 11)
394 #define RT5668_POLA_EXT_JD_LOW (0x1 << 11)
395 #define RT5668_POLA_EXT_JD_HIGH (0x0 << 11)
396 #define RT5668_EXT_JD_DIG (0x1 << 9)
397 #define RT5668_POL_FAST_OFF_MASK (0x1 << 8)
398 #define RT5668_POL_FAST_OFF_HIGH (0x1 << 8)
399 #define RT5668_POL_FAST_OFF_LOW (0x0 << 8)
400 #define RT5668_FAST_OFF_MASK (0x1 << 7)
401 #define RT5668_FAST_OFF_EN (0x1 << 7)
402 #define RT5668_FAST_OFF_DIS (0x0 << 7)
403 #define RT5668_VREF_POW_MASK (0x1 << 6)
404 #define RT5668_VREF_POW_FSM (0x0 << 6)
405 #define RT5668_VREF_POW_REG (0x1 << 6)
406 #define RT5668_MB1_PATH_MASK (0x1 << 5)
407 #define RT5668_CTRL_MB1_REG (0x1 << 5)
408 #define RT5668_CTRL_MB1_FSM (0x0 << 5)
409 #define RT5668_MB2_PATH_MASK (0x1 << 4)
410 #define RT5668_CTRL_MB2_REG (0x1 << 4)
411 #define RT5668_CTRL_MB2_FSM (0x0 << 4)
412 #define RT5668_TRIG_JD_MASK (0x1 << 3)
413 #define RT5668_TRIG_JD_HIGH (0x1 << 3)
414 #define RT5668_TRIG_JD_LOW (0x0 << 3)
415 #define RT5668_MIC_CAP_MASK (0x1 << 1)
416 #define RT5668_MIC_CAP_HS (0x1 << 1)
417 #define RT5668_MIC_CAP_HP (0x0 << 1)
418 #define RT5668_MIC_CAP_SRC_MASK (0x1)
419 #define RT5668_MIC_CAP_SRC_REG (0x1)
420 #define RT5668_MIC_CAP_SRC_ANA (0x0)
422 /* Embeeded Jack and Type Detection Control 2 (0x0011) */
423 #define RT5668_EXT_JD_SRC (0x7 << 4)
424 #define RT5668_EXT_JD_SRC_SFT 4
425 #define RT5668_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)
426 #define RT5668_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)
427 #define RT5668_EXT_JD_SRC_JDH (0x2 << 4)
428 #define RT5668_EXT_JD_SRC_JDL (0x3 << 4)
429 #define RT5668_EXT_JD_SRC_MANUAL (0x4 << 4)
430 #define RT5668_JACK_TYPE_MASK (0x3)
432 /* Combo Jack and Type Detection Control 3 (0x0012) */
433 #define RT5668_CBJ_IN_BUF_EN (0x1 << 7)
435 /* Combo Jack and Type Detection Control 4 (0x0013) */
436 #define RT5668_SEL_SHT_MID_TON_MASK (0x3 << 12)
437 #define RT5668_SEL_SHT_MID_TON_2 (0x0 << 12)
438 #define RT5668_SEL_SHT_MID_TON_3 (0x1 << 12)
439 #define RT5668_CBJ_JD_TEST_MASK (0x1 << 6)
440 #define RT5668_CBJ_JD_TEST_NORM (0x0 << 6)
441 #define RT5668_CBJ_JD_TEST_MODE (0x1 << 6)
443 /* DAC1 Digital Volume (0x0019) */
444 #define RT5668_DAC_L1_VOL_MASK (0xff << 8)
445 #define RT5668_DAC_L1_VOL_SFT 8
446 #define RT5668_DAC_R1_VOL_MASK (0xff)
447 #define RT5668_DAC_R1_VOL_SFT 0
449 /* ADC Digital Volume Control (0x001c) */
450 #define RT5668_ADC_L_VOL_MASK (0x7f << 8)
451 #define RT5668_ADC_L_VOL_SFT 8
452 #define RT5668_ADC_R_VOL_MASK (0x7f)
453 #define RT5668_ADC_R_VOL_SFT 0
455 /* Stereo1 ADC Boost Gain Control (0x001f) */
456 #define RT5668_STO1_ADC_L_BST_MASK (0x3 << 14)
457 #define RT5668_STO1_ADC_L_BST_SFT 14
458 #define RT5668_STO1_ADC_R_BST_MASK (0x3 << 12)
459 #define RT5668_STO1_ADC_R_BST_SFT 12
461 /* Sidetone Control (0x0024) */
462 #define RT5668_ST_SRC_SEL (0x1 << 8)
463 #define RT5668_ST_SRC_SFT 8
464 #define RT5668_ST_EN_MASK (0x1 << 6)
465 #define RT5668_ST_DIS (0x0 << 6)
466 #define RT5668_ST_EN (0x1 << 6)
467 #define RT5668_ST_EN_SFT 6
469 /* Stereo1 ADC Mixer Control (0x0026) */
470 #define RT5668_M_STO1_ADC_L1 (0x1 << 15)
471 #define RT5668_M_STO1_ADC_L1_SFT 15
472 #define RT5668_M_STO1_ADC_L2 (0x1 << 14)
473 #define RT5668_M_STO1_ADC_L2_SFT 14
474 #define RT5668_STO1_ADC1L_SRC_MASK (0x1 << 13)
475 #define RT5668_STO1_ADC1L_SRC_SFT 13
476 #define RT5668_STO1_ADC1_SRC_ADC (0x1 << 13)
477 #define RT5668_STO1_ADC1_SRC_DACMIX (0x0 << 13)
478 #define RT5668_STO1_ADC2L_SRC_MASK (0x1 << 12)
479 #define RT5668_STO1_ADC2L_SRC_SFT 12
480 #define RT5668_STO1_ADCL_SRC_MASK (0x3 << 10)
481 #define RT5668_STO1_ADCL_SRC_SFT 10
482 #define RT5668_STO1_DD_L_SRC_MASK (0x1 << 9)
483 #define RT5668_STO1_DD_L_SRC_SFT 9
484 #define RT5668_STO1_DMIC_SRC_MASK (0x1 << 8)
485 #define RT5668_STO1_DMIC_SRC_SFT 8
486 #define RT5668_STO1_DMIC_SRC_DMIC2 (0x1 << 8)
487 #define RT5668_STO1_DMIC_SRC_DMIC1 (0x0 << 8)
488 #define RT5668_M_STO1_ADC_R1 (0x1 << 7)
489 #define RT5668_M_STO1_ADC_R1_SFT 7
490 #define RT5668_M_STO1_ADC_R2 (0x1 << 6)
491 #define RT5668_M_STO1_ADC_R2_SFT 6
492 #define RT5668_STO1_ADC1R_SRC_MASK (0x1 << 5)
493 #define RT5668_STO1_ADC1R_SRC_SFT 5
494 #define RT5668_STO1_ADC2R_SRC_MASK (0x1 << 4)
495 #define RT5668_STO1_ADC2R_SRC_SFT 4
496 #define RT5668_STO1_ADCR_SRC_MASK (0x3 << 2)
497 #define RT5668_STO1_ADCR_SRC_SFT 2
499 /* ADC Mixer to DAC Mixer Control (0x0029) */
500 #define RT5668_M_ADCMIX_L (0x1 << 15)
501 #define RT5668_M_ADCMIX_L_SFT 15
502 #define RT5668_M_DAC1_L (0x1 << 14)
503 #define RT5668_M_DAC1_L_SFT 14
504 #define RT5668_DAC1_R_SEL_MASK (0x1 << 10)
505 #define RT5668_DAC1_R_SEL_SFT 10
506 #define RT5668_DAC1_L_SEL_MASK (0x1 << 8)
507 #define RT5668_DAC1_L_SEL_SFT 8
508 #define RT5668_M_ADCMIX_R (0x1 << 7)
509 #define RT5668_M_ADCMIX_R_SFT 7
510 #define RT5668_M_DAC1_R (0x1 << 6)
511 #define RT5668_M_DAC1_R_SFT 6
513 /* Stereo1 DAC Mixer Control (0x002a) */
514 #define RT5668_M_DAC_L1_STO_L (0x1 << 15)
515 #define RT5668_M_DAC_L1_STO_L_SFT 15
516 #define RT5668_G_DAC_L1_STO_L_MASK (0x1 << 14)
517 #define RT5668_G_DAC_L1_STO_L_SFT 14
518 #define RT5668_M_DAC_R1_STO_L (0x1 << 13)
519 #define RT5668_M_DAC_R1_STO_L_SFT 13
520 #define RT5668_G_DAC_R1_STO_L_MASK (0x1 << 12)
521 #define RT5668_G_DAC_R1_STO_L_SFT 12
522 #define RT5668_M_DAC_L1_STO_R (0x1 << 7)
523 #define RT5668_M_DAC_L1_STO_R_SFT 7
524 #define RT5668_G_DAC_L1_STO_R_MASK (0x1 << 6)
525 #define RT5668_G_DAC_L1_STO_R_SFT 6
526 #define RT5668_M_DAC_R1_STO_R (0x1 << 5)
527 #define RT5668_M_DAC_R1_STO_R_SFT 5
528 #define RT5668_G_DAC_R1_STO_R_MASK (0x1 << 4)
529 #define RT5668_G_DAC_R1_STO_R_SFT 4
531 /* Analog DAC1 Input Source Control (0x002b) */
532 #define RT5668_M_ST_STO_L (0x1 << 9)
533 #define RT5668_M_ST_STO_L_SFT 9
534 #define RT5668_M_ST_STO_R (0x1 << 8)
535 #define RT5668_M_ST_STO_R_SFT 8
536 #define RT5668_DAC_L1_SRC_MASK (0x3 << 4)
537 #define RT5668_A_DACL1_SFT 4
538 #define RT5668_DAC_R1_SRC_MASK (0x3)
539 #define RT5668_A_DACR1_SFT 0
541 /* Digital Interface Data Control (0x0030) */
542 #define RT5668_IF2_ADC_SEL_MASK (0x3 << 0)
543 #define RT5668_IF2_ADC_SEL_SFT 0
545 /* REC Left Mixer Control 2 (0x003c) */
546 #define RT5668_G_CBJ_RM1_L (0x7 << 10)
547 #define RT5668_G_CBJ_RM1_L_SFT 10
548 #define RT5668_M_CBJ_RM1_L (0x1 << 7)
549 #define RT5668_M_CBJ_RM1_L_SFT 7
551 /* Power Management for Digital 1 (0x0061) */
552 #define RT5668_PWR_I2S1 (0x1 << 15)
553 #define RT5668_PWR_I2S1_BIT 15
554 #define RT5668_PWR_I2S2 (0x1 << 14)
555 #define RT5668_PWR_I2S2_BIT 14
556 #define RT5668_PWR_DAC_L1 (0x1 << 11)
557 #define RT5668_PWR_DAC_L1_BIT 11
558 #define RT5668_PWR_DAC_R1 (0x1 << 10)
559 #define RT5668_PWR_DAC_R1_BIT 10
560 #define RT5668_PWR_LDO (0x1 << 8)
561 #define RT5668_PWR_LDO_BIT 8
562 #define RT5668_PWR_ADC_L1 (0x1 << 4)
563 #define RT5668_PWR_ADC_L1_BIT 4
564 #define RT5668_PWR_ADC_R1 (0x1 << 3)
565 #define RT5668_PWR_ADC_R1_BIT 3
566 #define RT5668_DIG_GATE_CTRL (0x1 << 0)
567 #define RT5668_DIG_GATE_CTRL_SFT 0
570 /* Power Management for Digital 2 (0x0062) */
571 #define RT5668_PWR_ADC_S1F (0x1 << 15)
572 #define RT5668_PWR_ADC_S1F_BIT 15
573 #define RT5668_PWR_DAC_S1F (0x1 << 10)
574 #define RT5668_PWR_DAC_S1F_BIT 10
576 /* Power Management for Analog 1 (0x0063) */
577 #define RT5668_PWR_VREF1 (0x1 << 15)
578 #define RT5668_PWR_VREF1_BIT 15
579 #define RT5668_PWR_FV1 (0x1 << 14)
580 #define RT5668_PWR_FV1_BIT 14
581 #define RT5668_PWR_VREF2 (0x1 << 13)
582 #define RT5668_PWR_VREF2_BIT 13
583 #define RT5668_PWR_FV2 (0x1 << 12)
584 #define RT5668_PWR_FV2_BIT 12
585 #define RT5668_LDO1_DBG_MASK (0x3 << 10)
586 #define RT5668_PWR_MB (0x1 << 9)
587 #define RT5668_PWR_MB_BIT 9
588 #define RT5668_PWR_BG (0x1 << 7)
589 #define RT5668_PWR_BG_BIT 7
590 #define RT5668_LDO1_BYPASS_MASK (0x1 << 6)
591 #define RT5668_LDO1_BYPASS (0x1 << 6)
592 #define RT5668_LDO1_NOT_BYPASS (0x0 << 6)
593 #define RT5668_PWR_MA_BIT 6
594 #define RT5668_LDO1_DVO_MASK (0x3 << 4)
595 #define RT5668_LDO1_DVO_09 (0x0 << 4)
596 #define RT5668_LDO1_DVO_10 (0x1 << 4)
597 #define RT5668_LDO1_DVO_12 (0x2 << 4)
598 #define RT5668_LDO1_DVO_14 (0x3 << 4)
599 #define RT5668_HP_DRIVER_MASK (0x3 << 2)
600 #define RT5668_HP_DRIVER_1X (0x0 << 2)
601 #define RT5668_HP_DRIVER_3X (0x1 << 2)
602 #define RT5668_HP_DRIVER_5X (0x3 << 2)
603 #define RT5668_PWR_HA_L (0x1 << 1)
604 #define RT5668_PWR_HA_L_BIT 1
605 #define RT5668_PWR_HA_R (0x1 << 0)
606 #define RT5668_PWR_HA_R_BIT 0
608 /* Power Management for Analog 2 (0x0064) */
609 #define RT5668_PWR_MB1 (0x1 << 11)
610 #define RT5668_PWR_MB1_PWR_DOWN (0x0 << 11)
611 #define RT5668_PWR_MB1_BIT 11
612 #define RT5668_PWR_MB2 (0x1 << 10)
613 #define RT5668_PWR_MB2_PWR_DOWN (0x0 << 10)
614 #define RT5668_PWR_MB2_BIT 10
615 #define RT5668_PWR_JDH (0x1 << 3)
616 #define RT5668_PWR_JDH_BIT 3
617 #define RT5668_PWR_JDL (0x1 << 2)
618 #define RT5668_PWR_JDL_BIT 2
619 #define RT5668_PWR_RM1_L (0x1 << 1)
620 #define RT5668_PWR_RM1_L_BIT 1
622 /* Power Management for Analog 3 (0x0065) */
623 #define RT5668_PWR_CBJ (0x1 << 9)
624 #define RT5668_PWR_CBJ_BIT 9
625 #define RT5668_PWR_PLL (0x1 << 6)
626 #define RT5668_PWR_PLL_BIT 6
627 #define RT5668_PWR_PLL2B (0x1 << 5)
628 #define RT5668_PWR_PLL2B_BIT 5
629 #define RT5668_PWR_PLL2F (0x1 << 4)
630 #define RT5668_PWR_PLL2F_BIT 4
631 #define RT5668_PWR_LDO2 (0x1 << 2)
632 #define RT5668_PWR_LDO2_BIT 2
633 #define RT5668_PWR_DET_SPKVDD (0x1 << 1)
634 #define RT5668_PWR_DET_SPKVDD_BIT 1
636 /* Power Management for Mixer (0x0066) */
637 #define RT5668_PWR_STO1_DAC_L (0x1 << 5)
638 #define RT5668_PWR_STO1_DAC_L_BIT 5
639 #define RT5668_PWR_STO1_DAC_R (0x1 << 4)
640 #define RT5668_PWR_STO1_DAC_R_BIT 4
642 /* MCLK and System Clock Detection Control (0x006b) */
643 #define RT5668_SYS_CLK_DET (0x1 << 15)
644 #define RT5668_SYS_CLK_DET_SFT 15
645 #define RT5668_PLL1_CLK_DET (0x1 << 14)
646 #define RT5668_PLL1_CLK_DET_SFT 14
647 #define RT5668_PLL2_CLK_DET (0x1 << 13)
648 #define RT5668_PLL2_CLK_DET_SFT 13
649 #define RT5668_POW_CLK_DET2_SFT 8
650 #define RT5668_POW_CLK_DET_SFT 0
652 /* Digital Microphone Control 1 (0x006e) */
653 #define RT5668_DMIC_1_EN_MASK (0x1 << 15)
654 #define RT5668_DMIC_1_EN_SFT 15
655 #define RT5668_DMIC_1_DIS (0x0 << 15)
656 #define RT5668_DMIC_1_EN (0x1 << 15)
657 #define RT5668_DMIC_1_DP_MASK (0x3 << 4)
658 #define RT5668_DMIC_1_DP_SFT 4
659 #define RT5668_DMIC_1_DP_GPIO2 (0x0 << 4)
660 #define RT5668_DMIC_1_DP_GPIO5 (0x1 << 4)
661 #define RT5668_DMIC_CLK_MASK (0xf << 0)
662 #define RT5668_DMIC_CLK_SFT 0
664 /* I2S1 Audio Serial Data Port Control (0x0070) */
665 #define RT5668_SEL_ADCDAT_MASK (0x1 << 15)
666 #define RT5668_SEL_ADCDAT_OUT (0x0 << 15)
667 #define RT5668_SEL_ADCDAT_IN (0x1 << 15)
668 #define RT5668_SEL_ADCDAT_SFT 15
669 #define RT5668_I2S1_TX_CHL_MASK (0x7 << 12)
670 #define RT5668_I2S1_TX_CHL_SFT 12
671 #define RT5668_I2S1_TX_CHL_16 (0x0 << 12)
672 #define RT5668_I2S1_TX_CHL_20 (0x1 << 12)
673 #define RT5668_I2S1_TX_CHL_24 (0x2 << 12)
674 #define RT5668_I2S1_TX_CHL_32 (0x3 << 12)
675 #define RT5668_I2S1_TX_CHL_8 (0x4 << 12)
676 #define RT5668_I2S1_RX_CHL_MASK (0x7 << 8)
677 #define RT5668_I2S1_RX_CHL_SFT 8
678 #define RT5668_I2S1_RX_CHL_16 (0x0 << 8)
679 #define RT5668_I2S1_RX_CHL_20 (0x1 << 8)
680 #define RT5668_I2S1_RX_CHL_24 (0x2 << 8)
681 #define RT5668_I2S1_RX_CHL_32 (0x3 << 8)
682 #define RT5668_I2S1_RX_CHL_8 (0x4 << 8)
683 #define RT5668_I2S1_MONO_MASK (0x1 << 7)
684 #define RT5668_I2S1_MONO_EN (0x1 << 7)
685 #define RT5668_I2S1_MONO_DIS (0x0 << 7)
686 #define RT5668_I2S2_MONO_MASK (0x1 << 6)
687 #define RT5668_I2S2_MONO_EN (0x1 << 6)
688 #define RT5668_I2S2_MONO_DIS (0x0 << 6)
689 #define RT5668_I2S1_DL_MASK (0x7 << 4)
690 #define RT5668_I2S1_DL_SFT 4
691 #define RT5668_I2S1_DL_16 (0x0 << 4)
692 #define RT5668_I2S1_DL_20 (0x1 << 4)
693 #define RT5668_I2S1_DL_24 (0x2 << 4)
694 #define RT5668_I2S1_DL_32 (0x3 << 4)
695 #define RT5668_I2S1_DL_8 (0x4 << 4)
697 /* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */
698 #define RT5668_I2S2_MS_MASK (0x1 << 15)
699 #define RT5668_I2S2_MS_SFT 15
700 #define RT5668_I2S2_MS_M (0x0 << 15)
701 #define RT5668_I2S2_MS_S (0x1 << 15)
702 #define RT5668_I2S2_PIN_CFG_MASK (0x1 << 14)
703 #define RT5668_I2S2_PIN_CFG_SFT 14
704 #define RT5668_I2S2_CLK_SEL_MASK (0x1 << 11)
705 #define RT5668_I2S2_CLK_SEL_SFT 11
706 #define RT5668_I2S2_OUT_MASK (0x1 << 9)
707 #define RT5668_I2S2_OUT_SFT 9
708 #define RT5668_I2S2_OUT_UM (0x0 << 9)
709 #define RT5668_I2S2_OUT_M (0x1 << 9)
710 #define RT5668_I2S_BP_MASK (0x1 << 8)
711 #define RT5668_I2S_BP_SFT 8
712 #define RT5668_I2S_BP_NOR (0x0 << 8)
713 #define RT5668_I2S_BP_INV (0x1 << 8)
714 #define RT5668_I2S2_MONO_EN (0x1 << 6)
715 #define RT5668_I2S2_MONO_DIS (0x0 << 6)
716 #define RT5668_I2S2_DL_MASK (0x3 << 4)
717 #define RT5668_I2S2_DL_SFT 4
718 #define RT5668_I2S2_DL_16 (0x0 << 4)
719 #define RT5668_I2S2_DL_20 (0x1 << 4)
720 #define RT5668_I2S2_DL_24 (0x2 << 4)
721 #define RT5668_I2S2_DL_8 (0x3 << 4)
722 #define RT5668_I2S_DF_MASK (0x7)
723 #define RT5668_I2S_DF_SFT 0
724 #define RT5668_I2S_DF_I2S (0x0)
725 #define RT5668_I2S_DF_LEFT (0x1)
726 #define RT5668_I2S_DF_PCM_A (0x2)
727 #define RT5668_I2S_DF_PCM_B (0x3)
728 #define RT5668_I2S_DF_PCM_A_N (0x6)
729 #define RT5668_I2S_DF_PCM_B_N (0x7)
731 /* ADC/DAC Clock Control 1 (0x0073) */
732 #define RT5668_ADC_OSR_MASK (0xf << 12)
733 #define RT5668_ADC_OSR_SFT 12
734 #define RT5668_ADC_OSR_D_1 (0x0 << 12)
735 #define RT5668_ADC_OSR_D_2 (0x1 << 12)
736 #define RT5668_ADC_OSR_D_4 (0x2 << 12)
737 #define RT5668_ADC_OSR_D_6 (0x3 << 12)
738 #define RT5668_ADC_OSR_D_8 (0x4 << 12)
739 #define RT5668_ADC_OSR_D_12 (0x5 << 12)
740 #define RT5668_ADC_OSR_D_16 (0x6 << 12)
741 #define RT5668_ADC_OSR_D_24 (0x7 << 12)
742 #define RT5668_ADC_OSR_D_32 (0x8 << 12)
743 #define RT5668_ADC_OSR_D_48 (0x9 << 12)
744 #define RT5668_I2S_M_DIV_MASK (0xf << 12)
745 #define RT5668_I2S_M_DIV_SFT 8
746 #define RT5668_I2S_M_D_1 (0x0 << 8)
747 #define RT5668_I2S_M_D_2 (0x1 << 8)
748 #define RT5668_I2S_M_D_3 (0x2 << 8)
749 #define RT5668_I2S_M_D_4 (0x3 << 8)
750 #define RT5668_I2S_M_D_6 (0x4 << 8)
751 #define RT5668_I2S_M_D_8 (0x5 << 8)
752 #define RT5668_I2S_M_D_12 (0x6 << 8)
753 #define RT5668_I2S_M_D_16 (0x7 << 8)
754 #define RT5668_I2S_M_D_24 (0x8 << 8)
755 #define RT5668_I2S_M_D_32 (0x9 << 8)
756 #define RT5668_I2S_M_D_48 (0x10 << 8)
757 #define RT5668_I2S_CLK_SRC_MASK (0x7 << 4)
758 #define RT5668_I2S_CLK_SRC_SFT 4
759 #define RT5668_I2S_CLK_SRC_MCLK (0x0 << 4)
760 #define RT5668_I2S_CLK_SRC_PLL1 (0x1 << 4)
761 #define RT5668_I2S_CLK_SRC_PLL2 (0x2 << 4)
762 #define RT5668_I2S_CLK_SRC_SDW (0x3 << 4)
763 #define RT5668_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */
764 #define RT5668_DAC_OSR_MASK (0xf << 0)
765 #define RT5668_DAC_OSR_SFT 0
766 #define RT5668_DAC_OSR_D_1 (0x0 << 0)
767 #define RT5668_DAC_OSR_D_2 (0x1 << 0)
768 #define RT5668_DAC_OSR_D_4 (0x2 << 0)
769 #define RT5668_DAC_OSR_D_6 (0x3 << 0)
770 #define RT5668_DAC_OSR_D_8 (0x4 << 0)
771 #define RT5668_DAC_OSR_D_12 (0x5 << 0)
772 #define RT5668_DAC_OSR_D_16 (0x6 << 0)
773 #define RT5668_DAC_OSR_D_24 (0x7 << 0)
774 #define RT5668_DAC_OSR_D_32 (0x8 << 0)
775 #define RT5668_DAC_OSR_D_48 (0x9 << 0)
777 /* ADC/DAC Clock Control 2 (0x0074) */
778 #define RT5668_I2S2_BCLK_MS2_MASK (0x1 << 11)
779 #define RT5668_I2S2_BCLK_MS2_SFT 11
780 #define RT5668_I2S2_BCLK_MS2_32 (0x0 << 11)
781 #define RT5668_I2S2_BCLK_MS2_64 (0x1 << 11)
784 /* TDM control 1 (0x0079) */
785 #define RT5668_TDM_TX_CH_MASK (0x3 << 12)
786 #define RT5668_TDM_TX_CH_2 (0x0 << 12)
787 #define RT5668_TDM_TX_CH_4 (0x1 << 12)
788 #define RT5668_TDM_TX_CH_6 (0x2 << 12)
789 #define RT5668_TDM_TX_CH_8 (0x3 << 12)
790 #define RT5668_TDM_RX_CH_MASK (0x3 << 8)
791 #define RT5668_TDM_RX_CH_2 (0x0 << 8)
792 #define RT5668_TDM_RX_CH_4 (0x1 << 8)
793 #define RT5668_TDM_RX_CH_6 (0x2 << 8)
794 #define RT5668_TDM_RX_CH_8 (0x3 << 8)
795 #define RT5668_TDM_ADC_LCA_MASK (0xf << 4)
796 #define RT5668_TDM_ADC_LCA_SFT 4
797 #define RT5668_TDM_ADC_DL_SFT 0
799 /* TDM control 3 (0x007a) */
800 #define RT5668_IF1_ADC1_SEL_SFT 14
801 #define RT5668_IF1_ADC2_SEL_SFT 12
802 #define RT5668_IF1_ADC3_SEL_SFT 10
803 #define RT5668_IF1_ADC4_SEL_SFT 8
804 #define RT5668_TDM_ADC_SEL_SFT 4
806 /* TDM/I2S control (0x007e) */
807 #define RT5668_TDM_S_BP_MASK (0x1 << 15)
808 #define RT5668_TDM_S_BP_SFT 15
809 #define RT5668_TDM_S_BP_NOR (0x0 << 15)
810 #define RT5668_TDM_S_BP_INV (0x1 << 15)
811 #define RT5668_TDM_S_LP_MASK (0x1 << 14)
812 #define RT5668_TDM_S_LP_SFT 14
813 #define RT5668_TDM_S_LP_NOR (0x0 << 14)
814 #define RT5668_TDM_S_LP_INV (0x1 << 14)
815 #define RT5668_TDM_DF_MASK (0x7 << 11)
816 #define RT5668_TDM_DF_SFT 11
817 #define RT5668_TDM_DF_I2S (0x0 << 11)
818 #define RT5668_TDM_DF_LEFT (0x1 << 11)
819 #define RT5668_TDM_DF_PCM_A (0x2 << 11)
820 #define RT5668_TDM_DF_PCM_B (0x3 << 11)
821 #define RT5668_TDM_DF_PCM_A_N (0x6 << 11)
822 #define RT5668_TDM_DF_PCM_B_N (0x7 << 11)
823 #define RT5668_TDM_CL_MASK (0x3 << 4)
824 #define RT5668_TDM_CL_16 (0x0 << 4)
825 #define RT5668_TDM_CL_20 (0x1 << 4)
826 #define RT5668_TDM_CL_24 (0x2 << 4)
827 #define RT5668_TDM_CL_32 (0x3 << 4)
828 #define RT5668_TDM_M_BP_MASK (0x1 << 2)
829 #define RT5668_TDM_M_BP_SFT 2
830 #define RT5668_TDM_M_BP_NOR (0x0 << 2)
831 #define RT5668_TDM_M_BP_INV (0x1 << 2)
832 #define RT5668_TDM_M_LP_MASK (0x1 << 1)
833 #define RT5668_TDM_M_LP_SFT 1
834 #define RT5668_TDM_M_LP_NOR (0x0 << 1)
835 #define RT5668_TDM_M_LP_INV (0x1 << 1)
836 #define RT5668_TDM_MS_MASK (0x1 << 0)
837 #define RT5668_TDM_MS_SFT 0
838 #define RT5668_TDM_MS_M (0x0 << 0)
839 #define RT5668_TDM_MS_S (0x1 << 0)
841 /* Global Clock Control (0x0080) */
842 #define RT5668_SCLK_SRC_MASK (0x7 << 13)
843 #define RT5668_SCLK_SRC_SFT 13
844 #define RT5668_SCLK_SRC_MCLK (0x0 << 13)
845 #define RT5668_SCLK_SRC_PLL1 (0x1 << 13)
846 #define RT5668_SCLK_SRC_PLL2 (0x2 << 13)
847 #define RT5668_SCLK_SRC_SDW (0x3 << 13)
848 #define RT5668_SCLK_SRC_RCCLK (0x4 << 13)
849 #define RT5668_PLL1_SRC_MASK (0x3 << 10)
850 #define RT5668_PLL1_SRC_SFT 10
851 #define RT5668_PLL1_SRC_MCLK (0x0 << 10)
852 #define RT5668_PLL1_SRC_BCLK1 (0x1 << 10)
853 #define RT5668_PLL1_SRC_SDW (0x2 << 10)
854 #define RT5668_PLL1_SRC_RC (0x3 << 10)
855 #define RT5668_PLL2_SRC_MASK (0x3 << 8)
856 #define RT5668_PLL2_SRC_SFT 8
857 #define RT5668_PLL2_SRC_MCLK (0x0 << 8)
858 #define RT5668_PLL2_SRC_BCLK1 (0x1 << 8)
859 #define RT5668_PLL2_SRC_SDW (0x2 << 8)
860 #define RT5668_PLL2_SRC_RC (0x3 << 8)
864 #define RT5668_PLL_INP_MAX 40000000
865 #define RT5668_PLL_INP_MIN 256000
866 /* PLL M/N/K Code Control 1 (0x0081) */
867 #define RT5668_PLL_N_MAX 0x001ff
868 #define RT5668_PLL_N_MASK (RT5668_PLL_N_MAX << 7)
869 #define RT5668_PLL_N_SFT 7
870 #define RT5668_PLL_K_MAX 0x001f
871 #define RT5668_PLL_K_MASK (RT5668_PLL_K_MAX)
872 #define RT5668_PLL_K_SFT 0
874 /* PLL M/N/K Code Control 2 (0x0082) */
875 #define RT5668_PLL_M_MAX 0x00f
876 #define RT5668_PLL_M_MASK (RT5668_PLL_M_MAX << 12)
877 #define RT5668_PLL_M_SFT 12
878 #define RT5668_PLL_M_BP (0x1 << 11)
879 #define RT5668_PLL_M_BP_SFT 11
880 #define RT5668_PLL_K_BP (0x1 << 10)
881 #define RT5668_PLL_K_BP_SFT 10
883 /* PLL tracking mode 1 (0x0083) */
884 #define RT5668_DA_ASRC_MASK (0x1 << 13)
885 #define RT5668_DA_ASRC_SFT 13
886 #define RT5668_DAC_STO1_ASRC_MASK (0x1 << 12)
887 #define RT5668_DAC_STO1_ASRC_SFT 12
888 #define RT5668_AD_ASRC_MASK (0x1 << 8)
889 #define RT5668_AD_ASRC_SFT 8
890 #define RT5668_AD_ASRC_SEL_MASK (0x1 << 4)
891 #define RT5668_AD_ASRC_SEL_SFT 4
892 #define RT5668_DMIC_ASRC_MASK (0x1 << 3)
893 #define RT5668_DMIC_ASRC_SFT 3
894 #define RT5668_ADC_STO1_ASRC_MASK (0x1 << 2)
895 #define RT5668_ADC_STO1_ASRC_SFT 2
896 #define RT5668_DA_ASRC_SEL_MASK (0x1 << 0)
897 #define RT5668_DA_ASRC_SEL_SFT 0
899 /* PLL tracking mode 2 3 (0x0084)(0x0085)*/
900 #define RT5668_FILTER_CLK_SEL_MASK (0x7 << 12)
901 #define RT5668_FILTER_CLK_SEL_SFT 12
903 /* ASRC Control 4 (0x0086) */
904 #define RT5668_ASRCIN_FTK_N1_MASK (0x3 << 14)
905 #define RT5668_ASRCIN_FTK_N1_SFT 14
906 #define RT5668_ASRCIN_FTK_N2_MASK (0x3 << 12)
907 #define RT5668_ASRCIN_FTK_N2_SFT 12
908 #define RT5668_ASRCIN_FTK_M1_MASK (0x7 << 8)
909 #define RT5668_ASRCIN_FTK_M1_SFT 8
910 #define RT5668_ASRCIN_FTK_M2_MASK (0x7 << 4)
911 #define RT5668_ASRCIN_FTK_M2_SFT 4
913 /* SoundWire reference clk (0x008d) */
914 #define RT5668_PLL2_OUT_MASK (0x1 << 8)
915 #define RT5668_PLL2_OUT_98M (0x0 << 8)
916 #define RT5668_PLL2_OUT_49M (0x1 << 8)
917 #define RT5668_SDW_REF_2_MASK (0xf << 4)
918 #define RT5668_SDW_REF_2_SFT 4
919 #define RT5668_SDW_REF_2_48K (0x0 << 4)
920 #define RT5668_SDW_REF_2_96K (0x1 << 4)
921 #define RT5668_SDW_REF_2_192K (0x2 << 4)
922 #define RT5668_SDW_REF_2_32K (0x3 << 4)
923 #define RT5668_SDW_REF_2_24K (0x4 << 4)
924 #define RT5668_SDW_REF_2_16K (0x5 << 4)
925 #define RT5668_SDW_REF_2_12K (0x6 << 4)
926 #define RT5668_SDW_REF_2_8K (0x7 << 4)
927 #define RT5668_SDW_REF_2_44K (0x8 << 4)
928 #define RT5668_SDW_REF_2_88K (0x9 << 4)
929 #define RT5668_SDW_REF_2_176K (0xa << 4)
930 #define RT5668_SDW_REF_2_353K (0xb << 4)
931 #define RT5668_SDW_REF_2_22K (0xc << 4)
932 #define RT5668_SDW_REF_2_384K (0xd << 4)
933 #define RT5668_SDW_REF_2_11K (0xe << 4)
934 #define RT5668_SDW_REF_1_MASK (0xf << 0)
935 #define RT5668_SDW_REF_1_SFT 0
936 #define RT5668_SDW_REF_1_48K (0x0 << 0)
937 #define RT5668_SDW_REF_1_96K (0x1 << 0)
938 #define RT5668_SDW_REF_1_192K (0x2 << 0)
939 #define RT5668_SDW_REF_1_32K (0x3 << 0)
940 #define RT5668_SDW_REF_1_24K (0x4 << 0)
941 #define RT5668_SDW_REF_1_16K (0x5 << 0)
942 #define RT5668_SDW_REF_1_12K (0x6 << 0)
943 #define RT5668_SDW_REF_1_8K (0x7 << 0)
944 #define RT5668_SDW_REF_1_44K (0x8 << 0)
945 #define RT5668_SDW_REF_1_88K (0x9 << 0)
946 #define RT5668_SDW_REF_1_176K (0xa << 0)
947 #define RT5668_SDW_REF_1_353K (0xb << 0)
948 #define RT5668_SDW_REF_1_22K (0xc << 0)
949 #define RT5668_SDW_REF_1_384K (0xd << 0)
950 #define RT5668_SDW_REF_1_11K (0xe << 0)
952 /* Depop Mode Control 1 (0x008e) */
953 #define RT5668_PUMP_EN (0x1 << 3)
954 #define RT5668_PUMP_EN_SFT 3
955 #define RT5668_CAPLESS_EN (0x1 << 0)
956 #define RT5668_CAPLESS_EN_SFT 0
958 /* Depop Mode Control 2 (0x8f) */
959 #define RT5668_RAMP_MASK (0x1 << 12)
960 #define RT5668_RAMP_SFT 12
961 #define RT5668_RAMP_DIS (0x0 << 12)
962 #define RT5668_RAMP_EN (0x1 << 12)
963 #define RT5668_BPS_MASK (0x1 << 11)
964 #define RT5668_BPS_SFT 11
965 #define RT5668_BPS_DIS (0x0 << 11)
966 #define RT5668_BPS_EN (0x1 << 11)
967 #define RT5668_FAST_UPDN_MASK (0x1 << 10)
968 #define RT5668_FAST_UPDN_SFT 10
969 #define RT5668_FAST_UPDN_DIS (0x0 << 10)
970 #define RT5668_FAST_UPDN_EN (0x1 << 10)
971 #define RT5668_VLO_MASK (0x1 << 7)
972 #define RT5668_VLO_SFT 7
973 #define RT5668_VLO_3V (0x0 << 7)
974 #define RT5668_VLO_33V (0x1 << 7)
976 /* HPOUT charge pump 1 (0x0091) */
977 #define RT5668_OSW_L_MASK (0x1 << 11)
978 #define RT5668_OSW_L_SFT 11
979 #define RT5668_OSW_L_DIS (0x0 << 11)
980 #define RT5668_OSW_L_EN (0x1 << 11)
981 #define RT5668_OSW_R_MASK (0x1 << 10)
982 #define RT5668_OSW_R_SFT 10
983 #define RT5668_OSW_R_DIS (0x0 << 10)
984 #define RT5668_OSW_R_EN (0x1 << 10)
985 #define RT5668_PM_HP_MASK (0x3 << 8)
986 #define RT5668_PM_HP_SFT 8
987 #define RT5668_PM_HP_LV (0x0 << 8)
988 #define RT5668_PM_HP_MV (0x1 << 8)
989 #define RT5668_PM_HP_HV (0x2 << 8)
990 #define RT5668_IB_HP_MASK (0x3 << 6)
991 #define RT5668_IB_HP_SFT 6
992 #define RT5668_IB_HP_125IL (0x0 << 6)
993 #define RT5668_IB_HP_25IL (0x1 << 6)
994 #define RT5668_IB_HP_5IL (0x2 << 6)
995 #define RT5668_IB_HP_1IL (0x3 << 6)
997 /* Micbias Control1 (0x93) */
998 #define RT5668_MIC1_OV_MASK (0x3 << 14)
999 #define RT5668_MIC1_OV_SFT 14
1000 #define RT5668_MIC1_OV_2V7 (0x0 << 14)
1001 #define RT5668_MIC1_OV_2V4 (0x1 << 14)
1002 #define RT5668_MIC1_OV_2V25 (0x3 << 14)
1003 #define RT5668_MIC1_OV_1V8 (0x4 << 14)
1004 #define RT5668_MIC1_CLK_MASK (0x1 << 13)
1005 #define RT5668_MIC1_CLK_SFT 13
1006 #define RT5668_MIC1_CLK_DIS (0x0 << 13)
1007 #define RT5668_MIC1_CLK_EN (0x1 << 13)
1008 #define RT5668_MIC1_OVCD_MASK (0x1 << 12)
1009 #define RT5668_MIC1_OVCD_SFT 12
1010 #define RT5668_MIC1_OVCD_DIS (0x0 << 12)
1011 #define RT5668_MIC1_OVCD_EN (0x1 << 12)
1012 #define RT5668_MIC1_OVTH_MASK (0x3 << 10)
1013 #define RT5668_MIC1_OVTH_SFT 10
1014 #define RT5668_MIC1_OVTH_768UA (0x0 << 10)
1015 #define RT5668_MIC1_OVTH_960UA (0x1 << 10)
1016 #define RT5668_MIC1_OVTH_1152UA (0x2 << 10)
1017 #define RT5668_MIC1_OVTH_1960UA (0x3 << 10)
1018 #define RT5668_MIC2_OV_MASK (0x3 << 8)
1019 #define RT5668_MIC2_OV_SFT 8
1020 #define RT5668_MIC2_OV_2V7 (0x0 << 8)
1021 #define RT5668_MIC2_OV_2V4 (0x1 << 8)
1022 #define RT5668_MIC2_OV_2V25 (0x3 << 8)
1023 #define RT5668_MIC2_OV_1V8 (0x4 << 8)
1024 #define RT5668_MIC2_CLK_MASK (0x1 << 7)
1025 #define RT5668_MIC2_CLK_SFT 7
1026 #define RT5668_MIC2_CLK_DIS (0x0 << 7)
1027 #define RT5668_MIC2_CLK_EN (0x1 << 7)
1028 #define RT5668_MIC2_OVTH_MASK (0x3 << 4)
1029 #define RT5668_MIC2_OVTH_SFT 4
1030 #define RT5668_MIC2_OVTH_768UA (0x0 << 4)
1031 #define RT5668_MIC2_OVTH_960UA (0x1 << 4)
1032 #define RT5668_MIC2_OVTH_1152UA (0x2 << 4)
1033 #define RT5668_MIC2_OVTH_1960UA (0x3 << 4)
1034 #define RT5668_PWR_MB_MASK (0x1 << 3)
1035 #define RT5668_PWR_MB_SFT 3
1036 #define RT5668_PWR_MB_PD (0x0 << 3)
1037 #define RT5668_PWR_MB_PU (0x1 << 3)
1039 /* Micbias Control2 (0x0094) */
1040 #define RT5668_PWR_CLK25M_MASK (0x1 << 9)
1041 #define RT5668_PWR_CLK25M_SFT 9
1042 #define RT5668_PWR_CLK25M_PD (0x0 << 9)
1043 #define RT5668_PWR_CLK25M_PU (0x1 << 9)
1044 #define RT5668_PWR_CLK1M_MASK (0x1 << 8)
1045 #define RT5668_PWR_CLK1M_SFT 8
1046 #define RT5668_PWR_CLK1M_PD (0x0 << 8)
1047 #define RT5668_PWR_CLK1M_PU (0x1 << 8)
1049 /* RC Clock Control (0x009f) */
1050 #define RT5668_POW_IRQ (0x1 << 15)
1051 #define RT5668_POW_JDH (0x1 << 14)
1052 #define RT5668_POW_JDL (0x1 << 13)
1053 #define RT5668_POW_ANA (0x1 << 12)
1055 /* I2S Master Mode Clock Control 1 (0x00a0) */
1056 #define RT5668_CLK_SRC_MCLK (0x0)
1057 #define RT5668_CLK_SRC_PLL1 (0x1)
1058 #define RT5668_CLK_SRC_PLL2 (0x2)
1059 #define RT5668_CLK_SRC_SDW (0x3)
1060 #define RT5668_CLK_SRC_RCCLK (0x4)
1061 #define RT5668_I2S_PD_1 (0x0)
1062 #define RT5668_I2S_PD_2 (0x1)
1063 #define RT5668_I2S_PD_3 (0x2)
1064 #define RT5668_I2S_PD_4 (0x3)
1065 #define RT5668_I2S_PD_6 (0x4)
1066 #define RT5668_I2S_PD_8 (0x5)
1067 #define RT5668_I2S_PD_12 (0x6)
1068 #define RT5668_I2S_PD_16 (0x7)
1069 #define RT5668_I2S_PD_24 (0x8)
1070 #define RT5668_I2S_PD_32 (0x9)
1071 #define RT5668_I2S_PD_48 (0xa)
1072 #define RT5668_I2S2_SRC_MASK (0x3 << 4)
1073 #define RT5668_I2S2_SRC_SFT 4
1074 #define RT5668_I2S2_M_PD_MASK (0xf << 0)
1075 #define RT5668_I2S2_M_PD_SFT 0
1077 /* IRQ Control 1 (0x00b6) */
1078 #define RT5668_JD1_PULSE_EN_MASK (0x1 << 10)
1079 #define RT5668_JD1_PULSE_EN_SFT 10
1080 #define RT5668_JD1_PULSE_DIS (0x0 << 10)
1081 #define RT5668_JD1_PULSE_EN (0x1 << 10)
1083 /* IRQ Control 2 (0x00b7) */
1084 #define RT5668_JD1_EN_MASK (0x1 << 15)
1085 #define RT5668_JD1_EN_SFT 15
1086 #define RT5668_JD1_DIS (0x0 << 15)
1087 #define RT5668_JD1_EN (0x1 << 15)
1088 #define RT5668_JD1_POL_MASK (0x1 << 13)
1089 #define RT5668_JD1_POL_NOR (0x0 << 13)
1090 #define RT5668_JD1_POL_INV (0x1 << 13)
1092 /* IRQ Control 3 (0x00b8) */
1093 #define RT5668_IL_IRQ_MASK (0x1 << 7)
1094 #define RT5668_IL_IRQ_DIS (0x0 << 7)
1095 #define RT5668_IL_IRQ_EN (0x1 << 7)
1097 /* GPIO Control 1 (0x00c0) */
1098 #define RT5668_GP1_PIN_MASK (0x3 << 14)
1099 #define RT5668_GP1_PIN_SFT 14
1100 #define RT5668_GP1_PIN_GPIO1 (0x0 << 14)
1101 #define RT5668_GP1_PIN_IRQ (0x1 << 14)
1102 #define RT5668_GP1_PIN_DMIC_CLK (0x2 << 14)
1103 #define RT5668_GP2_PIN_MASK (0x3 << 12)
1104 #define RT5668_GP2_PIN_SFT 12
1105 #define RT5668_GP2_PIN_GPIO2 (0x0 << 12)
1106 #define RT5668_GP2_PIN_LRCK2 (0x1 << 12)
1107 #define RT5668_GP2_PIN_DMIC_SDA (0x2 << 12)
1108 #define RT5668_GP3_PIN_MASK (0x3 << 10)
1109 #define RT5668_GP3_PIN_SFT 10
1110 #define RT5668_GP3_PIN_GPIO3 (0x0 << 10)
1111 #define RT5668_GP3_PIN_BCLK2 (0x1 << 10)
1112 #define RT5668_GP3_PIN_DMIC_CLK (0x2 << 10)
1113 #define RT5668_GP4_PIN_MASK (0x3 << 8)
1114 #define RT5668_GP4_PIN_SFT 8
1115 #define RT5668_GP4_PIN_GPIO4 (0x0 << 8)
1116 #define RT5668_GP4_PIN_ADCDAT1 (0x1 << 8)
1117 #define RT5668_GP4_PIN_DMIC_CLK (0x2 << 8)
1118 #define RT5668_GP4_PIN_ADCDAT2 (0x3 << 8)
1119 #define RT5668_GP5_PIN_MASK (0x3 << 6)
1120 #define RT5668_GP5_PIN_SFT 6
1121 #define RT5668_GP5_PIN_GPIO5 (0x0 << 6)
1122 #define RT5668_GP5_PIN_DACDAT1 (0x1 << 6)
1123 #define RT5668_GP5_PIN_DMIC_SDA (0x2 << 6)
1124 #define RT5668_GP6_PIN_MASK (0x1 << 5)
1125 #define RT5668_GP6_PIN_SFT 5
1126 #define RT5668_GP6_PIN_GPIO6 (0x0 << 5)
1127 #define RT5668_GP6_PIN_LRCK1 (0x1 << 5)
1129 /* GPIO Control 2 (0x00c1)*/
1130 #define RT5668_GP1_PF_MASK (0x1 << 15)
1131 #define RT5668_GP1_PF_IN (0x0 << 15)
1132 #define RT5668_GP1_PF_OUT (0x1 << 15)
1133 #define RT5668_GP1_OUT_MASK (0x1 << 14)
1134 #define RT5668_GP1_OUT_L (0x0 << 14)
1135 #define RT5668_GP1_OUT_H (0x1 << 14)
1136 #define RT5668_GP2_PF_MASK (0x1 << 13)
1137 #define RT5668_GP2_PF_IN (0x0 << 13)
1138 #define RT5668_GP2_PF_OUT (0x1 << 13)
1139 #define RT5668_GP2_OUT_MASK (0x1 << 12)
1140 #define RT5668_GP2_OUT_L (0x0 << 12)
1141 #define RT5668_GP2_OUT_H (0x1 << 12)
1142 #define RT5668_GP3_PF_MASK (0x1 << 11)
1143 #define RT5668_GP3_PF_IN (0x0 << 11)
1144 #define RT5668_GP3_PF_OUT (0x1 << 11)
1145 #define RT5668_GP3_OUT_MASK (0x1 << 10)
1146 #define RT5668_GP3_OUT_L (0x0 << 10)
1147 #define RT5668_GP3_OUT_H (0x1 << 10)
1148 #define RT5668_GP4_PF_MASK (0x1 << 9)
1149 #define RT5668_GP4_PF_IN (0x0 << 9)
1150 #define RT5668_GP4_PF_OUT (0x1 << 9)
1151 #define RT5668_GP4_OUT_MASK (0x1 << 8)
1152 #define RT5668_GP4_OUT_L (0x0 << 8)
1153 #define RT5668_GP4_OUT_H (0x1 << 8)
1154 #define RT5668_GP5_PF_MASK (0x1 << 7)
1155 #define RT5668_GP5_PF_IN (0x0 << 7)
1156 #define RT5668_GP5_PF_OUT (0x1 << 7)
1157 #define RT5668_GP5_OUT_MASK (0x1 << 6)
1158 #define RT5668_GP5_OUT_L (0x0 << 6)
1159 #define RT5668_GP5_OUT_H (0x1 << 6)
1160 #define RT5668_GP6_PF_MASK (0x1 << 5)
1161 #define RT5668_GP6_PF_IN (0x0 << 5)
1162 #define RT5668_GP6_PF_OUT (0x1 << 5)
1163 #define RT5668_GP6_OUT_MASK (0x1 << 4)
1164 #define RT5668_GP6_OUT_L (0x0 << 4)
1165 #define RT5668_GP6_OUT_H (0x1 << 4)
1168 /* GPIO Status (0x00c2) */
1169 #define RT5668_GP6_STA (0x1 << 6)
1170 #define RT5668_GP5_STA (0x1 << 5)
1171 #define RT5668_GP4_STA (0x1 << 4)
1172 #define RT5668_GP3_STA (0x1 << 3)
1173 #define RT5668_GP2_STA (0x1 << 2)
1174 #define RT5668_GP1_STA (0x1 << 1)
1176 /* Soft volume and zero cross control 1 (0x00d9) */
1177 #define RT5668_SV_MASK (0x1 << 15)
1178 #define RT5668_SV_SFT 15
1179 #define RT5668_SV_DIS (0x0 << 15)
1180 #define RT5668_SV_EN (0x1 << 15)
1181 #define RT5668_ZCD_MASK (0x1 << 10)
1182 #define RT5668_ZCD_SFT 10
1183 #define RT5668_ZCD_PD (0x0 << 10)
1184 #define RT5668_ZCD_PU (0x1 << 10)
1185 #define RT5668_SV_DLY_MASK (0xf)
1186 #define RT5668_SV_DLY_SFT 0
1188 /* Soft volume and zero cross control 2 (0x00da) */
1189 #define RT5668_ZCD_BST1_CBJ_MASK (0x1 << 7)
1190 #define RT5668_ZCD_BST1_CBJ_SFT 7
1191 #define RT5668_ZCD_BST1_CBJ_DIS (0x0 << 7)
1192 #define RT5668_ZCD_BST1_CBJ_EN (0x1 << 7)
1193 #define RT5668_ZCD_RECMIX_MASK (0x1)
1194 #define RT5668_ZCD_RECMIX_SFT 0
1195 #define RT5668_ZCD_RECMIX_DIS (0x0)
1196 #define RT5668_ZCD_RECMIX_EN (0x1)
1198 /* 4 Button Inline Command Control 2 (0x00e3) */
1199 #define RT5668_4BTN_IL_MASK (0x1 << 15)
1200 #define RT5668_4BTN_IL_EN (0x1 << 15)
1201 #define RT5668_4BTN_IL_DIS (0x0 << 15)
1202 #define RT5668_4BTN_IL_RST_MASK (0x1 << 14)
1203 #define RT5668_4BTN_IL_NOR (0x1 << 14)
1204 #define RT5668_4BTN_IL_RST (0x0 << 14)
1206 /* Analog JD Control (0x00f0) */
1207 #define RT5668_JDH_RS_MASK (0x1 << 4)
1208 #define RT5668_JDH_NO_PLUG (0x1 << 4)
1209 #define RT5668_JDH_PLUG (0x0 << 4)
1211 /* Chopper and Clock control for DAC (0x013a)*/
1212 #define RT5668_CKXEN_DAC1_MASK (0x1 << 13)
1213 #define RT5668_CKXEN_DAC1_SFT 13
1214 #define RT5668_CKGEN_DAC1_MASK (0x1 << 12)
1215 #define RT5668_CKGEN_DAC1_SFT 12
1217 /* Chopper and Clock control for ADC (0x013b)*/
1218 #define RT5668_CKXEN_ADC1_MASK (0x1 << 13)
1219 #define RT5668_CKXEN_ADC1_SFT 13
1220 #define RT5668_CKGEN_ADC1_MASK (0x1 << 12)
1221 #define RT5668_CKGEN_ADC1_SFT 12
1223 /* Volume test (0x013f)*/
1224 #define RT5668_SEL_CLK_VOL_MASK (0x1 << 15)
1225 #define RT5668_SEL_CLK_VOL_EN (0x1 << 15)
1226 #define RT5668_SEL_CLK_VOL_DIS (0x0 << 15)
1228 /* Test Mode Control 1 (0x0145) */
1229 #define RT5668_AD2DA_LB_MASK (0x1 << 10)
1230 #define RT5668_AD2DA_LB_SFT 10
1232 /* Stereo Noise Gate Control 1 (0x0160) */
1233 #define RT5668_NG2_EN_MASK (0x1 << 15)
1234 #define RT5668_NG2_EN (0x1 << 15)
1235 #define RT5668_NG2_DIS (0x0 << 15)
1237 /* Stereo1 DAC Silence Detection Control (0x0190) */
1238 #define RT5668_DEB_STO_DAC_MASK (0x7 << 4)
1239 #define RT5668_DEB_80_MS (0x0 << 4)
1241 /* SAR ADC Inline Command Control 1 (0x0210) */
1242 #define RT5668_SAR_BUTT_DET_MASK (0x1 << 15)
1243 #define RT5668_SAR_BUTT_DET_EN (0x1 << 15)
1244 #define RT5668_SAR_BUTT_DET_DIS (0x0 << 15)
1245 #define RT5668_SAR_BUTDET_MODE_MASK (0x1 << 14)
1246 #define RT5668_SAR_BUTDET_POW_SAV (0x1 << 14)
1247 #define RT5668_SAR_BUTDET_POW_NORM (0x0 << 14)
1248 #define RT5668_SAR_BUTDET_RST_MASK (0x1 << 13)
1249 #define RT5668_SAR_BUTDET_RST_NORMAL (0x1 << 13)
1250 #define RT5668_SAR_BUTDET_RST (0x0 << 13)
1251 #define RT5668_SAR_POW_MASK (0x1 << 12)
1252 #define RT5668_SAR_POW_EN (0x1 << 12)
1253 #define RT5668_SAR_POW_DIS (0x0 << 12)
1254 #define RT5668_SAR_RST_MASK (0x1 << 11)
1255 #define RT5668_SAR_RST_NORMAL (0x1 << 11)
1256 #define RT5668_SAR_RST (0x0 << 11)
1257 #define RT5668_SAR_BYPASS_MASK (0x1 << 10)
1258 #define RT5668_SAR_BYPASS_EN (0x1 << 10)
1259 #define RT5668_SAR_BYPASS_DIS (0x0 << 10)
1260 #define RT5668_SAR_SEL_MB1_MASK (0x1 << 9)
1261 #define RT5668_SAR_SEL_MB1_SEL (0x1 << 9)
1262 #define RT5668_SAR_SEL_MB1_NOSEL (0x0 << 9)
1263 #define RT5668_SAR_SEL_MB2_MASK (0x1 << 8)
1264 #define RT5668_SAR_SEL_MB2_SEL (0x1 << 8)
1265 #define RT5668_SAR_SEL_MB2_NOSEL (0x0 << 8)
1266 #define RT5668_SAR_SEL_MODE_MASK (0x1 << 7)
1267 #define RT5668_SAR_SEL_MODE_CMP (0x1 << 7)
1268 #define RT5668_SAR_SEL_MODE_ADC (0x0 << 7)
1269 #define RT5668_SAR_SEL_MB1_MB2_MASK (0x1 << 5)
1270 #define RT5668_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)
1271 #define RT5668_SAR_SEL_MB1_MB2_MANU (0x0 << 5)
1272 #define RT5668_SAR_SEL_SIGNAL_MASK (0x1 << 4)
1273 #define RT5668_SAR_SEL_SIGNAL_AUTO (0x1 << 4)
1274 #define RT5668_SAR_SEL_SIGNAL_MANU (0x0 << 4)
1276 /* SAR ADC Inline Command Control 13 (0x021c) */
1277 #define RT5668_SAR_SOUR_MASK (0x3f)
1278 #define RT5668_SAR_SOUR_BTN (0x3f)
1279 #define RT5668_SAR_SOUR_TYPE (0x0)
1282 /* System Clock Source */
1287 RT5668_SCLK_S_RCCLK,
1293 RT5668_PLL1_S_BCLK1,
1294 RT5668_PLL1_S_RCCLK,
1305 RT5668_DA_STEREO1_FILTER = 0x1,
1306 RT5668_AD_STEREO1_FILTER = (0x1 << 1),
1311 RT5668_CLK_SEL_I2S1_ASRC,
1312 RT5668_CLK_SEL_I2S2_ASRC,
1315 int rt5668_sel_asrc_clk_src(struct snd_soc_component *component,
1316 unsigned int filter_mask, unsigned int clk_src);
1318 #endif /* __RT5668_H__ */