1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt1316-sdw.c -- rt1316 SDCA ALSA SoC amplifier audio driver
5 // Copyright(c) 2021 Realtek Semiconductor Corp.
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/regmap.h>
14 #include <sound/core.h>
15 #include <sound/pcm.h>
16 #include <sound/pcm_params.h>
17 #include <sound/soc-dapm.h>
18 #include <sound/initval.h>
19 #include "rt1316-sdw.h"
21 static const struct reg_default rt1316_reg_defaults[] = {
62 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 },
63 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 0x01 },
64 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 0x01 },
65 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x01 },
66 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
67 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
68 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
71 static const struct reg_sequence rt1316_blind_write[] = {
121 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x00 },
144 static bool rt1316_readable_register(struct device *dev, unsigned int reg)
149 case 0x3203 ... 0x320e:
150 case 0xc000 ... 0xc7b4:
151 case 0xcf00 ... 0xcf03:
152 case 0xd101 ... 0xd103:
153 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0):
154 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L):
155 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R):
156 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
157 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
158 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
159 case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):
166 static bool rt1316_volatile_register(struct device *dev, unsigned int reg)
174 case 0xc427 ... 0xc428:
182 static const struct regmap_config rt1316_sdw_regmap = {
185 .readable_reg = rt1316_readable_register,
186 .volatile_reg = rt1316_volatile_register,
187 .max_register = 0x4108ffff,
188 .reg_defaults = rt1316_reg_defaults,
189 .num_reg_defaults = ARRAY_SIZE(rt1316_reg_defaults),
190 .cache_type = REGCACHE_RBTREE,
191 .use_single_read = true,
192 .use_single_write = true,
195 static int rt1316_read_prop(struct sdw_slave *slave)
197 struct sdw_slave_prop *prop = &slave->prop;
202 struct sdw_dpn_prop *dpn;
204 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
205 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
206 prop->is_sdca = true;
208 prop->paging_support = true;
210 /* first we need to allocate memory for set bits in port lists */
211 prop->source_ports = 0x04; /* BITMAP: 00000100 */
212 prop->sink_ports = 0x2; /* BITMAP: 00000010 */
214 nval = hweight32(prop->source_ports);
215 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
216 sizeof(*prop->src_dpn_prop), GFP_KERNEL);
217 if (!prop->src_dpn_prop)
221 dpn = prop->src_dpn_prop;
222 addr = prop->source_ports;
223 for_each_set_bit(bit, &addr, 32) {
225 dpn[i].type = SDW_DPN_FULL;
226 dpn[i].simple_ch_prep_sm = true;
227 dpn[i].ch_prep_timeout = 10;
231 /* do this again for sink now */
232 nval = hweight32(prop->sink_ports);
233 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
234 sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
235 if (!prop->sink_dpn_prop)
239 dpn = prop->sink_dpn_prop;
240 addr = prop->sink_ports;
241 for_each_set_bit(bit, &addr, 32) {
243 dpn[j].type = SDW_DPN_FULL;
244 dpn[j].simple_ch_prep_sm = true;
245 dpn[j].ch_prep_timeout = 10;
249 /* set the timeout values */
250 prop->clk_stop_timeout = 20;
252 dev_dbg(&slave->dev, "%s\n", __func__);
257 static int rt1316_io_init(struct device *dev, struct sdw_slave *slave)
259 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
264 if (rt1316->first_hw_init) {
265 regcache_cache_only(rt1316->regmap, false);
266 regcache_cache_bypass(rt1316->regmap, true);
269 * PM runtime is only enabled when a Slave reports as Attached
272 /* set autosuspend parameters */
273 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
274 pm_runtime_use_autosuspend(&slave->dev);
276 /* update count of parent 'active' children */
277 pm_runtime_set_active(&slave->dev);
279 /* make sure the device does not suspend immediately */
280 pm_runtime_mark_last_busy(&slave->dev);
282 pm_runtime_enable(&slave->dev);
285 pm_runtime_get_noresume(&slave->dev);
288 regmap_write(rt1316->regmap, 0xc000, 0x02);
290 /* initial settings - blind write */
291 regmap_multi_reg_write(rt1316->regmap, rt1316_blind_write,
292 ARRAY_SIZE(rt1316_blind_write));
294 if (rt1316->first_hw_init) {
295 regcache_cache_bypass(rt1316->regmap, false);
296 regcache_mark_dirty(rt1316->regmap);
298 rt1316->first_hw_init = true;
300 /* Mark Slave initialization complete */
301 rt1316->hw_init = true;
303 pm_runtime_mark_last_busy(&slave->dev);
304 pm_runtime_put_autosuspend(&slave->dev);
306 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
310 static int rt1316_update_status(struct sdw_slave *slave,
311 enum sdw_slave_status status)
313 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(&slave->dev);
315 /* Update the status */
316 rt1316->status = status;
318 if (status == SDW_SLAVE_UNATTACHED)
319 rt1316->hw_init = false;
322 * Perform initialization only if slave status is present and
323 * hw_init flag is false
325 if (rt1316->hw_init || rt1316->status != SDW_SLAVE_ATTACHED)
328 /* perform I/O transfers required for Slave initialization */
329 return rt1316_io_init(&slave->dev, slave);
332 static int rt1316_classd_event(struct snd_soc_dapm_widget *w,
333 struct snd_kcontrol *kcontrol, int event)
335 struct snd_soc_component *component =
336 snd_soc_dapm_to_component(w->dapm);
337 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
338 unsigned char ps0 = 0x0, ps3 = 0x3;
341 case SND_SOC_DAPM_POST_PMU:
342 regmap_write(rt1316->regmap,
343 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23,
344 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
346 regmap_write(rt1316->regmap,
347 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27,
348 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
350 regmap_write(rt1316->regmap,
351 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22,
352 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
355 case SND_SOC_DAPM_PRE_PMD:
356 regmap_write(rt1316->regmap,
357 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23,
358 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
360 regmap_write(rt1316->regmap,
361 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27,
362 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
364 regmap_write(rt1316->regmap,
365 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22,
366 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
377 static int rt1316_pde24_event(struct snd_soc_dapm_widget *w,
378 struct snd_kcontrol *kcontrol, int event)
380 struct snd_soc_component *component =
381 snd_soc_dapm_to_component(w->dapm);
382 struct rt1316_sdw_priv *rt1316 = snd_soc_component_get_drvdata(component);
383 unsigned char ps0 = 0x0, ps3 = 0x3;
386 case SND_SOC_DAPM_POST_PMU:
387 regmap_write(rt1316->regmap,
388 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24,
389 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
392 case SND_SOC_DAPM_PRE_PMD:
393 regmap_write(rt1316->regmap,
394 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24,
395 RT1316_SDCA_CTL_REQ_POWER_STATE, 0),
402 static const char * const rt1316_rx_data_ch_select[] = {
415 static SOC_ENUM_SINGLE_DECL(rt1316_rx_data_ch_enum,
416 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0,
417 rt1316_rx_data_ch_select);
419 static const struct snd_kcontrol_new rt1316_snd_controls[] = {
421 /* I2S Data Channel Selection */
422 SOC_ENUM("RX Channel Select", rt1316_rx_data_ch_enum),
424 /* XU24 Bypass Control */
425 SOC_SINGLE("XU24 Bypass Switch",
426 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0, 1, 0),
428 /* Left/Right IV tag */
429 SOC_SINGLE("Left V Tag Select", 0x3004, 0, 7, 0),
430 SOC_SINGLE("Left I Tag Select", 0x3004, 4, 7, 0),
431 SOC_SINGLE("Right V Tag Select", 0x3005, 0, 7, 0),
432 SOC_SINGLE("Right I Tag Select", 0x3005, 4, 7, 0),
434 /* IV mixer Control */
435 SOC_DOUBLE("Isense Mixer Switch", 0xc605, 2, 0, 1, 1),
436 SOC_DOUBLE("Vsense Mixer Switch", 0xc605, 3, 1, 1, 1),
439 static const struct snd_kcontrol_new rt1316_sto_dac =
440 SOC_DAPM_DOUBLE_R("Switch",
441 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L),
442 SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R),
445 static const struct snd_soc_dapm_widget rt1316_dapm_widgets[] = {
446 /* Audio Interface */
447 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
448 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
450 /* Digital Interface */
451 SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1316_sto_dac),
454 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
456 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
457 SND_SOC_DAPM_OUTPUT("SPOL"),
458 SND_SOC_DAPM_OUTPUT("SPOR"),
460 SND_SOC_DAPM_SUPPLY("PDE 24", SND_SOC_NOPM, 0, 0,
462 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
463 SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
464 SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
465 SND_SOC_DAPM_SIGGEN("I Gen"),
466 SND_SOC_DAPM_SIGGEN("V Gen"),
469 static const struct snd_soc_dapm_route rt1316_dapm_routes[] = {
470 { "DAC", "Switch", "DP1RX" },
471 { "CLASS D", NULL, "DAC" },
472 { "SPOL", NULL, "CLASS D" },
473 { "SPOR", NULL, "CLASS D" },
475 { "I Sense", NULL, "I Gen" },
476 { "V Sense", NULL, "V Gen" },
477 { "I Sense", NULL, "PDE 24" },
478 { "V Sense", NULL, "PDE 24" },
479 { "DP2TX", NULL, "I Sense" },
480 { "DP2TX", NULL, "V Sense" },
483 static int rt1316_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
486 struct sdw_stream_data *stream;
491 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
495 stream->sdw_stream = sdw_stream;
497 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
498 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
499 dai->playback_dma_data = stream;
501 dai->capture_dma_data = stream;
506 static void rt1316_sdw_shutdown(struct snd_pcm_substream *substream,
507 struct snd_soc_dai *dai)
509 struct sdw_stream_data *stream;
511 stream = snd_soc_dai_get_dma_data(dai, substream);
512 snd_soc_dai_set_dma_data(dai, substream, NULL);
516 static int rt1316_sdw_hw_params(struct snd_pcm_substream *substream,
517 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
519 struct snd_soc_component *component = dai->component;
520 struct rt1316_sdw_priv *rt1316 =
521 snd_soc_component_get_drvdata(component);
522 struct sdw_stream_config stream_config;
523 struct sdw_port_config port_config;
524 enum sdw_data_direction direction;
525 struct sdw_stream_data *stream;
526 int retval, port, num_channels, ch_mask;
528 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
529 stream = snd_soc_dai_get_dma_data(dai, substream);
534 if (!rt1316->sdw_slave)
537 /* SoundWire specific configuration */
538 /* port 1 for playback */
539 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
540 direction = SDW_DATA_DIR_RX;
543 direction = SDW_DATA_DIR_TX;
547 num_channels = params_channels(params);
548 ch_mask = (1 << num_channels) - 1;
550 stream_config.frame_rate = params_rate(params);
551 stream_config.ch_count = num_channels;
552 stream_config.bps = snd_pcm_format_width(params_format(params));
553 stream_config.direction = direction;
555 port_config.ch_mask = ch_mask;
556 port_config.num = port;
558 retval = sdw_stream_add_slave(rt1316->sdw_slave, &stream_config,
559 &port_config, 1, stream->sdw_stream);
561 dev_err(dai->dev, "Unable to configure port\n");
568 static int rt1316_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
569 struct snd_soc_dai *dai)
571 struct snd_soc_component *component = dai->component;
572 struct rt1316_sdw_priv *rt1316 =
573 snd_soc_component_get_drvdata(component);
574 struct sdw_stream_data *stream =
575 snd_soc_dai_get_dma_data(dai, substream);
577 if (!rt1316->sdw_slave)
580 sdw_stream_remove_slave(rt1316->sdw_slave, stream->sdw_stream);
585 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
586 * port_prep are not defined for now
588 static struct sdw_slave_ops rt1316_slave_ops = {
589 .read_prop = rt1316_read_prop,
590 .update_status = rt1316_update_status,
593 static const struct snd_soc_component_driver soc_component_sdw_rt1316 = {
594 .controls = rt1316_snd_controls,
595 .num_controls = ARRAY_SIZE(rt1316_snd_controls),
596 .dapm_widgets = rt1316_dapm_widgets,
597 .num_dapm_widgets = ARRAY_SIZE(rt1316_dapm_widgets),
598 .dapm_routes = rt1316_dapm_routes,
599 .num_dapm_routes = ARRAY_SIZE(rt1316_dapm_routes),
602 static const struct snd_soc_dai_ops rt1316_aif_dai_ops = {
603 .hw_params = rt1316_sdw_hw_params,
604 .hw_free = rt1316_sdw_pcm_hw_free,
605 .set_stream = rt1316_set_sdw_stream,
606 .shutdown = rt1316_sdw_shutdown,
609 #define RT1316_STEREO_RATES SNDRV_PCM_RATE_48000
610 #define RT1316_FORMATS (SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
611 SNDRV_PCM_FMTBIT_S24_LE)
613 static struct snd_soc_dai_driver rt1316_sdw_dai[] = {
615 .name = "rt1316-aif",
617 .stream_name = "DP1 Playback",
620 .rates = RT1316_STEREO_RATES,
621 .formats = RT1316_FORMATS,
624 .stream_name = "DP2 Capture",
627 .rates = RT1316_STEREO_RATES,
628 .formats = RT1316_FORMATS,
630 .ops = &rt1316_aif_dai_ops,
634 static int rt1316_sdw_init(struct device *dev, struct regmap *regmap,
635 struct sdw_slave *slave)
637 struct rt1316_sdw_priv *rt1316;
640 rt1316 = devm_kzalloc(dev, sizeof(*rt1316), GFP_KERNEL);
644 dev_set_drvdata(dev, rt1316);
645 rt1316->sdw_slave = slave;
646 rt1316->regmap = regmap;
649 * Mark hw_init to false
650 * HW init will be performed when device reports present
652 rt1316->hw_init = false;
653 rt1316->first_hw_init = false;
655 ret = devm_snd_soc_register_component(dev,
656 &soc_component_sdw_rt1316,
658 ARRAY_SIZE(rt1316_sdw_dai));
660 dev_dbg(&slave->dev, "%s\n", __func__);
665 static int rt1316_sdw_probe(struct sdw_slave *slave,
666 const struct sdw_device_id *id)
668 struct regmap *regmap;
670 /* Regmap Initialization */
671 regmap = devm_regmap_init_sdw(slave, &rt1316_sdw_regmap);
673 return PTR_ERR(regmap);
675 return rt1316_sdw_init(&slave->dev, regmap, slave);
678 static const struct sdw_device_id rt1316_id[] = {
679 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0),
682 MODULE_DEVICE_TABLE(sdw, rt1316_id);
684 static int __maybe_unused rt1316_dev_suspend(struct device *dev)
686 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
688 if (!rt1316->hw_init)
691 regcache_cache_only(rt1316->regmap, true);
696 #define RT1316_PROBE_TIMEOUT 5000
698 static int __maybe_unused rt1316_dev_resume(struct device *dev)
700 struct sdw_slave *slave = dev_to_sdw_dev(dev);
701 struct rt1316_sdw_priv *rt1316 = dev_get_drvdata(dev);
704 if (!rt1316->first_hw_init)
707 if (!slave->unattach_request)
710 time = wait_for_completion_timeout(&slave->initialization_complete,
711 msecs_to_jiffies(RT1316_PROBE_TIMEOUT));
713 dev_err(&slave->dev, "Initialization not complete, timed out\n");
718 slave->unattach_request = 0;
719 regcache_cache_only(rt1316->regmap, false);
720 regcache_sync(rt1316->regmap);
725 static const struct dev_pm_ops rt1316_pm = {
726 SET_SYSTEM_SLEEP_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume)
727 SET_RUNTIME_PM_OPS(rt1316_dev_suspend, rt1316_dev_resume, NULL)
730 static struct sdw_driver rt1316_sdw_driver = {
732 .name = "rt1316-sdca",
733 .owner = THIS_MODULE,
736 .probe = rt1316_sdw_probe,
737 .ops = &rt1316_slave_ops,
738 .id_table = rt1316_id,
740 module_sdw_driver(rt1316_sdw_driver);
742 MODULE_DESCRIPTION("ASoC RT1316 driver SDCA SDW");
743 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
744 MODULE_LICENSE("GPL");