sound/soc/codecs/rt1308-sdw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // rt1308-sdw.c -- rt1308 ALSA SoC audio driver
   4 //
   5 // Copyright(c) 2019 Realtek Semiconductor Corp.
   6 //
   7 //
   8 #include <linux/delay.h>
   9 #include <linux/device.h>
  10 #include <linux/pm_runtime.h>
  11 #include <linux/mod_devicetable.h>
  12 #include <linux/soundwire/sdw.h>
  13 #include <linux/soundwire/sdw_type.h>
  14 #include <linux/soundwire/sdw_registers.h>
  15 #include <linux/module.h>
  16 #include <linux/regmap.h>
  17 #include <sound/core.h>
  18 #include <sound/pcm.h>
  19 #include <sound/pcm_params.h>
  20 #include <sound/soc.h>
  21 #include <sound/soc-dapm.h>
  22 #include <sound/initval.h>
  23
  24 #include "rt1308.h"
  25 #include "rt1308-sdw.h"
  26
  27 static bool rt1308_readable_register(struct device *dev, unsigned int reg)
  28 {
  29         switch (reg) {
  30         case 0x00e0:
  31         case 0x00f0:
  32         case 0x2f01 ... 0x2f07:
  33         case 0x3000 ... 0x3001:
  34         case 0x3004 ... 0x3005:
  35         case 0x3008:
  36         case 0x300a:
  37         case 0xc000 ... 0xcff3:
  38                 return true;
  39         default:
  40                 return false;
  41         }
  42 }
  43
  44 static bool rt1308_volatile_register(struct device *dev, unsigned int reg)
  45 {
  46         switch (reg) {
  47         case 0x2f01 ... 0x2f07:
  48         case 0x3000 ... 0x3001:
  49         case 0x3004 ... 0x3005:
  50         case 0x3008:
  51         case 0x300a:
  52         case 0xc000:
  53         case 0xc710:
  54         case 0xc860 ... 0xc863:
  55         case 0xc870 ... 0xc873:
  56                 return true;
  57         default:
  58                 return false;
  59         }
  60 }
  61
  62 static const struct regmap_config rt1308_sdw_regmap = {
  63         .reg_bits = 32,
  64         .val_bits = 8,
  65         .readable_reg = rt1308_readable_register,
  66         .volatile_reg = rt1308_volatile_register,
  67         .max_register = 0xcfff,
  68         .reg_defaults = rt1308_reg_defaults,
  69         .num_reg_defaults = ARRAY_SIZE(rt1308_reg_defaults),
  70         .cache_type = REGCACHE_RBTREE,
  71         .use_single_read = true,
  72         .use_single_write = true,
  73 };
  74
  75 /* Bus clock frequency */
  76 #define RT1308_CLK_FREQ_9600000HZ 9600000
  77 #define RT1308_CLK_FREQ_12000000HZ 12000000
  78 #define RT1308_CLK_FREQ_6000000HZ 6000000
  79 #define RT1308_CLK_FREQ_4800000HZ 4800000
  80 #define RT1308_CLK_FREQ_2400000HZ 2400000
  81 #define RT1308_CLK_FREQ_12288000HZ 12288000
  82
  83 static int rt1308_clock_config(struct device *dev)
  84 {
  85         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
  86         unsigned int clk_freq, value;
  87
  88         clk_freq = (rt1308->params.curr_dr_freq >> 1);
  89
  90         switch (clk_freq) {
  91         case RT1308_CLK_FREQ_12000000HZ:
  92                 value = 0x0;
  93                 break;
  94         case RT1308_CLK_FREQ_6000000HZ:
  95                 value = 0x1;
  96                 break;
  97         case RT1308_CLK_FREQ_9600000HZ:
  98                 value = 0x2;
  99                 break;
 100         case RT1308_CLK_FREQ_4800000HZ:
 101                 value = 0x3;
 102                 break;
 103         case RT1308_CLK_FREQ_2400000HZ:
 104                 value = 0x4;
 105                 break;
 106         case RT1308_CLK_FREQ_12288000HZ:
 107                 value = 0x5;
 108                 break;
 109         default:
 110                 return -EINVAL;
 111         }
 112
 113         regmap_write(rt1308->regmap, 0xe0, value);
 114         regmap_write(rt1308->regmap, 0xf0, value);
 115
 116         dev_dbg(dev, "%s complete, clk_freq=%d\n", __func__, clk_freq);
 117
 118         return 0;
 119 }
 120
 121 static int rt1308_read_prop(struct sdw_slave *slave)
 122 {
 123         struct sdw_slave_prop *prop = &slave->prop;
 124         int nval, i;
 125         u32 bit;
 126         unsigned long addr;
 127         struct sdw_dpn_prop *dpn;
 128
 129         prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
 130         prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
 131
 132         prop->paging_support = true;
 133
 134         /* first we need to allocate memory for set bits in port lists */
 135         prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */
 136         prop->sink_ports = 0x2; /* BITMAP:  00000010 */
 137
 138         /* for sink */
 139         nval = hweight32(prop->sink_ports);
 140         prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
 141                                                 sizeof(*prop->sink_dpn_prop),
 142                                                 GFP_KERNEL);
 143         if (!prop->sink_dpn_prop)
 144                 return -ENOMEM;
 145
 146         i = 0;
 147         dpn = prop->sink_dpn_prop;
 148         addr = prop->sink_ports;
 149         for_each_set_bit(bit, &addr, 32) {
 150                 dpn[i].num = bit;
 151                 dpn[i].type = SDW_DPN_FULL;
 152                 dpn[i].simple_ch_prep_sm = true;
 153                 dpn[i].ch_prep_timeout = 10;
 154                 i++;
 155         }
 156
 157         /* set the timeout values */
 158         prop->clk_stop_timeout = 20;
 159
 160         dev_dbg(&slave->dev, "%s\n", __func__);
 161
 162         return 0;
 163 }
 164
 165 static void rt1308_apply_calib_params(struct rt1308_sdw_priv *rt1308)
 166 {
 167         unsigned int efuse_m_btl_l, efuse_m_btl_r, tmp;
 168         unsigned int efuse_c_btl_l, efuse_c_btl_r;
 169
 170         /* read efuse to apply calibration parameters */
 171         regmap_write(rt1308->regmap, 0xc7f0, 0x04);
 172         regmap_write(rt1308->regmap, 0xc7f1, 0xfe);
 173         msleep(100);
 174         regmap_write(rt1308->regmap, 0xc7f0, 0x44);
 175         msleep(20);
 176         regmap_write(rt1308->regmap, 0xc240, 0x10);
 177
 178         regmap_read(rt1308->regmap, 0xc861, &tmp);
 179         efuse_m_btl_l = tmp;
 180         regmap_read(rt1308->regmap, 0xc860, &tmp);
 181         efuse_m_btl_l = efuse_m_btl_l | (tmp << 8);
 182         regmap_read(rt1308->regmap, 0xc863, &tmp);
 183         efuse_c_btl_l = tmp;
 184         regmap_read(rt1308->regmap, 0xc862, &tmp);
 185         efuse_c_btl_l = efuse_c_btl_l | (tmp << 8);
 186         regmap_read(rt1308->regmap, 0xc871, &tmp);
 187         efuse_m_btl_r = tmp;
 188         regmap_read(rt1308->regmap, 0xc870, &tmp);
 189         efuse_m_btl_r = efuse_m_btl_r | (tmp << 8);
 190         regmap_read(rt1308->regmap, 0xc873, &tmp);
 191         efuse_c_btl_r = tmp;
 192         regmap_read(rt1308->regmap, 0xc872, &tmp);
 193         efuse_c_btl_r = efuse_c_btl_r | (tmp << 8);
 194         dev_dbg(&rt1308->sdw_slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__,
 195                 efuse_m_btl_l, efuse_m_btl_r);
 196         dev_dbg(&rt1308->sdw_slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__,
 197                 efuse_c_btl_l, efuse_c_btl_r);
 198 }
 199
 200 static void rt1308_apply_bq_params(struct rt1308_sdw_priv *rt1308)
 201 {
 202         unsigned int i, reg, data;
 203
 204         for (i = 0; i < rt1308->bq_params_cnt; i += 3) {
 205                 reg = rt1308->bq_params[i] | (rt1308->bq_params[i + 1] << 8);
 206                 data = rt1308->bq_params[i + 2];
 207                 regmap_write(rt1308->regmap, reg, data);
 208         }
 209 }
 210
 211 static int rt1308_io_init(struct device *dev, struct sdw_slave *slave)
 212 {
 213         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
 214         int ret = 0;
 215         unsigned int tmp;
 216
 217         if (rt1308->hw_init)
 218                 return 0;
 219
 220         if (rt1308->first_hw_init) {
 221                 regcache_cache_only(rt1308->regmap, false);
 222                 regcache_cache_bypass(rt1308->regmap, true);
 223         }
 224
 225         /*
 226          * PM runtime is only enabled when a Slave reports as Attached
 227          */
 228         if (!rt1308->first_hw_init) {
 229                 /* set autosuspend parameters */
 230                 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
 231                 pm_runtime_use_autosuspend(&slave->dev);
 232
 233                 /* update count of parent 'active' children */
 234                 pm_runtime_set_active(&slave->dev);
 235
 236                 /* make sure the device does not suspend immediately */
 237                 pm_runtime_mark_last_busy(&slave->dev);
 238
 239                 pm_runtime_enable(&slave->dev);
 240         }
 241
 242         pm_runtime_get_noresume(&slave->dev);
 243
 244         /* sw reset */
 245         regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0);
 246
 247         regmap_read(rt1308->regmap, 0xc710, &tmp);
 248         rt1308->hw_ver = tmp;
 249         dev_dbg(dev, "%s, hw_ver=0x%x\n", __func__, rt1308->hw_ver);
 250
 251         /* initial settings */
 252         regmap_write(rt1308->regmap, 0xc103, 0xc0);
 253         regmap_write(rt1308->regmap, 0xc030, 0x17);
 254         regmap_write(rt1308->regmap, 0xc031, 0x81);
 255         regmap_write(rt1308->regmap, 0xc032, 0x26);
 256         regmap_write(rt1308->regmap, 0xc040, 0x80);
 257         regmap_write(rt1308->regmap, 0xc041, 0x80);
 258         regmap_write(rt1308->regmap, 0xc042, 0x06);
 259         regmap_write(rt1308->regmap, 0xc052, 0x0a);
 260         regmap_write(rt1308->regmap, 0xc080, 0x0a);
 261         regmap_write(rt1308->regmap, 0xc060, 0x02);
 262         regmap_write(rt1308->regmap, 0xc061, 0x75);
 263         regmap_write(rt1308->regmap, 0xc062, 0x05);
 264         regmap_write(rt1308->regmap, 0xc171, 0x07);
 265         regmap_write(rt1308->regmap, 0xc173, 0x0d);
 266         if (rt1308->hw_ver == RT1308_VER_C) {
 267                 regmap_write(rt1308->regmap, 0xc311, 0x7f);
 268                 regmap_write(rt1308->regmap, 0xc300, 0x09);
 269         } else {
 270                 regmap_write(rt1308->regmap, 0xc311, 0x4f);
 271                 regmap_write(rt1308->regmap, 0xc300, 0x0b);
 272         }
 273         regmap_write(rt1308->regmap, 0xc900, 0x5a);
 274         regmap_write(rt1308->regmap, 0xc1a0, 0x84);
 275         regmap_write(rt1308->regmap, 0xc1a1, 0x01);
 276         regmap_write(rt1308->regmap, 0xc360, 0x78);
 277         regmap_write(rt1308->regmap, 0xc361, 0x87);
 278         regmap_write(rt1308->regmap, 0xc0a1, 0x71);
 279         regmap_write(rt1308->regmap, 0xc210, 0x00);
 280         regmap_write(rt1308->regmap, 0xc070, 0x00);
 281         regmap_write(rt1308->regmap, 0xc100, 0xd7);
 282         regmap_write(rt1308->regmap, 0xc101, 0xd7);
 283
 284         if (rt1308->first_hw_init) {
 285                 regcache_cache_bypass(rt1308->regmap, false);
 286                 regcache_mark_dirty(rt1308->regmap);
 287         } else
 288                 rt1308->first_hw_init = true;
 289
 290         /* Mark Slave initialization complete */
 291         rt1308->hw_init = true;
 292
 293         pm_runtime_mark_last_busy(&slave->dev);
 294         pm_runtime_put_autosuspend(&slave->dev);
 295
 296         dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
 297
 298         return ret;
 299 }
 300
 301 static int rt1308_update_status(struct sdw_slave *slave,
 302                                         enum sdw_slave_status status)
 303 {
 304         struct  rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
 305
 306         /* Update the status */
 307         rt1308->status = status;
 308
 309         if (status == SDW_SLAVE_UNATTACHED)
 310                 rt1308->hw_init = false;
 311
 312         /*
 313          * Perform initialization only if slave status is present and
 314          * hw_init flag is false
 315          */
 316         if (rt1308->hw_init || rt1308->status != SDW_SLAVE_ATTACHED)
 317                 return 0;
 318
 319         /* perform I/O transfers required for Slave initialization */
 320         return rt1308_io_init(&slave->dev, slave);
 321 }
 322
 323 static int rt1308_bus_config(struct sdw_slave *slave,
 324                                 struct sdw_bus_params *params)
 325 {
 326         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
 327         int ret;
 328
 329         memcpy(&rt1308->params, params, sizeof(*params));
 330
 331         ret = rt1308_clock_config(&slave->dev);
 332         if (ret < 0)
 333                 dev_err(&slave->dev, "Invalid clk config");
 334
 335         return ret;
 336 }
 337
 338 static int rt1308_interrupt_callback(struct sdw_slave *slave,
 339                                         struct sdw_slave_intr_status *status)
 340 {
 341         dev_dbg(&slave->dev,
 342                 "%s control_port_stat=%x", __func__, status->control_port);
 343
 344         return 0;
 345 }
 346
 347 static int rt1308_classd_event(struct snd_soc_dapm_widget *w,
 348         struct snd_kcontrol *kcontrol, int event)
 349 {
 350         struct snd_soc_component *component =
 351                 snd_soc_dapm_to_component(w->dapm);
 352         struct rt1308_sdw_priv *rt1308 =
 353                 snd_soc_component_get_drvdata(component);
 354
 355         switch (event) {
 356         case SND_SOC_DAPM_POST_PMU:
 357                 msleep(30);
 358                 snd_soc_component_update_bits(component,
 359                         RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
 360                         0x3,    0x3);
 361                 msleep(40);
 362                 rt1308_apply_calib_params(rt1308);
 363                 break;
 364         case SND_SOC_DAPM_PRE_PMD:
 365                 snd_soc_component_update_bits(component,
 366                         RT1308_SDW_OFFSET | (RT1308_POWER_STATUS << 4),
 367                         0x3, 0);
 368                 usleep_range(150000, 200000);
 369                 break;
 370
 371         default:
 372                 break;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static const char * const rt1308_rx_data_ch_select[] = {
 379         "LR",
 380         "LL",
 381         "RL",
 382         "RR",
 383 };
 384
 385 static SOC_ENUM_SINGLE_DECL(rt1308_rx_data_ch_enum,
 386         RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0,
 387         rt1308_rx_data_ch_select);
 388
 389 static const struct snd_kcontrol_new rt1308_snd_controls[] = {
 390
 391         /* I2S Data Channel Selection */
 392         SOC_ENUM("RX Channel Select", rt1308_rx_data_ch_enum),
 393 };
 394
 395 static const struct snd_kcontrol_new rt1308_sto_dac_l =
 396         SOC_DAPM_SINGLE_AUTODISABLE("Switch",
 397                 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
 398                 RT1308_DVOL_MUTE_L_EN_SFT, 1, 1);
 399
 400 static const struct snd_kcontrol_new rt1308_sto_dac_r =
 401         SOC_DAPM_SINGLE_AUTODISABLE("Switch",
 402                 RT1308_SDW_OFFSET_BYTE3 | (RT1308_DAC_SET << 4),
 403                 RT1308_DVOL_MUTE_R_EN_SFT, 1, 1);
 404
 405 static const struct snd_soc_dapm_widget rt1308_dapm_widgets[] = {
 406         /* Audio Interface */
 407         SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
 408
 409         /* Supply Widgets */
 410         SND_SOC_DAPM_SUPPLY("MBIAS20U",
 411                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        7, 0, NULL, 0),
 412         SND_SOC_DAPM_SUPPLY("ALDO",
 413                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        6, 0, NULL, 0),
 414         SND_SOC_DAPM_SUPPLY("DBG",
 415                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        5, 0, NULL, 0),
 416         SND_SOC_DAPM_SUPPLY("DACL",
 417                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        4, 0, NULL, 0),
 418         SND_SOC_DAPM_SUPPLY("CLK25M",
 419                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        2, 0, NULL, 0),
 420         SND_SOC_DAPM_SUPPLY("ADC_R",
 421                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        1, 0, NULL, 0),
 422         SND_SOC_DAPM_SUPPLY("ADC_L",
 423                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        0, 0, NULL, 0),
 424         SND_SOC_DAPM_SUPPLY("DAC Power",
 425                 RT1308_SDW_OFFSET | (RT1308_POWER << 4),        3, 0, NULL, 0),
 426
 427         SND_SOC_DAPM_SUPPLY("DLDO",
 428                 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  5, 0, NULL, 0),
 429         SND_SOC_DAPM_SUPPLY("VREF",
 430                 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  4, 0, NULL, 0),
 431         SND_SOC_DAPM_SUPPLY("MIXER_R",
 432                 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  2, 0, NULL, 0),
 433         SND_SOC_DAPM_SUPPLY("MIXER_L",
 434                 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  1, 0, NULL, 0),
 435         SND_SOC_DAPM_SUPPLY("MBIAS4U",
 436                 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4),  0, 0, NULL, 0),
 437
 438         SND_SOC_DAPM_SUPPLY("PLL2_LDO",
 439                 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0),
 440         SND_SOC_DAPM_SUPPLY("PLL2B",
 441                 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0),
 442         SND_SOC_DAPM_SUPPLY("PLL2F",
 443                 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0),
 444         SND_SOC_DAPM_SUPPLY("PLL2F2",
 445                 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0),
 446         SND_SOC_DAPM_SUPPLY("PLL2B2",
 447                 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0),
 448
 449         /* Digital Interface */
 450         SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
 451         SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
 452         SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
 453
 454         /* Output Lines */
 455         SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
 456                 rt1308_classd_event,
 457                 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
 458         SND_SOC_DAPM_OUTPUT("SPOL"),
 459         SND_SOC_DAPM_OUTPUT("SPOR"),
 460 };
 461
 462 static const struct snd_soc_dapm_route rt1308_dapm_routes[] = {
 463
 464         { "DAC", NULL, "AIF1RX" },
 465
 466         { "DAC", NULL, "MBIAS20U" },
 467         { "DAC", NULL, "ALDO" },
 468         { "DAC", NULL, "DBG" },
 469         { "DAC", NULL, "DACL" },
 470         { "DAC", NULL, "CLK25M" },
 471         { "DAC", NULL, "ADC_R" },
 472         { "DAC", NULL, "ADC_L" },
 473         { "DAC", NULL, "DLDO" },
 474         { "DAC", NULL, "VREF" },
 475         { "DAC", NULL, "MIXER_R" },
 476         { "DAC", NULL, "MIXER_L" },
 477         { "DAC", NULL, "MBIAS4U" },
 478         { "DAC", NULL, "PLL2_LDO" },
 479         { "DAC", NULL, "PLL2B" },
 480         { "DAC", NULL, "PLL2F" },
 481         { "DAC", NULL, "PLL2F2" },
 482         { "DAC", NULL, "PLL2B2" },
 483
 484         { "DAC L", "Switch", "DAC" },
 485         { "DAC R", "Switch", "DAC" },
 486         { "DAC L", NULL, "DAC Power" },
 487         { "DAC R", NULL, "DAC Power" },
 488
 489         { "CLASS D", NULL, "DAC L" },
 490         { "CLASS D", NULL, "DAC R" },
 491         { "SPOL", NULL, "CLASS D" },
 492         { "SPOR", NULL, "CLASS D" },
 493 };
 494
 495 static int rt1308_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
 496                                 int direction)
 497 {
 498         struct sdw_stream_data *stream;
 499
 500         if (!sdw_stream)
 501                 return 0;
 502
 503         stream = kzalloc(sizeof(*stream), GFP_KERNEL);
 504         if (!stream)
 505                 return -ENOMEM;
 506
 507         stream->sdw_stream = sdw_stream;
 508
 509         /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
 510         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
 511                 dai->playback_dma_data = stream;
 512         else
 513                 dai->capture_dma_data = stream;
 514
 515         return 0;
 516 }
 517
 518 static void rt1308_sdw_shutdown(struct snd_pcm_substream *substream,
 519                                 struct snd_soc_dai *dai)
 520 {
 521         struct sdw_stream_data *stream;
 522
 523         stream = snd_soc_dai_get_dma_data(dai, substream);
 524         snd_soc_dai_set_dma_data(dai, substream, NULL);
 525         kfree(stream);
 526 }
 527
 528 static int rt1308_sdw_set_tdm_slot(struct snd_soc_dai *dai,
 529                                    unsigned int tx_mask,
 530                                    unsigned int rx_mask,
 531                                    int slots, int slot_width)
 532 {
 533         struct snd_soc_component *component = dai->component;
 534         struct rt1308_sdw_priv *rt1308 =
 535                 snd_soc_component_get_drvdata(component);
 536
 537         if (tx_mask)
 538                 return -EINVAL;
 539
 540         if (slots > 2)
 541                 return -EINVAL;
 542
 543         rt1308->rx_mask = rx_mask;
 544         rt1308->slots = slots;
 545         /* slot_width is not used since it's irrelevant for SoundWire */
 546
 547         return 0;
 548 }
 549
 550 static int rt1308_sdw_hw_params(struct snd_pcm_substream *substream,
 551         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 552 {
 553         struct snd_soc_component *component = dai->component;
 554         struct rt1308_sdw_priv *rt1308 =
 555                 snd_soc_component_get_drvdata(component);
 556         struct sdw_stream_config stream_config;
 557         struct sdw_port_config port_config;
 558         enum sdw_data_direction direction;
 559         struct sdw_stream_data *stream;
 560         int retval, port, num_channels, ch_mask;
 561
 562         dev_dbg(dai->dev, "%s %s", __func__, dai->name);
 563         stream = snd_soc_dai_get_dma_data(dai, substream);
 564
 565         if (!stream)
 566                 return -EINVAL;
 567
 568         if (!rt1308->sdw_slave)
 569                 return -EINVAL;
 570
 571         /* SoundWire specific configuration */
 572         /* port 1 for playback */
 573         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 574                 direction = SDW_DATA_DIR_RX;
 575                 port = 1;
 576         } else {
 577                 return -EINVAL;
 578         }
 579
 580         if (rt1308->slots) {
 581                 num_channels = rt1308->slots;
 582                 ch_mask = rt1308->rx_mask;
 583         } else {
 584                 num_channels = params_channels(params);
 585                 ch_mask = (1 << num_channels) - 1;
 586         }
 587
 588         stream_config.frame_rate = params_rate(params);
 589         stream_config.ch_count = num_channels;
 590         stream_config.bps = snd_pcm_format_width(params_format(params));
 591         stream_config.direction = direction;
 592
 593         port_config.ch_mask = ch_mask;
 594         port_config.num = port;
 595
 596         retval = sdw_stream_add_slave(rt1308->sdw_slave, &stream_config,
 597                                 &port_config, 1, stream->sdw_stream);
 598         if (retval) {
 599                 dev_err(dai->dev, "Unable to configure port\n");
 600                 return retval;
 601         }
 602
 603         return retval;
 604 }
 605
 606 static int rt1308_sdw_pcm_hw_free(struct snd_pcm_substream *substream,
 607                                 struct snd_soc_dai *dai)
 608 {
 609         struct snd_soc_component *component = dai->component;
 610         struct rt1308_sdw_priv *rt1308 =
 611                 snd_soc_component_get_drvdata(component);
 612         struct sdw_stream_data *stream =
 613                 snd_soc_dai_get_dma_data(dai, substream);
 614
 615         if (!rt1308->sdw_slave)
 616                 return -EINVAL;
 617
 618         sdw_stream_remove_slave(rt1308->sdw_slave, stream->sdw_stream);
 619         return 0;
 620 }
 621
 622 /*
 623  * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
 624  * port_prep are not defined for now
 625  */
 626 static const struct sdw_slave_ops rt1308_slave_ops = {
 627         .read_prop = rt1308_read_prop,
 628         .interrupt_callback = rt1308_interrupt_callback,
 629         .update_status = rt1308_update_status,
 630         .bus_config = rt1308_bus_config,
 631 };
 632
 633 static int rt1308_sdw_parse_dt(struct rt1308_sdw_priv *rt1308, struct device *dev)
 634 {
 635         int ret = 0;
 636
 637         device_property_read_u32(dev, "realtek,bq-params-cnt", &rt1308->bq_params_cnt);
 638         if (rt1308->bq_params_cnt) {
 639                 rt1308->bq_params = devm_kzalloc(dev, rt1308->bq_params_cnt, GFP_KERNEL);
 640                 if (!rt1308->bq_params) {
 641                         dev_err(dev, "Could not allocate bq_params memory\n");
 642                         ret = -ENOMEM;
 643                 } else {
 644                         ret = device_property_read_u8_array(dev, "realtek,bq-params", rt1308->bq_params, rt1308->bq_params_cnt);
 645                         if (ret < 0)
 646                                 dev_err(dev, "Could not read list of realtek,bq-params\n");
 647                 }
 648         }
 649
 650         dev_dbg(dev, "bq_params_cnt=%d\n", rt1308->bq_params_cnt);
 651         return ret;
 652 }
 653
 654 static int rt1308_sdw_component_probe(struct snd_soc_component *component)
 655 {
 656         struct rt1308_sdw_priv *rt1308 = snd_soc_component_get_drvdata(component);
 657         int ret;
 658
 659         rt1308->component = component;
 660         rt1308_sdw_parse_dt(rt1308, &rt1308->sdw_slave->dev);
 661
 662         ret = pm_runtime_resume(component->dev);
 663         if (ret < 0 && ret != -EACCES)
 664                 return ret;
 665
 666         /* apply BQ params */
 667         rt1308_apply_bq_params(rt1308);
 668
 669         return 0;
 670 }
 671
 672 static const struct snd_soc_component_driver soc_component_sdw_rt1308 = {
 673         .probe = rt1308_sdw_component_probe,
 674         .controls = rt1308_snd_controls,
 675         .num_controls = ARRAY_SIZE(rt1308_snd_controls),
 676         .dapm_widgets = rt1308_dapm_widgets,
 677         .num_dapm_widgets = ARRAY_SIZE(rt1308_dapm_widgets),
 678         .dapm_routes = rt1308_dapm_routes,
 679         .num_dapm_routes = ARRAY_SIZE(rt1308_dapm_routes),
 680         .endianness = 1,
 681 };
 682
 683 static const struct snd_soc_dai_ops rt1308_aif_dai_ops = {
 684         .hw_params = rt1308_sdw_hw_params,
 685         .hw_free        = rt1308_sdw_pcm_hw_free,
 686         .set_stream     = rt1308_set_sdw_stream,
 687         .shutdown       = rt1308_sdw_shutdown,
 688         .set_tdm_slot   = rt1308_sdw_set_tdm_slot,
 689 };
 690
 691 #define RT1308_STEREO_RATES SNDRV_PCM_RATE_48000
 692 #define RT1308_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
 693                         SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
 694                         SNDRV_PCM_FMTBIT_S24_LE)
 695
 696 static struct snd_soc_dai_driver rt1308_sdw_dai[] = {
 697         {
 698                 .name = "rt1308-aif",
 699                 .playback = {
 700                         .stream_name = "DP1 Playback",
 701                         .channels_min = 1,
 702                         .channels_max = 2,
 703                         .rates = RT1308_STEREO_RATES,
 704                         .formats = RT1308_FORMATS,
 705                 },
 706                 .ops = &rt1308_aif_dai_ops,
 707         },
 708 };
 709
 710 static int rt1308_sdw_init(struct device *dev, struct regmap *regmap,
 711                                 struct sdw_slave *slave)
 712 {
 713         struct rt1308_sdw_priv *rt1308;
 714         int ret;
 715
 716         rt1308 = devm_kzalloc(dev, sizeof(*rt1308), GFP_KERNEL);
 717         if (!rt1308)
 718                 return -ENOMEM;
 719
 720         dev_set_drvdata(dev, rt1308);
 721         rt1308->sdw_slave = slave;
 722         rt1308->regmap = regmap;
 723
 724         /*
 725          * Mark hw_init to false
 726          * HW init will be performed when device reports present
 727          */
 728         rt1308->hw_init = false;
 729         rt1308->first_hw_init = false;
 730
 731         ret =  devm_snd_soc_register_component(dev,
 732                                 &soc_component_sdw_rt1308,
 733                                 rt1308_sdw_dai,
 734                                 ARRAY_SIZE(rt1308_sdw_dai));
 735
 736         dev_dbg(&slave->dev, "%s\n", __func__);
 737
 738         return ret;
 739 }
 740
 741 static int rt1308_sdw_probe(struct sdw_slave *slave,
 742                                 const struct sdw_device_id *id)
 743 {
 744         struct regmap *regmap;
 745
 746         /* Regmap Initialization */
 747         regmap = devm_regmap_init_sdw(slave, &rt1308_sdw_regmap);
 748         if (IS_ERR(regmap))
 749                 return PTR_ERR(regmap);
 750
 751         rt1308_sdw_init(&slave->dev, regmap, slave);
 752
 753         return 0;
 754 }
 755
 756 static int rt1308_sdw_remove(struct sdw_slave *slave)
 757 {
 758         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(&slave->dev);
 759
 760         if (rt1308->first_hw_init)
 761                 pm_runtime_disable(&slave->dev);
 762
 763         return 0;
 764 }
 765
 766 static const struct sdw_device_id rt1308_id[] = {
 767         SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0),
 768         {},
 769 };
 770 MODULE_DEVICE_TABLE(sdw, rt1308_id);
 771
 772 static int __maybe_unused rt1308_dev_suspend(struct device *dev)
 773 {
 774         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
 775
 776         if (!rt1308->hw_init)
 777                 return 0;
 778
 779         regcache_cache_only(rt1308->regmap, true);
 780
 781         return 0;
 782 }
 783
 784 #define RT1308_PROBE_TIMEOUT 5000
 785
 786 static int __maybe_unused rt1308_dev_resume(struct device *dev)
 787 {
 788         struct sdw_slave *slave = dev_to_sdw_dev(dev);
 789         struct rt1308_sdw_priv *rt1308 = dev_get_drvdata(dev);
 790         unsigned long time;
 791
 792         if (!rt1308->first_hw_init)
 793                 return 0;
 794
 795         if (!slave->unattach_request)
 796                 goto regmap_sync;
 797
 798         time = wait_for_completion_timeout(&slave->initialization_complete,
 799                                 msecs_to_jiffies(RT1308_PROBE_TIMEOUT));
 800         if (!time) {
 801                 dev_err(&slave->dev, "Initialization not complete, timed out\n");
 802                 sdw_show_ping_status(slave->bus, true);
 803
 804                 return -ETIMEDOUT;
 805         }
 806
 807 regmap_sync:
 808         slave->unattach_request = 0;
 809         regcache_cache_only(rt1308->regmap, false);
 810         regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff);
 811
 812         return 0;
 813 }
 814
 815 static const struct dev_pm_ops rt1308_pm = {
 816         SET_SYSTEM_SLEEP_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume)
 817         SET_RUNTIME_PM_OPS(rt1308_dev_suspend, rt1308_dev_resume, NULL)
 818 };
 819
 820 static struct sdw_driver rt1308_sdw_driver = {
 821         .driver = {
 822                 .name = "rt1308",
 823                 .owner = THIS_MODULE,
 824                 .pm = &rt1308_pm,
 825         },
 826         .probe = rt1308_sdw_probe,
 827         .remove = rt1308_sdw_remove,
 828         .ops = &rt1308_slave_ops,
 829         .id_table = rt1308_id,
 830 };
 831 module_sdw_driver(rt1308_sdw_driver);
 832
 833 MODULE_DESCRIPTION("ASoC RT1308 driver SDW");
 834 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
 835 MODULE_LICENSE("GPL v2");