2 * rt1305.c -- RT1305 ALSA SoC amplifier component driver
4 * Copyright 2018 Realtek Semiconductor Corp.
5 * Author: Shuming Fan <shumingf@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio.h>
19 #include <linux/i2c.h>
20 #include <linux/regmap.h>
21 #include <linux/of_gpio.h>
22 #include <linux/platform_device.h>
23 #include <linux/firmware.h>
24 #include <sound/core.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/initval.h>
30 #include <sound/tlv.h>
36 #define RT1305_PR_RANGE_BASE (0xff + 1)
37 #define RT1305_PR_SPACING 0x100
39 #define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
42 static const struct regmap_range_cfg rt1305_ranges[] = {
45 .range_min = RT1305_PR_BASE,
46 .range_max = RT1305_PR_BASE + 0xff,
47 .selector_reg = RT1305_PRIV_INDEX,
48 .selector_mask = 0xff,
49 .selector_shift = 0x0,
50 .window_start = RT1305_PRIV_DATA,
56 static const struct reg_sequence init_list[] = {
58 { RT1305_PR_BASE + 0xcf, 0x5548 },
59 { RT1305_PR_BASE + 0x5d, 0x0442 },
60 { RT1305_PR_BASE + 0xc1, 0x0320 },
62 { RT1305_POWER_STATUS, 0x0000 },
64 { RT1305_SPK_TEMP_PROTECTION_1, 0xd6de },
65 { RT1305_SPK_TEMP_PROTECTION_2, 0x0707 },
66 { RT1305_SPK_TEMP_PROTECTION_3, 0x4090 },
68 { RT1305_DAC_SET_1, 0xdfdf }, /* 4 ohm 2W */
69 { RT1305_ADC_SET_3, 0x0219 },
70 { RT1305_ADC_SET_1, 0x170f }, /* 0.2 ohm RSense*/
73 #define RT1305_INIT_REG_LEN ARRAY_SIZE(init_list)
76 struct snd_soc_component *component;
77 struct regmap *regmap;
90 static const struct reg_default rt1305_reg[] = {
248 static int rt1305_reg_init(struct snd_soc_component *component)
250 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
252 regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN);
256 static bool rt1305_volatile_register(struct device *dev, unsigned int reg)
260 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
261 if (reg >= rt1305_ranges[i].range_min &&
262 reg <= rt1305_ranges[i].range_max) {
269 case RT1305_SPDIF_IN_SET_1:
270 case RT1305_SPDIF_IN_SET_2:
271 case RT1305_SPDIF_IN_SET_3:
272 case RT1305_POWER_CTRL_2:
273 case RT1305_CLOCK_DETECT:
274 case RT1305_BIQUAD_SET_1:
275 case RT1305_BIQUAD_SET_2:
276 case RT1305_EQ_SET_2:
277 case RT1305_SPK_TEMP_PROTECTION_0:
278 case RT1305_SPK_TEMP_PROTECTION_2:
279 case RT1305_SPK_DC_DETECT_1:
280 case RT1305_SILENCE_DETECT:
281 case RT1305_VERSION_ID:
282 case RT1305_VENDOR_ID:
283 case RT1305_DEVICE_ID:
286 case RT1305_DC_CALIB_1:
287 case RT1305_DC_CALIB_3:
288 case RT1305_DAC_OFFSET_1:
289 case RT1305_DAC_OFFSET_2:
290 case RT1305_DAC_OFFSET_3:
291 case RT1305_DAC_OFFSET_4:
292 case RT1305_DAC_OFFSET_5:
293 case RT1305_DAC_OFFSET_6:
294 case RT1305_DAC_OFFSET_7:
295 case RT1305_DAC_OFFSET_8:
296 case RT1305_DAC_OFFSET_9:
297 case RT1305_DAC_OFFSET_10:
298 case RT1305_DAC_OFFSET_11:
308 static bool rt1305_readable_register(struct device *dev, unsigned int reg)
312 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
313 if (reg >= rt1305_ranges[i].range_min &&
314 reg <= rt1305_ranges[i].range_max) {
321 case RT1305_CLK_1 ... RT1305_CAL_EFUSE_CLOCK:
322 case RT1305_PLL0_1 ... RT1305_PLL1_2:
323 case RT1305_MIXER_CTRL_1:
324 case RT1305_MIXER_CTRL_2:
325 case RT1305_DAC_SET_1:
326 case RT1305_DAC_SET_2:
327 case RT1305_ADC_SET_1:
328 case RT1305_ADC_SET_2:
329 case RT1305_ADC_SET_3:
330 case RT1305_PATH_SET:
331 case RT1305_SPDIF_IN_SET_1:
332 case RT1305_SPDIF_IN_SET_2:
333 case RT1305_SPDIF_IN_SET_3:
334 case RT1305_SPDIF_OUT_SET_1:
335 case RT1305_SPDIF_OUT_SET_2:
336 case RT1305_SPDIF_OUT_SET_3:
337 case RT1305_I2S_SET_1:
338 case RT1305_I2S_SET_2:
339 case RT1305_PBTL_MONO_MODE_SRC:
340 case RT1305_MANUALLY_I2C_DEVICE:
341 case RT1305_POWER_STATUS:
342 case RT1305_POWER_CTRL_1:
343 case RT1305_POWER_CTRL_2:
344 case RT1305_POWER_CTRL_3:
345 case RT1305_POWER_CTRL_4:
346 case RT1305_POWER_CTRL_5:
347 case RT1305_CLOCK_DETECT:
348 case RT1305_BIQUAD_SET_1:
349 case RT1305_BIQUAD_SET_2:
350 case RT1305_ADJUSTED_HPF_1:
351 case RT1305_ADJUSTED_HPF_2:
352 case RT1305_EQ_SET_1:
353 case RT1305_EQ_SET_2:
354 case RT1305_SPK_TEMP_PROTECTION_0:
355 case RT1305_SPK_TEMP_PROTECTION_1:
356 case RT1305_SPK_TEMP_PROTECTION_2:
357 case RT1305_SPK_TEMP_PROTECTION_3:
358 case RT1305_SPK_DC_DETECT_1:
359 case RT1305_SPK_DC_DETECT_2:
360 case RT1305_LOUDNESS:
361 case RT1305_THERMAL_FOLD_BACK_1:
362 case RT1305_THERMAL_FOLD_BACK_2:
363 case RT1305_SILENCE_DETECT ... RT1305_SPK_EXCURSION_LIMITER_7:
364 case RT1305_VERSION_ID:
365 case RT1305_VENDOR_ID:
366 case RT1305_DEVICE_ID:
370 case RT1305_DC_CALIB_1:
371 case RT1305_DC_CALIB_2:
372 case RT1305_DC_CALIB_3:
373 case RT1305_DAC_OFFSET_1 ... RT1305_DAC_OFFSET_14:
376 case RT1305_TUNE_INTERNAL_OSC:
377 case RT1305_BIQUAD1_H0_L_28_16 ... RT1305_BIQUAD3_A2_R_15_0:
384 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
386 static const char * const rt1305_rx_data_ch_select[] = {
393 static SOC_ENUM_SINGLE_DECL(rt1305_rx_data_ch_enum, RT1305_I2S_SET_2, 2,
394 rt1305_rx_data_ch_select);
396 static void rt1305_reset(struct regmap *regmap)
398 regmap_write(regmap, RT1305_RESET, 0);
401 static const struct snd_kcontrol_new rt1305_snd_controls[] = {
402 SOC_DOUBLE_TLV("DAC Playback Volume", RT1305_DAC_SET_1,
403 8, 0, 0xff, 0, dac_vol_tlv),
405 /* I2S Data Channel Selection */
406 SOC_ENUM("RX Channel Select", rt1305_rx_data_ch_enum),
409 static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source,
410 struct snd_soc_dapm_widget *sink)
412 struct snd_soc_component *component =
413 snd_soc_dapm_to_component(source->dapm);
414 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
417 snd_soc_component_read(component, RT1305_CLK_1, &val);
419 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 &&
420 (val & RT1305_SEL_PLL_SRC_2_RCCLK))
426 static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
427 struct snd_soc_dapm_widget *sink)
429 struct snd_soc_component *component =
430 snd_soc_dapm_to_component(source->dapm);
431 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
433 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1)
439 static int rt1305_classd_event(struct snd_soc_dapm_widget *w,
440 struct snd_kcontrol *kcontrol, int event)
442 struct snd_soc_component *component =
443 snd_soc_dapm_to_component(w->dapm);
446 case SND_SOC_DAPM_POST_PMU:
447 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
448 RT1305_POW_PDB_JD_MASK, RT1305_POW_PDB_JD);
450 case SND_SOC_DAPM_PRE_PMD:
451 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
452 RT1305_POW_PDB_JD_MASK, 0);
453 usleep_range(150000, 200000);
463 static const struct snd_kcontrol_new rt1305_sto_dac_l =
464 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
465 RT1305_DVOL_MUTE_L_EN_SFT, 1, 1);
467 static const struct snd_kcontrol_new rt1305_sto_dac_r =
468 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
469 RT1305_DVOL_MUTE_R_EN_SFT, 1, 1);
471 static const struct snd_soc_dapm_widget rt1305_dapm_widgets[] = {
472 SND_SOC_DAPM_SUPPLY("PLL0", RT1305_POWER_CTRL_1,
473 RT1305_POW_PLL0_EN_BIT, 0, NULL, 0),
474 SND_SOC_DAPM_SUPPLY("PLL1", RT1305_POWER_CTRL_1,
475 RT1305_POW_PLL1_EN_BIT, 0, NULL, 0),
476 SND_SOC_DAPM_SUPPLY("MBIAS", RT1305_POWER_CTRL_1,
477 RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0),
478 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1305_POWER_CTRL_1,
479 RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
480 SND_SOC_DAPM_SUPPLY("LDO2", RT1305_POWER_CTRL_1,
481 RT1305_POW_LDO2_BIT, 0, NULL, 0),
482 SND_SOC_DAPM_SUPPLY("BG2", RT1305_POWER_CTRL_1,
483 RT1305_POW_BG2_BIT, 0, NULL, 0),
484 SND_SOC_DAPM_SUPPLY("LDO2 IB2", RT1305_POWER_CTRL_1,
485 RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0),
486 SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1,
487 RT1305_POW_VREF_BIT, 0, NULL, 0),
488 SND_SOC_DAPM_SUPPLY("VREF1", RT1305_POWER_CTRL_1,
489 RT1305_POW_VREF1_BIT, 0, NULL, 0),
490 SND_SOC_DAPM_SUPPLY("VREF2", RT1305_POWER_CTRL_1,
491 RT1305_POW_VREF2_BIT, 0, NULL, 0),
494 SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2,
495 RT1305_POW_DISC_VREF_BIT, 0, NULL, 0),
496 SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2,
497 RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0),
498 SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2,
499 RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0),
500 SND_SOC_DAPM_SUPPLY("CHOP DAC", RT1305_POWER_CTRL_2,
501 RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0),
502 SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1305_POWER_CTRL_2,
503 RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0),
504 SND_SOC_DAPM_SUPPLY("CLAMP", RT1305_POWER_CTRL_2,
505 RT1305_POW_CLAMP_BIT, 0, NULL, 0),
506 SND_SOC_DAPM_SUPPLY("BUFL", RT1305_POWER_CTRL_2,
507 RT1305_POW_BUFL_BIT, 0, NULL, 0),
508 SND_SOC_DAPM_SUPPLY("BUFR", RT1305_POWER_CTRL_2,
509 RT1305_POW_BUFR_BIT, 0, NULL, 0),
510 SND_SOC_DAPM_SUPPLY("CKGEN ADC", RT1305_POWER_CTRL_2,
511 RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0),
512 SND_SOC_DAPM_SUPPLY("ADC3 L", RT1305_POWER_CTRL_2,
513 RT1305_POW_ADC3_L_BIT, 0, NULL, 0),
514 SND_SOC_DAPM_SUPPLY("ADC3 R", RT1305_POWER_CTRL_2,
515 RT1305_POW_ADC3_R_BIT, 0, NULL, 0),
516 SND_SOC_DAPM_SUPPLY("TRIOSC", RT1305_POWER_CTRL_2,
517 RT1305_POW_TRIOSC_BIT, 0, NULL, 0),
518 SND_SOC_DAPM_SUPPLY("AVDD1", RT1305_POWER_CTRL_2,
519 RT1305_POR_AVDD1_BIT, 0, NULL, 0),
520 SND_SOC_DAPM_SUPPLY("AVDD2", RT1305_POWER_CTRL_2,
521 RT1305_POR_AVDD2_BIT, 0, NULL, 0),
524 SND_SOC_DAPM_SUPPLY("VSENSE R", RT1305_POWER_CTRL_3,
525 RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0),
526 SND_SOC_DAPM_SUPPLY("VSENSE L", RT1305_POWER_CTRL_3,
527 RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0),
528 SND_SOC_DAPM_SUPPLY("ISENSE R", RT1305_POWER_CTRL_3,
529 RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0),
530 SND_SOC_DAPM_SUPPLY("ISENSE L", RT1305_POWER_CTRL_3,
531 RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0),
532 SND_SOC_DAPM_SUPPLY("POR AVDD1", RT1305_POWER_CTRL_3,
533 RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0),
534 SND_SOC_DAPM_SUPPLY("POR AVDD2", RT1305_POWER_CTRL_3,
535 RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0),
536 SND_SOC_DAPM_SUPPLY("VCM 6172", RT1305_POWER_CTRL_3,
537 RT1305_EN_VCM_6172_BIT, 0, NULL, 0),
540 /* Audio Interface */
541 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
543 /* Digital Interface */
544 SND_SOC_DAPM_SUPPLY("DAC L Power", RT1305_POWER_CTRL_2,
545 RT1305_POW_DAC1_L_BIT, 0, NULL, 0),
546 SND_SOC_DAPM_SUPPLY("DAC R Power", RT1305_POWER_CTRL_2,
547 RT1305_POW_DAC1_R_BIT, 0, NULL, 0),
548 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
549 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l),
550 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r),
553 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
555 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
556 SND_SOC_DAPM_OUTPUT("SPOL"),
557 SND_SOC_DAPM_OUTPUT("SPOR"),
560 static const struct snd_soc_dapm_route rt1305_dapm_routes[] = {
562 { "DAC", NULL, "AIF1RX" },
564 { "DAC", NULL, "PLL0", rt1305_is_rc_clk_from_pll },
565 { "DAC", NULL, "PLL1", rt1305_is_sys_clk_from_pll },
567 { "DAC", NULL, "MBIAS" },
568 { "DAC", NULL, "BG MBIAS" },
569 { "DAC", NULL, "LDO2" },
570 { "DAC", NULL, "BG2" },
571 { "DAC", NULL, "LDO2 IB2" },
572 { "DAC", NULL, "VREF" },
573 { "DAC", NULL, "VREF1" },
574 { "DAC", NULL, "VREF2" },
576 { "DAC", NULL, "DISC VREF" },
577 { "DAC", NULL, "FASTB VREF" },
578 { "DAC", NULL, "ULTRA FAST VREF" },
579 { "DAC", NULL, "CHOP DAC" },
580 { "DAC", NULL, "CKGEN DAC" },
581 { "DAC", NULL, "CLAMP" },
582 { "DAC", NULL, "CKGEN ADC" },
583 { "DAC", NULL, "TRIOSC" },
584 { "DAC", NULL, "AVDD1" },
585 { "DAC", NULL, "AVDD2" },
587 { "DAC", NULL, "POR AVDD1" },
588 { "DAC", NULL, "POR AVDD2" },
589 { "DAC", NULL, "VCM 6172" },
591 { "DAC L", "Switch", "DAC" },
592 { "DAC R", "Switch", "DAC" },
594 { "DAC R", NULL, "VSENSE R" },
595 { "DAC L", NULL, "VSENSE L" },
596 { "DAC R", NULL, "ISENSE R" },
597 { "DAC L", NULL, "ISENSE L" },
598 { "DAC L", NULL, "ADC3 L" },
599 { "DAC R", NULL, "ADC3 R" },
600 { "DAC L", NULL, "BUFL" },
601 { "DAC R", NULL, "BUFR" },
602 { "DAC L", NULL, "DAC L Power" },
603 { "DAC R", NULL, "DAC R Power" },
605 { "CLASS D", NULL, "DAC L" },
606 { "CLASS D", NULL, "DAC R" },
608 { "SPOL", NULL, "CLASS D" },
609 { "SPOR", NULL, "CLASS D" },
612 static int rt1305_get_clk_info(int sclk, int rate)
614 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
616 if (sclk <= 0 || rate <= 0)
620 for (i = 0; i < ARRAY_SIZE(pd); i++)
621 if (sclk == rate * pd[i])
627 static int rt1305_hw_params(struct snd_pcm_substream *substream,
628 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
630 struct snd_soc_component *component = dai->component;
631 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
632 unsigned int val_len = 0, val_clk, mask_clk;
633 int pre_div, bclk_ms, frame_size;
635 rt1305->lrck = params_rate(params);
636 pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck);
638 dev_warn(component->dev, "Force using PLL ");
639 snd_soc_dai_set_pll(dai, 0, RT1305_PLL1_S_BCLK,
640 rt1305->lrck * 64, rt1305->lrck * 256);
641 snd_soc_dai_set_sysclk(dai, RT1305_FS_SYS_PRE_S_PLL1,
642 rt1305->lrck * 256, SND_SOC_CLOCK_IN);
645 frame_size = snd_soc_params_to_frame_size(params);
646 if (frame_size < 0) {
647 dev_err(component->dev, "Unsupported frame size: %d\n",
652 bclk_ms = frame_size > 32;
653 rt1305->bclk = rt1305->lrck * (32 << bclk_ms);
655 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
656 bclk_ms, pre_div, dai->id);
658 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
659 rt1305->lrck, pre_div, dai->id);
661 switch (params_width(params)) {
663 val_len |= RT1305_I2S_DL_SEL_16B;
666 val_len |= RT1305_I2S_DL_SEL_20B;
669 val_len |= RT1305_I2S_DL_SEL_24B;
672 val_len |= RT1305_I2S_DL_SEL_8B;
680 mask_clk = RT1305_DIV_FS_SYS_MASK;
681 val_clk = pre_div << RT1305_DIV_FS_SYS_SFT;
682 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
683 RT1305_I2S_DL_SEL_MASK,
687 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
691 snd_soc_component_update_bits(component, RT1305_CLK_2,
697 static int rt1305_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
699 struct snd_soc_component *component = dai->component;
700 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
701 unsigned int reg_val = 0, reg1_val = 0;
703 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
704 case SND_SOC_DAIFMT_CBM_CFM:
705 reg_val |= RT1305_SEL_I2S_OUT_MODE_M;
708 case SND_SOC_DAIFMT_CBS_CFS:
709 reg_val |= RT1305_SEL_I2S_OUT_MODE_S;
716 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
717 case SND_SOC_DAIFMT_NB_NF:
719 case SND_SOC_DAIFMT_IB_NF:
720 reg1_val |= RT1305_I2S_BCLK_INV;
726 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
727 case SND_SOC_DAIFMT_I2S:
729 case SND_SOC_DAIFMT_LEFT_J:
730 reg1_val |= RT1305_I2S_DF_SEL_LEFT;
732 case SND_SOC_DAIFMT_DSP_A:
733 reg1_val |= RT1305_I2S_DF_SEL_PCM_A;
735 case SND_SOC_DAIFMT_DSP_B:
736 reg1_val |= RT1305_I2S_DF_SEL_PCM_B;
744 snd_soc_component_update_bits(component, RT1305_I2S_SET_1,
745 RT1305_SEL_I2S_OUT_MODE_MASK, reg_val);
746 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
747 RT1305_I2S_DF_SEL_MASK | RT1305_I2S_BCLK_MASK,
751 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
757 static int rt1305_set_component_sysclk(struct snd_soc_component *component,
758 int clk_id, int source, unsigned int freq, int dir)
760 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
761 unsigned int reg_val = 0;
763 if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src)
767 case RT1305_FS_SYS_PRE_S_MCLK:
768 reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK;
769 snd_soc_component_update_bits(component,
770 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
771 RT1305_SEL_CLK_DET_SRC_MCLK);
773 case RT1305_FS_SYS_PRE_S_PLL1:
774 reg_val |= RT1305_SEL_FS_SYS_PRE_PLL;
776 case RT1305_FS_SYS_PRE_S_RCCLK:
777 reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK;
780 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
783 snd_soc_component_update_bits(component, RT1305_CLK_1,
784 RT1305_SEL_FS_SYS_PRE_MASK, reg_val);
785 rt1305->sysclk = freq;
786 rt1305->sysclk_src = clk_id;
788 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
794 static int rt1305_set_component_pll(struct snd_soc_component *component,
795 int pll_id, int source, unsigned int freq_in,
796 unsigned int freq_out)
798 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
799 struct rl6231_pll_code pll_code;
802 if (source == rt1305->pll_src && freq_in == rt1305->pll_in &&
803 freq_out == rt1305->pll_out)
806 if (!freq_in || !freq_out) {
807 dev_dbg(component->dev, "PLL disabled\n");
811 snd_soc_component_update_bits(component, RT1305_CLK_1,
812 RT1305_SEL_FS_SYS_PRE_MASK | RT1305_SEL_PLL_SRC_1_MASK,
813 RT1305_SEL_FS_SYS_PRE_PLL | RT1305_SEL_PLL_SRC_1_BCLK);
818 case RT1305_PLL2_S_MCLK:
819 snd_soc_component_update_bits(component, RT1305_CLK_1,
820 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
821 RT1305_DIV_PLL_SRC_2_MASK,
822 RT1305_SEL_PLL_SRC_2_MCLK | RT1305_SEL_PLL_SRC_1_PLL2);
823 snd_soc_component_update_bits(component,
824 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
825 RT1305_SEL_CLK_DET_SRC_MCLK);
827 case RT1305_PLL1_S_BCLK:
828 snd_soc_component_update_bits(component,
829 RT1305_CLK_1, RT1305_SEL_PLL_SRC_1_MASK,
830 RT1305_SEL_PLL_SRC_1_BCLK);
832 case RT1305_PLL2_S_RCCLK:
833 snd_soc_component_update_bits(component, RT1305_CLK_1,
834 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
835 RT1305_DIV_PLL_SRC_2_MASK,
836 RT1305_SEL_PLL_SRC_2_RCCLK | RT1305_SEL_PLL_SRC_1_PLL2);
840 dev_err(component->dev, "Unknown PLL Source %d\n", source);
844 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
846 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
850 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
851 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
852 pll_code.n_code, pll_code.k_code);
854 snd_soc_component_write(component, RT1305_PLL1_1,
855 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT |
856 pll_code.m_bp << RT1305_PLL_1_M_BYPASS_SFT |
858 snd_soc_component_write(component, RT1305_PLL1_2,
861 rt1305->pll_in = freq_in;
862 rt1305->pll_out = freq_out;
863 rt1305->pll_src = source;
868 static int rt1305_probe(struct snd_soc_component *component)
870 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
872 rt1305->component = component;
874 /* initial settings */
875 rt1305_reg_init(component);
880 static void rt1305_remove(struct snd_soc_component *component)
882 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
884 rt1305_reset(rt1305->regmap);
888 static int rt1305_suspend(struct snd_soc_component *component)
890 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
892 regcache_cache_only(rt1305->regmap, true);
893 regcache_mark_dirty(rt1305->regmap);
898 static int rt1305_resume(struct snd_soc_component *component)
900 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
902 regcache_cache_only(rt1305->regmap, false);
903 regcache_sync(rt1305->regmap);
908 #define rt1305_suspend NULL
909 #define rt1305_resume NULL
912 #define RT1305_STEREO_RATES SNDRV_PCM_RATE_8000_192000
913 #define RT1305_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
914 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
915 SNDRV_PCM_FMTBIT_S24_LE)
917 static const struct snd_soc_dai_ops rt1305_aif_dai_ops = {
918 .hw_params = rt1305_hw_params,
919 .set_fmt = rt1305_set_dai_fmt,
922 static struct snd_soc_dai_driver rt1305_dai[] = {
924 .name = "rt1305-aif",
926 .stream_name = "AIF1 Playback",
929 .rates = RT1305_STEREO_RATES,
930 .formats = RT1305_FORMATS,
932 .ops = &rt1305_aif_dai_ops,
936 static const struct snd_soc_component_driver soc_component_dev_rt1305 = {
937 .probe = rt1305_probe,
938 .remove = rt1305_remove,
939 .suspend = rt1305_suspend,
940 .resume = rt1305_resume,
941 .controls = rt1305_snd_controls,
942 .num_controls = ARRAY_SIZE(rt1305_snd_controls),
943 .dapm_widgets = rt1305_dapm_widgets,
944 .num_dapm_widgets = ARRAY_SIZE(rt1305_dapm_widgets),
945 .dapm_routes = rt1305_dapm_routes,
946 .num_dapm_routes = ARRAY_SIZE(rt1305_dapm_routes),
947 .set_sysclk = rt1305_set_component_sysclk,
948 .set_pll = rt1305_set_component_pll,
949 .use_pmdown_time = 1,
951 .non_legacy_dai_naming = 1,
954 static const struct regmap_config rt1305_regmap = {
957 .max_register = RT1305_MAX_REG + 1 + (ARRAY_SIZE(rt1305_ranges) *
959 .volatile_reg = rt1305_volatile_register,
960 .readable_reg = rt1305_readable_register,
961 .cache_type = REGCACHE_RBTREE,
962 .reg_defaults = rt1305_reg,
963 .num_reg_defaults = ARRAY_SIZE(rt1305_reg),
964 .ranges = rt1305_ranges,
965 .num_ranges = ARRAY_SIZE(rt1305_ranges),
966 .use_single_read = true,
967 .use_single_write = true,
970 #if defined(CONFIG_OF)
971 static const struct of_device_id rt1305_of_match[] = {
972 { .compatible = "realtek,rt1305", },
973 { .compatible = "realtek,rt1306", },
976 MODULE_DEVICE_TABLE(of, rt1305_of_match);
980 static struct acpi_device_id rt1305_acpi_match[] = {
985 MODULE_DEVICE_TABLE(acpi, rt1305_acpi_match);
988 static const struct i2c_device_id rt1305_i2c_id[] = {
993 MODULE_DEVICE_TABLE(i2c, rt1305_i2c_id);
995 static void rt1305_calibrate(struct rt1305_priv *rt1305)
997 unsigned int valmsb, vallsb, offsetl, offsetr;
998 unsigned int rh, rl, rhl, r0ohm;
1001 regcache_cache_bypass(rt1305->regmap, true);
1003 rt1305_reset(rt1305->regmap);
1004 regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219);
1005 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548);
1006 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1007 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000);
1008 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600);
1009 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0);
1010 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1011 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1012 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1015 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1017 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000);
1018 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0);
1019 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc);
1020 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1021 regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000);
1022 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1023 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1024 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0);
1025 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1026 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1027 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1030 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1031 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1032 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1033 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1034 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1035 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1036 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000);
1037 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000);
1039 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb);
1040 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb);
1041 offsetl = valmsb << 16 | vallsb;
1042 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb);
1043 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb);
1044 offsetr = valmsb << 16 | vallsb;
1045 pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr);
1047 /* R0 calibration */
1048 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542);
1049 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1050 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1051 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe);
1052 regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13);
1053 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650);
1055 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064);
1056 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770);
1057 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c);
1058 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200);
1059 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1060 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1062 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1063 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1064 rhl = (rh << 16) | rl;
1065 r0ohm = (rhl*10) / 33554432;
1067 pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1068 pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1070 r0l = 562949953421312ULL;
1073 pr_debug("Left_r0 = 0x%llx\n", r0l);
1075 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200);
1076 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1077 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1079 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1080 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1081 rhl = (rh << 16) | rl;
1082 r0ohm = (rhl*10) / 33554432;
1084 pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1085 pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1087 r0r = 562949953421312ULL;
1090 pr_debug("Right_r0 = 0x%llx\n", r0r);
1092 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec);
1094 if ((r0l > R0_UPPER) && (r0l < R0_LOWER) &&
1095 (r0r > R0_UPPER) && (r0r < R0_LOWER)) {
1096 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e,
1097 (r0l >> 16) & 0xffff);
1098 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f,
1100 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe,
1101 ((r0r >> 16) & 0xffff) | 0xf800);
1102 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd,
1105 pr_err("R0 calibration failed\n");
1108 /* restore some registers */
1109 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1110 usleep_range(200000, 400000);
1111 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1112 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000);
1113 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400);
1114 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000);
1115 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000);
1116 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020);
1117 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000);
1119 regcache_cache_bypass(rt1305->regmap, false);
1122 static int rt1305_i2c_probe(struct i2c_client *i2c,
1123 const struct i2c_device_id *id)
1125 struct rt1305_priv *rt1305;
1129 rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv),
1134 i2c_set_clientdata(i2c, rt1305);
1136 rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap);
1137 if (IS_ERR(rt1305->regmap)) {
1138 ret = PTR_ERR(rt1305->regmap);
1139 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1144 regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val);
1145 if (val != RT1305_DEVICE_ID_NUM) {
1147 "Device with ID register %x is not rt1305\n", val);
1151 rt1305_reset(rt1305->regmap);
1152 rt1305_calibrate(rt1305);
1154 return devm_snd_soc_register_component(&i2c->dev,
1155 &soc_component_dev_rt1305,
1156 rt1305_dai, ARRAY_SIZE(rt1305_dai));
1159 static void rt1305_i2c_shutdown(struct i2c_client *client)
1161 struct rt1305_priv *rt1305 = i2c_get_clientdata(client);
1163 rt1305_reset(rt1305->regmap);
1167 static struct i2c_driver rt1305_i2c_driver = {
1170 #if defined(CONFIG_OF)
1171 .of_match_table = rt1305_of_match,
1173 #if defined(CONFIG_ACPI)
1174 .acpi_match_table = ACPI_PTR(rt1305_acpi_match)
1177 .probe = rt1305_i2c_probe,
1178 .shutdown = rt1305_i2c_shutdown,
1179 .id_table = rt1305_i2c_id,
1181 module_i2c_driver(rt1305_i2c_driver);
1183 MODULE_DESCRIPTION("ASoC RT1305 amplifier driver");
1184 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
1185 MODULE_LICENSE("GPL v2");