1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt1305.c -- RT1305 ALSA SoC amplifier component driver
5 * Copyright 2018 Realtek Semiconductor Corp.
6 * Author: Shuming Fan <shumingf@realtek.com>
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
14 #include <linux/acpi.h>
15 #include <linux/gpio.h>
16 #include <linux/i2c.h>
17 #include <linux/regmap.h>
18 #include <linux/of_gpio.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
33 #define RT1305_PR_RANGE_BASE (0xff + 1)
34 #define RT1305_PR_SPACING 0x100
36 #define RT1305_PR_BASE (RT1305_PR_RANGE_BASE + (0 * RT1305_PR_SPACING))
39 static const struct regmap_range_cfg rt1305_ranges[] = {
42 .range_min = RT1305_PR_BASE,
43 .range_max = RT1305_PR_BASE + 0xff,
44 .selector_reg = RT1305_PRIV_INDEX,
45 .selector_mask = 0xff,
46 .selector_shift = 0x0,
47 .window_start = RT1305_PRIV_DATA,
53 static const struct reg_sequence init_list[] = {
55 { RT1305_PR_BASE + 0xcf, 0x5548 },
56 { RT1305_PR_BASE + 0x5d, 0x0442 },
57 { RT1305_PR_BASE + 0xc1, 0x0320 },
59 { RT1305_POWER_STATUS, 0x0000 },
61 { RT1305_SPK_TEMP_PROTECTION_1, 0xd6de },
62 { RT1305_SPK_TEMP_PROTECTION_2, 0x0707 },
63 { RT1305_SPK_TEMP_PROTECTION_3, 0x4090 },
65 { RT1305_DAC_SET_1, 0xdfdf }, /* 4 ohm 2W */
66 { RT1305_ADC_SET_3, 0x0219 },
67 { RT1305_ADC_SET_1, 0x170f }, /* 0.2 ohm RSense*/
70 #define RT1305_INIT_REG_LEN ARRAY_SIZE(init_list)
73 struct snd_soc_component *component;
74 struct regmap *regmap;
87 static const struct reg_default rt1305_reg[] = {
245 static int rt1305_reg_init(struct snd_soc_component *component)
247 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
249 regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN);
253 static bool rt1305_volatile_register(struct device *dev, unsigned int reg)
257 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
258 if (reg >= rt1305_ranges[i].range_min &&
259 reg <= rt1305_ranges[i].range_max) {
266 case RT1305_SPDIF_IN_SET_1:
267 case RT1305_SPDIF_IN_SET_2:
268 case RT1305_SPDIF_IN_SET_3:
269 case RT1305_POWER_CTRL_2:
270 case RT1305_CLOCK_DETECT:
271 case RT1305_BIQUAD_SET_1:
272 case RT1305_BIQUAD_SET_2:
273 case RT1305_EQ_SET_2:
274 case RT1305_SPK_TEMP_PROTECTION_0:
275 case RT1305_SPK_TEMP_PROTECTION_2:
276 case RT1305_SPK_DC_DETECT_1:
277 case RT1305_SILENCE_DETECT:
278 case RT1305_VERSION_ID:
279 case RT1305_VENDOR_ID:
280 case RT1305_DEVICE_ID:
283 case RT1305_DC_CALIB_1:
284 case RT1305_DC_CALIB_3:
285 case RT1305_DAC_OFFSET_1:
286 case RT1305_DAC_OFFSET_2:
287 case RT1305_DAC_OFFSET_3:
288 case RT1305_DAC_OFFSET_4:
289 case RT1305_DAC_OFFSET_5:
290 case RT1305_DAC_OFFSET_6:
291 case RT1305_DAC_OFFSET_7:
292 case RT1305_DAC_OFFSET_8:
293 case RT1305_DAC_OFFSET_9:
294 case RT1305_DAC_OFFSET_10:
295 case RT1305_DAC_OFFSET_11:
305 static bool rt1305_readable_register(struct device *dev, unsigned int reg)
309 for (i = 0; i < ARRAY_SIZE(rt1305_ranges); i++) {
310 if (reg >= rt1305_ranges[i].range_min &&
311 reg <= rt1305_ranges[i].range_max) {
318 case RT1305_CLK_1 ... RT1305_CAL_EFUSE_CLOCK:
319 case RT1305_PLL0_1 ... RT1305_PLL1_2:
320 case RT1305_MIXER_CTRL_1:
321 case RT1305_MIXER_CTRL_2:
322 case RT1305_DAC_SET_1:
323 case RT1305_DAC_SET_2:
324 case RT1305_ADC_SET_1:
325 case RT1305_ADC_SET_2:
326 case RT1305_ADC_SET_3:
327 case RT1305_PATH_SET:
328 case RT1305_SPDIF_IN_SET_1:
329 case RT1305_SPDIF_IN_SET_2:
330 case RT1305_SPDIF_IN_SET_3:
331 case RT1305_SPDIF_OUT_SET_1:
332 case RT1305_SPDIF_OUT_SET_2:
333 case RT1305_SPDIF_OUT_SET_3:
334 case RT1305_I2S_SET_1:
335 case RT1305_I2S_SET_2:
336 case RT1305_PBTL_MONO_MODE_SRC:
337 case RT1305_MANUALLY_I2C_DEVICE:
338 case RT1305_POWER_STATUS:
339 case RT1305_POWER_CTRL_1:
340 case RT1305_POWER_CTRL_2:
341 case RT1305_POWER_CTRL_3:
342 case RT1305_POWER_CTRL_4:
343 case RT1305_POWER_CTRL_5:
344 case RT1305_CLOCK_DETECT:
345 case RT1305_BIQUAD_SET_1:
346 case RT1305_BIQUAD_SET_2:
347 case RT1305_ADJUSTED_HPF_1:
348 case RT1305_ADJUSTED_HPF_2:
349 case RT1305_EQ_SET_1:
350 case RT1305_EQ_SET_2:
351 case RT1305_SPK_TEMP_PROTECTION_0:
352 case RT1305_SPK_TEMP_PROTECTION_1:
353 case RT1305_SPK_TEMP_PROTECTION_2:
354 case RT1305_SPK_TEMP_PROTECTION_3:
355 case RT1305_SPK_DC_DETECT_1:
356 case RT1305_SPK_DC_DETECT_2:
357 case RT1305_LOUDNESS:
358 case RT1305_THERMAL_FOLD_BACK_1:
359 case RT1305_THERMAL_FOLD_BACK_2:
360 case RT1305_SILENCE_DETECT ... RT1305_SPK_EXCURSION_LIMITER_7:
361 case RT1305_VERSION_ID:
362 case RT1305_VENDOR_ID:
363 case RT1305_DEVICE_ID:
367 case RT1305_DC_CALIB_1:
368 case RT1305_DC_CALIB_2:
369 case RT1305_DC_CALIB_3:
370 case RT1305_DAC_OFFSET_1 ... RT1305_DAC_OFFSET_14:
373 case RT1305_TUNE_INTERNAL_OSC:
374 case RT1305_BIQUAD1_H0_L_28_16 ... RT1305_BIQUAD3_A2_R_15_0:
381 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
383 static const char * const rt1305_rx_data_ch_select[] = {
390 static SOC_ENUM_SINGLE_DECL(rt1305_rx_data_ch_enum, RT1305_I2S_SET_2, 2,
391 rt1305_rx_data_ch_select);
393 static void rt1305_reset(struct regmap *regmap)
395 regmap_write(regmap, RT1305_RESET, 0);
398 static const struct snd_kcontrol_new rt1305_snd_controls[] = {
399 SOC_DOUBLE_TLV("DAC Playback Volume", RT1305_DAC_SET_1,
400 8, 0, 0xff, 0, dac_vol_tlv),
402 /* I2S Data Channel Selection */
403 SOC_ENUM("RX Channel Select", rt1305_rx_data_ch_enum),
406 static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source,
407 struct snd_soc_dapm_widget *sink)
409 struct snd_soc_component *component =
410 snd_soc_dapm_to_component(source->dapm);
411 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
414 snd_soc_component_read(component, RT1305_CLK_1, &val);
416 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 &&
417 (val & RT1305_SEL_PLL_SRC_2_RCCLK))
423 static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
424 struct snd_soc_dapm_widget *sink)
426 struct snd_soc_component *component =
427 snd_soc_dapm_to_component(source->dapm);
428 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
430 if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1)
436 static int rt1305_classd_event(struct snd_soc_dapm_widget *w,
437 struct snd_kcontrol *kcontrol, int event)
439 struct snd_soc_component *component =
440 snd_soc_dapm_to_component(w->dapm);
443 case SND_SOC_DAPM_POST_PMU:
444 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
445 RT1305_POW_PDB_JD_MASK, RT1305_POW_PDB_JD);
447 case SND_SOC_DAPM_PRE_PMD:
448 snd_soc_component_update_bits(component, RT1305_POWER_CTRL_1,
449 RT1305_POW_PDB_JD_MASK, 0);
450 usleep_range(150000, 200000);
460 static const struct snd_kcontrol_new rt1305_sto_dac_l =
461 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
462 RT1305_DVOL_MUTE_L_EN_SFT, 1, 1);
464 static const struct snd_kcontrol_new rt1305_sto_dac_r =
465 SOC_DAPM_SINGLE("Switch", RT1305_DAC_SET_2,
466 RT1305_DVOL_MUTE_R_EN_SFT, 1, 1);
468 static const struct snd_soc_dapm_widget rt1305_dapm_widgets[] = {
469 SND_SOC_DAPM_SUPPLY("PLL0", RT1305_POWER_CTRL_1,
470 RT1305_POW_PLL0_EN_BIT, 0, NULL, 0),
471 SND_SOC_DAPM_SUPPLY("PLL1", RT1305_POWER_CTRL_1,
472 RT1305_POW_PLL1_EN_BIT, 0, NULL, 0),
473 SND_SOC_DAPM_SUPPLY("MBIAS", RT1305_POWER_CTRL_1,
474 RT1305_POW_MBIAS_LV_BIT, 0, NULL, 0),
475 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1305_POWER_CTRL_1,
476 RT1305_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
477 SND_SOC_DAPM_SUPPLY("LDO2", RT1305_POWER_CTRL_1,
478 RT1305_POW_LDO2_BIT, 0, NULL, 0),
479 SND_SOC_DAPM_SUPPLY("BG2", RT1305_POWER_CTRL_1,
480 RT1305_POW_BG2_BIT, 0, NULL, 0),
481 SND_SOC_DAPM_SUPPLY("LDO2 IB2", RT1305_POWER_CTRL_1,
482 RT1305_POW_LDO2_IB2_BIT, 0, NULL, 0),
483 SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1,
484 RT1305_POW_VREF_BIT, 0, NULL, 0),
485 SND_SOC_DAPM_SUPPLY("VREF1", RT1305_POWER_CTRL_1,
486 RT1305_POW_VREF1_BIT, 0, NULL, 0),
487 SND_SOC_DAPM_SUPPLY("VREF2", RT1305_POWER_CTRL_1,
488 RT1305_POW_VREF2_BIT, 0, NULL, 0),
491 SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2,
492 RT1305_POW_DISC_VREF_BIT, 0, NULL, 0),
493 SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2,
494 RT1305_POW_FASTB_VREF_BIT, 0, NULL, 0),
495 SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2,
496 RT1305_POW_ULTRA_FAST_VREF_BIT, 0, NULL, 0),
497 SND_SOC_DAPM_SUPPLY("CHOP DAC", RT1305_POWER_CTRL_2,
498 RT1305_POW_CKXEN_DAC_BIT, 0, NULL, 0),
499 SND_SOC_DAPM_SUPPLY("CKGEN DAC", RT1305_POWER_CTRL_2,
500 RT1305_POW_EN_CKGEN_DAC_BIT, 0, NULL, 0),
501 SND_SOC_DAPM_SUPPLY("CLAMP", RT1305_POWER_CTRL_2,
502 RT1305_POW_CLAMP_BIT, 0, NULL, 0),
503 SND_SOC_DAPM_SUPPLY("BUFL", RT1305_POWER_CTRL_2,
504 RT1305_POW_BUFL_BIT, 0, NULL, 0),
505 SND_SOC_DAPM_SUPPLY("BUFR", RT1305_POWER_CTRL_2,
506 RT1305_POW_BUFR_BIT, 0, NULL, 0),
507 SND_SOC_DAPM_SUPPLY("CKGEN ADC", RT1305_POWER_CTRL_2,
508 RT1305_POW_EN_CKGEN_ADC_BIT, 0, NULL, 0),
509 SND_SOC_DAPM_SUPPLY("ADC3 L", RT1305_POWER_CTRL_2,
510 RT1305_POW_ADC3_L_BIT, 0, NULL, 0),
511 SND_SOC_DAPM_SUPPLY("ADC3 R", RT1305_POWER_CTRL_2,
512 RT1305_POW_ADC3_R_BIT, 0, NULL, 0),
513 SND_SOC_DAPM_SUPPLY("TRIOSC", RT1305_POWER_CTRL_2,
514 RT1305_POW_TRIOSC_BIT, 0, NULL, 0),
515 SND_SOC_DAPM_SUPPLY("AVDD1", RT1305_POWER_CTRL_2,
516 RT1305_POR_AVDD1_BIT, 0, NULL, 0),
517 SND_SOC_DAPM_SUPPLY("AVDD2", RT1305_POWER_CTRL_2,
518 RT1305_POR_AVDD2_BIT, 0, NULL, 0),
521 SND_SOC_DAPM_SUPPLY("VSENSE R", RT1305_POWER_CTRL_3,
522 RT1305_POW_VSENSE_RCH_BIT, 0, NULL, 0),
523 SND_SOC_DAPM_SUPPLY("VSENSE L", RT1305_POWER_CTRL_3,
524 RT1305_POW_VSENSE_LCH_BIT, 0, NULL, 0),
525 SND_SOC_DAPM_SUPPLY("ISENSE R", RT1305_POWER_CTRL_3,
526 RT1305_POW_ISENSE_RCH_BIT, 0, NULL, 0),
527 SND_SOC_DAPM_SUPPLY("ISENSE L", RT1305_POWER_CTRL_3,
528 RT1305_POW_ISENSE_LCH_BIT, 0, NULL, 0),
529 SND_SOC_DAPM_SUPPLY("POR AVDD1", RT1305_POWER_CTRL_3,
530 RT1305_POW_POR_AVDD1_BIT, 0, NULL, 0),
531 SND_SOC_DAPM_SUPPLY("POR AVDD2", RT1305_POWER_CTRL_3,
532 RT1305_POW_POR_AVDD2_BIT, 0, NULL, 0),
533 SND_SOC_DAPM_SUPPLY("VCM 6172", RT1305_POWER_CTRL_3,
534 RT1305_EN_VCM_6172_BIT, 0, NULL, 0),
537 /* Audio Interface */
538 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
540 /* Digital Interface */
541 SND_SOC_DAPM_SUPPLY("DAC L Power", RT1305_POWER_CTRL_2,
542 RT1305_POW_DAC1_L_BIT, 0, NULL, 0),
543 SND_SOC_DAPM_SUPPLY("DAC R Power", RT1305_POWER_CTRL_2,
544 RT1305_POW_DAC1_R_BIT, 0, NULL, 0),
545 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
546 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_l),
547 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1305_sto_dac_r),
550 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
552 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
553 SND_SOC_DAPM_OUTPUT("SPOL"),
554 SND_SOC_DAPM_OUTPUT("SPOR"),
557 static const struct snd_soc_dapm_route rt1305_dapm_routes[] = {
559 { "DAC", NULL, "AIF1RX" },
561 { "DAC", NULL, "PLL0", rt1305_is_rc_clk_from_pll },
562 { "DAC", NULL, "PLL1", rt1305_is_sys_clk_from_pll },
564 { "DAC", NULL, "MBIAS" },
565 { "DAC", NULL, "BG MBIAS" },
566 { "DAC", NULL, "LDO2" },
567 { "DAC", NULL, "BG2" },
568 { "DAC", NULL, "LDO2 IB2" },
569 { "DAC", NULL, "VREF" },
570 { "DAC", NULL, "VREF1" },
571 { "DAC", NULL, "VREF2" },
573 { "DAC", NULL, "DISC VREF" },
574 { "DAC", NULL, "FASTB VREF" },
575 { "DAC", NULL, "ULTRA FAST VREF" },
576 { "DAC", NULL, "CHOP DAC" },
577 { "DAC", NULL, "CKGEN DAC" },
578 { "DAC", NULL, "CLAMP" },
579 { "DAC", NULL, "CKGEN ADC" },
580 { "DAC", NULL, "TRIOSC" },
581 { "DAC", NULL, "AVDD1" },
582 { "DAC", NULL, "AVDD2" },
584 { "DAC", NULL, "POR AVDD1" },
585 { "DAC", NULL, "POR AVDD2" },
586 { "DAC", NULL, "VCM 6172" },
588 { "DAC L", "Switch", "DAC" },
589 { "DAC R", "Switch", "DAC" },
591 { "DAC R", NULL, "VSENSE R" },
592 { "DAC L", NULL, "VSENSE L" },
593 { "DAC R", NULL, "ISENSE R" },
594 { "DAC L", NULL, "ISENSE L" },
595 { "DAC L", NULL, "ADC3 L" },
596 { "DAC R", NULL, "ADC3 R" },
597 { "DAC L", NULL, "BUFL" },
598 { "DAC R", NULL, "BUFR" },
599 { "DAC L", NULL, "DAC L Power" },
600 { "DAC R", NULL, "DAC R Power" },
602 { "CLASS D", NULL, "DAC L" },
603 { "CLASS D", NULL, "DAC R" },
605 { "SPOL", NULL, "CLASS D" },
606 { "SPOR", NULL, "CLASS D" },
609 static int rt1305_get_clk_info(int sclk, int rate)
611 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
613 if (sclk <= 0 || rate <= 0)
617 for (i = 0; i < ARRAY_SIZE(pd); i++)
618 if (sclk == rate * pd[i])
624 static int rt1305_hw_params(struct snd_pcm_substream *substream,
625 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
627 struct snd_soc_component *component = dai->component;
628 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
629 unsigned int val_len = 0, val_clk, mask_clk;
630 int pre_div, bclk_ms, frame_size;
632 rt1305->lrck = params_rate(params);
633 pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck);
635 dev_warn(component->dev, "Force using PLL ");
636 snd_soc_dai_set_pll(dai, 0, RT1305_PLL1_S_BCLK,
637 rt1305->lrck * 64, rt1305->lrck * 256);
638 snd_soc_dai_set_sysclk(dai, RT1305_FS_SYS_PRE_S_PLL1,
639 rt1305->lrck * 256, SND_SOC_CLOCK_IN);
642 frame_size = snd_soc_params_to_frame_size(params);
643 if (frame_size < 0) {
644 dev_err(component->dev, "Unsupported frame size: %d\n",
649 bclk_ms = frame_size > 32;
650 rt1305->bclk = rt1305->lrck * (32 << bclk_ms);
652 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
653 bclk_ms, pre_div, dai->id);
655 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
656 rt1305->lrck, pre_div, dai->id);
658 switch (params_width(params)) {
660 val_len |= RT1305_I2S_DL_SEL_16B;
663 val_len |= RT1305_I2S_DL_SEL_20B;
666 val_len |= RT1305_I2S_DL_SEL_24B;
669 val_len |= RT1305_I2S_DL_SEL_8B;
677 mask_clk = RT1305_DIV_FS_SYS_MASK;
678 val_clk = pre_div << RT1305_DIV_FS_SYS_SFT;
679 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
680 RT1305_I2S_DL_SEL_MASK,
684 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
688 snd_soc_component_update_bits(component, RT1305_CLK_2,
694 static int rt1305_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
696 struct snd_soc_component *component = dai->component;
697 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
698 unsigned int reg_val = 0, reg1_val = 0;
700 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
701 case SND_SOC_DAIFMT_CBM_CFM:
702 reg_val |= RT1305_SEL_I2S_OUT_MODE_M;
705 case SND_SOC_DAIFMT_CBS_CFS:
706 reg_val |= RT1305_SEL_I2S_OUT_MODE_S;
713 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
714 case SND_SOC_DAIFMT_NB_NF:
716 case SND_SOC_DAIFMT_IB_NF:
717 reg1_val |= RT1305_I2S_BCLK_INV;
723 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
724 case SND_SOC_DAIFMT_I2S:
726 case SND_SOC_DAIFMT_LEFT_J:
727 reg1_val |= RT1305_I2S_DF_SEL_LEFT;
729 case SND_SOC_DAIFMT_DSP_A:
730 reg1_val |= RT1305_I2S_DF_SEL_PCM_A;
732 case SND_SOC_DAIFMT_DSP_B:
733 reg1_val |= RT1305_I2S_DF_SEL_PCM_B;
741 snd_soc_component_update_bits(component, RT1305_I2S_SET_1,
742 RT1305_SEL_I2S_OUT_MODE_MASK, reg_val);
743 snd_soc_component_update_bits(component, RT1305_I2S_SET_2,
744 RT1305_I2S_DF_SEL_MASK | RT1305_I2S_BCLK_MASK,
748 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
754 static int rt1305_set_component_sysclk(struct snd_soc_component *component,
755 int clk_id, int source, unsigned int freq, int dir)
757 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
758 unsigned int reg_val = 0;
760 if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src)
764 case RT1305_FS_SYS_PRE_S_MCLK:
765 reg_val |= RT1305_SEL_FS_SYS_PRE_MCLK;
766 snd_soc_component_update_bits(component,
767 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
768 RT1305_SEL_CLK_DET_SRC_MCLK);
770 case RT1305_FS_SYS_PRE_S_PLL1:
771 reg_val |= RT1305_SEL_FS_SYS_PRE_PLL;
773 case RT1305_FS_SYS_PRE_S_RCCLK:
774 reg_val |= RT1305_SEL_FS_SYS_PRE_RCCLK;
777 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
780 snd_soc_component_update_bits(component, RT1305_CLK_1,
781 RT1305_SEL_FS_SYS_PRE_MASK, reg_val);
782 rt1305->sysclk = freq;
783 rt1305->sysclk_src = clk_id;
785 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
791 static int rt1305_set_component_pll(struct snd_soc_component *component,
792 int pll_id, int source, unsigned int freq_in,
793 unsigned int freq_out)
795 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
796 struct rl6231_pll_code pll_code;
799 if (source == rt1305->pll_src && freq_in == rt1305->pll_in &&
800 freq_out == rt1305->pll_out)
803 if (!freq_in || !freq_out) {
804 dev_dbg(component->dev, "PLL disabled\n");
808 snd_soc_component_update_bits(component, RT1305_CLK_1,
809 RT1305_SEL_FS_SYS_PRE_MASK | RT1305_SEL_PLL_SRC_1_MASK,
810 RT1305_SEL_FS_SYS_PRE_PLL | RT1305_SEL_PLL_SRC_1_BCLK);
815 case RT1305_PLL2_S_MCLK:
816 snd_soc_component_update_bits(component, RT1305_CLK_1,
817 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
818 RT1305_DIV_PLL_SRC_2_MASK,
819 RT1305_SEL_PLL_SRC_2_MCLK | RT1305_SEL_PLL_SRC_1_PLL2);
820 snd_soc_component_update_bits(component,
821 RT1305_CLOCK_DETECT, RT1305_SEL_CLK_DET_SRC_MASK,
822 RT1305_SEL_CLK_DET_SRC_MCLK);
824 case RT1305_PLL1_S_BCLK:
825 snd_soc_component_update_bits(component,
826 RT1305_CLK_1, RT1305_SEL_PLL_SRC_1_MASK,
827 RT1305_SEL_PLL_SRC_1_BCLK);
829 case RT1305_PLL2_S_RCCLK:
830 snd_soc_component_update_bits(component, RT1305_CLK_1,
831 RT1305_SEL_PLL_SRC_2_MASK | RT1305_SEL_PLL_SRC_1_MASK |
832 RT1305_DIV_PLL_SRC_2_MASK,
833 RT1305_SEL_PLL_SRC_2_RCCLK | RT1305_SEL_PLL_SRC_1_PLL2);
837 dev_err(component->dev, "Unknown PLL Source %d\n", source);
841 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
843 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
847 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
848 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
849 pll_code.n_code, pll_code.k_code);
851 snd_soc_component_write(component, RT1305_PLL1_1,
852 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1305_PLL_1_M_SFT |
853 pll_code.m_bp << RT1305_PLL_1_M_BYPASS_SFT |
855 snd_soc_component_write(component, RT1305_PLL1_2,
858 rt1305->pll_in = freq_in;
859 rt1305->pll_out = freq_out;
860 rt1305->pll_src = source;
865 static int rt1305_probe(struct snd_soc_component *component)
867 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
869 rt1305->component = component;
871 /* initial settings */
872 rt1305_reg_init(component);
877 static void rt1305_remove(struct snd_soc_component *component)
879 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
881 rt1305_reset(rt1305->regmap);
885 static int rt1305_suspend(struct snd_soc_component *component)
887 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
889 regcache_cache_only(rt1305->regmap, true);
890 regcache_mark_dirty(rt1305->regmap);
895 static int rt1305_resume(struct snd_soc_component *component)
897 struct rt1305_priv *rt1305 = snd_soc_component_get_drvdata(component);
899 regcache_cache_only(rt1305->regmap, false);
900 regcache_sync(rt1305->regmap);
905 #define rt1305_suspend NULL
906 #define rt1305_resume NULL
909 #define RT1305_STEREO_RATES SNDRV_PCM_RATE_8000_192000
910 #define RT1305_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
911 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
912 SNDRV_PCM_FMTBIT_S24_LE)
914 static const struct snd_soc_dai_ops rt1305_aif_dai_ops = {
915 .hw_params = rt1305_hw_params,
916 .set_fmt = rt1305_set_dai_fmt,
919 static struct snd_soc_dai_driver rt1305_dai[] = {
921 .name = "rt1305-aif",
923 .stream_name = "AIF1 Playback",
926 .rates = RT1305_STEREO_RATES,
927 .formats = RT1305_FORMATS,
929 .ops = &rt1305_aif_dai_ops,
933 static const struct snd_soc_component_driver soc_component_dev_rt1305 = {
934 .probe = rt1305_probe,
935 .remove = rt1305_remove,
936 .suspend = rt1305_suspend,
937 .resume = rt1305_resume,
938 .controls = rt1305_snd_controls,
939 .num_controls = ARRAY_SIZE(rt1305_snd_controls),
940 .dapm_widgets = rt1305_dapm_widgets,
941 .num_dapm_widgets = ARRAY_SIZE(rt1305_dapm_widgets),
942 .dapm_routes = rt1305_dapm_routes,
943 .num_dapm_routes = ARRAY_SIZE(rt1305_dapm_routes),
944 .set_sysclk = rt1305_set_component_sysclk,
945 .set_pll = rt1305_set_component_pll,
946 .use_pmdown_time = 1,
948 .non_legacy_dai_naming = 1,
951 static const struct regmap_config rt1305_regmap = {
954 .max_register = RT1305_MAX_REG + 1 + (ARRAY_SIZE(rt1305_ranges) *
956 .volatile_reg = rt1305_volatile_register,
957 .readable_reg = rt1305_readable_register,
958 .cache_type = REGCACHE_RBTREE,
959 .reg_defaults = rt1305_reg,
960 .num_reg_defaults = ARRAY_SIZE(rt1305_reg),
961 .ranges = rt1305_ranges,
962 .num_ranges = ARRAY_SIZE(rt1305_ranges),
963 .use_single_read = true,
964 .use_single_write = true,
967 #if defined(CONFIG_OF)
968 static const struct of_device_id rt1305_of_match[] = {
969 { .compatible = "realtek,rt1305", },
970 { .compatible = "realtek,rt1306", },
973 MODULE_DEVICE_TABLE(of, rt1305_of_match);
977 static struct acpi_device_id rt1305_acpi_match[] = {
982 MODULE_DEVICE_TABLE(acpi, rt1305_acpi_match);
985 static const struct i2c_device_id rt1305_i2c_id[] = {
990 MODULE_DEVICE_TABLE(i2c, rt1305_i2c_id);
992 static void rt1305_calibrate(struct rt1305_priv *rt1305)
994 unsigned int valmsb, vallsb, offsetl, offsetr;
995 unsigned int rh, rl, rhl, r0ohm;
998 regcache_cache_bypass(rt1305->regmap, true);
1000 rt1305_reset(rt1305->regmap);
1001 regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219);
1002 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548);
1003 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1004 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000);
1005 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600);
1006 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0);
1007 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1008 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1009 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1012 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1014 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000);
1015 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0);
1016 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc);
1017 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);
1018 regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000);
1019 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1020 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1021 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0);
1022 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1023 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1024 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1027 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);
1028 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1029 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);
1030 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);
1031 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);
1032 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);
1033 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000);
1034 regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000);
1036 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb);
1037 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb);
1038 offsetl = valmsb << 16 | vallsb;
1039 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb);
1040 regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb);
1041 offsetr = valmsb << 16 | vallsb;
1042 pr_info("DC offsetl=0x%x, offsetr=0x%x\n", offsetl, offsetr);
1044 /* R0 calibration */
1045 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542);
1046 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);
1047 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);
1048 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe);
1049 regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13);
1050 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650);
1052 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064);
1053 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770);
1054 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c);
1055 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200);
1056 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1057 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1059 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1060 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1061 rhl = (rh << 16) | rl;
1062 r0ohm = (rhl*10) / 33554432;
1064 pr_debug("Left_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1065 pr_info("Left channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1067 r0l = 562949953421312ULL;
1070 pr_debug("Left_r0 = 0x%llx\n", r0l);
1072 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200);
1073 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);
1074 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);
1076 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);
1077 regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);
1078 rhl = (rh << 16) | rl;
1079 r0ohm = (rhl*10) / 33554432;
1081 pr_debug("Right_rhl = 0x%x rh=0x%x rl=0x%x\n", rhl, rh, rl);
1082 pr_info("Right channel %d.%dohm\n", (r0ohm/10), (r0ohm%10));
1084 r0r = 562949953421312ULL;
1087 pr_debug("Right_r0 = 0x%llx\n", r0r);
1089 regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec);
1091 if ((r0l > R0_UPPER) && (r0l < R0_LOWER) &&
1092 (r0r > R0_UPPER) && (r0r < R0_LOWER)) {
1093 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e,
1094 (r0l >> 16) & 0xffff);
1095 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f,
1097 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe,
1098 ((r0r >> 16) & 0xffff) | 0xf800);
1099 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd,
1102 pr_err("R0 calibration failed\n");
1105 /* restore some registers */
1106 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);
1107 usleep_range(200000, 400000);
1108 regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);
1109 regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000);
1110 regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400);
1111 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000);
1112 regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000);
1113 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020);
1114 regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000);
1116 regcache_cache_bypass(rt1305->regmap, false);
1119 static int rt1305_i2c_probe(struct i2c_client *i2c,
1120 const struct i2c_device_id *id)
1122 struct rt1305_priv *rt1305;
1126 rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv),
1131 i2c_set_clientdata(i2c, rt1305);
1133 rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap);
1134 if (IS_ERR(rt1305->regmap)) {
1135 ret = PTR_ERR(rt1305->regmap);
1136 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1141 regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val);
1142 if (val != RT1305_DEVICE_ID_NUM) {
1144 "Device with ID register %x is not rt1305\n", val);
1148 rt1305_reset(rt1305->regmap);
1149 rt1305_calibrate(rt1305);
1151 return devm_snd_soc_register_component(&i2c->dev,
1152 &soc_component_dev_rt1305,
1153 rt1305_dai, ARRAY_SIZE(rt1305_dai));
1156 static void rt1305_i2c_shutdown(struct i2c_client *client)
1158 struct rt1305_priv *rt1305 = i2c_get_clientdata(client);
1160 rt1305_reset(rt1305->regmap);
1164 static struct i2c_driver rt1305_i2c_driver = {
1167 #if defined(CONFIG_OF)
1168 .of_match_table = rt1305_of_match,
1170 #if defined(CONFIG_ACPI)
1171 .acpi_match_table = ACPI_PTR(rt1305_acpi_match)
1174 .probe = rt1305_i2c_probe,
1175 .shutdown = rt1305_i2c_shutdown,
1176 .id_table = rt1305_i2c_id,
1178 module_i2c_driver(rt1305_i2c_driver);
1180 MODULE_DESCRIPTION("ASoC RT1305 amplifier driver");
1181 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
1182 MODULE_LICENSE("GPL v2");