Merge tag 'v5.13-rc2' into spi-5.13
[linux-2.6-microblaze.git] / sound / soc / codecs / rt1019.h
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * rt1019.h  --  RT1019 ALSA SoC audio amplifier driver
4  *
5  * Copyright(c) 2021 Realtek Semiconductor Corp.
6  */
7
8 #ifndef __RT1019_H__
9 #define __RT1019_H__
10
11 #define RT1019_DEVICE_ID_VAL                    0x1019
12 #define RT1019_DEVICE_ID_VAL2                   0x6731
13
14 #define RT1019_RESET                            0x0000
15 #define RT1019_IDS_CTRL                         0x0011
16 #define RT1019_ASEL_CTRL                        0x0013
17 #define RT1019_PWR_STRP_2                       0x0019
18 #define RT1019_BEEP_TONE                        0x001b
19 #define RT1019_VER_ID                           0x005c
20 #define RT1019_VEND_ID_1                        0x005e
21 #define RT1019_VEND_ID_2                        0x005f
22 #define RT1019_DEV_ID_1                         0x0061
23 #define RT1019_DEV_ID_2                         0x0062
24 #define RT1019_SDB_CTRL                         0x0066
25 #define RT1019_CLK_TREE_1                       0x0100
26 #define RT1019_CLK_TREE_2                       0x0101
27 #define RT1019_CLK_TREE_3                       0x0102
28 #define RT1019_PLL_1                            0x0311
29 #define RT1019_PLL_2                            0x0312
30 #define RT1019_PLL_3                            0x0313
31 #define RT1019_TDM_1                            0x0400
32 #define RT1019_TDM_2                            0x0401
33 #define RT1019_TDM_3                            0x0402
34 #define RT1019_DMIX_MONO_1                      0x0504
35 #define RT1019_DMIX_MONO_2                      0x0505
36 #define RT1019_BEEP_1                           0x0b00
37 #define RT1019_BEEP_2                           0x0b01
38
39 /* 0x0019 Power On Strap Control-2 */
40 #define RT1019_AUTO_BITS_SEL_MASK               (0x1 << 5)
41 #define RT1019_AUTO_BITS_SEL_AUTO               (0x1 << 5)
42 #define RT1019_AUTO_BITS_SEL_MANU               (0x0 << 5)
43 #define RT1019_AUTO_CLK_SEL_MASK                (0x1 << 4)
44 #define RT1019_AUTO_CLK_SEL_AUTO                (0x1 << 4)
45 #define RT1019_AUTO_CLK_SEL_MANU                (0x0 << 4)
46
47 /* 0x0100 Clock Tree Control-1 */
48 #define RT1019_CLK_SYS_PRE_SEL_MASK             (0x1 << 7)
49 #define RT1019_CLK_SYS_PRE_SEL_SFT              7
50 #define RT1019_CLK_SYS_PRE_SEL_BCLK             (0x0 << 7)
51 #define RT1019_CLK_SYS_PRE_SEL_PLL              (0x1 << 7)
52 #define RT1019_PLL_SRC_MASK                             (0x1 << 4)
53 #define RT1019_PLL_SRC_SFT                              4
54 #define RT1019_PLL_SRC_SEL_BCLK                 (0x0 << 4)
55 #define RT1019_PLL_SRC_SEL_RC                   (0x1 << 4)
56 #define RT1019_SEL_FIFO_MASK                    (0x3 << 2)
57 #define RT1019_SEL_FIFO_DIV1                    (0x0 << 2)
58 #define RT1019_SEL_FIFO_DIV2                    (0x1 << 2)
59 #define RT1019_SEL_FIFO_DIV4                    (0x2 << 2)
60
61 /* 0x0101 clock tree control-2 */
62 #define RT1019_SYS_DIV_DA_FIL_MASK              (0x7 << 5)
63 #define RT1019_SYS_DIV_DA_FIL_DIV1              (0x2 << 5)
64 #define RT1019_SYS_DIV_DA_FIL_DIV2              (0x3 << 5)
65 #define RT1019_SYS_DIV_DA_FIL_DIV4              (0x4 << 5)
66 #define RT1019_SYS_DA_OSR_MASK                  (0x3 << 2)
67 #define RT1019_SYS_DA_OSR_DIV1                  (0x0 << 2)
68 #define RT1019_SYS_DA_OSR_DIV2                  (0x1 << 2)
69 #define RT1019_SYS_DA_OSR_DIV4                  (0x2 << 2)
70 #define RT1019_ASRC_256FS_MASK                  0x3
71 #define RT1019_ASRC_256FS_DIV1                  0x0
72 #define RT1019_ASRC_256FS_DIV2                  0x1
73 #define RT1019_ASRC_256FS_DIV4                  0x2
74
75 /* 0x0102 clock tree control-3 */
76 #define RT1019_SEL_CLK_CAL_MASK                 (0x3 << 6)
77 #define RT1019_SEL_CLK_CAL_DIV1                 (0x0 << 6)
78 #define RT1019_SEL_CLK_CAL_DIV2                 (0x1 << 6)
79 #define RT1019_SEL_CLK_CAL_DIV4                 (0x2 << 6)
80
81 /* 0x0311 PLL-1 */
82 #define RT1019_PLL_M_MASK                       (0xf << 4)
83 #define RT1019_PLL_M_SFT                        4
84 #define RT1019_PLL_M_BP_MASK            (0x1 << 1)
85 #define RT1019_PLL_M_BP_SFT                     1
86 #define RT1019_PLL_Q_8_8_MASK           (0x1)
87
88 /* 0x0312 PLL-2 */
89 #define RT1019_PLL_Q_7_0_MASK           0xff
90
91 /* 0x0313 PLL-3 */
92 #define RT1019_PLL_K_MASK               0x1f
93
94 /* 0x0400 TDM Control-1 */
95 #define RT1019_TDM_BCLK_MASK            (0x1 << 6)
96 #define RT1019_TDM_BCLK_NORM            (0x0 << 6)
97 #define RT1019_TDM_BCLK_INV                     (0x1 << 6)
98
99 /* 0x0401 TDM Control-2 */
100 #define RT1019_I2S_CH_TX_MASK           (0x3 << 6)
101 #define RT1019_I2S_CH_TX_SFT            6
102 #define RT1019_I2S_TX_2CH                       (0x0 << 6)
103 #define RT1019_I2S_TX_4CH                       (0x1 << 6)
104 #define RT1019_I2S_TX_6CH                       (0x2 << 6)
105 #define RT1019_I2S_TX_8CH                       (0x3 << 6)
106 #define RT1019_I2S_DF_MASK                      (0x7 << 3)
107 #define RT1019_I2S_DF_SFT                       3
108 #define RT1019_I2S_DF_I2S                       (0x0 << 3)
109 #define RT1019_I2S_DF_LEFT                      (0x1 << 3)
110 #define RT1019_I2S_DF_PCM_A_R           (0x2 << 3)
111 #define RT1019_I2S_DF_PCM_B_R           (0x3 << 3)
112 #define RT1019_I2S_DF_PCM_A_F           (0x6 << 3)
113 #define RT1019_I2S_DF_PCM_B_F           (0x7 << 3)
114 #define RT1019_I2S_DL_MASK                      0x7
115 #define RT1019_I2S_DL_SFT                       0
116 #define RT1019_I2S_DL_16                        0x0
117 #define RT1019_I2S_DL_20                        0x1
118 #define RT1019_I2S_DL_24                        0x2
119 #define RT1019_I2S_DL_32                        0x3
120 #define RT1019_I2S_DL_8                         0x4
121
122 /* TDM1 Control-3 (0x0402) */
123 #define RT1019_TDM_I2S_TX_L_DAC1_1_MASK         (0x7 << 4)
124 #define RT1019_TDM_I2S_TX_R_DAC1_1_MASK         0x7
125 #define RT1019_TDM_I2S_TX_L_DAC1_1_SFT          4
126 #define RT1019_TDM_I2S_TX_R_DAC1_1_SFT          0
127
128 /* System Clock Source */
129 enum {
130         RT1019_SCLK_S_BCLK,
131         RT1019_SCLK_S_PLL,
132 };
133
134 /* PLL1 Source */
135 enum {
136         RT1019_PLL_S_BCLK,
137         RT1019_PLL_S_RC25M,
138 };
139
140 enum {
141         RT1019_AIF1,
142         RT1019_AIFS
143 };
144
145 struct rt1019_priv {
146         struct snd_soc_component *component;
147         struct regmap *regmap;
148         int sysclk;
149         int sysclk_src;
150         int lrck;
151         int bclk;
152         int pll_src;
153         int pll_in;
154         int pll_out;
155         unsigned int bclk_ratio;
156 };
157
158 #endif /* __RT1019_H__ */