1 // SPDX-License-Identifier: GPL-2.0
3 // rt1015.c -- RT1015 ALSA SoC audio amplifier driver
5 // Copyright 2019 Realtek Semiconductor Corp.
7 // Author: Jack Yu <jack.yu@realtek.com>
11 #include <linux/acpi.h>
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
15 #include <linux/gpio.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <sound/core.h>
24 #include <sound/initval.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/rt1015.h>
28 #include <sound/soc-dapm.h>
29 #include <sound/soc.h>
30 #include <sound/tlv.h>
35 static const struct rt1015_platform_data i2s_default_platform_data = {
36 .power_up_delay_ms = 50,
39 static const struct reg_default rt1015_reg[] = {
202 static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
209 case RT1015_VENDOR_ID:
210 case RT1015_DEVICE_ID:
213 case RT1015_VBAT_TEST_OUT1:
214 case RT1015_VBAT_TEST_OUT2:
215 case RT1015_VBAT_PROT_ATT:
216 case RT1015_VBAT_DET_CODE:
217 case RT1015_SMART_BST_CTRL1:
218 case RT1015_SPK_DC_DETECT1:
219 case RT1015_SPK_DC_DETECT4:
220 case RT1015_SPK_DC_DETECT5:
221 case RT1015_DC_CALIB_CLSD1:
222 case RT1015_DC_CALIB_CLSD5:
223 case RT1015_DC_CALIB_CLSD6:
224 case RT1015_DC_CALIB_CLSD7:
225 case RT1015_DC_CALIB_CLSD8:
226 case RT1015_S_BST_TIMING_INTER1:
227 case RT1015_OSCK_STA:
228 case RT1015_MONO_DYNA_CTRL1:
229 case RT1015_MONO_DYNA_CTRL5:
237 static bool rt1015_readable_register(struct device *dev, unsigned int reg)
253 case RT1015_CUSTOMER_ID:
254 case RT1015_PCODE_FWVER:
256 case RT1015_VENDOR_ID:
257 case RT1015_DEVICE_ID:
258 case RT1015_PAD_DRV1:
259 case RT1015_PAD_DRV2:
260 case RT1015_GAT_BOOST:
262 case RT1015_OSCK_STA:
269 case RT1015_TDM_MASTER:
270 case RT1015_TDM_TCON:
278 case RT1015_ANA_PROTECT1:
279 case RT1015_ANA_CTRL_SEQ1:
280 case RT1015_ANA_CTRL_SEQ2:
281 case RT1015_VBAT_DET_DEB:
282 case RT1015_VBAT_VOLT_DET1:
283 case RT1015_VBAT_VOLT_DET2:
284 case RT1015_VBAT_TEST_OUT1:
285 case RT1015_VBAT_TEST_OUT2:
286 case RT1015_VBAT_PROT_ATT:
287 case RT1015_VBAT_DET_CODE:
295 case RT1015_CLASSD_SEQ:
296 case RT1015_SMART_BST_CTRL1:
297 case RT1015_SMART_BST_CTRL2:
298 case RT1015_ANA_CTRL1:
299 case RT1015_ANA_CTRL2:
300 case RT1015_PWR_STATE_CTRL:
301 case RT1015_MONO_DYNA_CTRL:
302 case RT1015_MONO_DYNA_CTRL1:
303 case RT1015_MONO_DYNA_CTRL2:
304 case RT1015_MONO_DYNA_CTRL3:
305 case RT1015_MONO_DYNA_CTRL4:
306 case RT1015_MONO_DYNA_CTRL5:
308 case RT1015_SHORT_DETTOP1:
309 case RT1015_SHORT_DETTOP2:
310 case RT1015_SPK_DC_DETECT1:
311 case RT1015_SPK_DC_DETECT2:
312 case RT1015_SPK_DC_DETECT3:
313 case RT1015_SPK_DC_DETECT4:
314 case RT1015_SPK_DC_DETECT5:
315 case RT1015_BAT_RPO_STEP1:
316 case RT1015_BAT_RPO_STEP2:
317 case RT1015_BAT_RPO_STEP3:
318 case RT1015_BAT_RPO_STEP4:
319 case RT1015_BAT_RPO_STEP5:
320 case RT1015_BAT_RPO_STEP6:
321 case RT1015_BAT_RPO_STEP7:
322 case RT1015_BAT_RPO_STEP8:
323 case RT1015_BAT_RPO_STEP9:
324 case RT1015_BAT_RPO_STEP10:
325 case RT1015_BAT_RPO_STEP11:
326 case RT1015_BAT_RPO_STEP12:
327 case RT1015_SPREAD_SPEC1:
328 case RT1015_SPREAD_SPEC2:
329 case RT1015_PAD_STATUS:
330 case RT1015_PADS_PULLING_CTRL1:
331 case RT1015_PADS_DRIVING:
332 case RT1015_SYS_RST1:
333 case RT1015_SYS_RST2:
334 case RT1015_SYS_GATING1:
335 case RT1015_TEST_MODE1:
336 case RT1015_TEST_MODE2:
337 case RT1015_TIMING_CTRL1:
339 case RT1015_TEST_OUT1:
340 case RT1015_DC_CALIB_CLSD1:
341 case RT1015_DC_CALIB_CLSD2:
342 case RT1015_DC_CALIB_CLSD3:
343 case RT1015_DC_CALIB_CLSD4:
344 case RT1015_DC_CALIB_CLSD5:
345 case RT1015_DC_CALIB_CLSD6:
346 case RT1015_DC_CALIB_CLSD7:
347 case RT1015_DC_CALIB_CLSD8:
348 case RT1015_DC_CALIB_CLSD9:
349 case RT1015_DC_CALIB_CLSD10:
350 case RT1015_CLSD_INTERNAL1:
351 case RT1015_CLSD_INTERNAL2:
352 case RT1015_CLSD_INTERNAL3:
353 case RT1015_CLSD_INTERNAL4:
354 case RT1015_CLSD_INTERNAL5:
355 case RT1015_CLSD_INTERNAL6:
356 case RT1015_CLSD_INTERNAL7:
357 case RT1015_CLSD_INTERNAL8:
358 case RT1015_CLSD_INTERNAL9:
359 case RT1015_CLSD_OCP_CTRL:
365 case RT1015_VREF_LV1:
366 case RT1015_S_BST_TIMING_INTER1:
367 case RT1015_S_BST_TIMING_INTER2:
368 case RT1015_S_BST_TIMING_INTER3:
369 case RT1015_S_BST_TIMING_INTER4:
370 case RT1015_S_BST_TIMING_INTER5:
371 case RT1015_S_BST_TIMING_INTER6:
372 case RT1015_S_BST_TIMING_INTER7:
373 case RT1015_S_BST_TIMING_INTER8:
374 case RT1015_S_BST_TIMING_INTER9:
375 case RT1015_S_BST_TIMING_INTER10:
376 case RT1015_S_BST_TIMING_INTER11:
377 case RT1015_S_BST_TIMING_INTER12:
378 case RT1015_S_BST_TIMING_INTER13:
379 case RT1015_S_BST_TIMING_INTER14:
380 case RT1015_S_BST_TIMING_INTER15:
381 case RT1015_S_BST_TIMING_INTER16:
382 case RT1015_S_BST_TIMING_INTER17:
383 case RT1015_S_BST_TIMING_INTER18:
384 case RT1015_S_BST_TIMING_INTER19:
385 case RT1015_S_BST_TIMING_INTER20:
386 case RT1015_S_BST_TIMING_INTER21:
387 case RT1015_S_BST_TIMING_INTER22:
388 case RT1015_S_BST_TIMING_INTER23:
389 case RT1015_S_BST_TIMING_INTER24:
390 case RT1015_S_BST_TIMING_INTER25:
391 case RT1015_S_BST_TIMING_INTER26:
392 case RT1015_S_BST_TIMING_INTER27:
393 case RT1015_S_BST_TIMING_INTER28:
394 case RT1015_S_BST_TIMING_INTER29:
395 case RT1015_S_BST_TIMING_INTER30:
396 case RT1015_S_BST_TIMING_INTER31:
397 case RT1015_S_BST_TIMING_INTER32:
398 case RT1015_S_BST_TIMING_INTER33:
399 case RT1015_S_BST_TIMING_INTER34:
400 case RT1015_S_BST_TIMING_INTER35:
401 case RT1015_S_BST_TIMING_INTER36:
409 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
411 static const char * const rt1015_din_source_select[] = {
414 "Left + Right average",
417 static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
418 rt1015_din_source_select);
420 static const char * const rt1015_boost_mode[] = {
421 "Bypass", "Adaptive", "Fixed Adaptive"
424 static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
427 static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
428 struct snd_ctl_elem_value *ucontrol)
430 struct snd_soc_component *component =
431 snd_soc_kcontrol_component(kcontrol);
432 struct rt1015_priv *rt1015 =
433 snd_soc_component_get_drvdata(component);
435 ucontrol->value.integer.value[0] = rt1015->boost_mode;
440 static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
441 struct snd_ctl_elem_value *ucontrol)
443 struct snd_soc_component *component =
444 snd_soc_kcontrol_component(kcontrol);
445 struct rt1015_priv *rt1015 =
446 snd_soc_component_get_drvdata(component);
447 int boost_mode = ucontrol->value.integer.value[0];
449 switch (boost_mode) {
451 snd_soc_component_update_bits(component,
452 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
453 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
454 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
455 RT1015_BYPASS_SWRREG_BYPASS);
458 snd_soc_component_update_bits(component,
459 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
460 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
461 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
462 RT1015_BYPASS_SWRREG_PASS);
465 snd_soc_component_update_bits(component,
466 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
467 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
468 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
469 RT1015_BYPASS_SWRREG_PASS);
472 dev_err(component->dev, "Unknown boost control.\n");
476 rt1015->boost_mode = boost_mode;
481 static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
482 struct snd_ctl_elem_value *ucontrol)
484 struct snd_soc_component *component =
485 snd_soc_kcontrol_component(kcontrol);
486 struct rt1015_priv *rt1015 =
487 snd_soc_component_get_drvdata(component);
489 ucontrol->value.integer.value[0] = rt1015->bypass_boost;
494 static void rt1015_calibrate(struct rt1015_priv *rt1015)
496 struct snd_soc_component *component = rt1015->component;
497 struct regmap *regmap = rt1015->regmap;
499 snd_soc_dapm_mutex_lock(&component->dapm);
500 regcache_cache_bypass(regmap, true);
502 regmap_write(regmap, RT1015_CLK_DET, 0x0000);
503 regmap_write(regmap, RT1015_PWR4, 0x00B2);
504 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0009);
506 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000A);
508 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000C);
510 regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2028);
511 regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0140);
512 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000D);
514 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x0008);
515 regmap_write(regmap, RT1015_SYS_RST1, 0x05F5);
517 regcache_cache_bypass(regmap, false);
518 regcache_mark_dirty(regmap);
519 regcache_sync(regmap);
520 snd_soc_dapm_mutex_unlock(&component->dapm);
523 static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
524 struct snd_ctl_elem_value *ucontrol)
526 struct snd_soc_component *component =
527 snd_soc_kcontrol_component(kcontrol);
528 struct rt1015_priv *rt1015 =
529 snd_soc_component_get_drvdata(component);
531 if (rt1015->dac_is_used) {
532 dev_err(component->dev, "DAC is being used!\n");
536 rt1015->bypass_boost = ucontrol->value.integer.value[0];
537 if (rt1015->bypass_boost == RT1015_Bypass_Boost &&
538 !rt1015->cali_done) {
539 rt1015_calibrate(rt1015);
540 rt1015->cali_done = 1;
542 regmap_write(rt1015->regmap, RT1015_MONO_DYNA_CTRL, 0x0010);
548 static void rt1015_flush_work(struct work_struct *work)
550 struct rt1015_priv *rt1015 = container_of(work, struct rt1015_priv,
552 struct snd_soc_component *component = rt1015->component;
555 for (i = 0; i < 200; ++i) {
556 usleep_range(1000, 1500);
557 dev_dbg(component->dev, "Flush DAC (retry:%u)\n", i);
558 regmap_read(rt1015->regmap, RT1015_CLK_DET, &val);
563 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x0597);
564 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x05f7);
565 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x0028);
568 dev_dbg(component->dev, "Flush DAC completed.\n");
570 dev_warn(component->dev, "Fail to flush DAC data.\n");
573 static const struct snd_kcontrol_new rt1015_snd_controls[] = {
574 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
575 127, 0, dac_vol_tlv),
576 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
577 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
578 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
579 rt1015_boost_mode_get, rt1015_boost_mode_put),
580 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
581 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
582 rt1015_bypass_boost_get, rt1015_bypass_boost_put),
585 static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
586 struct snd_soc_dapm_widget *sink)
588 struct snd_soc_component *component =
589 snd_soc_dapm_to_component(source->dapm);
590 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
592 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
598 static int r1015_dac_event(struct snd_soc_dapm_widget *w,
599 struct snd_kcontrol *kcontrol, int event)
601 struct snd_soc_component *component =
602 snd_soc_dapm_to_component(w->dapm);
603 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
606 case SND_SOC_DAPM_PRE_PMU:
607 rt1015->dac_is_used = 1;
608 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
609 snd_soc_component_write(component,
610 RT1015_SYS_RST1, 0x05f7);
611 snd_soc_component_write(component,
612 RT1015_SYS_RST2, 0x0b0a);
613 snd_soc_component_write(component,
614 RT1015_GAT_BOOST, 0xacfe);
615 snd_soc_component_write(component,
616 RT1015_PWR9, 0xaa00);
617 snd_soc_component_write(component,
618 RT1015_GAT_BOOST, 0xecfe);
620 snd_soc_component_write(component,
622 snd_soc_component_write(component,
623 RT1015_SYS_RST1, 0x05f7);
624 snd_soc_component_write(component,
625 RT1015_SYS_RST2, 0x0b0a);
626 snd_soc_component_write(component,
627 RT1015_PWR_STATE_CTRL, 0x008e);
631 case SND_SOC_DAPM_POST_PMU:
632 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x00a8);
635 case SND_SOC_DAPM_POST_PMD:
636 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
637 snd_soc_component_write(component,
638 RT1015_PWR9, 0xa800);
639 snd_soc_component_write(component,
640 RT1015_SYS_RST1, 0x05f5);
641 snd_soc_component_write(component,
642 RT1015_SYS_RST2, 0x0b9a);
644 snd_soc_component_write(component,
646 snd_soc_component_write(component,
647 RT1015_PWR_STATE_CTRL, 0x0088);
648 snd_soc_component_write(component,
649 RT1015_SYS_RST1, 0x05f5);
650 snd_soc_component_write(component,
651 RT1015_SYS_RST2, 0x0b9a);
653 rt1015->dac_is_used = 0;
655 cancel_delayed_work_sync(&rt1015->flush_work);
664 static int rt1015_amp_drv_event(struct snd_soc_dapm_widget *w,
665 struct snd_kcontrol *kcontrol, int event)
667 struct snd_soc_component *component =
668 snd_soc_dapm_to_component(w->dapm);
669 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
672 case SND_SOC_DAPM_POST_PMU:
673 if (rt1015->hw_config == RT1015_HW_28)
674 schedule_delayed_work(&rt1015->flush_work, msecs_to_jiffies(10));
675 msleep(rt1015->pdata.power_up_delay_ms);
683 static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
684 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
686 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
687 SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
688 r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
689 SND_SOC_DAPM_POST_PMD),
690 SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0,
691 rt1015_amp_drv_event, SND_SOC_DAPM_POST_PMU),
692 SND_SOC_DAPM_OUTPUT("SPO"),
695 static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
696 { "DAC", NULL, "AIFRX" },
697 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
698 { "Amp Drv", NULL, "DAC" },
699 { "SPO", NULL, "Amp Drv" },
702 static int rt1015_hw_params(struct snd_pcm_substream *substream,
703 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
705 struct snd_soc_component *component = dai->component;
706 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
707 int pre_div, bclk_ms, frame_size, lrck;
708 unsigned int val_len = 0;
710 lrck = params_rate(params);
711 pre_div = rl6231_get_clk_info(rt1015->sysclk, lrck);
713 dev_err(component->dev, "Unsupported clock rate\n");
717 frame_size = snd_soc_params_to_frame_size(params);
718 if (frame_size < 0) {
719 dev_err(component->dev, "Unsupported frame size: %d\n",
724 bclk_ms = frame_size > 32;
726 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
727 bclk_ms, pre_div, dai->id);
729 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
730 lrck, pre_div, dai->id);
732 switch (params_width(params)) {
736 val_len = RT1015_I2S_DL_20;
739 val_len = RT1015_I2S_DL_24;
742 val_len = RT1015_I2S_DL_8;
748 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
749 RT1015_I2S_DL_MASK, val_len);
750 snd_soc_component_update_bits(component, RT1015_CLK2,
751 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
756 static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
758 struct snd_soc_component *component = dai->component;
759 unsigned int reg_val = 0, reg_val2 = 0;
761 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
762 case SND_SOC_DAIFMT_CBM_CFM:
763 reg_val |= RT1015_TCON_TDM_MS_M;
765 case SND_SOC_DAIFMT_CBS_CFS:
766 reg_val |= RT1015_TCON_TDM_MS_S;
772 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
773 case SND_SOC_DAIFMT_NB_NF:
775 case SND_SOC_DAIFMT_IB_NF:
776 reg_val2 |= RT1015_TDM_INV_BCLK;
782 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
783 case SND_SOC_DAIFMT_I2S:
786 case SND_SOC_DAIFMT_LEFT_J:
787 reg_val |= RT1015_I2S_M_DF_LEFT;
790 case SND_SOC_DAIFMT_DSP_A:
791 reg_val |= RT1015_I2S_M_DF_PCM_A;
794 case SND_SOC_DAIFMT_DSP_B:
795 reg_val |= RT1015_I2S_M_DF_PCM_B;
802 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
803 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
805 snd_soc_component_update_bits(component, RT1015_TDM1_1,
806 RT1015_TDM_INV_BCLK_MASK, reg_val2);
811 static int rt1015_set_component_sysclk(struct snd_soc_component *component,
812 int clk_id, int source, unsigned int freq, int dir)
814 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
815 unsigned int reg_val = 0;
817 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
821 case RT1015_SCLK_S_MCLK:
822 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
825 case RT1015_SCLK_S_PLL:
826 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
830 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
834 rt1015->sysclk = freq;
835 rt1015->sysclk_src = clk_id;
837 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
840 snd_soc_component_update_bits(component, RT1015_CLK2,
841 RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);
846 static int rt1015_set_component_pll(struct snd_soc_component *component,
847 int pll_id, int source, unsigned int freq_in,
848 unsigned int freq_out)
850 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
851 struct rl6231_pll_code pll_code;
854 if (!freq_in || !freq_out) {
855 dev_dbg(component->dev, "PLL disabled\n");
863 if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
864 freq_out == rt1015->pll_out)
868 case RT1015_PLL_S_MCLK:
869 snd_soc_component_update_bits(component, RT1015_CLK2,
870 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
873 case RT1015_PLL_S_BCLK:
874 snd_soc_component_update_bits(component, RT1015_CLK2,
875 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
879 dev_err(component->dev, "Unknown PLL Source %d\n", source);
883 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
885 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
889 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
890 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
891 pll_code.n_code, pll_code.k_code);
893 snd_soc_component_write(component, RT1015_PLL1,
894 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT |
895 pll_code.m_bp << RT1015_PLL_M_BP_SFT | pll_code.n_code);
896 snd_soc_component_write(component, RT1015_PLL2,
899 rt1015->pll_in = freq_in;
900 rt1015->pll_out = freq_out;
901 rt1015->pll_src = source;
906 static int rt1015_set_tdm_slot(struct snd_soc_dai *dai,
907 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
909 struct snd_soc_component *component = dai->component;
910 unsigned int val = 0, rx_slotnum, tx_slotnum;
911 int ret = 0, first_bit;
915 val |= RT1015_I2S_TX_2CH;
918 val |= RT1015_I2S_TX_4CH;
921 val |= RT1015_I2S_TX_6CH;
924 val |= RT1015_I2S_TX_8CH;
931 switch (slot_width) {
933 val |= RT1015_I2S_CH_TX_LEN_16B;
936 val |= RT1015_I2S_CH_TX_LEN_20B;
939 val |= RT1015_I2S_CH_TX_LEN_24B;
942 val |= RT1015_I2S_CH_TX_LEN_32B;
949 /* Rx slot configuration */
950 rx_slotnum = hweight_long(rx_mask);
951 if (rx_slotnum != 1) {
953 dev_err(component->dev, "too many rx slots or zero slot\n");
957 /* This is an assumption that the system sends stereo audio to the amplifier typically.
958 * And the stereo audio is placed in slot 0/2/4/6 as the starting slot.
959 * The users could select the channel from L/R/L+R by "Mono LR Select" control.
961 first_bit = __ffs(rx_mask);
967 snd_soc_component_update_bits(component,
969 RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
970 RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
971 (first_bit << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
972 ((first_bit+1) << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
978 snd_soc_component_update_bits(component,
980 RT1015_TDM_I2S_TX_L_DAC1_1_MASK |
981 RT1015_TDM_I2S_TX_R_DAC1_1_MASK,
982 ((first_bit-1) << RT1015_TDM_I2S_TX_L_DAC1_1_SFT) |
983 (first_bit << RT1015_TDM_I2S_TX_R_DAC1_1_SFT));
990 /* Tx slot configuration */
991 tx_slotnum = hweight_long(tx_mask);
994 dev_err(component->dev, "doesn't need to support tx slots\n");
998 snd_soc_component_update_bits(component, RT1015_TDM1_1,
999 RT1015_I2S_CH_TX_MASK | RT1015_I2S_CH_RX_MASK |
1000 RT1015_I2S_CH_TX_LEN_MASK | RT1015_I2S_CH_RX_LEN_MASK, val);
1006 static int rt1015_probe(struct snd_soc_component *component)
1008 struct rt1015_priv *rt1015 =
1009 snd_soc_component_get_drvdata(component);
1011 rt1015->component = component;
1012 INIT_DELAYED_WORK(&rt1015->flush_work, rt1015_flush_work);
1017 static void rt1015_remove(struct snd_soc_component *component)
1019 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1021 cancel_delayed_work_sync(&rt1015->flush_work);
1022 regmap_write(rt1015->regmap, RT1015_RESET, 0);
1025 #define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1026 #define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1027 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1029 static struct snd_soc_dai_ops rt1015_aif_dai_ops = {
1030 .hw_params = rt1015_hw_params,
1031 .set_fmt = rt1015_set_dai_fmt,
1032 .set_tdm_slot = rt1015_set_tdm_slot,
1035 static struct snd_soc_dai_driver rt1015_dai[] = {
1037 .name = "rt1015-aif",
1040 .stream_name = "AIF Playback",
1043 .rates = RT1015_STEREO_RATES,
1044 .formats = RT1015_FORMATS,
1046 .ops = &rt1015_aif_dai_ops,
1051 static int rt1015_suspend(struct snd_soc_component *component)
1053 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1055 regcache_cache_only(rt1015->regmap, true);
1056 regcache_mark_dirty(rt1015->regmap);
1061 static int rt1015_resume(struct snd_soc_component *component)
1063 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
1065 regcache_cache_only(rt1015->regmap, false);
1066 regcache_sync(rt1015->regmap);
1068 if (rt1015->cali_done)
1069 rt1015_calibrate(rt1015);
1074 #define rt1015_suspend NULL
1075 #define rt1015_resume NULL
1078 static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
1079 .probe = rt1015_probe,
1080 .remove = rt1015_remove,
1081 .suspend = rt1015_suspend,
1082 .resume = rt1015_resume,
1083 .controls = rt1015_snd_controls,
1084 .num_controls = ARRAY_SIZE(rt1015_snd_controls),
1085 .dapm_widgets = rt1015_dapm_widgets,
1086 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
1087 .dapm_routes = rt1015_dapm_routes,
1088 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
1089 .set_sysclk = rt1015_set_component_sysclk,
1090 .set_pll = rt1015_set_component_pll,
1091 .use_pmdown_time = 1,
1093 .non_legacy_dai_naming = 1,
1096 static const struct regmap_config rt1015_regmap = {
1099 .max_register = RT1015_S_BST_TIMING_INTER36,
1100 .volatile_reg = rt1015_volatile_register,
1101 .readable_reg = rt1015_readable_register,
1102 .cache_type = REGCACHE_RBTREE,
1103 .reg_defaults = rt1015_reg,
1104 .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
1107 static const struct i2c_device_id rt1015_i2c_id[] = {
1111 MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
1113 #if defined(CONFIG_OF)
1114 static const struct of_device_id rt1015_of_match[] = {
1115 { .compatible = "realtek,rt1015", },
1118 MODULE_DEVICE_TABLE(of, rt1015_of_match);
1122 static struct acpi_device_id rt1015_acpi_match[] = {
1126 MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
1129 static void rt1015_parse_dt(struct rt1015_priv *rt1015, struct device *dev)
1131 device_property_read_u32(dev, "realtek,power-up-delay-ms",
1132 &rt1015->pdata.power_up_delay_ms);
1135 static int rt1015_i2c_probe(struct i2c_client *i2c,
1136 const struct i2c_device_id *id)
1138 struct rt1015_platform_data *pdata = dev_get_platdata(&i2c->dev);
1139 struct rt1015_priv *rt1015;
1143 rt1015 = devm_kzalloc(&i2c->dev, sizeof(*rt1015), GFP_KERNEL);
1147 i2c_set_clientdata(i2c, rt1015);
1149 rt1015->pdata = i2s_default_platform_data;
1152 rt1015->pdata = *pdata;
1154 rt1015_parse_dt(rt1015, &i2c->dev);
1156 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
1157 if (IS_ERR(rt1015->regmap)) {
1158 ret = PTR_ERR(rt1015->regmap);
1159 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1164 rt1015->hw_config = (i2c->addr == 0x29) ? RT1015_HW_29 : RT1015_HW_28;
1166 ret = regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
1169 "Failed to read device register: %d\n", ret);
1171 } else if ((val != RT1015_DEVICE_ID_VAL) &&
1172 (val != RT1015_DEVICE_ID_VAL2)) {
1174 "Device with ID register %x is not rt1015\n", val);
1178 return devm_snd_soc_register_component(&i2c->dev,
1179 &soc_component_dev_rt1015,
1180 rt1015_dai, ARRAY_SIZE(rt1015_dai));
1183 static void rt1015_i2c_shutdown(struct i2c_client *client)
1185 struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
1187 regmap_write(rt1015->regmap, RT1015_RESET, 0);
1190 static struct i2c_driver rt1015_i2c_driver = {
1193 .of_match_table = of_match_ptr(rt1015_of_match),
1194 .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
1196 .probe = rt1015_i2c_probe,
1197 .shutdown = rt1015_i2c_shutdown,
1198 .id_table = rt1015_i2c_id,
1200 module_i2c_driver(rt1015_i2c_driver);
1202 MODULE_DESCRIPTION("ASoC RT1015 driver");
1203 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1204 MODULE_LICENSE("GPL v2");