1 // SPDX-License-Identifier: GPL-2.0
3 // rt1015.c -- RT1015 ALSA SoC audio amplifier driver
5 // Copyright 2019 Realtek Semiconductor Corp.
7 // Author: Jack Yu <jack.yu@realtek.com>
11 #include <linux/acpi.h>
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
15 #include <linux/gpio.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23 #include <sound/core.h>
24 #include <sound/initval.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/soc.h>
29 #include <sound/tlv.h>
34 static const struct reg_default rt1015_reg[] = {
197 static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
204 case RT1015_VENDOR_ID:
205 case RT1015_DEVICE_ID:
208 case RT1015_VBAT_TEST_OUT1:
209 case RT1015_VBAT_TEST_OUT2:
210 case RT1015_VBAT_PROT_ATT:
211 case RT1015_VBAT_DET_CODE:
212 case RT1015_SMART_BST_CTRL1:
213 case RT1015_SPK_DC_DETECT1:
214 case RT1015_SPK_DC_DETECT4:
215 case RT1015_SPK_DC_DETECT5:
216 case RT1015_DC_CALIB_CLSD1:
217 case RT1015_DC_CALIB_CLSD5:
218 case RT1015_DC_CALIB_CLSD6:
219 case RT1015_DC_CALIB_CLSD7:
220 case RT1015_DC_CALIB_CLSD8:
221 case RT1015_S_BST_TIMING_INTER1:
222 case RT1015_OSCK_STA:
223 case RT1015_MONO_DYNA_CTRL1:
224 case RT1015_MONO_DYNA_CTRL5:
232 static bool rt1015_readable_register(struct device *dev, unsigned int reg)
248 case RT1015_CUSTOMER_ID:
249 case RT1015_PCODE_FWVER:
251 case RT1015_VENDOR_ID:
252 case RT1015_DEVICE_ID:
253 case RT1015_PAD_DRV1:
254 case RT1015_PAD_DRV2:
255 case RT1015_GAT_BOOST:
257 case RT1015_OSCK_STA:
264 case RT1015_TDM_MASTER:
265 case RT1015_TDM_TCON:
273 case RT1015_ANA_PROTECT1:
274 case RT1015_ANA_CTRL_SEQ1:
275 case RT1015_ANA_CTRL_SEQ2:
276 case RT1015_VBAT_DET_DEB:
277 case RT1015_VBAT_VOLT_DET1:
278 case RT1015_VBAT_VOLT_DET2:
279 case RT1015_VBAT_TEST_OUT1:
280 case RT1015_VBAT_TEST_OUT2:
281 case RT1015_VBAT_PROT_ATT:
282 case RT1015_VBAT_DET_CODE:
290 case RT1015_CLASSD_SEQ:
291 case RT1015_SMART_BST_CTRL1:
292 case RT1015_SMART_BST_CTRL2:
293 case RT1015_ANA_CTRL1:
294 case RT1015_ANA_CTRL2:
295 case RT1015_PWR_STATE_CTRL:
296 case RT1015_MONO_DYNA_CTRL:
297 case RT1015_MONO_DYNA_CTRL1:
298 case RT1015_MONO_DYNA_CTRL2:
299 case RT1015_MONO_DYNA_CTRL3:
300 case RT1015_MONO_DYNA_CTRL4:
301 case RT1015_MONO_DYNA_CTRL5:
303 case RT1015_SHORT_DETTOP1:
304 case RT1015_SHORT_DETTOP2:
305 case RT1015_SPK_DC_DETECT1:
306 case RT1015_SPK_DC_DETECT2:
307 case RT1015_SPK_DC_DETECT3:
308 case RT1015_SPK_DC_DETECT4:
309 case RT1015_SPK_DC_DETECT5:
310 case RT1015_BAT_RPO_STEP1:
311 case RT1015_BAT_RPO_STEP2:
312 case RT1015_BAT_RPO_STEP3:
313 case RT1015_BAT_RPO_STEP4:
314 case RT1015_BAT_RPO_STEP5:
315 case RT1015_BAT_RPO_STEP6:
316 case RT1015_BAT_RPO_STEP7:
317 case RT1015_BAT_RPO_STEP8:
318 case RT1015_BAT_RPO_STEP9:
319 case RT1015_BAT_RPO_STEP10:
320 case RT1015_BAT_RPO_STEP11:
321 case RT1015_BAT_RPO_STEP12:
322 case RT1015_SPREAD_SPEC1:
323 case RT1015_SPREAD_SPEC2:
324 case RT1015_PAD_STATUS:
325 case RT1015_PADS_PULLING_CTRL1:
326 case RT1015_PADS_DRIVING:
327 case RT1015_SYS_RST1:
328 case RT1015_SYS_RST2:
329 case RT1015_SYS_GATING1:
330 case RT1015_TEST_MODE1:
331 case RT1015_TEST_MODE2:
332 case RT1015_TIMING_CTRL1:
334 case RT1015_TEST_OUT1:
335 case RT1015_DC_CALIB_CLSD1:
336 case RT1015_DC_CALIB_CLSD2:
337 case RT1015_DC_CALIB_CLSD3:
338 case RT1015_DC_CALIB_CLSD4:
339 case RT1015_DC_CALIB_CLSD5:
340 case RT1015_DC_CALIB_CLSD6:
341 case RT1015_DC_CALIB_CLSD7:
342 case RT1015_DC_CALIB_CLSD8:
343 case RT1015_DC_CALIB_CLSD9:
344 case RT1015_DC_CALIB_CLSD10:
345 case RT1015_CLSD_INTERNAL1:
346 case RT1015_CLSD_INTERNAL2:
347 case RT1015_CLSD_INTERNAL3:
348 case RT1015_CLSD_INTERNAL4:
349 case RT1015_CLSD_INTERNAL5:
350 case RT1015_CLSD_INTERNAL6:
351 case RT1015_CLSD_INTERNAL7:
352 case RT1015_CLSD_INTERNAL8:
353 case RT1015_CLSD_INTERNAL9:
354 case RT1015_CLSD_OCP_CTRL:
360 case RT1015_VREF_LV1:
361 case RT1015_S_BST_TIMING_INTER1:
362 case RT1015_S_BST_TIMING_INTER2:
363 case RT1015_S_BST_TIMING_INTER3:
364 case RT1015_S_BST_TIMING_INTER4:
365 case RT1015_S_BST_TIMING_INTER5:
366 case RT1015_S_BST_TIMING_INTER6:
367 case RT1015_S_BST_TIMING_INTER7:
368 case RT1015_S_BST_TIMING_INTER8:
369 case RT1015_S_BST_TIMING_INTER9:
370 case RT1015_S_BST_TIMING_INTER10:
371 case RT1015_S_BST_TIMING_INTER11:
372 case RT1015_S_BST_TIMING_INTER12:
373 case RT1015_S_BST_TIMING_INTER13:
374 case RT1015_S_BST_TIMING_INTER14:
375 case RT1015_S_BST_TIMING_INTER15:
376 case RT1015_S_BST_TIMING_INTER16:
377 case RT1015_S_BST_TIMING_INTER17:
378 case RT1015_S_BST_TIMING_INTER18:
379 case RT1015_S_BST_TIMING_INTER19:
380 case RT1015_S_BST_TIMING_INTER20:
381 case RT1015_S_BST_TIMING_INTER21:
382 case RT1015_S_BST_TIMING_INTER22:
383 case RT1015_S_BST_TIMING_INTER23:
384 case RT1015_S_BST_TIMING_INTER24:
385 case RT1015_S_BST_TIMING_INTER25:
386 case RT1015_S_BST_TIMING_INTER26:
387 case RT1015_S_BST_TIMING_INTER27:
388 case RT1015_S_BST_TIMING_INTER28:
389 case RT1015_S_BST_TIMING_INTER29:
390 case RT1015_S_BST_TIMING_INTER30:
391 case RT1015_S_BST_TIMING_INTER31:
392 case RT1015_S_BST_TIMING_INTER32:
393 case RT1015_S_BST_TIMING_INTER33:
394 case RT1015_S_BST_TIMING_INTER34:
395 case RT1015_S_BST_TIMING_INTER35:
396 case RT1015_S_BST_TIMING_INTER36:
404 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
406 static const char * const rt1015_din_source_select[] = {
409 "Left + Right average",
412 static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
413 rt1015_din_source_select);
415 static const char * const rt1015_boost_mode[] = {
416 "Bypass", "Adaptive", "Fixed Adaptive"
419 static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
422 static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
423 struct snd_ctl_elem_value *ucontrol)
425 struct snd_soc_component *component =
426 snd_soc_kcontrol_component(kcontrol);
427 struct rt1015_priv *rt1015 =
428 snd_soc_component_get_drvdata(component);
430 ucontrol->value.integer.value[0] = rt1015->boost_mode;
435 static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
436 struct snd_ctl_elem_value *ucontrol)
438 struct snd_soc_component *component =
439 snd_soc_kcontrol_component(kcontrol);
440 struct rt1015_priv *rt1015 =
441 snd_soc_component_get_drvdata(component);
443 rt1015->boost_mode = ucontrol->value.integer.value[0];
445 switch (rt1015->boost_mode) {
447 snd_soc_component_update_bits(component,
448 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
449 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
450 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
451 RT1015_BYPASS_SWRREG_BYPASS);
454 snd_soc_component_update_bits(component,
455 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
456 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
457 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
458 RT1015_BYPASS_SWRREG_PASS);
461 snd_soc_component_update_bits(component,
462 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
463 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
464 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
465 RT1015_BYPASS_SWRREG_PASS);
468 dev_err(component->dev, "Unknown boost control.\n");
474 static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
475 struct snd_ctl_elem_value *ucontrol)
477 struct snd_soc_component *component =
478 snd_soc_kcontrol_component(kcontrol);
479 struct rt1015_priv *rt1015 =
480 snd_soc_component_get_drvdata(component);
482 ucontrol->value.integer.value[0] = rt1015->bypass_boost;
487 static void rt1015_calibrate(struct rt1015_priv *rt1015)
489 struct snd_soc_component *component = rt1015->component;
490 struct regmap *regmap = rt1015->regmap;
492 snd_soc_dapm_mutex_lock(&component->dapm);
493 regcache_cache_bypass(regmap, true);
495 regmap_write(regmap, RT1015_PWR1, 0xd7df);
496 regmap_write(regmap, RT1015_PWR4, 0x00b2);
497 regmap_write(regmap, RT1015_CLSD_INTERNAL8, 0x2008);
498 regmap_write(regmap, RT1015_CLSD_INTERNAL9, 0x0140);
499 regmap_write(regmap, RT1015_GAT_BOOST, 0x0efe);
500 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000d);
501 regmap_write(regmap, RT1015_PWR_STATE_CTRL, 0x000e);
502 regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a00);
503 regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a01);
504 regmap_write(regmap, RT1015_DC_CALIB_CLSD1, 0x5a05);
506 regmap_write(regmap, RT1015_PWR1, 0x0);
508 regcache_cache_bypass(regmap, false);
509 regcache_mark_dirty(regmap);
510 regcache_sync(regmap);
511 snd_soc_dapm_mutex_unlock(&component->dapm);
514 static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
515 struct snd_ctl_elem_value *ucontrol)
517 struct snd_soc_component *component =
518 snd_soc_kcontrol_component(kcontrol);
519 struct rt1015_priv *rt1015 =
520 snd_soc_component_get_drvdata(component);
522 if (!rt1015->dac_is_used) {
523 rt1015->bypass_boost = ucontrol->value.integer.value[0];
524 if (rt1015->bypass_boost == RT1015_Bypass_Boost &&
525 !rt1015->cali_done) {
526 rt1015_calibrate(rt1015);
527 rt1015->cali_done = 1;
529 regmap_write(rt1015->regmap, RT1015_MONO_DYNA_CTRL, 0x0010);
532 dev_err(component->dev, "DAC is being used!\n");
537 static const struct snd_kcontrol_new rt1015_snd_controls[] = {
538 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
539 127, 0, dac_vol_tlv),
540 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
541 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
542 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
543 rt1015_boost_mode_get, rt1015_boost_mode_put),
544 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
545 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
546 rt1015_bypass_boost_get, rt1015_bypass_boost_put),
549 static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
550 struct snd_soc_dapm_widget *sink)
552 struct snd_soc_component *component =
553 snd_soc_dapm_to_component(source->dapm);
554 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
556 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
562 static int r1015_dac_event(struct snd_soc_dapm_widget *w,
563 struct snd_kcontrol *kcontrol, int event)
565 struct snd_soc_component *component =
566 snd_soc_dapm_to_component(w->dapm);
567 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
570 case SND_SOC_DAPM_PRE_PMU:
571 rt1015->dac_is_used = 1;
572 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
573 snd_soc_component_write(component,
574 RT1015_SYS_RST1, 0x05f7);
575 snd_soc_component_write(component,
576 RT1015_GAT_BOOST, 0xacfe);
577 snd_soc_component_write(component,
578 RT1015_PWR9, 0xaa00);
579 snd_soc_component_write(component,
580 RT1015_GAT_BOOST, 0xecfe);
582 snd_soc_component_write(component,
583 RT1015_SYS_RST1, 0x05f7);
584 snd_soc_component_write(component,
585 RT1015_PWR_STATE_CTRL, 0x026e);
589 case SND_SOC_DAPM_POST_PMU:
590 if (rt1015->bypass_boost == RT1015_Bypass_Boost) {
591 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x00a8);
592 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x0597);
593 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x05f7);
594 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x0028);
598 case SND_SOC_DAPM_POST_PMD:
599 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
600 snd_soc_component_write(component,
601 RT1015_PWR9, 0xa800);
602 snd_soc_component_write(component,
603 RT1015_SYS_RST1, 0x05f5);
605 snd_soc_component_write(component,
606 RT1015_PWR_STATE_CTRL, 0x0268);
607 snd_soc_component_write(component,
608 RT1015_SYS_RST1, 0x05f5);
610 rt1015->dac_is_used = 0;
619 static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
620 SND_SOC_DAPM_SUPPLY("LDO2", RT1015_PWR1, RT1015_PWR_LDO2_BIT, 0,
622 SND_SOC_DAPM_SUPPLY("INT RC CLK", RT1015_PWR1, RT1015_PWR_INTCLK_BIT,
624 SND_SOC_DAPM_SUPPLY("ISENSE", RT1015_PWR1, RT1015_PWR_ISENSE_BIT, 0,
626 SND_SOC_DAPM_SUPPLY("VSENSE", RT1015_PWR1, RT1015_PWR_VSENSE_BIT, 0,
628 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
630 SND_SOC_DAPM_SUPPLY("BG1 BG2", RT1015_PWR1, RT1015_PWR_BG_1_2_BIT, 0,
632 SND_SOC_DAPM_SUPPLY("MBIAS BG", RT1015_PWR1, RT1015_PWR_MBIAS_BG_BIT, 0,
634 SND_SOC_DAPM_SUPPLY("VBAT", RT1015_PWR1, RT1015_PWR_VBAT_BIT, 0, NULL,
636 SND_SOC_DAPM_SUPPLY("MBIAS", RT1015_PWR1, RT1015_PWR_MBIAS_BIT, 0,
638 SND_SOC_DAPM_SUPPLY("ADCV", RT1015_PWR1, RT1015_PWR_ADCV_BIT, 0, NULL,
640 SND_SOC_DAPM_SUPPLY("MIXERV", RT1015_PWR1, RT1015_PWR_MIXERV_BIT, 0,
642 SND_SOC_DAPM_SUPPLY("SUMV", RT1015_PWR1, RT1015_PWR_SUMV_BIT, 0, NULL,
644 SND_SOC_DAPM_SUPPLY("VREFLV", RT1015_PWR1, RT1015_PWR_VREFLV_BIT, 0,
647 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
648 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1015_PWR1, RT1015_PWR_DAC_BIT, 0,
649 r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
650 SND_SOC_DAPM_POST_PMD),
652 SND_SOC_DAPM_OUTPUT("SPO"),
655 static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
656 { "DAC", NULL, "AIFRX" },
657 { "DAC", NULL, "LDO2" },
658 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
659 { "DAC", NULL, "INT RC CLK" },
660 { "DAC", NULL, "ISENSE" },
661 { "DAC", NULL, "VSENSE" },
662 { "DAC", NULL, "BG1 BG2" },
663 { "DAC", NULL, "MBIAS BG" },
664 { "DAC", NULL, "VBAT" },
665 { "DAC", NULL, "MBIAS" },
666 { "DAC", NULL, "ADCV" },
667 { "DAC", NULL, "MIXERV" },
668 { "DAC", NULL, "SUMV" },
669 { "DAC", NULL, "VREFLV" },
670 { "SPO", NULL, "DAC" },
673 static int rt1015_hw_params(struct snd_pcm_substream *substream,
674 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
676 struct snd_soc_component *component = dai->component;
677 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
678 int pre_div, bclk_ms, frame_size;
679 unsigned int val_len = 0;
681 rt1015->lrck = params_rate(params);
682 pre_div = rl6231_get_clk_info(rt1015->sysclk, rt1015->lrck);
684 dev_err(component->dev, "Unsupported clock rate\n");
688 frame_size = snd_soc_params_to_frame_size(params);
689 if (frame_size < 0) {
690 dev_err(component->dev, "Unsupported frame size: %d\n",
695 bclk_ms = frame_size > 32;
696 rt1015->bclk = rt1015->lrck * (32 << bclk_ms);
698 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
699 bclk_ms, pre_div, dai->id);
701 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
702 rt1015->lrck, pre_div, dai->id);
704 switch (params_width(params)) {
708 val_len = RT1015_I2S_DL_20;
711 val_len = RT1015_I2S_DL_24;
714 val_len = RT1015_I2S_DL_8;
720 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
721 RT1015_I2S_DL_MASK, val_len);
722 snd_soc_component_update_bits(component, RT1015_CLK2,
723 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
728 static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
730 struct snd_soc_component *component = dai->component;
731 unsigned int reg_val = 0, reg_val2 = 0;
733 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
734 case SND_SOC_DAIFMT_CBM_CFM:
735 reg_val |= RT1015_TCON_TDM_MS_M;
737 case SND_SOC_DAIFMT_CBS_CFS:
738 reg_val |= RT1015_TCON_TDM_MS_S;
744 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
745 case SND_SOC_DAIFMT_NB_NF:
747 case SND_SOC_DAIFMT_IB_NF:
748 reg_val2 |= RT1015_TDM_INV_BCLK;
754 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
755 case SND_SOC_DAIFMT_I2S:
758 case SND_SOC_DAIFMT_LEFT_J:
759 reg_val |= RT1015_I2S_M_DF_LEFT;
762 case SND_SOC_DAIFMT_DSP_A:
763 reg_val |= RT1015_I2S_M_DF_PCM_A;
766 case SND_SOC_DAIFMT_DSP_B:
767 reg_val |= RT1015_I2S_M_DF_PCM_B;
774 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
775 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
777 snd_soc_component_update_bits(component, RT1015_TDM1_1,
778 RT1015_TDM_INV_BCLK_MASK, reg_val2);
783 static int rt1015_set_component_sysclk(struct snd_soc_component *component,
784 int clk_id, int source, unsigned int freq, int dir)
786 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
787 unsigned int reg_val = 0;
789 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
793 case RT1015_SCLK_S_MCLK:
794 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
797 case RT1015_SCLK_S_PLL:
798 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
802 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
806 rt1015->sysclk = freq;
807 rt1015->sysclk_src = clk_id;
809 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
812 snd_soc_component_update_bits(component, RT1015_CLK2,
813 RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);
818 static int rt1015_set_component_pll(struct snd_soc_component *component,
819 int pll_id, int source, unsigned int freq_in,
820 unsigned int freq_out)
822 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
823 struct rl6231_pll_code pll_code;
826 if (!freq_in || !freq_out) {
827 dev_dbg(component->dev, "PLL disabled\n");
835 if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
836 freq_out == rt1015->pll_out)
839 if (source == RT1015_PLL_S_BCLK) {
840 if (rt1015->bclk_ratio == 0) {
841 dev_err(component->dev,
842 "Can not support bclk ratio as 0.\n");
848 case RT1015_PLL_S_MCLK:
849 snd_soc_component_update_bits(component, RT1015_CLK2,
850 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
853 case RT1015_PLL_S_BCLK:
854 snd_soc_component_update_bits(component, RT1015_CLK2,
855 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
859 dev_err(component->dev, "Unknown PLL Source %d\n", source);
863 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
865 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
869 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
870 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
871 pll_code.n_code, pll_code.k_code);
873 snd_soc_component_write(component, RT1015_PLL1,
874 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT |
875 pll_code.m_bp << RT1015_PLL_M_BP_SFT | pll_code.n_code);
876 snd_soc_component_write(component, RT1015_PLL2,
879 rt1015->pll_in = freq_in;
880 rt1015->pll_out = freq_out;
881 rt1015->pll_src = source;
886 static int rt1015_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
888 struct snd_soc_component *component = dai->component;
889 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
891 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
893 rt1015->bclk_ratio = ratio;
896 dev_dbg(component->dev, "Unsupport bclk ratio\n");
903 static int rt1015_probe(struct snd_soc_component *component)
905 struct rt1015_priv *rt1015 =
906 snd_soc_component_get_drvdata(component);
908 rt1015->component = component;
909 rt1015->bclk_ratio = 0;
910 rt1015->cali_done = 0;
911 snd_soc_component_write(component, RT1015_BAT_RPO_STEP1, 0x061c);
916 static void rt1015_remove(struct snd_soc_component *component)
918 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
920 regmap_write(rt1015->regmap, RT1015_RESET, 0);
923 #define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
924 #define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
925 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
927 static struct snd_soc_dai_ops rt1015_aif_dai_ops = {
928 .hw_params = rt1015_hw_params,
929 .set_fmt = rt1015_set_dai_fmt,
930 .set_bclk_ratio = rt1015_set_bclk_ratio,
933 static struct snd_soc_dai_driver rt1015_dai[] = {
935 .name = "rt1015-aif",
938 .stream_name = "AIF Playback",
941 .rates = RT1015_STEREO_RATES,
942 .formats = RT1015_FORMATS,
944 .ops = &rt1015_aif_dai_ops,
949 static int rt1015_suspend(struct snd_soc_component *component)
951 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
953 regcache_cache_only(rt1015->regmap, true);
954 regcache_mark_dirty(rt1015->regmap);
959 static int rt1015_resume(struct snd_soc_component *component)
961 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
963 regcache_cache_only(rt1015->regmap, false);
964 regcache_sync(rt1015->regmap);
968 #define rt1015_suspend NULL
969 #define rt1015_resume NULL
972 static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
973 .probe = rt1015_probe,
974 .remove = rt1015_remove,
975 .suspend = rt1015_suspend,
976 .resume = rt1015_resume,
977 .controls = rt1015_snd_controls,
978 .num_controls = ARRAY_SIZE(rt1015_snd_controls),
979 .dapm_widgets = rt1015_dapm_widgets,
980 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
981 .dapm_routes = rt1015_dapm_routes,
982 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
983 .set_sysclk = rt1015_set_component_sysclk,
984 .set_pll = rt1015_set_component_pll,
985 .use_pmdown_time = 1,
987 .non_legacy_dai_naming = 1,
990 static const struct regmap_config rt1015_regmap = {
993 .max_register = RT1015_S_BST_TIMING_INTER36,
994 .volatile_reg = rt1015_volatile_register,
995 .readable_reg = rt1015_readable_register,
996 .cache_type = REGCACHE_RBTREE,
997 .reg_defaults = rt1015_reg,
998 .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
1001 static const struct i2c_device_id rt1015_i2c_id[] = {
1005 MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
1007 #if defined(CONFIG_OF)
1008 static const struct of_device_id rt1015_of_match[] = {
1009 { .compatible = "realtek,rt1015", },
1012 MODULE_DEVICE_TABLE(of, rt1015_of_match);
1016 static struct acpi_device_id rt1015_acpi_match[] = {
1020 MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
1023 static int rt1015_i2c_probe(struct i2c_client *i2c,
1024 const struct i2c_device_id *id)
1026 struct rt1015_priv *rt1015;
1030 rt1015 = devm_kzalloc(&i2c->dev, sizeof(struct rt1015_priv),
1035 i2c_set_clientdata(i2c, rt1015);
1037 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
1038 if (IS_ERR(rt1015->regmap)) {
1039 ret = PTR_ERR(rt1015->regmap);
1040 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1045 regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
1046 if ((val != RT1015_DEVICE_ID_VAL) && (val != RT1015_DEVICE_ID_VAL2)) {
1048 "Device with ID register %x is not rt1015\n", val);
1052 return devm_snd_soc_register_component(&i2c->dev,
1053 &soc_component_dev_rt1015,
1054 rt1015_dai, ARRAY_SIZE(rt1015_dai));
1057 static void rt1015_i2c_shutdown(struct i2c_client *client)
1059 struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
1061 regmap_write(rt1015->regmap, RT1015_RESET, 0);
1064 static struct i2c_driver rt1015_i2c_driver = {
1067 .of_match_table = of_match_ptr(rt1015_of_match),
1068 .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
1070 .probe = rt1015_i2c_probe,
1071 .shutdown = rt1015_i2c_shutdown,
1072 .id_table = rt1015_i2c_id,
1074 module_i2c_driver(rt1015_i2c_driver);
1076 MODULE_DESCRIPTION("ASoC RT1015 driver");
1077 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1078 MODULE_LICENSE("GPL v2");