1 // SPDX-License-Identifier: GPL-2.0
3 * rt1011.c -- rt1011 ALSA SoC amplifier component driver
5 * Copyright(c) 2019 Realtek Semiconductor Corp.
7 * Author: Shuming Fan <shumingf@realtek.com>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/i2c.h>
18 #include <linux/acpi.h>
19 #include <linux/regmap.h>
20 #include <linux/of_gpio.h>
21 #include <linux/platform_device.h>
22 #include <linux/firmware.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
34 static int rt1011_calibrate(struct rt1011_priv *rt1011,
35 unsigned char cali_flag);
37 static const struct reg_sequence init_list[] = {
39 { RT1011_POWER_9, 0xa840 },
41 { RT1011_ADC_SET_5, 0x0a20 },
42 { RT1011_DAC_SET_2, 0xa032 },
44 { RT1011_SPK_PRO_DC_DET_1, 0xb00c },
45 { RT1011_SPK_PRO_DC_DET_2, 0xcccc },
47 { RT1011_A_TIMING_1, 0x6054 },
49 { RT1011_POWER_7, 0x3e55 },
50 { RT1011_POWER_8, 0x0520 },
51 { RT1011_BOOST_CON_1, 0xe188 },
52 { RT1011_POWER_4, 0x16f2 },
54 { RT1011_CROSS_BQ_SET_1, 0x0004 },
55 { RT1011_SIL_DET, 0xc313 },
56 { RT1011_SINE_GEN_REG_1, 0x0707 },
58 { RT1011_DC_CALIB_CLASSD_3, 0xcb00 },
60 { RT1011_DAC_SET_1, 0xe702 },
61 { RT1011_DAC_SET_3, 0x2004 },
64 static const struct reg_default rt1011_reg[] = {
681 static int rt1011_reg_init(struct snd_soc_component *component)
683 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
685 regmap_multi_reg_write(rt1011->regmap,
686 init_list, ARRAY_SIZE(init_list));
690 static bool rt1011_volatile_register(struct device *dev, unsigned int reg)
697 case RT1011_VERSION_ID:
698 case RT1011_VENDOR_ID:
699 case RT1011_DEVICE_ID:
701 case RT1011_DAC_SET_3:
703 case RT1011_SPK_VOL_TEST_OUT:
704 case RT1011_VBAT_VOL_DET_1:
705 case RT1011_VBAT_TEST_OUT_1:
706 case RT1011_VBAT_TEST_OUT_2:
707 case RT1011_VBAT_PROTECTION:
708 case RT1011_VBAT_DET:
709 case RT1011_BOOST_CON_1:
710 case RT1011_SHORT_CIRCUIT_DET_1:
711 case RT1011_SPK_TEMP_PROTECT_3:
712 case RT1011_SPK_TEMP_PROTECT_6:
713 case RT1011_SPK_PRO_DC_DET_3:
714 case RT1011_SPK_PRO_DC_DET_7:
715 case RT1011_SPK_PRO_DC_DET_8:
718 case RT1011_EXCUR_PROTECT_1:
719 case RT1011_CROSS_BQ_SET_1:
720 case RT1011_CROSS_BQ_SET_2:
721 case RT1011_BQ_SET_0:
722 case RT1011_BQ_SET_1:
723 case RT1011_BQ_SET_2:
724 case RT1011_TEST_PAD_STATUS:
725 case RT1011_DC_CALIB_CLASSD_1:
726 case RT1011_DC_CALIB_CLASSD_5:
727 case RT1011_DC_CALIB_CLASSD_6:
728 case RT1011_DC_CALIB_CLASSD_7:
729 case RT1011_DC_CALIB_CLASSD_8:
730 case RT1011_SINE_GEN_REG_2:
731 case RT1011_STP_CALIB_RS_TEMP:
732 case RT1011_SPK_RESISTANCE_1:
733 case RT1011_SPK_RESISTANCE_2:
734 case RT1011_SPK_THERMAL:
735 case RT1011_ALC_BK_GAIN_O:
736 case RT1011_ALC_BK_GAIN_O_PRE:
737 case RT1011_SPK_DC_O_23_16:
738 case RT1011_SPK_DC_O_15_0:
739 case RT1011_INIT_RECIPROCAL_SYN_24_16:
740 case RT1011_INIT_RECIPROCAL_SYN_15_0:
741 case RT1011_SPK_EXCURSION_23_16:
742 case RT1011_SPK_EXCURSION_15_0:
743 case RT1011_SEP_MAIN_OUT_23_16:
744 case RT1011_SEP_MAIN_OUT_15_0:
745 case RT1011_ALC_DRC_HB_INTERNAL_5:
746 case RT1011_ALC_DRC_HB_INTERNAL_6:
747 case RT1011_ALC_DRC_HB_INTERNAL_7:
748 case RT1011_ALC_DRC_BB_INTERNAL_5:
749 case RT1011_ALC_DRC_BB_INTERNAL_6:
750 case RT1011_ALC_DRC_BB_INTERNAL_7:
751 case RT1011_ALC_DRC_POS_INTERNAL_5:
752 case RT1011_ALC_DRC_POS_INTERNAL_6:
753 case RT1011_ALC_DRC_POS_INTERNAL_7:
754 case RT1011_ALC_DRC_POS_INTERNAL_8:
755 case RT1011_ALC_DRC_POS_INTERNAL_9:
756 case RT1011_ALC_DRC_POS_INTERNAL_10:
757 case RT1011_ALC_DRC_POS_INTERNAL_11:
759 case RT1011_EFUSE_CONTROL_1:
760 case RT1011_EFUSE_CONTROL_2:
761 case RT1011_EFUSE_MATCH_DONE ... RT1011_EFUSE_READ_R0_3_15_0:
769 static bool rt1011_readable_register(struct device *dev, unsigned int reg)
784 case RT1011_PRIV_INDEX:
785 case RT1011_PRIV_DATA:
786 case RT1011_CUSTOMER_ID:
788 case RT1011_VERSION_ID:
789 case RT1011_VENDOR_ID:
790 case RT1011_DEVICE_ID:
791 case RT1011_DUM_RW_0:
793 case RT1011_DUM_RW_1:
795 case RT1011_MAN_I2C_DEV:
796 case RT1011_DAC_SET_1:
797 case RT1011_DAC_SET_2:
798 case RT1011_DAC_SET_3:
800 case RT1011_ADC_SET_1:
801 case RT1011_ADC_SET_2:
802 case RT1011_ADC_SET_3:
803 case RT1011_ADC_SET_4:
804 case RT1011_ADC_SET_5:
805 case RT1011_TDM_TOTAL_SET:
806 case RT1011_TDM1_SET_TCON:
807 case RT1011_TDM1_SET_1:
808 case RT1011_TDM1_SET_2:
809 case RT1011_TDM1_SET_3:
810 case RT1011_TDM1_SET_4:
811 case RT1011_TDM1_SET_5:
812 case RT1011_TDM2_SET_1:
813 case RT1011_TDM2_SET_2:
814 case RT1011_TDM2_SET_3:
815 case RT1011_TDM2_SET_4:
816 case RT1011_TDM2_SET_5:
820 case RT1011_ADRC_LIMIT:
822 case RT1011_A_TIMING_1:
823 case RT1011_A_TIMING_2:
824 case RT1011_A_TEMP_SEN:
825 case RT1011_SPK_VOL_DET_1:
826 case RT1011_SPK_VOL_DET_2:
827 case RT1011_SPK_VOL_TEST_OUT:
828 case RT1011_VBAT_VOL_DET_1:
829 case RT1011_VBAT_VOL_DET_2:
830 case RT1011_VBAT_TEST_OUT_1:
831 case RT1011_VBAT_TEST_OUT_2:
832 case RT1011_VBAT_PROTECTION:
833 case RT1011_VBAT_DET:
843 case RT1011_CLASS_D_POS:
844 case RT1011_BOOST_CON_1:
845 case RT1011_BOOST_CON_2:
846 case RT1011_ANALOG_CTRL:
847 case RT1011_POWER_SEQ:
848 case RT1011_SHORT_CIRCUIT_DET_1:
849 case RT1011_SHORT_CIRCUIT_DET_2:
850 case RT1011_SPK_TEMP_PROTECT_0:
851 case RT1011_SPK_TEMP_PROTECT_1:
852 case RT1011_SPK_TEMP_PROTECT_2:
853 case RT1011_SPK_TEMP_PROTECT_3:
854 case RT1011_SPK_TEMP_PROTECT_4:
855 case RT1011_SPK_TEMP_PROTECT_5:
856 case RT1011_SPK_TEMP_PROTECT_6:
857 case RT1011_SPK_TEMP_PROTECT_7:
858 case RT1011_SPK_TEMP_PROTECT_8:
859 case RT1011_SPK_TEMP_PROTECT_9:
860 case RT1011_SPK_PRO_DC_DET_1:
861 case RT1011_SPK_PRO_DC_DET_2:
862 case RT1011_SPK_PRO_DC_DET_3:
863 case RT1011_SPK_PRO_DC_DET_4:
864 case RT1011_SPK_PRO_DC_DET_5:
865 case RT1011_SPK_PRO_DC_DET_6:
866 case RT1011_SPK_PRO_DC_DET_7:
867 case RT1011_SPK_PRO_DC_DET_8:
872 case RT1011_THER_FOLD_BACK_1:
873 case RT1011_THER_FOLD_BACK_2:
874 case RT1011_EXCUR_PROTECT_1:
875 case RT1011_EXCUR_PROTECT_2:
876 case RT1011_EXCUR_PROTECT_3:
877 case RT1011_EXCUR_PROTECT_4:
878 case RT1011_BAT_GAIN_1:
879 case RT1011_BAT_GAIN_2:
880 case RT1011_BAT_GAIN_3:
881 case RT1011_BAT_GAIN_4:
882 case RT1011_BAT_GAIN_5:
883 case RT1011_BAT_GAIN_6:
884 case RT1011_BAT_GAIN_7:
885 case RT1011_BAT_GAIN_8:
886 case RT1011_BAT_GAIN_9:
887 case RT1011_BAT_GAIN_10:
888 case RT1011_BAT_GAIN_11:
889 case RT1011_BAT_RT_THMAX_1:
890 case RT1011_BAT_RT_THMAX_2:
891 case RT1011_BAT_RT_THMAX_3:
892 case RT1011_BAT_RT_THMAX_4:
893 case RT1011_BAT_RT_THMAX_5:
894 case RT1011_BAT_RT_THMAX_6:
895 case RT1011_BAT_RT_THMAX_7:
896 case RT1011_BAT_RT_THMAX_8:
897 case RT1011_BAT_RT_THMAX_9:
898 case RT1011_BAT_RT_THMAX_10:
899 case RT1011_BAT_RT_THMAX_11:
900 case RT1011_BAT_RT_THMAX_12:
901 case RT1011_SPREAD_SPECTURM:
902 case RT1011_PRO_GAIN_MODE:
903 case RT1011_RT_DRC_CROSS:
904 case RT1011_RT_DRC_HB_1:
905 case RT1011_RT_DRC_HB_2:
906 case RT1011_RT_DRC_HB_3:
907 case RT1011_RT_DRC_HB_4:
908 case RT1011_RT_DRC_HB_5:
909 case RT1011_RT_DRC_HB_6:
910 case RT1011_RT_DRC_HB_7:
911 case RT1011_RT_DRC_HB_8:
912 case RT1011_RT_DRC_BB_1:
913 case RT1011_RT_DRC_BB_2:
914 case RT1011_RT_DRC_BB_3:
915 case RT1011_RT_DRC_BB_4:
916 case RT1011_RT_DRC_BB_5:
917 case RT1011_RT_DRC_BB_6:
918 case RT1011_RT_DRC_BB_7:
919 case RT1011_RT_DRC_BB_8:
920 case RT1011_RT_DRC_POS_1:
921 case RT1011_RT_DRC_POS_2:
922 case RT1011_RT_DRC_POS_3:
923 case RT1011_RT_DRC_POS_4:
924 case RT1011_RT_DRC_POS_5:
925 case RT1011_RT_DRC_POS_6:
926 case RT1011_RT_DRC_POS_7:
927 case RT1011_RT_DRC_POS_8:
928 case RT1011_CROSS_BQ_SET_1:
929 case RT1011_CROSS_BQ_SET_2:
930 case RT1011_BQ_SET_0:
931 case RT1011_BQ_SET_1:
932 case RT1011_BQ_SET_2:
933 case RT1011_BQ_PRE_GAIN_28_16:
934 case RT1011_BQ_PRE_GAIN_15_0:
935 case RT1011_BQ_POST_GAIN_28_16:
936 case RT1011_BQ_POST_GAIN_15_0:
937 case RT1011_BQ_H0_28_16 ... RT1011_BQ_A2_15_0:
938 case RT1011_BQ_1_H0_28_16 ... RT1011_BQ_1_A2_15_0:
939 case RT1011_BQ_2_H0_28_16 ... RT1011_BQ_2_A2_15_0:
940 case RT1011_BQ_3_H0_28_16 ... RT1011_BQ_3_A2_15_0:
941 case RT1011_BQ_4_H0_28_16 ... RT1011_BQ_4_A2_15_0:
942 case RT1011_BQ_5_H0_28_16 ... RT1011_BQ_5_A2_15_0:
943 case RT1011_BQ_6_H0_28_16 ... RT1011_BQ_6_A2_15_0:
944 case RT1011_BQ_7_H0_28_16 ... RT1011_BQ_7_A2_15_0:
945 case RT1011_BQ_8_H0_28_16 ... RT1011_BQ_8_A2_15_0:
946 case RT1011_BQ_9_H0_28_16 ... RT1011_BQ_9_A2_15_0:
947 case RT1011_BQ_10_H0_28_16 ... RT1011_BQ_10_A2_15_0:
948 case RT1011_TEST_PAD_STATUS ... RT1011_PLL_INTERNAL_SET:
949 case RT1011_TEST_OUT_1 ... RT1011_TEST_OUT_3:
950 case RT1011_DC_CALIB_CLASSD_1 ... RT1011_DC_CALIB_CLASSD_10:
951 case RT1011_CLASSD_INTERNAL_SET_1 ... RT1011_VREF_LV_1:
952 case RT1011_SMART_BOOST_TIMING_1 ... RT1011_SMART_BOOST_TIMING_36:
953 case RT1011_SINE_GEN_REG_1 ... RT1011_SINE_GEN_REG_3:
954 case RT1011_STP_INITIAL_RS_TEMP ... RT1011_SPK_THERMAL:
955 case RT1011_STP_OTP_TH ... RT1011_INIT_RECIPROCAL_SYN_15_0:
956 case RT1011_STP_BQ_1_A1_L_28_16 ... RT1011_STP_BQ_1_H0_R_15_0:
957 case RT1011_STP_BQ_2_A1_L_28_16 ... RT1011_SEP_RE_REG_15_0:
958 case RT1011_DRC_CF_PARAMS_1 ... RT1011_DRC_CF_PARAMS_12:
959 case RT1011_ALC_DRC_HB_INTERNAL_1 ... RT1011_ALC_DRC_HB_INTERNAL_7:
960 case RT1011_ALC_DRC_BB_INTERNAL_1 ... RT1011_ALC_DRC_BB_INTERNAL_7:
961 case RT1011_ALC_DRC_POS_INTERNAL_1 ... RT1011_ALC_DRC_POS_INTERNAL_8:
962 case RT1011_ALC_DRC_POS_INTERNAL_9 ... RT1011_BQ_1_PARAMS_CHECK_5:
963 case RT1011_BQ_2_PARAMS_CHECK_1 ... RT1011_BQ_2_PARAMS_CHECK_5:
964 case RT1011_BQ_3_PARAMS_CHECK_1 ... RT1011_BQ_3_PARAMS_CHECK_5:
965 case RT1011_BQ_4_PARAMS_CHECK_1 ... RT1011_BQ_4_PARAMS_CHECK_5:
966 case RT1011_BQ_5_PARAMS_CHECK_1 ... RT1011_BQ_5_PARAMS_CHECK_5:
967 case RT1011_BQ_6_PARAMS_CHECK_1 ... RT1011_BQ_6_PARAMS_CHECK_5:
968 case RT1011_BQ_7_PARAMS_CHECK_1 ... RT1011_BQ_7_PARAMS_CHECK_5:
969 case RT1011_BQ_8_PARAMS_CHECK_1 ... RT1011_BQ_8_PARAMS_CHECK_5:
970 case RT1011_BQ_9_PARAMS_CHECK_1 ... RT1011_BQ_9_PARAMS_CHECK_5:
971 case RT1011_BQ_10_PARAMS_CHECK_1 ... RT1011_BQ_10_PARAMS_CHECK_5:
972 case RT1011_IRQ_1 ... RT1011_PART_NUMBER_EFUSE:
973 case RT1011_EFUSE_CONTROL_1 ... RT1011_EFUSE_READ_R0_3_15_0:
980 static const char * const rt1011_din_source_select[] = {
983 "Left + Right average",
986 static SOC_ENUM_SINGLE_DECL(rt1011_din_source_enum, RT1011_CROSS_BQ_SET_1, 5,
987 rt1011_din_source_select);
989 static const char * const rt1011_tdm_data_out_select[] = {
990 "TDM_O_LR", "BQ1", "DVOL", "BQ10", "ALC", "DMIX", "ADC_SRC_LR",
991 "ADC_O_LR", "ADC_MONO", "RSPK_BPF_LR", "DMIX_ADD", "ENVELOPE_FS",
992 "SEP_O_GAIN", "ALC_BK_GAIN", "STP_V_C", "DMIX_ABST"
995 static const char * const rt1011_tdm_l_ch_data_select[] = {
996 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
998 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_l_dac1_enum, RT1011_TDM1_SET_4, 12,
999 rt1011_tdm_l_ch_data_select);
1000 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_l_dac1_enum, RT1011_TDM2_SET_4, 12,
1001 rt1011_tdm_l_ch_data_select);
1003 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_dat_enum,
1004 RT1011_ADCDAT_OUT_SOURCE, 0, rt1011_tdm_data_out_select);
1005 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_loc_enum, RT1011_TDM1_SET_2, 0,
1006 rt1011_tdm_l_ch_data_select);
1008 static const char * const rt1011_adc_data_mode_select[] = {
1011 static SOC_ENUM_SINGLE_DECL(rt1011_adc_dout_mode_enum, RT1011_TDM1_SET_1, 12,
1012 rt1011_adc_data_mode_select);
1014 static const char * const rt1011_tdm_adc_data_len_control[] = {
1015 "1CH", "2CH", "3CH", "4CH", "5CH", "6CH", "7CH", "8CH"
1017 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_dout_len_enum, RT1011_TDM1_SET_2, 13,
1018 rt1011_tdm_adc_data_len_control);
1019 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_dout_len_enum, RT1011_TDM2_SET_2, 13,
1020 rt1011_tdm_adc_data_len_control);
1022 static const char * const rt1011_tdm_adc_swap_select[] = {
1023 "L/R", "R/L", "L/L", "R/R"
1026 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc1_1_enum, RT1011_TDM1_SET_3, 6,
1027 rt1011_tdm_adc_swap_select);
1028 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc2_1_enum, RT1011_TDM1_SET_3, 4,
1029 rt1011_tdm_adc_swap_select);
1031 static void rt1011_reset(struct regmap *regmap)
1033 regmap_write(regmap, RT1011_RESET, 0);
1036 static int rt1011_recv_spk_mode_get(struct snd_kcontrol *kcontrol,
1037 struct snd_ctl_elem_value *ucontrol)
1039 struct snd_soc_component *component =
1040 snd_soc_kcontrol_component(kcontrol);
1041 struct rt1011_priv *rt1011 =
1042 snd_soc_component_get_drvdata(component);
1044 ucontrol->value.integer.value[0] = rt1011->recv_spk_mode;
1049 static int rt1011_recv_spk_mode_put(struct snd_kcontrol *kcontrol,
1050 struct snd_ctl_elem_value *ucontrol)
1052 struct snd_soc_component *component =
1053 snd_soc_kcontrol_component(kcontrol);
1054 struct rt1011_priv *rt1011 =
1055 snd_soc_component_get_drvdata(component);
1057 if (ucontrol->value.integer.value[0] == rt1011->recv_spk_mode)
1060 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1061 rt1011->recv_spk_mode = ucontrol->value.integer.value[0];
1063 if (rt1011->recv_spk_mode) {
1065 /* 1: recevier mode on */
1066 snd_soc_component_update_bits(component,
1067 RT1011_CLASSD_INTERNAL_SET_3,
1068 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1069 RT1011_REG_GAIN_CLASSD_RI_410K);
1070 snd_soc_component_update_bits(component,
1071 RT1011_CLASSD_INTERNAL_SET_1,
1072 RT1011_RECV_MODE_SPK_MASK,
1075 /* 0: speaker mode on */
1076 snd_soc_component_update_bits(component,
1077 RT1011_CLASSD_INTERNAL_SET_3,
1078 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1079 RT1011_REG_GAIN_CLASSD_RI_72P5K);
1080 snd_soc_component_update_bits(component,
1081 RT1011_CLASSD_INTERNAL_SET_1,
1082 RT1011_RECV_MODE_SPK_MASK,
1090 static bool rt1011_validate_bq_drc_coeff(unsigned short reg)
1092 if ((reg == RT1011_DAC_SET_1) ||
1093 (reg >= RT1011_ADC_SET && reg <= RT1011_ADC_SET_1) ||
1094 (reg == RT1011_ADC_SET_4) || (reg == RT1011_ADC_SET_5) ||
1095 (reg == RT1011_MIXER_1) ||
1096 (reg == RT1011_A_TIMING_1) ||
1097 (reg >= RT1011_POWER_7 && reg <= RT1011_POWER_8) ||
1098 (reg == RT1011_CLASS_D_POS) || (reg == RT1011_ANALOG_CTRL) ||
1099 (reg >= RT1011_SPK_TEMP_PROTECT_0 && reg <= RT1011_SPK_TEMP_PROTECT_6) ||
1100 (reg >= RT1011_SPK_PRO_DC_DET_5 && reg <= RT1011_BAT_GAIN_1) ||
1101 (reg >= RT1011_RT_DRC_CROSS && reg <= RT1011_RT_DRC_POS_8) ||
1102 (reg >= RT1011_CROSS_BQ_SET_1 && reg <= RT1011_BQ_10_A2_15_0) ||
1103 (reg >= RT1011_SMART_BOOST_TIMING_1 && reg <= RT1011_SMART_BOOST_TIMING_36) ||
1104 (reg == RT1011_SINE_GEN_REG_1) ||
1105 (reg >= RT1011_STP_ALPHA_RECIPROCAL_MSB && reg <= RT1011_BQ_6_PARAMS_CHECK_5) ||
1106 (reg >= RT1011_BQ_7_PARAMS_CHECK_1 && reg <= RT1011_BQ_10_PARAMS_CHECK_5))
1112 static int rt1011_bq_drc_coeff_get(struct snd_kcontrol *kcontrol,
1113 struct snd_ctl_elem_value *ucontrol)
1115 struct snd_soc_component *component =
1116 snd_soc_kcontrol_component(kcontrol);
1117 struct rt1011_priv *rt1011 =
1118 snd_soc_component_get_drvdata(component);
1119 struct rt1011_bq_drc_params *bq_drc_info;
1120 struct rt1011_bq_drc_params *params =
1121 (struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1122 unsigned int i, mode_idx = 0;
1124 if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1125 mode_idx = RT1011_ADVMODE_INITIAL_SET;
1126 else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1127 mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1128 else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1129 mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1130 else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1131 mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1132 else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1133 mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1137 pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1138 ucontrol->id.name, mode_idx);
1139 bq_drc_info = rt1011->bq_drc_params[mode_idx];
1141 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1142 params[i].reg = bq_drc_info[i].reg;
1143 params[i].val = bq_drc_info[i].val;
1149 static int rt1011_bq_drc_coeff_put(struct snd_kcontrol *kcontrol,
1150 struct snd_ctl_elem_value *ucontrol)
1152 struct snd_soc_component *component =
1153 snd_soc_kcontrol_component(kcontrol);
1154 struct rt1011_priv *rt1011 =
1155 snd_soc_component_get_drvdata(component);
1156 struct rt1011_bq_drc_params *bq_drc_info;
1157 struct rt1011_bq_drc_params *params =
1158 (struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1159 unsigned int i, mode_idx = 0;
1161 if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1162 mode_idx = RT1011_ADVMODE_INITIAL_SET;
1163 else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1164 mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1165 else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1166 mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1167 else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1168 mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1169 else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1170 mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1174 bq_drc_info = rt1011->bq_drc_params[mode_idx];
1175 memset(bq_drc_info, 0,
1176 sizeof(struct rt1011_bq_drc_params) * RT1011_BQ_DRC_NUM);
1178 pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1179 ucontrol->id.name, mode_idx);
1180 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1181 bq_drc_info[i].reg = params[i].reg;
1182 bq_drc_info[i].val = params[i].val;
1185 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1186 if (bq_drc_info[i].reg == 0)
1188 else if (rt1011_validate_bq_drc_coeff(bq_drc_info[i].reg)) {
1189 snd_soc_component_write(component, bq_drc_info[i].reg,
1190 bq_drc_info[i].val);
1197 static int rt1011_bq_drc_info(struct snd_kcontrol *kcontrol,
1198 struct snd_ctl_elem_info *uinfo)
1200 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1202 uinfo->value.integer.max = 0x17ffffff;
1207 #define RT1011_BQ_DRC(xname) \
1208 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1209 .info = rt1011_bq_drc_info, \
1210 .get = rt1011_bq_drc_coeff_get, \
1211 .put = rt1011_bq_drc_coeff_put \
1214 static int rt1011_r0_cali_get(struct snd_kcontrol *kcontrol,
1215 struct snd_ctl_elem_value *ucontrol)
1217 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1218 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1220 ucontrol->value.integer.value[0] = rt1011->cali_done;
1225 static int rt1011_r0_cali_put(struct snd_kcontrol *kcontrol,
1226 struct snd_ctl_elem_value *ucontrol)
1228 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1229 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1231 rt1011->cali_done = 0;
1232 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF &&
1233 ucontrol->value.integer.value[0])
1234 rt1011_calibrate(rt1011, 1);
1239 static int rt1011_r0_load(struct rt1011_priv *rt1011)
1241 if (!rt1011->r0_reg)
1244 /* write R0 to register */
1245 regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_24_16,
1246 ((rt1011->r0_reg>>16) & 0x1ff));
1247 regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_15_0,
1248 (rt1011->r0_reg & 0xffff));
1249 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4080);
1254 static int rt1011_r0_load_mode_get(struct snd_kcontrol *kcontrol,
1255 struct snd_ctl_elem_value *ucontrol)
1257 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1258 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1260 ucontrol->value.integer.value[0] = rt1011->r0_reg;
1265 static int rt1011_r0_load_mode_put(struct snd_kcontrol *kcontrol,
1266 struct snd_ctl_elem_value *ucontrol)
1268 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1269 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1271 unsigned int r0_integer, r0_factor, format;
1273 if (ucontrol->value.integer.value[0] == rt1011->r0_reg)
1276 if (ucontrol->value.integer.value[0] == 0)
1279 dev = regmap_get_device(rt1011->regmap);
1280 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1281 rt1011->r0_reg = ucontrol->value.integer.value[0];
1283 format = 2147483648U; /* 2^24 * 128 */
1284 r0_integer = format / rt1011->r0_reg / 128;
1285 r0_factor = ((format / rt1011->r0_reg * 100) / 128)
1286 - (r0_integer * 100);
1287 dev_info(dev, "New r0 resistance about %d.%02d ohm, reg=0x%X\n",
1288 r0_integer, r0_factor, rt1011->r0_reg);
1291 rt1011_r0_load(rt1011);
1297 static int rt1011_r0_load_info(struct snd_kcontrol *kcontrol,
1298 struct snd_ctl_elem_info *uinfo)
1300 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1302 uinfo->value.integer.max = 0x1ffffff;
1307 #define RT1011_R0_LOAD(xname) \
1308 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1309 .info = rt1011_r0_load_info, \
1310 .get = rt1011_r0_load_mode_get, \
1311 .put = rt1011_r0_load_mode_put \
1314 static const char * const rt1011_i2s_ref[] = {
1315 "None", "Left Channel", "Right Channel"
1318 static SOC_ENUM_SINGLE_DECL(rt1011_i2s_ref_enum, 0, 0,
1321 static int rt1011_i2s_ref_put(struct snd_kcontrol *kcontrol,
1322 struct snd_ctl_elem_value *ucontrol)
1324 struct snd_soc_component *component =
1325 snd_soc_kcontrol_component(kcontrol);
1326 struct rt1011_priv *rt1011 =
1327 snd_soc_component_get_drvdata(component);
1329 rt1011->i2s_ref = ucontrol->value.enumerated.item[0];
1330 switch (rt1011->i2s_ref) {
1331 case RT1011_I2S_REF_LEFT_CH:
1332 regmap_write(rt1011->regmap, RT1011_TDM_TOTAL_SET, 0x0240);
1333 regmap_write(rt1011->regmap, RT1011_TDM1_SET_2, 0x8);
1334 regmap_write(rt1011->regmap, RT1011_TDM1_SET_1, 0x1022);
1335 regmap_write(rt1011->regmap, RT1011_ADCDAT_OUT_SOURCE, 0x4);
1337 case RT1011_I2S_REF_RIGHT_CH:
1338 regmap_write(rt1011->regmap, RT1011_TDM_TOTAL_SET, 0x0240);
1339 regmap_write(rt1011->regmap, RT1011_TDM1_SET_2, 0x8);
1340 regmap_write(rt1011->regmap, RT1011_TDM1_SET_1, 0x10a2);
1341 regmap_write(rt1011->regmap, RT1011_ADCDAT_OUT_SOURCE, 0x4);
1344 dev_info(component->dev, "I2S Reference: Do nothing\n");
1350 static int rt1011_i2s_ref_get(struct snd_kcontrol *kcontrol,
1351 struct snd_ctl_elem_value *ucontrol)
1353 struct snd_soc_component *component =
1354 snd_soc_kcontrol_component(kcontrol);
1355 struct rt1011_priv *rt1011 =
1356 snd_soc_component_get_drvdata(component);
1358 ucontrol->value.enumerated.item[0] = rt1011->i2s_ref;
1363 static const struct snd_kcontrol_new rt1011_snd_controls[] = {
1364 /* I2S Data In Selection */
1365 SOC_ENUM("DIN Source", rt1011_din_source_enum),
1367 /* TDM Data In Selection */
1368 SOC_ENUM("TDM1 DIN Source", rt1011_tdm1_l_dac1_enum),
1369 SOC_ENUM("TDM2 DIN Source", rt1011_tdm2_l_dac1_enum),
1371 /* TDM1 Data Out Selection */
1372 SOC_ENUM("TDM1 DOUT Source", rt1011_tdm1_adc1_dat_enum),
1373 SOC_ENUM("TDM1 DOUT Location", rt1011_tdm1_adc1_loc_enum),
1374 SOC_ENUM("TDM1 ADC1DAT Swap Select", rt1011_tdm_adc1_1_enum),
1375 SOC_ENUM("TDM1 ADC2DAT Swap Select", rt1011_tdm_adc2_1_enum),
1378 SOC_ENUM("I2S ADC DOUT Mode", rt1011_adc_dout_mode_enum),
1379 SOC_ENUM("TDM1 DOUT Length", rt1011_tdm1_dout_len_enum),
1380 SOC_ENUM("TDM2 DOUT Length", rt1011_tdm2_dout_len_enum),
1382 /* Speaker/Receiver Mode */
1383 SOC_SINGLE_EXT("RECV SPK Mode", SND_SOC_NOPM, 0, 1, 0,
1384 rt1011_recv_spk_mode_get, rt1011_recv_spk_mode_put),
1386 /* BiQuad/DRC/SmartBoost Settings */
1387 RT1011_BQ_DRC("AdvanceMode Initial Set"),
1388 RT1011_BQ_DRC("AdvanceMode SEP BQ Coeff"),
1389 RT1011_BQ_DRC("AdvanceMode EQ BQ Coeff"),
1390 RT1011_BQ_DRC("AdvanceMode BQ UI Coeff"),
1391 RT1011_BQ_DRC("AdvanceMode SmartBoost Coeff"),
1394 SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0,
1395 rt1011_r0_cali_get, rt1011_r0_cali_put),
1396 RT1011_R0_LOAD("R0 Load Mode"),
1398 /* R0 temperature */
1399 SOC_SINGLE("R0 Temperature", RT1011_STP_INITIAL_RESISTANCE_TEMP,
1402 SOC_ENUM_EXT("I2S Reference", rt1011_i2s_ref_enum,
1403 rt1011_i2s_ref_get, rt1011_i2s_ref_put),
1406 static int rt1011_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
1407 struct snd_soc_dapm_widget *sink)
1409 struct snd_soc_component *component =
1410 snd_soc_dapm_to_component(source->dapm);
1411 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1413 if (rt1011->sysclk_src == RT1011_FS_SYS_PRE_S_PLL1)
1419 static int rt1011_dac_event(struct snd_soc_dapm_widget *w,
1420 struct snd_kcontrol *kcontrol, int event)
1422 struct snd_soc_component *component =
1423 snd_soc_dapm_to_component(w->dapm);
1426 case SND_SOC_DAPM_POST_PMU:
1427 snd_soc_component_update_bits(component,
1428 RT1011_SPK_TEMP_PROTECT_0,
1429 RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK,
1430 RT1011_STP_EN | RT1011_STP_RS_CLB_EN);
1431 snd_soc_component_update_bits(component, RT1011_POWER_9,
1432 RT1011_POW_MNL_SDB_MASK, RT1011_POW_MNL_SDB);
1434 snd_soc_component_update_bits(component,
1435 RT1011_CLASSD_INTERNAL_SET_1,
1436 RT1011_DRIVER_READY_SPK, RT1011_DRIVER_READY_SPK);
1438 case SND_SOC_DAPM_PRE_PMD:
1439 snd_soc_component_update_bits(component, RT1011_POWER_9,
1440 RT1011_POW_MNL_SDB_MASK, 0);
1441 snd_soc_component_update_bits(component,
1442 RT1011_SPK_TEMP_PROTECT_0,
1443 RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 0);
1445 snd_soc_component_update_bits(component,
1446 RT1011_CLASSD_INTERNAL_SET_1,
1447 RT1011_DRIVER_READY_SPK, 0);
1458 static const struct snd_soc_dapm_widget rt1011_dapm_widgets[] = {
1459 SND_SOC_DAPM_SUPPLY("LDO2", RT1011_POWER_1,
1460 RT1011_POW_LDO2_BIT, 0, NULL, 0),
1461 SND_SOC_DAPM_SUPPLY("ISENSE SPK", RT1011_POWER_1,
1462 RT1011_POW_ISENSE_SPK_BIT, 0, NULL, 0),
1463 SND_SOC_DAPM_SUPPLY("VSENSE SPK", RT1011_POWER_1,
1464 RT1011_POW_VSENSE_SPK_BIT, 0, NULL, 0),
1466 SND_SOC_DAPM_SUPPLY("PLL", RT1011_POWER_2,
1467 RT1011_PLLEN_BIT, 0, NULL, 0),
1468 SND_SOC_DAPM_SUPPLY("BG", RT1011_POWER_2,
1469 RT1011_POW_BG_BIT, 0, NULL, 0),
1470 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1011_POWER_2,
1471 RT1011_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
1473 SND_SOC_DAPM_SUPPLY("DET VBAT", RT1011_POWER_3,
1474 RT1011_POW_DET_VBAT_BIT, 0, NULL, 0),
1475 SND_SOC_DAPM_SUPPLY("MBIAS", RT1011_POWER_3,
1476 RT1011_POW_MBIAS_LV_BIT, 0, NULL, 0),
1477 SND_SOC_DAPM_SUPPLY("ADC I", RT1011_POWER_3,
1478 RT1011_POW_ADC_I_BIT, 0, NULL, 0),
1479 SND_SOC_DAPM_SUPPLY("ADC V", RT1011_POWER_3,
1480 RT1011_POW_ADC_V_BIT, 0, NULL, 0),
1481 SND_SOC_DAPM_SUPPLY("ADC T", RT1011_POWER_3,
1482 RT1011_POW_ADC_T_BIT, 0, NULL, 0),
1483 SND_SOC_DAPM_SUPPLY("DITHER ADC T", RT1011_POWER_3,
1484 RT1011_POWD_ADC_T_BIT, 0, NULL, 0),
1485 SND_SOC_DAPM_SUPPLY("MIX I", RT1011_POWER_3,
1486 RT1011_POW_MIX_I_BIT, 0, NULL, 0),
1487 SND_SOC_DAPM_SUPPLY("MIX V", RT1011_POWER_3,
1488 RT1011_POW_MIX_V_BIT, 0, NULL, 0),
1489 SND_SOC_DAPM_SUPPLY("SUM I", RT1011_POWER_3,
1490 RT1011_POW_SUM_I_BIT, 0, NULL, 0),
1491 SND_SOC_DAPM_SUPPLY("SUM V", RT1011_POWER_3,
1492 RT1011_POW_SUM_V_BIT, 0, NULL, 0),
1493 SND_SOC_DAPM_SUPPLY("MIX T", RT1011_POWER_3,
1494 RT1011_POW_MIX_T_BIT, 0, NULL, 0),
1495 SND_SOC_DAPM_SUPPLY("VREF", RT1011_POWER_3,
1496 RT1011_POW_VREF_LV_BIT, 0, NULL, 0),
1498 SND_SOC_DAPM_SUPPLY("BOOST SWR", RT1011_POWER_4,
1499 RT1011_POW_EN_SWR_BIT, 0, NULL, 0),
1500 SND_SOC_DAPM_SUPPLY("BGOK SWR", RT1011_POWER_4,
1501 RT1011_POW_EN_PASS_BGOK_SWR_BIT, 0, NULL, 0),
1502 SND_SOC_DAPM_SUPPLY("VPOK SWR", RT1011_POWER_4,
1503 RT1011_POW_EN_PASS_VPOK_SWR_BIT, 0, NULL, 0),
1505 SND_SOC_DAPM_SUPPLY("TEMP REG", RT1011_A_TEMP_SEN,
1506 RT1011_POW_TEMP_REG_BIT, 0, NULL, 0),
1508 /* Audio Interface */
1509 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1510 /* Digital Interface */
1511 SND_SOC_DAPM_SUPPLY("DAC Power", RT1011_POWER_1,
1512 RT1011_POW_DAC_BIT, 0, NULL, 0),
1513 SND_SOC_DAPM_SUPPLY("CLK12M", RT1011_POWER_1,
1514 RT1011_POW_CLK12M_BIT, 0, NULL, 0),
1515 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1011_DAC_SET_3,
1516 RT1011_DA_MUTE_EN_SFT, 1, rt1011_dac_event,
1517 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1520 SND_SOC_DAPM_OUTPUT("SPO"),
1523 static const struct snd_soc_dapm_route rt1011_dapm_routes[] = {
1525 { "DAC", NULL, "AIF1RX" },
1526 { "DAC", NULL, "DAC Power" },
1527 { "DAC", NULL, "LDO2" },
1528 { "DAC", NULL, "ISENSE SPK" },
1529 { "DAC", NULL, "VSENSE SPK" },
1530 { "DAC", NULL, "CLK12M" },
1532 { "DAC", NULL, "PLL", rt1011_is_sys_clk_from_pll },
1533 { "DAC", NULL, "BG" },
1534 { "DAC", NULL, "BG MBIAS" },
1536 { "DAC", NULL, "BOOST SWR" },
1537 { "DAC", NULL, "BGOK SWR" },
1538 { "DAC", NULL, "VPOK SWR" },
1540 { "DAC", NULL, "DET VBAT" },
1541 { "DAC", NULL, "MBIAS" },
1542 { "DAC", NULL, "VREF" },
1543 { "DAC", NULL, "ADC I" },
1544 { "DAC", NULL, "ADC V" },
1545 { "DAC", NULL, "ADC T" },
1546 { "DAC", NULL, "DITHER ADC T" },
1547 { "DAC", NULL, "MIX I" },
1548 { "DAC", NULL, "MIX V" },
1549 { "DAC", NULL, "SUM I" },
1550 { "DAC", NULL, "SUM V" },
1551 { "DAC", NULL, "MIX T" },
1553 { "DAC", NULL, "TEMP REG" },
1555 { "SPO", NULL, "DAC" },
1558 static int rt1011_get_clk_info(int sclk, int rate)
1561 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1563 if (sclk <= 0 || rate <= 0)
1567 for (i = 0; i < ARRAY_SIZE(pd); i++)
1568 if (sclk == rate * pd[i])
1574 static int rt1011_hw_params(struct snd_pcm_substream *substream,
1575 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1577 struct snd_soc_component *component = dai->component;
1578 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1579 unsigned int val_len = 0, ch_len = 0, val_clk, mask_clk;
1580 int pre_div, bclk_ms, frame_size;
1582 rt1011->lrck = params_rate(params);
1583 pre_div = rt1011_get_clk_info(rt1011->sysclk, rt1011->lrck);
1585 dev_warn(component->dev, "Force using PLL ");
1586 snd_soc_dai_set_pll(dai, 0, RT1011_PLL1_S_BCLK,
1587 rt1011->lrck * 64, rt1011->lrck * 256);
1588 snd_soc_dai_set_sysclk(dai, RT1011_FS_SYS_PRE_S_PLL1,
1589 rt1011->lrck * 256, SND_SOC_CLOCK_IN);
1592 frame_size = snd_soc_params_to_frame_size(params);
1593 if (frame_size < 0) {
1594 dev_err(component->dev, "Unsupported frame size: %d\n",
1599 bclk_ms = frame_size > 32;
1600 rt1011->bclk = rt1011->lrck * (32 << bclk_ms);
1602 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1603 bclk_ms, pre_div, dai->id);
1605 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1606 rt1011->lrck, pre_div, dai->id);
1608 switch (params_width(params)) {
1610 val_len |= RT1011_I2S_TX_DL_16B;
1611 val_len |= RT1011_I2S_RX_DL_16B;
1612 ch_len |= RT1011_I2S_CH_TX_LEN_16B;
1613 ch_len |= RT1011_I2S_CH_RX_LEN_16B;
1616 val_len |= RT1011_I2S_TX_DL_20B;
1617 val_len |= RT1011_I2S_RX_DL_20B;
1618 ch_len |= RT1011_I2S_CH_TX_LEN_20B;
1619 ch_len |= RT1011_I2S_CH_RX_LEN_20B;
1622 val_len |= RT1011_I2S_TX_DL_24B;
1623 val_len |= RT1011_I2S_RX_DL_24B;
1624 ch_len |= RT1011_I2S_CH_TX_LEN_24B;
1625 ch_len |= RT1011_I2S_CH_RX_LEN_24B;
1628 val_len |= RT1011_I2S_TX_DL_32B;
1629 val_len |= RT1011_I2S_RX_DL_32B;
1630 ch_len |= RT1011_I2S_CH_TX_LEN_32B;
1631 ch_len |= RT1011_I2S_CH_RX_LEN_32B;
1634 val_len |= RT1011_I2S_TX_DL_8B;
1635 val_len |= RT1011_I2S_RX_DL_8B;
1636 ch_len |= RT1011_I2S_CH_TX_LEN_8B;
1637 ch_len |= RT1011_I2S_CH_RX_LEN_8B;
1645 mask_clk = RT1011_FS_SYS_DIV_MASK;
1646 val_clk = pre_div << RT1011_FS_SYS_DIV_SFT;
1647 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1648 RT1011_I2S_TX_DL_MASK | RT1011_I2S_RX_DL_MASK,
1650 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1651 RT1011_I2S_CH_TX_LEN_MASK |
1652 RT1011_I2S_CH_RX_LEN_MASK,
1656 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1660 snd_soc_component_update_bits(component,
1661 RT1011_CLK_2, mask_clk, val_clk);
1666 static int rt1011_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1668 struct snd_soc_component *component = dai->component;
1669 struct snd_soc_dapm_context *dapm =
1670 snd_soc_component_get_dapm(component);
1671 unsigned int reg_val = 0, reg_bclk_inv = 0;
1674 snd_soc_dapm_mutex_lock(dapm);
1675 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1676 case SND_SOC_DAIFMT_CBS_CFS:
1677 reg_val |= RT1011_I2S_TDM_MS_S;
1684 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1685 case SND_SOC_DAIFMT_NB_NF:
1687 case SND_SOC_DAIFMT_IB_NF:
1688 reg_bclk_inv |= RT1011_TDM_INV_BCLK;
1695 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1696 case SND_SOC_DAIFMT_I2S:
1698 case SND_SOC_DAIFMT_LEFT_J:
1699 reg_val |= RT1011_I2S_TDM_DF_LEFT;
1701 case SND_SOC_DAIFMT_DSP_A:
1702 reg_val |= RT1011_I2S_TDM_DF_PCM_A;
1704 case SND_SOC_DAIFMT_DSP_B:
1705 reg_val |= RT1011_I2S_TDM_DF_PCM_B;
1714 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1715 RT1011_I2S_TDM_MS_MASK | RT1011_I2S_TDM_DF_MASK,
1717 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1718 RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1719 snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
1720 RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1723 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1728 snd_soc_dapm_mutex_unlock(dapm);
1732 static int rt1011_set_component_sysclk(struct snd_soc_component *component,
1733 int clk_id, int source, unsigned int freq, int dir)
1735 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1736 unsigned int reg_val = 0;
1738 if (freq == rt1011->sysclk && clk_id == rt1011->sysclk_src)
1741 /* disable MCLK detect in default */
1742 snd_soc_component_update_bits(component, RT1011_CLK_DET,
1743 RT1011_EN_MCLK_DET_MASK, 0);
1746 case RT1011_FS_SYS_PRE_S_MCLK:
1747 reg_val |= RT1011_FS_SYS_PRE_MCLK;
1748 snd_soc_component_update_bits(component, RT1011_CLK_DET,
1749 RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1751 case RT1011_FS_SYS_PRE_S_BCLK:
1752 reg_val |= RT1011_FS_SYS_PRE_BCLK;
1754 case RT1011_FS_SYS_PRE_S_PLL1:
1755 reg_val |= RT1011_FS_SYS_PRE_PLL1;
1757 case RT1011_FS_SYS_PRE_S_RCCLK:
1758 reg_val |= RT1011_FS_SYS_PRE_RCCLK;
1761 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
1764 snd_soc_component_update_bits(component, RT1011_CLK_2,
1765 RT1011_FS_SYS_PRE_MASK, reg_val);
1766 rt1011->sysclk = freq;
1767 rt1011->sysclk_src = clk_id;
1769 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
1775 static int rt1011_set_component_pll(struct snd_soc_component *component,
1776 int pll_id, int source, unsigned int freq_in,
1777 unsigned int freq_out)
1779 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1780 struct rl6231_pll_code pll_code;
1783 if (source == rt1011->pll_src && freq_in == rt1011->pll_in &&
1784 freq_out == rt1011->pll_out)
1787 if (!freq_in || !freq_out) {
1788 dev_dbg(component->dev, "PLL disabled\n");
1791 rt1011->pll_out = 0;
1792 snd_soc_component_update_bits(component, RT1011_CLK_2,
1793 RT1011_FS_SYS_PRE_MASK, RT1011_FS_SYS_PRE_BCLK);
1798 case RT1011_PLL2_S_MCLK:
1799 snd_soc_component_update_bits(component, RT1011_CLK_2,
1800 RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_MCLK);
1801 snd_soc_component_update_bits(component, RT1011_CLK_2,
1802 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1803 snd_soc_component_update_bits(component, RT1011_CLK_DET,
1804 RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1806 case RT1011_PLL1_S_BCLK:
1807 snd_soc_component_update_bits(component, RT1011_CLK_2,
1808 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_BCLK);
1810 case RT1011_PLL2_S_RCCLK:
1811 snd_soc_component_update_bits(component, RT1011_CLK_2,
1812 RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_RCCLK);
1813 snd_soc_component_update_bits(component, RT1011_CLK_2,
1814 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1817 dev_err(component->dev, "Unknown PLL Source %d\n", source);
1821 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1823 dev_err(component->dev, "Unsupported input clock %d\n",
1828 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
1829 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1830 pll_code.n_code, pll_code.k_code);
1832 snd_soc_component_write(component, RT1011_PLL_1,
1833 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT1011_PLL1_QM_SFT) |
1834 (pll_code.m_bp << RT1011_PLL1_BPM_SFT) |
1836 snd_soc_component_write(component, RT1011_PLL_2,
1839 rt1011->pll_in = freq_in;
1840 rt1011->pll_out = freq_out;
1841 rt1011->pll_src = source;
1846 static int rt1011_set_tdm_slot(struct snd_soc_dai *dai,
1847 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1849 struct snd_soc_component *component = dai->component;
1850 struct snd_soc_dapm_context *dapm =
1851 snd_soc_component_get_dapm(component);
1852 unsigned int val = 0, tdm_en = 0, rx_slotnum, tx_slotnum;
1853 int ret = 0, first_bit, last_bit;
1855 snd_soc_dapm_mutex_lock(dapm);
1856 if (rx_mask || tx_mask)
1857 tdm_en = RT1011_TDM_I2S_DOCK_EN_1;
1861 val |= RT1011_I2S_TX_4CH;
1862 val |= RT1011_I2S_RX_4CH;
1865 val |= RT1011_I2S_TX_6CH;
1866 val |= RT1011_I2S_RX_6CH;
1869 val |= RT1011_I2S_TX_8CH;
1870 val |= RT1011_I2S_RX_8CH;
1879 switch (slot_width) {
1881 val |= RT1011_I2S_CH_TX_LEN_20B;
1882 val |= RT1011_I2S_CH_RX_LEN_20B;
1885 val |= RT1011_I2S_CH_TX_LEN_24B;
1886 val |= RT1011_I2S_CH_RX_LEN_24B;
1889 val |= RT1011_I2S_CH_TX_LEN_32B;
1890 val |= RT1011_I2S_CH_RX_LEN_32B;
1899 /* Rx slot configuration */
1900 rx_slotnum = hweight_long(rx_mask);
1901 if (rx_slotnum > 1 || !rx_slotnum) {
1903 dev_err(component->dev, "too many rx slots or zero slot\n");
1907 first_bit = __ffs(rx_mask);
1908 switch (first_bit) {
1913 snd_soc_component_update_bits(component,
1914 RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
1915 RT1011_MONO_L_CHANNEL);
1916 snd_soc_component_update_bits(component,
1918 RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
1919 RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
1920 (first_bit << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
1921 ((first_bit+1) << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
1927 snd_soc_component_update_bits(component,
1928 RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
1929 RT1011_MONO_R_CHANNEL);
1930 snd_soc_component_update_bits(component,
1932 RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
1933 RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
1934 ((first_bit-1) << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
1935 (first_bit << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
1942 /* Tx slot configuration */
1943 tx_slotnum = hweight_long(tx_mask);
1944 if (tx_slotnum > 2 || !tx_slotnum) {
1946 dev_err(component->dev, "too many tx slots or zero slot\n");
1950 first_bit = __ffs(tx_mask);
1951 last_bit = __fls(tx_mask);
1952 if (last_bit - first_bit > 1) {
1954 dev_err(component->dev, "tx slot location error\n");
1958 if (tx_slotnum == 1) {
1959 snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
1960 RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
1961 RT1011_TDM_ADCDAT1_DATA_LOCATION, first_bit);
1962 switch (first_bit) {
1964 snd_soc_component_update_bits(component,
1966 RT1011_TDM_I2S_RX_ADC1_1_MASK,
1967 RT1011_TDM_I2S_RX_ADC1_1_LL);
1970 snd_soc_component_update_bits(component,
1972 RT1011_TDM_I2S_RX_ADC2_1_MASK,
1973 RT1011_TDM_I2S_RX_ADC2_1_LL);
1976 snd_soc_component_update_bits(component,
1978 RT1011_TDM_I2S_RX_ADC3_1_MASK,
1979 RT1011_TDM_I2S_RX_ADC3_1_LL);
1982 snd_soc_component_update_bits(component,
1984 RT1011_TDM_I2S_RX_ADC4_1_MASK,
1985 RT1011_TDM_I2S_RX_ADC4_1_LL);
1988 snd_soc_component_update_bits(component,
1990 RT1011_TDM_I2S_RX_ADC1_1_MASK, 0);
1993 snd_soc_component_update_bits(component,
1995 RT1011_TDM_I2S_RX_ADC2_1_MASK, 0);
1998 snd_soc_component_update_bits(component,
2000 RT1011_TDM_I2S_RX_ADC3_1_MASK, 0);
2003 snd_soc_component_update_bits(component,
2005 RT1011_TDM_I2S_RX_ADC4_1_MASK, 0);
2009 dev_dbg(component->dev,
2010 "tx slot location error\n");
2013 } else if (tx_slotnum == 2) {
2014 switch (first_bit) {
2019 snd_soc_component_update_bits(component,
2021 RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
2022 RT1011_TDM_ADCDAT1_DATA_LOCATION,
2023 RT1011_TDM_I2S_DOCK_ADCDAT_2CH | first_bit);
2027 dev_dbg(component->dev,
2028 "tx slot location should be paired and start from slot0/2/4/6\n");
2033 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
2034 RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
2035 RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
2036 snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
2037 RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
2038 RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
2039 snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
2040 RT1011_TDM_I2S_DOCK_EN_1_MASK, tdm_en);
2041 snd_soc_component_update_bits(component, RT1011_TDM2_SET_2,
2042 RT1011_TDM_I2S_DOCK_EN_2_MASK, tdm_en);
2044 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
2045 RT1011_ADCDAT1_PIN_CONFIG | RT1011_ADCDAT2_PIN_CONFIG,
2046 RT1011_ADCDAT1_OUTPUT | RT1011_ADCDAT2_OUTPUT);
2049 snd_soc_dapm_mutex_unlock(dapm);
2053 static int rt1011_probe(struct snd_soc_component *component)
2055 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2058 rt1011->component = component;
2060 schedule_work(&rt1011->cali_work);
2062 rt1011->i2s_ref = 0;
2063 rt1011->bq_drc_params = devm_kcalloc(component->dev,
2064 RT1011_ADVMODE_NUM, sizeof(struct rt1011_bq_drc_params *),
2066 if (!rt1011->bq_drc_params)
2069 for (i = 0; i < RT1011_ADVMODE_NUM; i++) {
2070 rt1011->bq_drc_params[i] = devm_kcalloc(component->dev,
2071 RT1011_BQ_DRC_NUM, sizeof(struct rt1011_bq_drc_params),
2073 if (!rt1011->bq_drc_params[i])
2080 static void rt1011_remove(struct snd_soc_component *component)
2082 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2084 cancel_work_sync(&rt1011->cali_work);
2085 rt1011_reset(rt1011->regmap);
2089 static int rt1011_suspend(struct snd_soc_component *component)
2091 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2093 regcache_cache_only(rt1011->regmap, true);
2094 regcache_mark_dirty(rt1011->regmap);
2099 static int rt1011_resume(struct snd_soc_component *component)
2101 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2103 regcache_cache_only(rt1011->regmap, false);
2104 regcache_sync(rt1011->regmap);
2109 #define rt1011_suspend NULL
2110 #define rt1011_resume NULL
2113 static int rt1011_set_bias_level(struct snd_soc_component *component,
2114 enum snd_soc_bias_level level)
2117 case SND_SOC_BIAS_OFF:
2118 snd_soc_component_write(component,
2119 RT1011_SYSTEM_RESET_1, 0x0000);
2120 snd_soc_component_write(component,
2121 RT1011_SYSTEM_RESET_2, 0x0000);
2122 snd_soc_component_write(component,
2123 RT1011_SYSTEM_RESET_3, 0x0001);
2124 snd_soc_component_write(component,
2125 RT1011_SYSTEM_RESET_1, 0x003f);
2126 snd_soc_component_write(component,
2127 RT1011_SYSTEM_RESET_2, 0x7fd7);
2128 snd_soc_component_write(component,
2129 RT1011_SYSTEM_RESET_3, 0x770f);
2138 #define RT1011_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2139 #define RT1011_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
2140 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
2141 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2143 static const struct snd_soc_dai_ops rt1011_aif_dai_ops = {
2144 .hw_params = rt1011_hw_params,
2145 .set_fmt = rt1011_set_dai_fmt,
2146 .set_tdm_slot = rt1011_set_tdm_slot,
2149 static struct snd_soc_dai_driver rt1011_dai[] = {
2151 .name = "rt1011-aif",
2153 .stream_name = "AIF1 Playback",
2156 .rates = RT1011_STEREO_RATES,
2157 .formats = RT1011_FORMATS,
2159 .ops = &rt1011_aif_dai_ops,
2163 static const struct snd_soc_component_driver soc_component_dev_rt1011 = {
2164 .probe = rt1011_probe,
2165 .remove = rt1011_remove,
2166 .suspend = rt1011_suspend,
2167 .resume = rt1011_resume,
2168 .set_bias_level = rt1011_set_bias_level,
2169 .controls = rt1011_snd_controls,
2170 .num_controls = ARRAY_SIZE(rt1011_snd_controls),
2171 .dapm_widgets = rt1011_dapm_widgets,
2172 .num_dapm_widgets = ARRAY_SIZE(rt1011_dapm_widgets),
2173 .dapm_routes = rt1011_dapm_routes,
2174 .num_dapm_routes = ARRAY_SIZE(rt1011_dapm_routes),
2175 .set_sysclk = rt1011_set_component_sysclk,
2176 .set_pll = rt1011_set_component_pll,
2177 .use_pmdown_time = 1,
2179 .non_legacy_dai_naming = 1,
2182 static const struct regmap_config rt1011_regmap = {
2185 .max_register = RT1011_MAX_REG + 1,
2186 .volatile_reg = rt1011_volatile_register,
2187 .readable_reg = rt1011_readable_register,
2188 .cache_type = REGCACHE_RBTREE,
2189 .reg_defaults = rt1011_reg,
2190 .num_reg_defaults = ARRAY_SIZE(rt1011_reg),
2191 .use_single_read = true,
2192 .use_single_write = true,
2195 #if defined(CONFIG_OF)
2196 static const struct of_device_id rt1011_of_match[] = {
2197 { .compatible = "realtek,rt1011", },
2200 MODULE_DEVICE_TABLE(of, rt1011_of_match);
2204 static const struct acpi_device_id rt1011_acpi_match[] = {
2208 MODULE_DEVICE_TABLE(acpi, rt1011_acpi_match);
2211 static const struct i2c_device_id rt1011_i2c_id[] = {
2215 MODULE_DEVICE_TABLE(i2c, rt1011_i2c_id);
2217 static int rt1011_calibrate(struct rt1011_priv *rt1011, unsigned char cali_flag)
2219 unsigned int value, count = 0, r0[3];
2220 unsigned int chk_cnt = 50; /* DONT change this */
2221 unsigned int dc_offset;
2222 unsigned int r0_integer, r0_factor, format;
2223 struct device *dev = regmap_get_device(rt1011->regmap);
2224 struct snd_soc_dapm_context *dapm =
2225 snd_soc_component_get_dapm(rt1011->component);
2228 snd_soc_dapm_mutex_lock(dapm);
2229 regcache_cache_bypass(rt1011->regmap, true);
2231 regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2232 regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x740f);
2233 regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x770f);
2236 regmap_write(rt1011->regmap, RT1011_CLK_2, 0x9400);
2237 regmap_write(rt1011->regmap, RT1011_PLL_1, 0x0800);
2238 regmap_write(rt1011->regmap, RT1011_PLL_2, 0x0020);
2239 regmap_write(rt1011->regmap, RT1011_CLK_DET, 0x0800);
2241 /* ADC/DAC setting */
2242 regmap_write(rt1011->regmap, RT1011_ADC_SET_5, 0x0a20);
2243 regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xe232);
2244 regmap_write(rt1011->regmap, RT1011_ADC_SET_4, 0xc000);
2247 regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_1, 0xb00c);
2248 regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_2, 0xcccc);
2251 regmap_write(rt1011->regmap, RT1011_POWER_1, 0xe0e0);
2252 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5003);
2253 regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa860);
2254 regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xa032);
2256 /* POW_PLL / POW_BG / POW_BG_MBIAS_LV / POW_V/I */
2257 regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0007);
2258 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5ff7);
2259 regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f44);
2260 regmap_write(rt1011->regmap, RT1011_A_TIMING_1, 0x4054);
2261 regmap_write(rt1011->regmap, RT1011_BAT_GAIN_1, 0x309c);
2263 /* DC offset from EFUSE */
2264 regmap_write(rt1011->regmap, RT1011_DC_CALIB_CLASSD_3, 0xcb00);
2265 regmap_write(rt1011->regmap, RT1011_BOOST_CON_1, 0xe080);
2266 regmap_write(rt1011->regmap, RT1011_POWER_4, 0x16f2);
2267 regmap_write(rt1011->regmap, RT1011_POWER_6, 0x36ad);
2270 regmap_write(rt1011->regmap, RT1011_MIXER_1, 0x3f1d);
2273 regmap_write(rt1011->regmap, RT1011_EFUSE_CONTROL_1, 0x0d0a);
2276 regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_18_16, &value);
2277 dc_offset = value << 16;
2278 regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_15_0, &value);
2279 dc_offset |= (value & 0xffff);
2280 dev_info(dev, "ADC offset=0x%x\n", dc_offset);
2281 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_20_16, &value);
2282 dc_offset = value << 16;
2283 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_15_0, &value);
2284 dc_offset |= (value & 0xffff);
2285 dev_info(dev, "Gain0 offset=0x%x\n", dc_offset);
2286 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_20_16, &value);
2287 dc_offset = value << 16;
2288 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_15_0, &value);
2289 dc_offset |= (value & 0xffff);
2290 dev_info(dev, "Gain1 offset=0x%x\n", dc_offset);
2294 regmap_write(rt1011->regmap, RT1011_ADC_SET_1, 0x2925);
2296 regmap_write(rt1011->regmap, RT1011_CLASS_D_POS, 0x010e);
2297 regmap_write(rt1011->regmap,
2298 RT1011_CLASSD_INTERNAL_SET_1, 0x1701);
2301 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x8000);
2302 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_7, 0xf000);
2303 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4040);
2304 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0xc000);
2305 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x07c2);
2307 r0[0] = r0[1] = r0[2] = count = 0;
2308 while (count < chk_cnt) {
2310 regmap_read(rt1011->regmap,
2311 RT1011_INIT_RECIPROCAL_SYN_24_16, &value);
2312 r0[count%3] = value << 16;
2313 regmap_read(rt1011->regmap,
2314 RT1011_INIT_RECIPROCAL_SYN_15_0, &value);
2315 r0[count%3] |= value;
2317 if (r0[count%3] == 0)
2322 if (r0[0] == r0[1] && r0[1] == r0[2])
2325 if (count > chk_cnt) {
2326 dev_err(dev, "Calibrate R0 Failure\n");
2329 format = 2147483648U; /* 2^24 * 128 */
2330 r0_integer = format / r0[0] / 128;
2331 r0_factor = ((format / r0[0] * 100) / 128)
2332 - (r0_integer * 100);
2333 rt1011->r0_reg = r0[0];
2334 rt1011->cali_done = 1;
2335 dev_info(dev, "r0 resistance about %d.%02d ohm, reg=0x%X\n",
2336 r0_integer, r0_factor, r0[0]);
2341 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x0000);
2343 regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa840);
2344 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x0702);
2345 regmap_write(rt1011->regmap, RT1011_MIXER_1, 0xffdd);
2346 regmap_write(rt1011->regmap, RT1011_CLASSD_INTERNAL_SET_1, 0x0701);
2347 regmap_write(rt1011->regmap, RT1011_DAC_SET_3, 0xe004);
2348 regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f40);
2349 regmap_write(rt1011->regmap, RT1011_POWER_1, 0x0000);
2350 regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0000);
2351 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x0002);
2352 regmap_write(rt1011->regmap, RT1011_POWER_4, 0x00f2);
2354 regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2357 if (count <= chk_cnt) {
2358 regmap_write(rt1011->regmap,
2359 RT1011_INIT_RECIPROCAL_REG_24_16,
2360 ((r0[0]>>16) & 0x1ff));
2361 regmap_write(rt1011->regmap,
2362 RT1011_INIT_RECIPROCAL_REG_15_0,
2364 regmap_write(rt1011->regmap,
2365 RT1011_SPK_TEMP_PROTECT_4, 0x4080);
2369 regcache_cache_bypass(rt1011->regmap, false);
2370 regcache_mark_dirty(rt1011->regmap);
2371 regcache_sync(rt1011->regmap);
2372 snd_soc_dapm_mutex_unlock(dapm);
2377 static void rt1011_calibration_work(struct work_struct *work)
2379 struct rt1011_priv *rt1011 =
2380 container_of(work, struct rt1011_priv, cali_work);
2381 struct snd_soc_component *component = rt1011->component;
2382 unsigned int r0_integer, r0_factor, format;
2384 if (rt1011->r0_calib)
2385 rt1011_calibrate(rt1011, 0);
2387 rt1011_calibrate(rt1011, 1);
2390 * This flag should reset after booting.
2391 * The factory test will do calibration again and use this flag to check
2392 * whether the calibration completed
2394 rt1011->cali_done = 0;
2397 rt1011_reg_init(component);
2399 /* Apply temperature and calibration data from device property */
2400 if (rt1011->temperature_calib <= 0xff &&
2401 rt1011->temperature_calib > 0) {
2402 snd_soc_component_update_bits(component,
2403 RT1011_STP_INITIAL_RESISTANCE_TEMP, 0x3ff,
2404 (rt1011->temperature_calib << 2));
2407 if (rt1011->r0_calib) {
2408 rt1011->r0_reg = rt1011->r0_calib;
2410 format = 2147483648U; /* 2^24 * 128 */
2411 r0_integer = format / rt1011->r0_reg / 128;
2412 r0_factor = ((format / rt1011->r0_reg * 100) / 128)
2413 - (r0_integer * 100);
2414 dev_info(component->dev, "DP r0 resistance about %d.%02d ohm, reg=0x%X\n",
2415 r0_integer, r0_factor, rt1011->r0_reg);
2417 rt1011_r0_load(rt1011);
2420 snd_soc_component_write(component, RT1011_ADC_SET_1, 0x2925);
2423 static int rt1011_parse_dp(struct rt1011_priv *rt1011, struct device *dev)
2425 device_property_read_u32(dev, "realtek,temperature_calib",
2426 &rt1011->temperature_calib);
2427 device_property_read_u32(dev, "realtek,r0_calib",
2430 dev_dbg(dev, "%s: r0_calib: 0x%x, temperature_calib: 0x%x",
2431 __func__, rt1011->r0_calib, rt1011->temperature_calib);
2436 static int rt1011_i2c_probe(struct i2c_client *i2c,
2437 const struct i2c_device_id *id)
2439 struct rt1011_priv *rt1011;
2443 rt1011 = devm_kzalloc(&i2c->dev, sizeof(struct rt1011_priv),
2448 i2c_set_clientdata(i2c, rt1011);
2450 rt1011_parse_dp(rt1011, &i2c->dev);
2452 rt1011->regmap = devm_regmap_init_i2c(i2c, &rt1011_regmap);
2453 if (IS_ERR(rt1011->regmap)) {
2454 ret = PTR_ERR(rt1011->regmap);
2455 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2460 regmap_read(rt1011->regmap, RT1011_DEVICE_ID, &val);
2461 if (val != RT1011_DEVICE_ID_NUM) {
2463 "Device with ID register %x is not rt1011\n", val);
2467 INIT_WORK(&rt1011->cali_work, rt1011_calibration_work);
2469 return devm_snd_soc_register_component(&i2c->dev,
2470 &soc_component_dev_rt1011,
2471 rt1011_dai, ARRAY_SIZE(rt1011_dai));
2475 static void rt1011_i2c_shutdown(struct i2c_client *client)
2477 struct rt1011_priv *rt1011 = i2c_get_clientdata(client);
2479 rt1011_reset(rt1011->regmap);
2482 static struct i2c_driver rt1011_i2c_driver = {
2485 .of_match_table = of_match_ptr(rt1011_of_match),
2486 .acpi_match_table = ACPI_PTR(rt1011_acpi_match)
2488 .probe = rt1011_i2c_probe,
2489 .shutdown = rt1011_i2c_shutdown,
2490 .id_table = rt1011_i2c_id,
2492 module_i2c_driver(rt1011_i2c_driver);
2494 MODULE_DESCRIPTION("ASoC RT1011 amplifier driver");
2495 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
2496 MODULE_LICENSE("GPL");