1 // SPDX-License-Identifier: GPL-2.0
3 * rt1011.c -- rt1011 ALSA SoC amplifier component driver
5 * Copyright(c) 2019 Realtek Semiconductor Corp.
7 * Author: Shuming Fan <shumingf@realtek.com>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/i2c.h>
18 #include <linux/acpi.h>
19 #include <linux/regmap.h>
20 #include <linux/of_gpio.h>
21 #include <linux/platform_device.h>
22 #include <linux/firmware.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
34 static int rt1011_calibrate(struct rt1011_priv *rt1011,
35 unsigned char cali_flag);
37 static const struct reg_sequence init_list[] = {
39 { RT1011_POWER_9, 0xa840 },
41 { RT1011_ADC_SET_5, 0x0a20 },
42 { RT1011_DAC_SET_2, 0xa232 },
43 { RT1011_ADC_SET_1, 0x2925 },
45 { RT1011_SPK_PRO_DC_DET_1, 0xb00c },
46 { RT1011_SPK_PRO_DC_DET_2, 0xcccc },
48 { RT1011_A_TIMING_1, 0x6054 },
50 { RT1011_POWER_7, 0x3e55 },
51 { RT1011_POWER_8, 0x0520 },
52 { RT1011_BOOST_CON_1, 0xe188 },
53 { RT1011_POWER_4, 0x16f2 },
55 { RT1011_CROSS_BQ_SET_1, 0x0004 },
56 { RT1011_SIL_DET, 0xc313 },
57 { RT1011_SINE_GEN_REG_1, 0x0707 },
59 { RT1011_DC_CALIB_CLASSD_3, 0xcb00 },
61 { RT1011_DAC_SET_1, 0xe702 },
62 { RT1011_DAC_SET_3, 0x2004 },
64 #define RT1011_INIT_REG_LEN ARRAY_SIZE(init_list)
66 static const struct reg_default rt1011_reg[] = {
683 static int rt1011_reg_init(struct snd_soc_component *component)
685 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
687 regmap_multi_reg_write(rt1011->regmap, init_list, RT1011_INIT_REG_LEN);
691 static bool rt1011_volatile_register(struct device *dev, unsigned int reg)
698 case RT1011_VERSION_ID:
699 case RT1011_VENDOR_ID:
700 case RT1011_DEVICE_ID:
702 case RT1011_DAC_SET_3:
704 case RT1011_SPK_VOL_TEST_OUT:
705 case RT1011_VBAT_VOL_DET_1:
706 case RT1011_VBAT_TEST_OUT_1:
707 case RT1011_VBAT_TEST_OUT_2:
708 case RT1011_VBAT_PROTECTION:
709 case RT1011_VBAT_DET:
710 case RT1011_BOOST_CON_1:
711 case RT1011_SHORT_CIRCUIT_DET_1:
712 case RT1011_SPK_TEMP_PROTECT_3:
713 case RT1011_SPK_TEMP_PROTECT_6:
714 case RT1011_SPK_PRO_DC_DET_3:
715 case RT1011_SPK_PRO_DC_DET_7:
716 case RT1011_SPK_PRO_DC_DET_8:
719 case RT1011_EXCUR_PROTECT_1:
720 case RT1011_CROSS_BQ_SET_1:
721 case RT1011_CROSS_BQ_SET_2:
722 case RT1011_BQ_SET_0:
723 case RT1011_BQ_SET_1:
724 case RT1011_BQ_SET_2:
725 case RT1011_TEST_PAD_STATUS:
726 case RT1011_DC_CALIB_CLASSD_1:
727 case RT1011_DC_CALIB_CLASSD_5:
728 case RT1011_DC_CALIB_CLASSD_6:
729 case RT1011_DC_CALIB_CLASSD_7:
730 case RT1011_DC_CALIB_CLASSD_8:
731 case RT1011_SINE_GEN_REG_2:
732 case RT1011_STP_CALIB_RS_TEMP:
733 case RT1011_SPK_RESISTANCE_1:
734 case RT1011_SPK_RESISTANCE_2:
735 case RT1011_SPK_THERMAL:
736 case RT1011_ALC_BK_GAIN_O:
737 case RT1011_ALC_BK_GAIN_O_PRE:
738 case RT1011_SPK_DC_O_23_16:
739 case RT1011_SPK_DC_O_15_0:
740 case RT1011_INIT_RECIPROCAL_SYN_24_16:
741 case RT1011_INIT_RECIPROCAL_SYN_15_0:
742 case RT1011_SPK_EXCURSION_23_16:
743 case RT1011_SPK_EXCURSION_15_0:
744 case RT1011_SEP_MAIN_OUT_23_16:
745 case RT1011_SEP_MAIN_OUT_15_0:
746 case RT1011_ALC_DRC_HB_INTERNAL_5:
747 case RT1011_ALC_DRC_HB_INTERNAL_6:
748 case RT1011_ALC_DRC_HB_INTERNAL_7:
749 case RT1011_ALC_DRC_BB_INTERNAL_5:
750 case RT1011_ALC_DRC_BB_INTERNAL_6:
751 case RT1011_ALC_DRC_BB_INTERNAL_7:
752 case RT1011_ALC_DRC_POS_INTERNAL_5:
753 case RT1011_ALC_DRC_POS_INTERNAL_6:
754 case RT1011_ALC_DRC_POS_INTERNAL_7:
755 case RT1011_ALC_DRC_POS_INTERNAL_8:
756 case RT1011_ALC_DRC_POS_INTERNAL_9:
757 case RT1011_ALC_DRC_POS_INTERNAL_10:
758 case RT1011_ALC_DRC_POS_INTERNAL_11:
760 case RT1011_EFUSE_CONTROL_1:
761 case RT1011_EFUSE_CONTROL_2:
762 case RT1011_EFUSE_MATCH_DONE ... RT1011_EFUSE_READ_R0_3_15_0:
770 static bool rt1011_readable_register(struct device *dev, unsigned int reg)
785 case RT1011_PRIV_INDEX:
786 case RT1011_PRIV_DATA:
787 case RT1011_CUSTOMER_ID:
789 case RT1011_VERSION_ID:
790 case RT1011_VENDOR_ID:
791 case RT1011_DEVICE_ID:
792 case RT1011_DUM_RW_0:
794 case RT1011_DUM_RW_1:
796 case RT1011_MAN_I2C_DEV:
797 case RT1011_DAC_SET_1:
798 case RT1011_DAC_SET_2:
799 case RT1011_DAC_SET_3:
801 case RT1011_ADC_SET_1:
802 case RT1011_ADC_SET_2:
803 case RT1011_ADC_SET_3:
804 case RT1011_ADC_SET_4:
805 case RT1011_ADC_SET_5:
806 case RT1011_TDM_TOTAL_SET:
807 case RT1011_TDM1_SET_TCON:
808 case RT1011_TDM1_SET_1:
809 case RT1011_TDM1_SET_2:
810 case RT1011_TDM1_SET_3:
811 case RT1011_TDM1_SET_4:
812 case RT1011_TDM1_SET_5:
813 case RT1011_TDM2_SET_1:
814 case RT1011_TDM2_SET_2:
815 case RT1011_TDM2_SET_3:
816 case RT1011_TDM2_SET_4:
817 case RT1011_TDM2_SET_5:
821 case RT1011_ADRC_LIMIT:
823 case RT1011_A_TIMING_1:
824 case RT1011_A_TIMING_2:
825 case RT1011_A_TEMP_SEN:
826 case RT1011_SPK_VOL_DET_1:
827 case RT1011_SPK_VOL_DET_2:
828 case RT1011_SPK_VOL_TEST_OUT:
829 case RT1011_VBAT_VOL_DET_1:
830 case RT1011_VBAT_VOL_DET_2:
831 case RT1011_VBAT_TEST_OUT_1:
832 case RT1011_VBAT_TEST_OUT_2:
833 case RT1011_VBAT_PROTECTION:
834 case RT1011_VBAT_DET:
844 case RT1011_CLASS_D_POS:
845 case RT1011_BOOST_CON_1:
846 case RT1011_BOOST_CON_2:
847 case RT1011_ANALOG_CTRL:
848 case RT1011_POWER_SEQ:
849 case RT1011_SHORT_CIRCUIT_DET_1:
850 case RT1011_SHORT_CIRCUIT_DET_2:
851 case RT1011_SPK_TEMP_PROTECT_0:
852 case RT1011_SPK_TEMP_PROTECT_1:
853 case RT1011_SPK_TEMP_PROTECT_2:
854 case RT1011_SPK_TEMP_PROTECT_3:
855 case RT1011_SPK_TEMP_PROTECT_4:
856 case RT1011_SPK_TEMP_PROTECT_5:
857 case RT1011_SPK_TEMP_PROTECT_6:
858 case RT1011_SPK_TEMP_PROTECT_7:
859 case RT1011_SPK_TEMP_PROTECT_8:
860 case RT1011_SPK_TEMP_PROTECT_9:
861 case RT1011_SPK_PRO_DC_DET_1:
862 case RT1011_SPK_PRO_DC_DET_2:
863 case RT1011_SPK_PRO_DC_DET_3:
864 case RT1011_SPK_PRO_DC_DET_4:
865 case RT1011_SPK_PRO_DC_DET_5:
866 case RT1011_SPK_PRO_DC_DET_6:
867 case RT1011_SPK_PRO_DC_DET_7:
868 case RT1011_SPK_PRO_DC_DET_8:
873 case RT1011_THER_FOLD_BACK_1:
874 case RT1011_THER_FOLD_BACK_2:
875 case RT1011_EXCUR_PROTECT_1:
876 case RT1011_EXCUR_PROTECT_2:
877 case RT1011_EXCUR_PROTECT_3:
878 case RT1011_EXCUR_PROTECT_4:
879 case RT1011_BAT_GAIN_1:
880 case RT1011_BAT_GAIN_2:
881 case RT1011_BAT_GAIN_3:
882 case RT1011_BAT_GAIN_4:
883 case RT1011_BAT_GAIN_5:
884 case RT1011_BAT_GAIN_6:
885 case RT1011_BAT_GAIN_7:
886 case RT1011_BAT_GAIN_8:
887 case RT1011_BAT_GAIN_9:
888 case RT1011_BAT_GAIN_10:
889 case RT1011_BAT_GAIN_11:
890 case RT1011_BAT_RT_THMAX_1:
891 case RT1011_BAT_RT_THMAX_2:
892 case RT1011_BAT_RT_THMAX_3:
893 case RT1011_BAT_RT_THMAX_4:
894 case RT1011_BAT_RT_THMAX_5:
895 case RT1011_BAT_RT_THMAX_6:
896 case RT1011_BAT_RT_THMAX_7:
897 case RT1011_BAT_RT_THMAX_8:
898 case RT1011_BAT_RT_THMAX_9:
899 case RT1011_BAT_RT_THMAX_10:
900 case RT1011_BAT_RT_THMAX_11:
901 case RT1011_BAT_RT_THMAX_12:
902 case RT1011_SPREAD_SPECTURM:
903 case RT1011_PRO_GAIN_MODE:
904 case RT1011_RT_DRC_CROSS:
905 case RT1011_RT_DRC_HB_1:
906 case RT1011_RT_DRC_HB_2:
907 case RT1011_RT_DRC_HB_3:
908 case RT1011_RT_DRC_HB_4:
909 case RT1011_RT_DRC_HB_5:
910 case RT1011_RT_DRC_HB_6:
911 case RT1011_RT_DRC_HB_7:
912 case RT1011_RT_DRC_HB_8:
913 case RT1011_RT_DRC_BB_1:
914 case RT1011_RT_DRC_BB_2:
915 case RT1011_RT_DRC_BB_3:
916 case RT1011_RT_DRC_BB_4:
917 case RT1011_RT_DRC_BB_5:
918 case RT1011_RT_DRC_BB_6:
919 case RT1011_RT_DRC_BB_7:
920 case RT1011_RT_DRC_BB_8:
921 case RT1011_RT_DRC_POS_1:
922 case RT1011_RT_DRC_POS_2:
923 case RT1011_RT_DRC_POS_3:
924 case RT1011_RT_DRC_POS_4:
925 case RT1011_RT_DRC_POS_5:
926 case RT1011_RT_DRC_POS_6:
927 case RT1011_RT_DRC_POS_7:
928 case RT1011_RT_DRC_POS_8:
929 case RT1011_CROSS_BQ_SET_1:
930 case RT1011_CROSS_BQ_SET_2:
931 case RT1011_BQ_SET_0:
932 case RT1011_BQ_SET_1:
933 case RT1011_BQ_SET_2:
934 case RT1011_BQ_PRE_GAIN_28_16:
935 case RT1011_BQ_PRE_GAIN_15_0:
936 case RT1011_BQ_POST_GAIN_28_16:
937 case RT1011_BQ_POST_GAIN_15_0:
938 case RT1011_BQ_H0_28_16 ... RT1011_BQ_A2_15_0:
939 case RT1011_BQ_1_H0_28_16 ... RT1011_BQ_1_A2_15_0:
940 case RT1011_BQ_2_H0_28_16 ... RT1011_BQ_2_A2_15_0:
941 case RT1011_BQ_3_H0_28_16 ... RT1011_BQ_3_A2_15_0:
942 case RT1011_BQ_4_H0_28_16 ... RT1011_BQ_4_A2_15_0:
943 case RT1011_BQ_5_H0_28_16 ... RT1011_BQ_5_A2_15_0:
944 case RT1011_BQ_6_H0_28_16 ... RT1011_BQ_6_A2_15_0:
945 case RT1011_BQ_7_H0_28_16 ... RT1011_BQ_7_A2_15_0:
946 case RT1011_BQ_8_H0_28_16 ... RT1011_BQ_8_A2_15_0:
947 case RT1011_BQ_9_H0_28_16 ... RT1011_BQ_9_A2_15_0:
948 case RT1011_BQ_10_H0_28_16 ... RT1011_BQ_10_A2_15_0:
949 case RT1011_TEST_PAD_STATUS ... RT1011_PLL_INTERNAL_SET:
950 case RT1011_TEST_OUT_1 ... RT1011_TEST_OUT_3:
951 case RT1011_DC_CALIB_CLASSD_1 ... RT1011_DC_CALIB_CLASSD_10:
952 case RT1011_CLASSD_INTERNAL_SET_1 ... RT1011_VREF_LV_1:
953 case RT1011_SMART_BOOST_TIMING_1 ... RT1011_SMART_BOOST_TIMING_36:
954 case RT1011_SINE_GEN_REG_1 ... RT1011_SINE_GEN_REG_3:
955 case RT1011_STP_INITIAL_RS_TEMP ... RT1011_SPK_THERMAL:
956 case RT1011_STP_OTP_TH ... RT1011_INIT_RECIPROCAL_SYN_15_0:
957 case RT1011_STP_BQ_1_A1_L_28_16 ... RT1011_STP_BQ_1_H0_R_15_0:
958 case RT1011_STP_BQ_2_A1_L_28_16 ... RT1011_SEP_RE_REG_15_0:
959 case RT1011_DRC_CF_PARAMS_1 ... RT1011_DRC_CF_PARAMS_12:
960 case RT1011_ALC_DRC_HB_INTERNAL_1 ... RT1011_ALC_DRC_HB_INTERNAL_7:
961 case RT1011_ALC_DRC_BB_INTERNAL_1 ... RT1011_ALC_DRC_BB_INTERNAL_7:
962 case RT1011_ALC_DRC_POS_INTERNAL_1 ... RT1011_ALC_DRC_POS_INTERNAL_8:
963 case RT1011_ALC_DRC_POS_INTERNAL_9 ... RT1011_BQ_1_PARAMS_CHECK_5:
964 case RT1011_BQ_2_PARAMS_CHECK_1 ... RT1011_BQ_2_PARAMS_CHECK_5:
965 case RT1011_BQ_3_PARAMS_CHECK_1 ... RT1011_BQ_3_PARAMS_CHECK_5:
966 case RT1011_BQ_4_PARAMS_CHECK_1 ... RT1011_BQ_4_PARAMS_CHECK_5:
967 case RT1011_BQ_5_PARAMS_CHECK_1 ... RT1011_BQ_5_PARAMS_CHECK_5:
968 case RT1011_BQ_6_PARAMS_CHECK_1 ... RT1011_BQ_6_PARAMS_CHECK_5:
969 case RT1011_BQ_7_PARAMS_CHECK_1 ... RT1011_BQ_7_PARAMS_CHECK_5:
970 case RT1011_BQ_8_PARAMS_CHECK_1 ... RT1011_BQ_8_PARAMS_CHECK_5:
971 case RT1011_BQ_9_PARAMS_CHECK_1 ... RT1011_BQ_9_PARAMS_CHECK_5:
972 case RT1011_BQ_10_PARAMS_CHECK_1 ... RT1011_BQ_10_PARAMS_CHECK_5:
973 case RT1011_IRQ_1 ... RT1011_PART_NUMBER_EFUSE:
974 case RT1011_EFUSE_CONTROL_1 ... RT1011_EFUSE_READ_R0_3_15_0:
981 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
982 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1739, 37, 0);
984 static const char * const rt1011_din_source_select[] = {
987 "Left + Right average",
990 static SOC_ENUM_SINGLE_DECL(rt1011_din_source_enum, RT1011_CROSS_BQ_SET_1, 5,
991 rt1011_din_source_select);
993 static const char * const rt1011_tdm_data_out_select[] = {
994 "TDM_O_LR", "BQ1", "DVOL", "BQ10", "ALC", "DMIX", "ADC_SRC_LR",
995 "ADC_O_LR", "ADC_MONO", "RSPK_BPF_LR", "DMIX_ADD", "ENVELOPE_FS",
996 "SEP_O_GAIN", "ALC_BK_GAIN", "STP_V_C", "DMIX_ABST"
999 static const char * const rt1011_tdm_l_ch_data_select[] = {
1000 "Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
1002 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_l_dac1_enum, RT1011_TDM1_SET_4, 12,
1003 rt1011_tdm_l_ch_data_select);
1004 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_l_dac1_enum, RT1011_TDM2_SET_4, 12,
1005 rt1011_tdm_l_ch_data_select);
1007 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_dat_enum,
1008 RT1011_ADCDAT_OUT_SOURCE, 0, rt1011_tdm_data_out_select);
1009 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_loc_enum, RT1011_TDM1_SET_2, 0,
1010 rt1011_tdm_l_ch_data_select);
1012 static const char * const rt1011_adc_data_mode_select[] = {
1015 static SOC_ENUM_SINGLE_DECL(rt1011_adc_dout_mode_enum, RT1011_TDM1_SET_1, 12,
1016 rt1011_adc_data_mode_select);
1018 static const char * const rt1011_tdm_adc_data_len_control[] = {
1019 "1CH", "2CH", "3CH", "4CH", "5CH", "6CH", "7CH", "8CH"
1021 static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_dout_len_enum, RT1011_TDM1_SET_2, 13,
1022 rt1011_tdm_adc_data_len_control);
1023 static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_dout_len_enum, RT1011_TDM2_SET_2, 13,
1024 rt1011_tdm_adc_data_len_control);
1026 static const char * const rt1011_tdm_adc_swap_select[] = {
1027 "L/R", "R/L", "L/L", "R/R"
1030 static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc1_1_enum, RT1011_TDM1_SET_3, 6,
1031 rt1011_tdm_adc_swap_select);
1033 static void rt1011_reset(struct regmap *regmap)
1035 regmap_write(regmap, RT1011_RESET, 0);
1038 static int rt1011_recv_spk_mode_get(struct snd_kcontrol *kcontrol,
1039 struct snd_ctl_elem_value *ucontrol)
1041 struct snd_soc_component *component =
1042 snd_soc_kcontrol_component(kcontrol);
1043 struct rt1011_priv *rt1011 =
1044 snd_soc_component_get_drvdata(component);
1046 ucontrol->value.integer.value[0] = rt1011->recv_spk_mode;
1051 static int rt1011_recv_spk_mode_put(struct snd_kcontrol *kcontrol,
1052 struct snd_ctl_elem_value *ucontrol)
1054 struct snd_soc_component *component =
1055 snd_soc_kcontrol_component(kcontrol);
1056 struct rt1011_priv *rt1011 =
1057 snd_soc_component_get_drvdata(component);
1059 if (ucontrol->value.integer.value[0] == rt1011->recv_spk_mode)
1062 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1063 rt1011->recv_spk_mode = ucontrol->value.integer.value[0];
1065 if (rt1011->recv_spk_mode) {
1067 /* 1: recevier mode on */
1068 snd_soc_component_update_bits(component,
1069 RT1011_CLASSD_INTERNAL_SET_3,
1070 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1071 RT1011_REG_GAIN_CLASSD_RI_410K);
1072 snd_soc_component_update_bits(component,
1073 RT1011_CLASSD_INTERNAL_SET_1,
1074 RT1011_RECV_MODE_SPK_MASK,
1077 /* 0: speaker mode on */
1078 snd_soc_component_update_bits(component,
1079 RT1011_CLASSD_INTERNAL_SET_3,
1080 RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1081 RT1011_REG_GAIN_CLASSD_RI_72P5K);
1082 snd_soc_component_update_bits(component,
1083 RT1011_CLASSD_INTERNAL_SET_1,
1084 RT1011_RECV_MODE_SPK_MASK,
1092 static bool rt1011_validate_bq_drc_coeff(unsigned short reg)
1094 if ((reg == RT1011_DAC_SET_1) |
1095 (reg >= RT1011_ADC_SET && reg <= RT1011_ADC_SET_1) |
1096 (reg == RT1011_ADC_SET_4) | (reg == RT1011_ADC_SET_5) |
1097 (reg == RT1011_MIXER_1) |
1098 (reg == RT1011_A_TIMING_1) | (reg >= RT1011_POWER_7 &&
1099 reg <= RT1011_POWER_8) |
1100 (reg == RT1011_CLASS_D_POS) | (reg == RT1011_ANALOG_CTRL) |
1101 (reg >= RT1011_SPK_TEMP_PROTECT_0 &&
1102 reg <= RT1011_SPK_TEMP_PROTECT_6) |
1103 (reg >= RT1011_SPK_PRO_DC_DET_5 && reg <= RT1011_BAT_GAIN_1) |
1104 (reg >= RT1011_RT_DRC_CROSS && reg <= RT1011_RT_DRC_POS_8) |
1105 (reg >= RT1011_CROSS_BQ_SET_1 && reg <= RT1011_BQ_10_A2_15_0) |
1106 (reg >= RT1011_SMART_BOOST_TIMING_1 &&
1107 reg <= RT1011_SMART_BOOST_TIMING_36) |
1108 (reg == RT1011_SINE_GEN_REG_1) |
1109 (reg >= RT1011_STP_ALPHA_RECIPROCAL_MSB &&
1110 reg <= RT1011_BQ_6_PARAMS_CHECK_5) |
1111 (reg >= RT1011_BQ_7_PARAMS_CHECK_1 &&
1112 reg <= RT1011_BQ_10_PARAMS_CHECK_5))
1118 static int rt1011_bq_drc_coeff_get(struct snd_kcontrol *kcontrol,
1119 struct snd_ctl_elem_value *ucontrol)
1121 struct snd_soc_component *component =
1122 snd_soc_kcontrol_component(kcontrol);
1123 struct rt1011_priv *rt1011 =
1124 snd_soc_component_get_drvdata(component);
1125 struct rt1011_bq_drc_params *bq_drc_info;
1126 struct rt1011_bq_drc_params *params =
1127 (struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1128 unsigned int i, mode_idx = 0;
1130 if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1131 mode_idx = RT1011_ADVMODE_INITIAL_SET;
1132 else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1133 mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1134 else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1135 mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1136 else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1137 mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1138 else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1139 mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1143 pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1144 ucontrol->id.name, mode_idx);
1145 bq_drc_info = rt1011->bq_drc_params[mode_idx];
1147 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1148 params[i].reg = bq_drc_info[i].reg;
1149 params[i].val = bq_drc_info[i].val;
1155 static int rt1011_bq_drc_coeff_put(struct snd_kcontrol *kcontrol,
1156 struct snd_ctl_elem_value *ucontrol)
1158 struct snd_soc_component *component =
1159 snd_soc_kcontrol_component(kcontrol);
1160 struct rt1011_priv *rt1011 =
1161 snd_soc_component_get_drvdata(component);
1162 struct rt1011_bq_drc_params *bq_drc_info;
1163 struct rt1011_bq_drc_params *params =
1164 (struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1165 unsigned int i, mode_idx = 0;
1167 if (!component->card->instantiated)
1170 if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1171 mode_idx = RT1011_ADVMODE_INITIAL_SET;
1172 else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1173 mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1174 else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1175 mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1176 else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1177 mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1178 else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1179 mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1183 bq_drc_info = rt1011->bq_drc_params[mode_idx];
1184 memset(bq_drc_info, 0,
1185 sizeof(struct rt1011_bq_drc_params) * RT1011_BQ_DRC_NUM);
1187 pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1188 ucontrol->id.name, mode_idx);
1189 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1190 bq_drc_info[i].reg = params[i].reg;
1191 bq_drc_info[i].val = params[i].val;
1194 for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1195 if (bq_drc_info[i].reg == 0)
1197 else if (rt1011_validate_bq_drc_coeff(bq_drc_info[i].reg)) {
1198 snd_soc_component_write(component, bq_drc_info[i].reg,
1199 bq_drc_info[i].val);
1206 static int rt1011_bq_drc_info(struct snd_kcontrol *kcontrol,
1207 struct snd_ctl_elem_info *uinfo)
1209 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1211 uinfo->value.integer.max = 0x17ffffff;
1216 #define RT1011_BQ_DRC(xname) \
1217 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1218 .info = rt1011_bq_drc_info, \
1219 .get = rt1011_bq_drc_coeff_get, \
1220 .put = rt1011_bq_drc_coeff_put \
1223 static int rt1011_r0_cali_get(struct snd_kcontrol *kcontrol,
1224 struct snd_ctl_elem_value *ucontrol)
1226 ucontrol->value.integer.value[0] = 0;
1231 static int rt1011_r0_cali_put(struct snd_kcontrol *kcontrol,
1232 struct snd_ctl_elem_value *ucontrol)
1234 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1235 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1237 if (!component->card->instantiated)
1240 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF &&
1241 ucontrol->value.integer.value[0])
1242 rt1011_calibrate(rt1011, 1);
1247 static int rt1011_r0_load(struct rt1011_priv *rt1011)
1249 if (!rt1011->r0_reg)
1252 /* write R0 to register */
1253 regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_24_16,
1254 ((rt1011->r0_reg>>16) & 0x1ff));
1255 regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_15_0,
1256 (rt1011->r0_reg & 0xffff));
1257 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4080);
1262 static int rt1011_r0_load_mode_get(struct snd_kcontrol *kcontrol,
1263 struct snd_ctl_elem_value *ucontrol)
1265 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1266 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1268 ucontrol->value.integer.value[0] = rt1011->r0_reg;
1273 static int rt1011_r0_load_mode_put(struct snd_kcontrol *kcontrol,
1274 struct snd_ctl_elem_value *ucontrol)
1276 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1277 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1279 unsigned int r0_integer, r0_factor, format;
1281 if (ucontrol->value.integer.value[0] == rt1011->r0_reg)
1284 if (!component->card->instantiated)
1287 if (ucontrol->value.integer.value[0] == 0)
1290 dev = regmap_get_device(rt1011->regmap);
1291 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1292 rt1011->r0_reg = ucontrol->value.integer.value[0];
1294 format = 2147483648U; /* 2^24 * 128 */
1295 r0_integer = format / rt1011->r0_reg / 128;
1296 r0_factor = ((format / rt1011->r0_reg * 100) / 128)
1297 - (r0_integer * 100);
1298 dev_info(dev, "New r0 resistance about %d.%02d ohm, reg=0x%X\n",
1299 r0_integer, r0_factor, rt1011->r0_reg);
1302 rt1011_r0_load(rt1011);
1308 static int rt1011_r0_load_info(struct snd_kcontrol *kcontrol,
1309 struct snd_ctl_elem_info *uinfo)
1311 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1313 uinfo->value.integer.max = 0x1ffffff;
1318 #define RT1011_R0_LOAD(xname) \
1319 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1320 .info = rt1011_r0_load_info, \
1321 .get = rt1011_r0_load_mode_get, \
1322 .put = rt1011_r0_load_mode_put \
1325 static const struct snd_kcontrol_new rt1011_snd_controls[] = {
1326 /* I2S Data In Selection */
1327 SOC_ENUM("DIN Source", rt1011_din_source_enum),
1329 /* TDM Data In Selection */
1330 SOC_ENUM("TDM1 DIN Source", rt1011_tdm1_l_dac1_enum),
1331 SOC_ENUM("TDM2 DIN Source", rt1011_tdm2_l_dac1_enum),
1333 /* TDM1 Data Out Selection */
1334 SOC_ENUM("TDM1 DOUT Source", rt1011_tdm1_adc1_dat_enum),
1335 SOC_ENUM("TDM1 DOUT Location", rt1011_tdm1_adc1_loc_enum),
1336 SOC_ENUM("TDM1 ADCDAT Swap Select", rt1011_tdm_adc1_1_enum),
1339 SOC_ENUM("I2S ADC DOUT Mode", rt1011_adc_dout_mode_enum),
1340 SOC_ENUM("TDM1 DOUT Length", rt1011_tdm1_dout_len_enum),
1341 SOC_ENUM("TDM2 DOUT Length", rt1011_tdm2_dout_len_enum),
1343 /* Speaker/Receiver Mode */
1344 SOC_SINGLE_EXT("RECV SPK Mode", SND_SOC_NOPM, 0, 1, 0,
1345 rt1011_recv_spk_mode_get, rt1011_recv_spk_mode_put),
1347 /* BiQuad/DRC/SmartBoost Settings */
1348 RT1011_BQ_DRC("AdvanceMode Initial Set"),
1349 RT1011_BQ_DRC("AdvanceMode SEP BQ Coeff"),
1350 RT1011_BQ_DRC("AdvanceMode EQ BQ Coeff"),
1351 RT1011_BQ_DRC("AdvanceMode BQ UI Coeff"),
1352 RT1011_BQ_DRC("AdvanceMode SmartBoost Coeff"),
1355 SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0,
1356 rt1011_r0_cali_get, rt1011_r0_cali_put),
1357 RT1011_R0_LOAD("R0 Load Mode"),
1360 static int rt1011_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
1361 struct snd_soc_dapm_widget *sink)
1363 struct snd_soc_component *component =
1364 snd_soc_dapm_to_component(source->dapm);
1365 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1367 if (rt1011->sysclk_src == RT1011_FS_SYS_PRE_S_PLL1)
1373 static int rt1011_dac_event(struct snd_soc_dapm_widget *w,
1374 struct snd_kcontrol *kcontrol, int event)
1376 struct snd_soc_component *component =
1377 snd_soc_dapm_to_component(w->dapm);
1380 case SND_SOC_DAPM_POST_PMU:
1381 snd_soc_component_update_bits(component,
1382 RT1011_SPK_TEMP_PROTECT_0,
1383 RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK,
1384 RT1011_STP_EN | RT1011_STP_RS_CLB_EN);
1385 snd_soc_component_update_bits(component, RT1011_POWER_9,
1386 RT1011_POW_MNL_SDB_MASK, RT1011_POW_MNL_SDB);
1388 snd_soc_component_update_bits(component,
1389 RT1011_CLASSD_INTERNAL_SET_1,
1390 RT1011_DRIVER_READY_SPK, RT1011_DRIVER_READY_SPK);
1392 case SND_SOC_DAPM_PRE_PMD:
1393 snd_soc_component_update_bits(component, RT1011_POWER_9,
1394 RT1011_POW_MNL_SDB_MASK, 0);
1395 snd_soc_component_update_bits(component,
1396 RT1011_SPK_TEMP_PROTECT_0,
1397 RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 0);
1399 snd_soc_component_update_bits(component,
1400 RT1011_CLASSD_INTERNAL_SET_1,
1401 RT1011_DRIVER_READY_SPK, 0);
1412 static const struct snd_soc_dapm_widget rt1011_dapm_widgets[] = {
1413 SND_SOC_DAPM_SUPPLY("LDO2", RT1011_POWER_1,
1414 RT1011_POW_LDO2_BIT, 0, NULL, 0),
1415 SND_SOC_DAPM_SUPPLY("ISENSE SPK", RT1011_POWER_1,
1416 RT1011_POW_ISENSE_SPK_BIT, 0, NULL, 0),
1417 SND_SOC_DAPM_SUPPLY("VSENSE SPK", RT1011_POWER_1,
1418 RT1011_POW_VSENSE_SPK_BIT, 0, NULL, 0),
1420 SND_SOC_DAPM_SUPPLY("PLL", RT1011_POWER_2,
1421 RT1011_PLLEN_BIT, 0, NULL, 0),
1422 SND_SOC_DAPM_SUPPLY("BG", RT1011_POWER_2,
1423 RT1011_POW_BG_BIT, 0, NULL, 0),
1424 SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1011_POWER_2,
1425 RT1011_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
1427 SND_SOC_DAPM_SUPPLY("DET VBAT", RT1011_POWER_3,
1428 RT1011_POW_DET_VBAT_BIT, 0, NULL, 0),
1429 SND_SOC_DAPM_SUPPLY("MBIAS", RT1011_POWER_3,
1430 RT1011_POW_MBIAS_LV_BIT, 0, NULL, 0),
1431 SND_SOC_DAPM_SUPPLY("ADC I", RT1011_POWER_3,
1432 RT1011_POW_ADC_I_BIT, 0, NULL, 0),
1433 SND_SOC_DAPM_SUPPLY("ADC V", RT1011_POWER_3,
1434 RT1011_POW_ADC_V_BIT, 0, NULL, 0),
1435 SND_SOC_DAPM_SUPPLY("ADC T", RT1011_POWER_3,
1436 RT1011_POW_ADC_T_BIT, 0, NULL, 0),
1437 SND_SOC_DAPM_SUPPLY("DITHER ADC T", RT1011_POWER_3,
1438 RT1011_POWD_ADC_T_BIT, 0, NULL, 0),
1439 SND_SOC_DAPM_SUPPLY("MIX I", RT1011_POWER_3,
1440 RT1011_POW_MIX_I_BIT, 0, NULL, 0),
1441 SND_SOC_DAPM_SUPPLY("MIX V", RT1011_POWER_3,
1442 RT1011_POW_MIX_V_BIT, 0, NULL, 0),
1443 SND_SOC_DAPM_SUPPLY("SUM I", RT1011_POWER_3,
1444 RT1011_POW_SUM_I_BIT, 0, NULL, 0),
1445 SND_SOC_DAPM_SUPPLY("SUM V", RT1011_POWER_3,
1446 RT1011_POW_SUM_V_BIT, 0, NULL, 0),
1447 SND_SOC_DAPM_SUPPLY("MIX T", RT1011_POWER_3,
1448 RT1011_POW_MIX_T_BIT, 0, NULL, 0),
1449 SND_SOC_DAPM_SUPPLY("VREF", RT1011_POWER_3,
1450 RT1011_POW_VREF_LV_BIT, 0, NULL, 0),
1452 SND_SOC_DAPM_SUPPLY("BOOST SWR", RT1011_POWER_4,
1453 RT1011_POW_EN_SWR_BIT, 0, NULL, 0),
1454 SND_SOC_DAPM_SUPPLY("BGOK SWR", RT1011_POWER_4,
1455 RT1011_POW_EN_PASS_BGOK_SWR_BIT, 0, NULL, 0),
1456 SND_SOC_DAPM_SUPPLY("VPOK SWR", RT1011_POWER_4,
1457 RT1011_POW_EN_PASS_VPOK_SWR_BIT, 0, NULL, 0),
1459 SND_SOC_DAPM_SUPPLY("TEMP REG", RT1011_A_TEMP_SEN,
1460 RT1011_POW_TEMP_REG_BIT, 0, NULL, 0),
1462 /* Audio Interface */
1463 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1464 /* Digital Interface */
1465 SND_SOC_DAPM_SUPPLY("DAC Power", RT1011_POWER_1,
1466 RT1011_POW_DAC_BIT, 0, NULL, 0),
1467 SND_SOC_DAPM_SUPPLY("CLK12M", RT1011_POWER_1,
1468 RT1011_POW_CLK12M_BIT, 0, NULL, 0),
1469 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1011_DAC_SET_3,
1470 RT1011_DA_MUTE_EN_SFT, 1, rt1011_dac_event,
1471 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1474 SND_SOC_DAPM_OUTPUT("SPO"),
1477 static const struct snd_soc_dapm_route rt1011_dapm_routes[] = {
1479 { "DAC", NULL, "AIF1RX" },
1480 { "DAC", NULL, "DAC Power" },
1481 { "DAC", NULL, "LDO2" },
1482 { "DAC", NULL, "ISENSE SPK" },
1483 { "DAC", NULL, "VSENSE SPK" },
1484 { "DAC", NULL, "CLK12M" },
1486 { "DAC", NULL, "PLL", rt1011_is_sys_clk_from_pll },
1487 { "DAC", NULL, "BG" },
1488 { "DAC", NULL, "BG MBIAS" },
1490 { "DAC", NULL, "BOOST SWR" },
1491 { "DAC", NULL, "BGOK SWR" },
1492 { "DAC", NULL, "VPOK SWR" },
1494 { "DAC", NULL, "DET VBAT" },
1495 { "DAC", NULL, "MBIAS" },
1496 { "DAC", NULL, "VREF" },
1497 { "DAC", NULL, "ADC I" },
1498 { "DAC", NULL, "ADC V" },
1499 { "DAC", NULL, "ADC T" },
1500 { "DAC", NULL, "DITHER ADC T" },
1501 { "DAC", NULL, "MIX I" },
1502 { "DAC", NULL, "MIX V" },
1503 { "DAC", NULL, "SUM I" },
1504 { "DAC", NULL, "SUM V" },
1505 { "DAC", NULL, "MIX T" },
1507 { "DAC", NULL, "TEMP REG" },
1509 { "SPO", NULL, "DAC" },
1512 static int rt1011_get_clk_info(int sclk, int rate)
1514 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1516 if (sclk <= 0 || rate <= 0)
1520 for (i = 0; i < ARRAY_SIZE(pd); i++)
1521 if (sclk == rate * pd[i])
1527 static int rt1011_hw_params(struct snd_pcm_substream *substream,
1528 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1530 struct snd_soc_component *component = dai->component;
1531 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1532 unsigned int val_len = 0, ch_len = 0, val_clk, mask_clk;
1533 int pre_div, bclk_ms, frame_size;
1535 rt1011->lrck = params_rate(params);
1536 pre_div = rt1011_get_clk_info(rt1011->sysclk, rt1011->lrck);
1538 dev_warn(component->dev, "Force using PLL ");
1539 snd_soc_dai_set_pll(dai, 0, RT1011_PLL1_S_BCLK,
1540 rt1011->lrck * 64, rt1011->lrck * 256);
1541 snd_soc_dai_set_sysclk(dai, RT1011_FS_SYS_PRE_S_PLL1,
1542 rt1011->lrck * 256, SND_SOC_CLOCK_IN);
1545 frame_size = snd_soc_params_to_frame_size(params);
1546 if (frame_size < 0) {
1547 dev_err(component->dev, "Unsupported frame size: %d\n",
1552 bclk_ms = frame_size > 32;
1553 rt1011->bclk = rt1011->lrck * (32 << bclk_ms);
1555 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1556 bclk_ms, pre_div, dai->id);
1558 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1559 rt1011->lrck, pre_div, dai->id);
1561 switch (params_width(params)) {
1563 val_len |= RT1011_I2S_TX_DL_16B;
1564 val_len |= RT1011_I2S_RX_DL_16B;
1565 ch_len |= RT1011_I2S_CH_TX_LEN_16B;
1566 ch_len |= RT1011_I2S_CH_RX_LEN_16B;
1569 val_len |= RT1011_I2S_TX_DL_20B;
1570 val_len |= RT1011_I2S_RX_DL_20B;
1571 ch_len |= RT1011_I2S_CH_TX_LEN_20B;
1572 ch_len |= RT1011_I2S_CH_RX_LEN_20B;
1575 val_len |= RT1011_I2S_TX_DL_24B;
1576 val_len |= RT1011_I2S_RX_DL_24B;
1577 ch_len |= RT1011_I2S_CH_TX_LEN_24B;
1578 ch_len |= RT1011_I2S_CH_RX_LEN_24B;
1581 val_len |= RT1011_I2S_TX_DL_32B;
1582 val_len |= RT1011_I2S_RX_DL_32B;
1583 ch_len |= RT1011_I2S_CH_TX_LEN_32B;
1584 ch_len |= RT1011_I2S_CH_RX_LEN_32B;
1587 val_len |= RT1011_I2S_TX_DL_8B;
1588 val_len |= RT1011_I2S_RX_DL_8B;
1589 ch_len |= RT1011_I2S_CH_TX_LEN_8B;
1590 ch_len |= RT1011_I2S_CH_RX_LEN_8B;
1598 mask_clk = RT1011_FS_SYS_DIV_MASK;
1599 val_clk = pre_div << RT1011_FS_SYS_DIV_SFT;
1600 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1601 RT1011_I2S_TX_DL_MASK | RT1011_I2S_RX_DL_MASK,
1603 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1604 RT1011_I2S_CH_TX_LEN_MASK |
1605 RT1011_I2S_CH_RX_LEN_MASK,
1609 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1613 snd_soc_component_update_bits(component,
1614 RT1011_CLK_2, mask_clk, val_clk);
1619 static int rt1011_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1621 struct snd_soc_component *component = dai->component;
1622 unsigned int reg_val = 0, reg_bclk_inv = 0;
1624 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1625 case SND_SOC_DAIFMT_CBS_CFS:
1626 reg_val |= RT1011_I2S_TDM_MS_S;
1632 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1633 case SND_SOC_DAIFMT_NB_NF:
1635 case SND_SOC_DAIFMT_IB_NF:
1636 reg_bclk_inv |= RT1011_TDM_INV_BCLK;
1642 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1643 case SND_SOC_DAIFMT_I2S:
1645 case SND_SOC_DAIFMT_LEFT_J:
1646 reg_val |= RT1011_I2S_TDM_DF_LEFT;
1648 case SND_SOC_DAIFMT_DSP_A:
1649 reg_val |= RT1011_I2S_TDM_DF_PCM_A;
1651 case SND_SOC_DAIFMT_DSP_B:
1652 reg_val |= RT1011_I2S_TDM_DF_PCM_B;
1660 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1661 RT1011_I2S_TDM_MS_MASK | RT1011_I2S_TDM_DF_MASK,
1663 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1664 RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1665 snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
1666 RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1669 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1675 static int rt1011_set_component_sysclk(struct snd_soc_component *component,
1676 int clk_id, int source, unsigned int freq, int dir)
1678 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1679 unsigned int reg_val = 0;
1681 if (freq == rt1011->sysclk && clk_id == rt1011->sysclk_src)
1684 /* disable MCLK detect in default */
1685 snd_soc_component_update_bits(component, RT1011_CLK_DET,
1686 RT1011_EN_MCLK_DET_MASK, 0);
1689 case RT1011_FS_SYS_PRE_S_MCLK:
1690 reg_val |= RT1011_FS_SYS_PRE_MCLK;
1691 snd_soc_component_update_bits(component, RT1011_CLK_DET,
1692 RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1694 case RT1011_FS_SYS_PRE_S_BCLK:
1695 reg_val |= RT1011_FS_SYS_PRE_BCLK;
1697 case RT1011_FS_SYS_PRE_S_PLL1:
1698 reg_val |= RT1011_FS_SYS_PRE_PLL1;
1700 case RT1011_FS_SYS_PRE_S_RCCLK:
1701 reg_val |= RT1011_FS_SYS_PRE_RCCLK;
1704 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
1707 snd_soc_component_update_bits(component, RT1011_CLK_2,
1708 RT1011_FS_SYS_PRE_MASK, reg_val);
1709 rt1011->sysclk = freq;
1710 rt1011->sysclk_src = clk_id;
1712 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
1718 static int rt1011_set_component_pll(struct snd_soc_component *component,
1719 int pll_id, int source, unsigned int freq_in,
1720 unsigned int freq_out)
1722 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1723 struct rl6231_pll_code pll_code;
1726 if (source == rt1011->pll_src && freq_in == rt1011->pll_in &&
1727 freq_out == rt1011->pll_out)
1730 if (!freq_in || !freq_out) {
1731 dev_dbg(component->dev, "PLL disabled\n");
1734 rt1011->pll_out = 0;
1735 snd_soc_component_update_bits(component, RT1011_CLK_2,
1736 RT1011_FS_SYS_PRE_MASK, RT1011_FS_SYS_PRE_BCLK);
1741 case RT1011_PLL2_S_MCLK:
1742 snd_soc_component_update_bits(component, RT1011_CLK_2,
1743 RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_MCLK);
1744 snd_soc_component_update_bits(component, RT1011_CLK_2,
1745 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1746 snd_soc_component_update_bits(component, RT1011_CLK_DET,
1747 RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1749 case RT1011_PLL1_S_BCLK:
1750 snd_soc_component_update_bits(component, RT1011_CLK_2,
1751 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_BCLK);
1753 case RT1011_PLL2_S_RCCLK:
1754 snd_soc_component_update_bits(component, RT1011_CLK_2,
1755 RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_RCCLK);
1756 snd_soc_component_update_bits(component, RT1011_CLK_2,
1757 RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1760 dev_err(component->dev, "Unknown PLL Source %d\n", source);
1764 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1766 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
1770 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
1771 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1772 pll_code.n_code, pll_code.k_code);
1774 snd_soc_component_write(component, RT1011_PLL_1,
1775 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1011_PLL1_QM_SFT |
1776 pll_code.m_bp << RT1011_PLL1_BPM_SFT | pll_code.n_code);
1777 snd_soc_component_write(component, RT1011_PLL_2,
1780 rt1011->pll_in = freq_in;
1781 rt1011->pll_out = freq_out;
1782 rt1011->pll_src = source;
1787 static int rt1011_set_tdm_slot(struct snd_soc_dai *dai,
1788 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1790 struct snd_soc_component *component = dai->component;
1791 unsigned int val = 0, tdm_en = 0;
1793 if (rx_mask || tx_mask)
1794 tdm_en = RT1011_TDM_I2S_DOCK_EN_1;
1798 val |= RT1011_I2S_TX_4CH;
1799 val |= RT1011_I2S_RX_4CH;
1802 val |= RT1011_I2S_TX_6CH;
1803 val |= RT1011_I2S_RX_6CH;
1806 val |= RT1011_I2S_TX_8CH;
1807 val |= RT1011_I2S_RX_8CH;
1815 switch (slot_width) {
1817 val |= RT1011_I2S_CH_TX_LEN_20B;
1818 val |= RT1011_I2S_CH_RX_LEN_20B;
1821 val |= RT1011_I2S_CH_TX_LEN_24B;
1822 val |= RT1011_I2S_CH_RX_LEN_24B;
1825 val |= RT1011_I2S_CH_TX_LEN_32B;
1826 val |= RT1011_I2S_CH_RX_LEN_32B;
1834 snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1835 RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
1836 RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
1837 snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
1838 RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
1839 RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
1840 snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
1841 RT1011_TDM_I2S_DOCK_EN_1_MASK, tdm_en);
1842 snd_soc_component_update_bits(component, RT1011_TDM2_SET_2,
1843 RT1011_TDM_I2S_DOCK_EN_2_MASK, tdm_en);
1844 snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1845 RT1011_ADCDAT1_PIN_CONFIG | RT1011_ADCDAT2_PIN_CONFIG,
1846 RT1011_ADCDAT1_OUTPUT | RT1011_ADCDAT2_OUTPUT);
1851 static int rt1011_probe(struct snd_soc_component *component)
1853 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1856 rt1011->component = component;
1858 schedule_work(&rt1011->cali_work);
1860 rt1011->bq_drc_params = devm_kcalloc(component->dev,
1861 RT1011_ADVMODE_NUM, sizeof(struct rt1011_bq_drc_params *),
1863 if (!rt1011->bq_drc_params)
1866 for (i = 0; i < RT1011_ADVMODE_NUM; i++) {
1867 rt1011->bq_drc_params[i] = devm_kcalloc(component->dev,
1868 RT1011_BQ_DRC_NUM, sizeof(struct rt1011_bq_drc_params),
1870 if (!rt1011->bq_drc_params[i])
1877 static void rt1011_remove(struct snd_soc_component *component)
1879 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1881 cancel_work_sync(&rt1011->cali_work);
1882 rt1011_reset(rt1011->regmap);
1886 static int rt1011_suspend(struct snd_soc_component *component)
1888 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1890 regcache_cache_only(rt1011->regmap, true);
1891 regcache_mark_dirty(rt1011->regmap);
1896 static int rt1011_resume(struct snd_soc_component *component)
1898 struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1900 regcache_cache_only(rt1011->regmap, false);
1901 regcache_sync(rt1011->regmap);
1906 #define rt1011_suspend NULL
1907 #define rt1011_resume NULL
1910 static int rt1011_set_bias_level(struct snd_soc_component *component,
1911 enum snd_soc_bias_level level)
1914 case SND_SOC_BIAS_OFF:
1915 snd_soc_component_write(component,
1916 RT1011_SYSTEM_RESET_1, 0x0000);
1917 snd_soc_component_write(component,
1918 RT1011_SYSTEM_RESET_2, 0x0000);
1919 snd_soc_component_write(component,
1920 RT1011_SYSTEM_RESET_3, 0x0000);
1921 snd_soc_component_write(component,
1922 RT1011_SYSTEM_RESET_1, 0x003f);
1923 snd_soc_component_write(component,
1924 RT1011_SYSTEM_RESET_2, 0x7fd7);
1925 snd_soc_component_write(component,
1926 RT1011_SYSTEM_RESET_3, 0x770f);
1935 #define RT1011_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1936 #define RT1011_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
1937 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
1938 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1940 static const struct snd_soc_dai_ops rt1011_aif_dai_ops = {
1941 .hw_params = rt1011_hw_params,
1942 .set_fmt = rt1011_set_dai_fmt,
1943 .set_tdm_slot = rt1011_set_tdm_slot,
1946 static struct snd_soc_dai_driver rt1011_dai[] = {
1948 .name = "rt1011-aif",
1950 .stream_name = "AIF1 Playback",
1953 .rates = RT1011_STEREO_RATES,
1954 .formats = RT1011_FORMATS,
1956 .ops = &rt1011_aif_dai_ops,
1960 static const struct snd_soc_component_driver soc_component_dev_rt1011 = {
1961 .probe = rt1011_probe,
1962 .remove = rt1011_remove,
1963 .suspend = rt1011_suspend,
1964 .resume = rt1011_resume,
1965 .set_bias_level = rt1011_set_bias_level,
1966 .controls = rt1011_snd_controls,
1967 .num_controls = ARRAY_SIZE(rt1011_snd_controls),
1968 .dapm_widgets = rt1011_dapm_widgets,
1969 .num_dapm_widgets = ARRAY_SIZE(rt1011_dapm_widgets),
1970 .dapm_routes = rt1011_dapm_routes,
1971 .num_dapm_routes = ARRAY_SIZE(rt1011_dapm_routes),
1972 .set_sysclk = rt1011_set_component_sysclk,
1973 .set_pll = rt1011_set_component_pll,
1974 .use_pmdown_time = 1,
1976 .non_legacy_dai_naming = 1,
1979 static const struct regmap_config rt1011_regmap = {
1982 .max_register = RT1011_MAX_REG + 1,
1983 .volatile_reg = rt1011_volatile_register,
1984 .readable_reg = rt1011_readable_register,
1985 .cache_type = REGCACHE_RBTREE,
1986 .reg_defaults = rt1011_reg,
1987 .num_reg_defaults = ARRAY_SIZE(rt1011_reg),
1988 .use_single_read = true,
1989 .use_single_write = true,
1992 #if defined(CONFIG_OF)
1993 static const struct of_device_id rt1011_of_match[] = {
1994 { .compatible = "realtek,rt1011", },
1997 MODULE_DEVICE_TABLE(of, rt1011_of_match);
2001 static struct acpi_device_id rt1011_acpi_match[] = {
2005 MODULE_DEVICE_TABLE(acpi, rt1011_acpi_match);
2008 static const struct i2c_device_id rt1011_i2c_id[] = {
2012 MODULE_DEVICE_TABLE(i2c, rt1011_i2c_id);
2014 static int rt1011_calibrate(struct rt1011_priv *rt1011, unsigned char cali_flag)
2016 unsigned int value, count = 0, r0[3];
2017 unsigned int chk_cnt = 50; /* DONT change this */
2018 unsigned int dc_offset;
2019 unsigned int r0_integer, r0_factor, format;
2020 struct device *dev = regmap_get_device(rt1011->regmap);
2021 struct snd_soc_dapm_context *dapm =
2022 snd_soc_component_get_dapm(rt1011->component);
2025 snd_soc_dapm_mutex_lock(dapm);
2026 regcache_cache_bypass(rt1011->regmap, true);
2028 regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2029 regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x740f);
2030 regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x770f);
2033 regmap_write(rt1011->regmap, RT1011_CLK_2, 0x9400);
2034 regmap_write(rt1011->regmap, RT1011_PLL_1, 0x0800);
2035 regmap_write(rt1011->regmap, RT1011_PLL_2, 0x0020);
2036 regmap_write(rt1011->regmap, RT1011_CLK_DET, 0x0800);
2038 /* ADC/DAC setting */
2039 regmap_write(rt1011->regmap, RT1011_ADC_SET_5, 0x0a20);
2040 regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xe232);
2041 regmap_write(rt1011->regmap, RT1011_ADC_SET_1, 0x2925);
2042 regmap_write(rt1011->regmap, RT1011_ADC_SET_4, 0xc000);
2045 regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_1, 0xb00c);
2046 regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_2, 0xcccc);
2049 regmap_write(rt1011->regmap, RT1011_POWER_1, 0xe0e0);
2050 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5003);
2051 regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa860);
2052 regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xa032);
2054 /* POW_PLL / POW_BG / POW_BG_MBIAS_LV / POW_V/I */
2055 regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0007);
2056 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5ff7);
2057 regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f44);
2058 regmap_write(rt1011->regmap, RT1011_A_TIMING_1, 0x4054);
2059 regmap_write(rt1011->regmap, RT1011_BAT_GAIN_1, 0x309c);
2061 /* DC offset from EFUSE */
2062 regmap_write(rt1011->regmap, RT1011_DC_CALIB_CLASSD_3, 0xcb00);
2063 regmap_write(rt1011->regmap, RT1011_BOOST_CON_1, 0xe080);
2064 regmap_write(rt1011->regmap, RT1011_POWER_4, 0x16f2);
2065 regmap_write(rt1011->regmap, RT1011_POWER_6, 0x36ad);
2068 regmap_write(rt1011->regmap, RT1011_MIXER_1, 0x3f1d);
2071 regmap_write(rt1011->regmap, RT1011_EFUSE_CONTROL_1, 0x0d0a);
2074 regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_18_16, &value);
2075 dc_offset = value << 16;
2076 regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_15_0, &value);
2077 dc_offset |= (value & 0xffff);
2078 dev_info(dev, "ADC offset=0x%x\n", dc_offset);
2079 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_20_16, &value);
2080 dc_offset = value << 16;
2081 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_15_0, &value);
2082 dc_offset |= (value & 0xffff);
2083 dev_info(dev, "Gain0 offset=0x%x\n", dc_offset);
2084 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_20_16, &value);
2085 dc_offset = value << 16;
2086 regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_15_0, &value);
2087 dc_offset |= (value & 0xffff);
2088 dev_info(dev, "Gain1 offset=0x%x\n", dc_offset);
2093 regmap_write(rt1011->regmap, RT1011_CLASS_D_POS, 0x010e);
2094 regmap_write(rt1011->regmap,
2095 RT1011_CLASSD_INTERNAL_SET_1, 0x1701);
2098 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x8000);
2099 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_7, 0xf000);
2100 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4040);
2101 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0xc000);
2102 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x07c2);
2104 r0[0] = r0[1] = r0[2] = count = 0;
2105 while (count < chk_cnt) {
2107 regmap_read(rt1011->regmap,
2108 RT1011_INIT_RECIPROCAL_SYN_24_16, &value);
2109 r0[count%3] = value << 16;
2110 regmap_read(rt1011->regmap,
2111 RT1011_INIT_RECIPROCAL_SYN_15_0, &value);
2112 r0[count%3] |= value;
2114 if (r0[count%3] == 0)
2119 if (r0[0] == r0[1] && r0[1] == r0[2])
2122 if (count > chk_cnt) {
2123 dev_err(dev, "Calibrate R0 Failure\n");
2126 format = 2147483648U; /* 2^24 * 128 */
2127 r0_integer = format / r0[0] / 128;
2128 r0_factor = ((format / r0[0] * 100) / 128)
2129 - (r0_integer * 100);
2130 rt1011->r0_reg = r0[0];
2131 dev_info(dev, "r0 resistance about %d.%02d ohm, reg=0x%X\n",
2132 r0_integer, r0_factor, r0[0]);
2137 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x0000);
2139 regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa840);
2140 regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x0702);
2141 regmap_write(rt1011->regmap, RT1011_MIXER_1, 0xffdd);
2142 regmap_write(rt1011->regmap, RT1011_CLASSD_INTERNAL_SET_1, 0x0701);
2143 regmap_write(rt1011->regmap, RT1011_DAC_SET_3, 0xe004);
2144 regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f40);
2145 regmap_write(rt1011->regmap, RT1011_POWER_1, 0x0000);
2146 regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0000);
2147 regmap_write(rt1011->regmap, RT1011_POWER_3, 0x0002);
2148 regmap_write(rt1011->regmap, RT1011_POWER_4, 0x00f2);
2150 regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2153 if (count <= chk_cnt) {
2154 regmap_write(rt1011->regmap,
2155 RT1011_INIT_RECIPROCAL_REG_24_16,
2156 ((r0[0]>>16) & 0x1ff));
2157 regmap_write(rt1011->regmap,
2158 RT1011_INIT_RECIPROCAL_REG_15_0,
2160 regmap_write(rt1011->regmap,
2161 RT1011_SPK_TEMP_PROTECT_4, 0x4080);
2165 regcache_cache_bypass(rt1011->regmap, false);
2166 regcache_mark_dirty(rt1011->regmap);
2167 regcache_sync(rt1011->regmap);
2168 snd_soc_dapm_mutex_unlock(dapm);
2173 static void rt1011_calibration_work(struct work_struct *work)
2175 struct rt1011_priv *rt1011 =
2176 container_of(work, struct rt1011_priv, cali_work);
2177 struct snd_soc_component *component = rt1011->component;
2179 rt1011_calibrate(rt1011, 1);
2182 rt1011_reg_init(component);
2185 static int rt1011_i2c_probe(struct i2c_client *i2c,
2186 const struct i2c_device_id *id)
2188 struct rt1011_priv *rt1011;
2192 rt1011 = devm_kzalloc(&i2c->dev, sizeof(struct rt1011_priv),
2197 i2c_set_clientdata(i2c, rt1011);
2199 rt1011->regmap = devm_regmap_init_i2c(i2c, &rt1011_regmap);
2200 if (IS_ERR(rt1011->regmap)) {
2201 ret = PTR_ERR(rt1011->regmap);
2202 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2207 regmap_read(rt1011->regmap, RT1011_DEVICE_ID, &val);
2208 if (val != RT1011_DEVICE_ID_NUM) {
2210 "Device with ID register %x is not rt1011\n", val);
2214 INIT_WORK(&rt1011->cali_work, rt1011_calibration_work);
2216 return devm_snd_soc_register_component(&i2c->dev,
2217 &soc_component_dev_rt1011,
2218 rt1011_dai, ARRAY_SIZE(rt1011_dai));
2222 static void rt1011_i2c_shutdown(struct i2c_client *client)
2224 struct rt1011_priv *rt1011 = i2c_get_clientdata(client);
2226 rt1011_reset(rt1011->regmap);
2230 static struct i2c_driver rt1011_i2c_driver = {
2233 .of_match_table = of_match_ptr(rt1011_of_match),
2234 .acpi_match_table = ACPI_PTR(rt1011_acpi_match)
2236 .probe = rt1011_i2c_probe,
2237 .shutdown = rt1011_i2c_shutdown,
2238 .id_table = rt1011_i2c_id,
2240 module_i2c_driver(rt1011_i2c_driver);
2242 MODULE_DESCRIPTION("ASoC RT1011 amplifier driver");
2243 MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
2244 MODULE_LICENSE("GPL");