1 // SPDX-License-Identifier: GPL-2.0-only
3 * rl6231.c - RL6231 class device shared support
5 * Copyright 2014 Realtek Semiconductor Corp.
7 * Author: Oder Chiou <oder_chiou@realtek.com>
10 #include <linux/module.h>
11 #include <linux/regmap.h>
13 #include <linux/gcd.h>
17 * rl6231_get_pre_div - Return the value of pre divider.
19 * @map: map for setting.
23 * Return the value of pre divider from given register value.
24 * Return negative error code for unexpected register value.
26 int rl6231_get_pre_div(struct regmap *map, unsigned int reg, int sft)
30 regmap_read(map, reg, &val);
32 val = (val >> sft) & 0x7;
60 EXPORT_SYMBOL_GPL(rl6231_get_pre_div);
63 * rl6231_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
65 * @rate: base clock rate.
67 * Choose divider parameter that gives the highest possible DMIC frequency in
70 int rl6231_calc_dmic_clk(int rate)
72 static const int div[] = {2, 3, 4, 6, 8, 12};
75 if (rate < 1000000 * div[0]) {
76 pr_warn("Base clock rate %d is too low\n", rate);
80 for (i = 0; i < ARRAY_SIZE(div); i++) {
81 if ((div[i] % 3) == 0)
83 /* find divider that gives DMIC frequency below 3.072MHz */
84 if (3072000 * div[i] >= rate)
88 pr_warn("Base clock rate %d is too high\n", rate);
91 EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk);
102 static const struct pll_calc_map pll_preset_table[] = {
103 {19200000, 4096000, 23, 14, 1, false},
104 {19200000, 24576000, 3, 30, 3, false},
105 {3840000, 24576000, 3, 30, 0, true},
108 static unsigned int find_best_div(unsigned int in,
109 unsigned int max, unsigned int div)
128 * rl6231_pll_calc - Calcualte PLL M/N/K code.
129 * @freq_in: external clock provided to codec.
130 * @freq_out: target clock which codec works on.
131 * @pll_code: Pointer to structure with M, N, K and bypass flag.
133 * Calcualte M/N/K code to configure PLL for codec.
135 * Returns 0 for success or negative error code.
137 int rl6231_pll_calc(const unsigned int freq_in,
138 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
140 int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX;
142 int k_t, min_k, max_k, n = 0, m = 0, m_t = 0;
143 unsigned int red, pll_out, in_t, out_t, div, div_t;
144 unsigned int red_t = abs(freq_out - freq_in);
145 unsigned int f_in, f_out, f_max;
148 if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in)
151 for (i = 0; i < ARRAY_SIZE(pll_preset_table); i++) {
152 if (freq_in == pll_preset_table[i].pll_in &&
153 freq_out == pll_preset_table[i].pll_out) {
154 k = pll_preset_table[i].k;
155 m = pll_preset_table[i].m;
156 n = pll_preset_table[i].n;
157 bypass = pll_preset_table[i].m_bp;
158 pr_debug("Use preset PLL parameter table\n");
163 min_k = 80000000 / freq_out - 2;
164 max_k = 150000000 / freq_out - 2;
165 if (max_k > RL6231_PLL_K_MAX)
166 max_k = RL6231_PLL_K_MAX;
167 if (min_k > RL6231_PLL_K_MAX)
168 min_k = max_k = RL6231_PLL_K_MAX;
169 div_t = gcd(freq_in, freq_out);
170 f_max = 0xffffffff / RL6231_PLL_N_MAX;
171 div = find_best_div(freq_in, f_max, div_t);
172 f_in = freq_in / div;
173 f_out = freq_out / div;
175 for (k_t = min_k; k_t <= max_k; k_t++) {
176 for (n_t = 0; n_t <= max_n; n_t++) {
177 in_t = f_in * (n_t + 2);
178 pll_out = f_out * (k_t + 2);
179 if (in_t == pll_out) {
185 out_t = in_t / (k_t + 2);
186 red = abs(f_out - out_t);
196 for (m_t = 0; m_t <= max_m; m_t++) {
197 out_t = in_t / ((m_t + 2) * (k_t + 2));
198 red = abs(f_out - out_t);
211 pr_debug("Only get approximation about PLL\n");
215 pll_code->m_bp = bypass;
216 pll_code->m_code = m;
217 pll_code->n_code = n;
218 pll_code->k_code = k;
221 EXPORT_SYMBOL_GPL(rl6231_pll_calc);
223 int rl6231_get_clk_info(int sclk, int rate)
226 static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
228 if (sclk <= 0 || rate <= 0)
232 for (i = 0; i < ARRAY_SIZE(pd); i++)
233 if (sclk == rate * pd[i])
238 EXPORT_SYMBOL_GPL(rl6231_get_clk_info);
240 MODULE_DESCRIPTION("RL6231 class device shared support");
241 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
242 MODULE_LICENSE("GPL v2");