sound/soc/codecs/mt6358.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // mt6358.c  --  mt6358 ALSA SoC audio codec driver
   4 //
   5 // Copyright (c) 2018 MediaTek Inc.
   6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
   7
   8 #include <linux/platform_device.h>
   9 #include <linux/module.h>
  10 #include <linux/of_device.h>
  11 #include <linux/delay.h>
  12 #include <linux/kthread.h>
  13 #include <linux/sched.h>
  14 #include <linux/mfd/mt6397/core.h>
  15 #include <linux/regulator/consumer.h>
  16
  17 #include <sound/soc.h>
  18 #include <sound/tlv.h>
  19
  20 #include "mt6358.h"
  21
  22 enum {
  23         AUDIO_ANALOG_VOLUME_HSOUTL,
  24         AUDIO_ANALOG_VOLUME_HSOUTR,
  25         AUDIO_ANALOG_VOLUME_HPOUTL,
  26         AUDIO_ANALOG_VOLUME_HPOUTR,
  27         AUDIO_ANALOG_VOLUME_LINEOUTL,
  28         AUDIO_ANALOG_VOLUME_LINEOUTR,
  29         AUDIO_ANALOG_VOLUME_MICAMP1,
  30         AUDIO_ANALOG_VOLUME_MICAMP2,
  31         AUDIO_ANALOG_VOLUME_TYPE_MAX
  32 };
  33
  34 enum {
  35         MUX_ADC_L,
  36         MUX_ADC_R,
  37         MUX_PGA_L,
  38         MUX_PGA_R,
  39         MUX_MIC_TYPE,
  40         MUX_HP_L,
  41         MUX_HP_R,
  42         MUX_NUM,
  43 };
  44
  45 enum {
  46         DEVICE_HP,
  47         DEVICE_LO,
  48         DEVICE_RCV,
  49         DEVICE_MIC1,
  50         DEVICE_MIC2,
  51         DEVICE_NUM
  52 };
  53
  54 /* Supply widget subseq */
  55 enum {
  56         /* common */
  57         SUPPLY_SEQ_CLK_BUF,
  58         SUPPLY_SEQ_AUD_GLB,
  59         SUPPLY_SEQ_CLKSQ,
  60         SUPPLY_SEQ_VOW_AUD_LPW,
  61         SUPPLY_SEQ_AUD_VOW,
  62         SUPPLY_SEQ_VOW_CLK,
  63         SUPPLY_SEQ_VOW_LDO,
  64         SUPPLY_SEQ_TOP_CK,
  65         SUPPLY_SEQ_TOP_CK_LAST,
  66         SUPPLY_SEQ_AUD_TOP,
  67         SUPPLY_SEQ_AUD_TOP_LAST,
  68         SUPPLY_SEQ_AFE,
  69         /* capture */
  70         SUPPLY_SEQ_ADC_SUPPLY,
  71 };
  72
  73 enum {
  74         CH_L = 0,
  75         CH_R,
  76         NUM_CH,
  77 };
  78
  79 #define REG_STRIDE 2
  80
  81 struct mt6358_priv {
  82         struct device *dev;
  83         struct regmap *regmap;
  84
  85         unsigned int dl_rate;
  86         unsigned int ul_rate;
  87
  88         int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
  89         unsigned int mux_select[MUX_NUM];
  90
  91         int dev_counter[DEVICE_NUM];
  92
  93         int mtkaif_protocol;
  94
  95         struct regulator *avdd_reg;
  96
  97         int wov_enabled;
  98
  99         unsigned int dmic_one_wire_mode;
 100 };
 101
 102 int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
 103                                int mtkaif_protocol)
 104 {
 105         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 106
 107         priv->mtkaif_protocol = mtkaif_protocol;
 108         return 0;
 109 }
 110
 111 static void playback_gpio_set(struct mt6358_priv *priv)
 112 {
 113         /* set gpio mosi mode */
 114         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
 115                            0x01f8, 0x01f8);
 116         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET,
 117                            0xffff, 0x0249);
 118         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
 119                            0xffff, 0x0249);
 120 }
 121
 122 static void playback_gpio_reset(struct mt6358_priv *priv)
 123 {
 124         /* set pad_aud_*_mosi to GPIO mode and dir input
 125          * reason:
 126          * pad_aud_dat_mosi*, because the pin is used as boot strap
 127          * don't clean clk/sync, for mtkaif protocol 2
 128          */
 129         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR,
 130                            0x01f8, 0x01f8);
 131         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2,
 132                            0x01f8, 0x0000);
 133         regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
 134                            0xf << 8, 0x0);
 135 }
 136
 137 static void capture_gpio_set(struct mt6358_priv *priv)
 138 {
 139         /* set gpio miso mode */
 140         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
 141                            0xffff, 0xffff);
 142         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET,
 143                            0xffff, 0x0249);
 144         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
 145                            0xffff, 0x0249);
 146 }
 147
 148 static void capture_gpio_reset(struct mt6358_priv *priv)
 149 {
 150         /* set pad_aud_*_miso to GPIO mode and dir input
 151          * reason:
 152          * pad_aud_clk_miso, because when playback only the miso_clk
 153          * will also have 26m, so will have power leak
 154          * pad_aud_dat_miso*, because the pin is used as boot strap
 155          */
 156         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR,
 157                            0xffff, 0xffff);
 158         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3,
 159                            0xffff, 0x0000);
 160         regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0,
 161                            0xf << 12, 0x0);
 162 }
 163
 164 /* use only when not govern by DAPM */
 165 static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable)
 166 {
 167         regmap_update_bits(priv->regmap, MT6358_DCXO_CW14,
 168                            0x1 << RG_XO_AUDIO_EN_M_SFT,
 169                            (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
 170         return 0;
 171 }
 172
 173 /* use only when not govern by DAPM */
 174 static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable)
 175 {
 176         /* audio clk source from internal dcxo */
 177         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
 178                            RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
 179                            0x0);
 180
 181         /* Enable/disable CLKSQ 26MHz */
 182         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
 183                            RG_CLKSQ_EN_MASK_SFT,
 184                            (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
 185         return 0;
 186 }
 187
 188 /* use only when not govern by DAPM */
 189 static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable)
 190 {
 191         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
 192                            RG_AUDGLB_PWRDN_VA28_MASK_SFT,
 193                            (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT);
 194         return 0;
 195 }
 196
 197 /* use only when not govern by DAPM */
 198 static int mt6358_set_topck(struct mt6358_priv *priv, bool enable)
 199 {
 200         regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
 201                            0x0066, enable ? 0x0 : 0x66);
 202         return 0;
 203 }
 204
 205 static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv)
 206 {
 207         switch (priv->mtkaif_protocol) {
 208         case MT6358_MTKAIF_PROTOCOL_2_CLK_P2:
 209                 /* MTKAIF TX format setting */
 210                 regmap_update_bits(priv->regmap,
 211                                    MT6358_AFE_ADDA_MTKAIF_CFG0,
 212                                    0xffff, 0x0010);
 213                 /* enable aud_pad TX fifos */
 214                 regmap_update_bits(priv->regmap,
 215                                    MT6358_AFE_AUD_PAD_TOP,
 216                                    0xff00, 0x3800);
 217                 regmap_update_bits(priv->regmap,
 218                                    MT6358_AFE_AUD_PAD_TOP,
 219                                    0xff00, 0x3900);
 220                 break;
 221         case MT6358_MTKAIF_PROTOCOL_2:
 222                 /* MTKAIF TX format setting */
 223                 regmap_update_bits(priv->regmap,
 224                                    MT6358_AFE_ADDA_MTKAIF_CFG0,
 225                                    0xffff, 0x0010);
 226                 /* enable aud_pad TX fifos */
 227                 regmap_update_bits(priv->regmap,
 228                                    MT6358_AFE_AUD_PAD_TOP,
 229                                    0xff00, 0x3100);
 230                 break;
 231         case MT6358_MTKAIF_PROTOCOL_1:
 232         default:
 233                 /* MTKAIF TX format setting */
 234                 regmap_update_bits(priv->regmap,
 235                                    MT6358_AFE_ADDA_MTKAIF_CFG0,
 236                                    0xffff, 0x0000);
 237                 /* enable aud_pad TX fifos */
 238                 regmap_update_bits(priv->regmap,
 239                                    MT6358_AFE_AUD_PAD_TOP,
 240                                    0xff00, 0x3100);
 241                 break;
 242         }
 243         return 0;
 244 }
 245
 246 static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv)
 247 {
 248         /* disable aud_pad TX fifos */
 249         regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP,
 250                            0xff00, 0x3000);
 251         return 0;
 252 }
 253
 254 int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt)
 255 {
 256         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 257
 258         playback_gpio_set(priv);
 259         capture_gpio_set(priv);
 260         mt6358_mtkaif_tx_enable(priv);
 261
 262         mt6358_set_dcxo(priv, true);
 263         mt6358_set_aud_global_bias(priv, true);
 264         mt6358_set_clksq(priv, true);
 265         mt6358_set_topck(priv, true);
 266
 267         /* set dat_miso_loopback on */
 268         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 269                            RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
 270                            1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
 271         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 272                            RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
 273                            1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
 274         return 0;
 275 }
 276
 277 int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt)
 278 {
 279         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 280
 281         /* set dat_miso_loopback off */
 282         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 283                            RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT,
 284                            0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT);
 285         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 286                            RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT,
 287                            0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT);
 288
 289         mt6358_set_topck(priv, false);
 290         mt6358_set_clksq(priv, false);
 291         mt6358_set_aud_global_bias(priv, false);
 292         mt6358_set_dcxo(priv, false);
 293
 294         mt6358_mtkaif_tx_disable(priv);
 295         playback_gpio_reset(priv);
 296         capture_gpio_reset(priv);
 297         return 0;
 298 }
 299
 300 int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
 301                                         int phase_1, int phase_2)
 302 {
 303         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 304
 305         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 306                            RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT,
 307                            phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT);
 308         regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG,
 309                            RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT,
 310                            phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT);
 311         return 0;
 312 }
 313
 314 /* dl pga gain */
 315 enum {
 316         DL_GAIN_8DB = 0,
 317         DL_GAIN_0DB = 8,
 318         DL_GAIN_N_1DB = 9,
 319         DL_GAIN_N_10DB = 18,
 320         DL_GAIN_N_40DB = 0x1f,
 321 };
 322
 323 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
 324 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
 325 #define DL_GAIN_REG_MASK 0x0f9f
 326
 327 static void hp_zcd_disable(struct mt6358_priv *priv)
 328 {
 329         regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000);
 330 }
 331
 332 static void hp_main_output_ramp(struct mt6358_priv *priv, bool up)
 333 {
 334         int i = 0, stage = 0;
 335         int target = 7;
 336
 337         /* Enable/Reduce HPL/R main output stage step by step */
 338         for (i = 0; i <= target; i++) {
 339                 stage = up ? i : target - i;
 340                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
 341                                    0x7 << 8, stage << 8);
 342                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
 343                                    0x7 << 11, stage << 11);
 344                 usleep_range(100, 150);
 345         }
 346 }
 347
 348 static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up)
 349 {
 350         int i = 0, stage = 0;
 351
 352         /* Reduce HP aux feedback loop gain step by step */
 353         for (i = 0; i <= 0xf; i++) {
 354                 stage = up ? i : 0xf - i;
 355                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
 356                                    0xf << 12, stage << 12);
 357                 usleep_range(100, 150);
 358         }
 359 }
 360
 361 static void hp_pull_down(struct mt6358_priv *priv, bool enable)
 362 {
 363         int i;
 364
 365         if (enable) {
 366                 for (i = 0x0; i <= 0x6; i++) {
 367                         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
 368                                            0x7, i);
 369                         usleep_range(600, 700);
 370                 }
 371         } else {
 372                 for (i = 0x6; i >= 0x1; i--) {
 373                         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
 374                                            0x7, i);
 375                         usleep_range(600, 700);
 376                 }
 377         }
 378 }
 379
 380 static bool is_valid_hp_pga_idx(int reg_idx)
 381 {
 382         return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) ||
 383                reg_idx == DL_GAIN_N_40DB;
 384 }
 385
 386 static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to)
 387 {
 388         int offset = 0, count = 0, reg_idx;
 389
 390         if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to))
 391                 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
 392                          __func__, from, to);
 393
 394         dev_info(priv->dev, "%s(), from %d, to %d\n",
 395                  __func__, from, to);
 396
 397         if (to > from)
 398                 offset = to - from;
 399         else
 400                 offset = from - to;
 401
 402         while (offset >= 0) {
 403                 if (to > from)
 404                         reg_idx = from + count;
 405                 else
 406                         reg_idx = from - count;
 407
 408                 if (is_valid_hp_pga_idx(reg_idx)) {
 409                         regmap_update_bits(priv->regmap,
 410                                            MT6358_ZCD_CON2,
 411                                            DL_GAIN_REG_MASK,
 412                                            (reg_idx << 7) | reg_idx);
 413                         usleep_range(200, 300);
 414                 }
 415                 offset--;
 416                 count++;
 417         }
 418 }
 419
 420 static int mt6358_put_volsw(struct snd_kcontrol *kcontrol,
 421                             struct snd_ctl_elem_value *ucontrol)
 422 {
 423         struct snd_soc_component *component =
 424                         snd_soc_kcontrol_component(kcontrol);
 425         struct mt6358_priv *priv = snd_soc_component_get_drvdata(component);
 426         struct soc_mixer_control *mc =
 427                         (struct soc_mixer_control *)kcontrol->private_value;
 428         unsigned int reg;
 429         int ret;
 430
 431         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 432         if (ret < 0)
 433                 return ret;
 434
 435         switch (mc->reg) {
 436         case MT6358_ZCD_CON2:
 437                 regmap_read(priv->regmap, MT6358_ZCD_CON2, &reg);
 438                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
 439                         (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK;
 440                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
 441                         (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK;
 442                 break;
 443         case MT6358_ZCD_CON1:
 444                 regmap_read(priv->regmap, MT6358_ZCD_CON1, &reg);
 445                 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
 446                         (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK;
 447                 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
 448                         (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK;
 449                 break;
 450         case MT6358_ZCD_CON3:
 451                 regmap_read(priv->regmap, MT6358_ZCD_CON3, &reg);
 452                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
 453                         (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
 454                 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] =
 455                         (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK;
 456                 break;
 457         case MT6358_AUDENC_ANA_CON0:
 458         case MT6358_AUDENC_ANA_CON1:
 459                 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, &reg);
 460                 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
 461                         (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK;
 462                 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, &reg);
 463                 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
 464                         (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK;
 465                 break;
 466         }
 467
 468         return ret;
 469 }
 470
 471 static void mt6358_restore_pga(struct mt6358_priv *priv);
 472
 473 static int mt6358_enable_wov_phase2(struct mt6358_priv *priv)
 474 {
 475         /* analog */
 476         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
 477                            0xffff, 0x0000);
 478         regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
 479         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
 480                            0xffff, 0x0800);
 481         mt6358_restore_pga(priv);
 482
 483         regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929);
 484         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
 485                            0xffff, 0x0025);
 486         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
 487                            0xffff, 0x0005);
 488
 489         /* digital */
 490         regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
 491                            0xffff, 0x0000);
 492         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120);
 493         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff);
 494         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200);
 495         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424);
 496         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac);
 497         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e);
 498         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000);
 499         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
 500                            0xffff, 0x0000);
 501         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
 502                            0xffff, 0x0451);
 503         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1);
 504
 505         return 0;
 506 }
 507
 508 static int mt6358_disable_wov_phase2(struct mt6358_priv *priv)
 509 {
 510         /* digital */
 511         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000);
 512         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0,
 513                            0xffff, 0x0450);
 514         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0,
 515                            0xffff, 0x0c00);
 516         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100);
 517         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c);
 518         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879);
 519         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323);
 520         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400);
 521         regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000);
 522         regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8);
 523         regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0,
 524                            0xffff, 0x0000);
 525
 526         /* analog */
 527         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8,
 528                            0xffff, 0x0004);
 529         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
 530                            0xffff, 0x0000);
 531         regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829);
 532         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
 533                            0xffff, 0x0000);
 534         mt6358_restore_pga(priv);
 535         regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5);
 536         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
 537                            0xffff, 0x0010);
 538
 539         return 0;
 540 }
 541
 542 static int mt6358_get_wov(struct snd_kcontrol *kcontrol,
 543                           struct snd_ctl_elem_value *ucontrol)
 544 {
 545         struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
 546         struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
 547
 548         ucontrol->value.integer.value[0] = priv->wov_enabled;
 549         return 0;
 550 }
 551
 552 static int mt6358_put_wov(struct snd_kcontrol *kcontrol,
 553                           struct snd_ctl_elem_value *ucontrol)
 554 {
 555         struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol);
 556         struct mt6358_priv *priv = snd_soc_component_get_drvdata(c);
 557         int enabled = ucontrol->value.integer.value[0];
 558
 559         if (priv->wov_enabled != enabled) {
 560                 if (enabled)
 561                         mt6358_enable_wov_phase2(priv);
 562                 else
 563                         mt6358_disable_wov_phase2(priv);
 564
 565                 priv->wov_enabled = enabled;
 566         }
 567
 568         return 0;
 569 }
 570
 571 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
 572 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0);
 573
 574 static const struct snd_kcontrol_new mt6358_snd_controls[] = {
 575         /* dl pga gain */
 576         SOC_DOUBLE_EXT_TLV("Headphone Volume",
 577                            MT6358_ZCD_CON2, 0, 7, 0x12, 1,
 578                            snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
 579         SOC_DOUBLE_EXT_TLV("Lineout Volume",
 580                            MT6358_ZCD_CON1, 0, 7, 0x12, 1,
 581                            snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
 582         SOC_SINGLE_EXT_TLV("Handset Volume",
 583                            MT6358_ZCD_CON3, 0, 0x12, 1,
 584                            snd_soc_get_volsw, mt6358_put_volsw, playback_tlv),
 585         /* ul pga gain */
 586         SOC_DOUBLE_R_EXT_TLV("PGA Volume",
 587                              MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1,
 588                              8, 4, 0,
 589                              snd_soc_get_volsw, mt6358_put_volsw, pga_tlv),
 590
 591         SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0,
 592                             mt6358_get_wov, mt6358_put_wov),
 593 };
 594
 595 /* MUX */
 596 /* LOL MUX */
 597 static const char * const lo_in_mux_map[] = {
 598         "Open", "Mute", "Playback", "Test Mode"
 599 };
 600
 601 static int lo_in_mux_map_value[] = {
 602         0x0, 0x1, 0x2, 0x3,
 603 };
 604
 605 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum,
 606                                   MT6358_AUDDEC_ANA_CON7,
 607                                   RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT,
 608                                   RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK,
 609                                   lo_in_mux_map,
 610                                   lo_in_mux_map_value);
 611
 612 static const struct snd_kcontrol_new lo_in_mux_control =
 613         SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum);
 614
 615 /*HP MUX */
 616 enum {
 617         HP_MUX_OPEN = 0,
 618         HP_MUX_HPSPK,
 619         HP_MUX_HP,
 620         HP_MUX_TEST_MODE,
 621         HP_MUX_HP_IMPEDANCE,
 622         HP_MUX_MASK = 0x7,
 623 };
 624
 625 static const char * const hp_in_mux_map[] = {
 626         "Open",
 627         "LoudSPK Playback",
 628         "Audio Playback",
 629         "Test Mode",
 630         "HP Impedance",
 631         "undefined1",
 632         "undefined2",
 633         "undefined3",
 634 };
 635
 636 static int hp_in_mux_map_value[] = {
 637         HP_MUX_OPEN,
 638         HP_MUX_HPSPK,
 639         HP_MUX_HP,
 640         HP_MUX_TEST_MODE,
 641         HP_MUX_HP_IMPEDANCE,
 642         HP_MUX_OPEN,
 643         HP_MUX_OPEN,
 644         HP_MUX_OPEN,
 645 };
 646
 647 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum,
 648                                   SND_SOC_NOPM,
 649                                   0,
 650                                   HP_MUX_MASK,
 651                                   hp_in_mux_map,
 652                                   hp_in_mux_map_value);
 653
 654 static const struct snd_kcontrol_new hpl_in_mux_control =
 655         SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum);
 656
 657 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum,
 658                                   SND_SOC_NOPM,
 659                                   0,
 660                                   HP_MUX_MASK,
 661                                   hp_in_mux_map,
 662                                   hp_in_mux_map_value);
 663
 664 static const struct snd_kcontrol_new hpr_in_mux_control =
 665         SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum);
 666
 667 /* RCV MUX */
 668 enum {
 669         RCV_MUX_OPEN = 0,
 670         RCV_MUX_MUTE,
 671         RCV_MUX_VOICE_PLAYBACK,
 672         RCV_MUX_TEST_MODE,
 673         RCV_MUX_MASK = 0x3,
 674 };
 675
 676 static const char * const rcv_in_mux_map[] = {
 677         "Open", "Mute", "Voice Playback", "Test Mode"
 678 };
 679
 680 static int rcv_in_mux_map_value[] = {
 681         RCV_MUX_OPEN,
 682         RCV_MUX_MUTE,
 683         RCV_MUX_VOICE_PLAYBACK,
 684         RCV_MUX_TEST_MODE,
 685 };
 686
 687 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum,
 688                                   SND_SOC_NOPM,
 689                                   0,
 690                                   RCV_MUX_MASK,
 691                                   rcv_in_mux_map,
 692                                   rcv_in_mux_map_value);
 693
 694 static const struct snd_kcontrol_new rcv_in_mux_control =
 695         SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum);
 696
 697 /* DAC In MUX */
 698 static const char * const dac_in_mux_map[] = {
 699         "Normal Path", "Sgen"
 700 };
 701
 702 static int dac_in_mux_map_value[] = {
 703         0x0, 0x1,
 704 };
 705
 706 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum,
 707                                   MT6358_AFE_TOP_CON0,
 708                                   DL_SINE_ON_SFT,
 709                                   DL_SINE_ON_MASK,
 710                                   dac_in_mux_map,
 711                                   dac_in_mux_map_value);
 712
 713 static const struct snd_kcontrol_new dac_in_mux_control =
 714         SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum);
 715
 716 /* AIF Out MUX */
 717 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum,
 718                                   MT6358_AFE_TOP_CON0,
 719                                   UL_SINE_ON_SFT,
 720                                   UL_SINE_ON_MASK,
 721                                   dac_in_mux_map,
 722                                   dac_in_mux_map_value);
 723
 724 static const struct snd_kcontrol_new aif_out_mux_control =
 725         SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum);
 726
 727 /* Mic Type MUX */
 728 enum {
 729         MIC_TYPE_MUX_IDLE = 0,
 730         MIC_TYPE_MUX_ACC,
 731         MIC_TYPE_MUX_DMIC,
 732         MIC_TYPE_MUX_DCC,
 733         MIC_TYPE_MUX_DCC_ECM_DIFF,
 734         MIC_TYPE_MUX_DCC_ECM_SINGLE,
 735         MIC_TYPE_MUX_MASK = 0x7,
 736 };
 737
 738 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
 739                         (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
 740                         (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
 741
 742 static const char * const mic_type_mux_map[] = {
 743         "Idle",
 744         "ACC",
 745         "DMIC",
 746         "DCC",
 747         "DCC_ECM_DIFF",
 748         "DCC_ECM_SINGLE",
 749 };
 750
 751 static int mic_type_mux_map_value[] = {
 752         MIC_TYPE_MUX_IDLE,
 753         MIC_TYPE_MUX_ACC,
 754         MIC_TYPE_MUX_DMIC,
 755         MIC_TYPE_MUX_DCC,
 756         MIC_TYPE_MUX_DCC_ECM_DIFF,
 757         MIC_TYPE_MUX_DCC_ECM_SINGLE,
 758 };
 759
 760 static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum,
 761                                   SND_SOC_NOPM,
 762                                   0,
 763                                   MIC_TYPE_MUX_MASK,
 764                                   mic_type_mux_map,
 765                                   mic_type_mux_map_value);
 766
 767 static const struct snd_kcontrol_new mic_type_mux_control =
 768         SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum);
 769
 770 /* ADC L MUX */
 771 enum {
 772         ADC_MUX_IDLE = 0,
 773         ADC_MUX_AIN0,
 774         ADC_MUX_PREAMPLIFIER,
 775         ADC_MUX_IDLE1,
 776         ADC_MUX_MASK = 0x3,
 777 };
 778
 779 static const char * const adc_left_mux_map[] = {
 780         "Idle", "AIN0", "Left Preamplifier", "Idle_1"
 781 };
 782
 783 static int adc_mux_map_value[] = {
 784         ADC_MUX_IDLE,
 785         ADC_MUX_AIN0,
 786         ADC_MUX_PREAMPLIFIER,
 787         ADC_MUX_IDLE1,
 788 };
 789
 790 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum,
 791                                   SND_SOC_NOPM,
 792                                   0,
 793                                   ADC_MUX_MASK,
 794                                   adc_left_mux_map,
 795                                   adc_mux_map_value);
 796
 797 static const struct snd_kcontrol_new adc_left_mux_control =
 798         SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum);
 799
 800 /* ADC R MUX */
 801 static const char * const adc_right_mux_map[] = {
 802         "Idle", "AIN0", "Right Preamplifier", "Idle_1"
 803 };
 804
 805 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum,
 806                                   SND_SOC_NOPM,
 807                                   0,
 808                                   ADC_MUX_MASK,
 809                                   adc_right_mux_map,
 810                                   adc_mux_map_value);
 811
 812 static const struct snd_kcontrol_new adc_right_mux_control =
 813         SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum);
 814
 815 /* PGA L MUX */
 816 enum {
 817         PGA_MUX_NONE = 0,
 818         PGA_MUX_AIN0,
 819         PGA_MUX_AIN1,
 820         PGA_MUX_AIN2,
 821         PGA_MUX_MASK = 0x3,
 822 };
 823
 824 static const char * const pga_mux_map[] = {
 825         "None", "AIN0", "AIN1", "AIN2"
 826 };
 827
 828 static int pga_mux_map_value[] = {
 829         PGA_MUX_NONE,
 830         PGA_MUX_AIN0,
 831         PGA_MUX_AIN1,
 832         PGA_MUX_AIN2,
 833 };
 834
 835 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum,
 836                                   SND_SOC_NOPM,
 837                                   0,
 838                                   PGA_MUX_MASK,
 839                                   pga_mux_map,
 840                                   pga_mux_map_value);
 841
 842 static const struct snd_kcontrol_new pga_left_mux_control =
 843         SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum);
 844
 845 /* PGA R MUX */
 846 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum,
 847                                   SND_SOC_NOPM,
 848                                   0,
 849                                   PGA_MUX_MASK,
 850                                   pga_mux_map,
 851                                   pga_mux_map_value);
 852
 853 static const struct snd_kcontrol_new pga_right_mux_control =
 854         SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum);
 855
 856 static int mt_clksq_event(struct snd_soc_dapm_widget *w,
 857                           struct snd_kcontrol *kcontrol,
 858                           int event)
 859 {
 860         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 861         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 862
 863         dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
 864
 865         switch (event) {
 866         case SND_SOC_DAPM_PRE_PMU:
 867                 /* audio clk source from internal dcxo */
 868                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6,
 869                                    RG_CLKSQ_IN_SEL_TEST_MASK_SFT,
 870                                    0x0);
 871                 break;
 872         default:
 873                 break;
 874         }
 875
 876         return 0;
 877 }
 878
 879 static int mt_sgen_event(struct snd_soc_dapm_widget *w,
 880                          struct snd_kcontrol *kcontrol,
 881                          int event)
 882 {
 883         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 884         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 885
 886         dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
 887
 888         switch (event) {
 889         case SND_SOC_DAPM_PRE_PMU:
 890                 /* sdm audio fifo clock power on */
 891                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
 892                 /* scrambler clock on enable */
 893                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
 894                 /* sdm power on */
 895                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
 896                 /* sdm fifo enable */
 897                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
 898
 899                 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0,
 900                                    0xff3f,
 901                                    0x0000);
 902                 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1,
 903                                    0xffff,
 904                                    0x0001);
 905                 break;
 906         case SND_SOC_DAPM_POST_PMD:
 907                 /* DL scrambler disabling sequence */
 908                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
 909                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
 910                 break;
 911         default:
 912                 break;
 913         }
 914
 915         return 0;
 916 }
 917
 918 static int mt_aif_in_event(struct snd_soc_dapm_widget *w,
 919                            struct snd_kcontrol *kcontrol,
 920                            int event)
 921 {
 922         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
 923         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
 924
 925         dev_info(priv->dev, "%s(), event 0x%x, rate %d\n",
 926                  __func__, event, priv->dl_rate);
 927
 928         switch (event) {
 929         case SND_SOC_DAPM_PRE_PMU:
 930                 playback_gpio_set(priv);
 931
 932                 /* sdm audio fifo clock power on */
 933                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006);
 934                 /* scrambler clock on enable */
 935                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1);
 936                 /* sdm power on */
 937                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003);
 938                 /* sdm fifo enable */
 939                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B);
 940                 break;
 941         case SND_SOC_DAPM_POST_PMD:
 942                 /* DL scrambler disabling sequence */
 943                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000);
 944                 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0);
 945
 946                 playback_gpio_reset(priv);
 947                 break;
 948         default:
 949                 break;
 950         }
 951
 952         return 0;
 953 }
 954
 955 static int mtk_hp_enable(struct mt6358_priv *priv)
 956 {
 957         /* Pull-down HPL/R to AVSS28_AUD */
 958         hp_pull_down(priv, true);
 959         /* release HP CMFB gate rstb */
 960         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
 961                            0x1 << 6, 0x1 << 6);
 962
 963         /* Reduce ESD resistance of AU_REFN */
 964         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
 965
 966         /* Set HPR/HPL gain as minimum (~ -40dB) */
 967         regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG);
 968
 969         /* Turn on DA_600K_NCP_VA18 */
 970         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
 971         /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
 972         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
 973         /* Toggle RG_DIVCKS_CHG */
 974         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
 975         /* Set NCP soft start mode as default mode: 100us */
 976         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
 977         /* Enable NCP */
 978         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
 979         usleep_range(250, 270);
 980
 981         /* Enable cap-less LDOs (1.5V) */
 982         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
 983                            0x1055, 0x1055);
 984         /* Enable NV regulator (-1.2V) */
 985         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
 986         usleep_range(100, 120);
 987
 988         /* Disable AUD_ZCD */
 989         hp_zcd_disable(priv);
 990
 991         /* Disable headphone short-circuit protection */
 992         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
 993
 994         /* Enable IBIST */
 995         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
 996
 997         /* Set HP DR bias current optimization, 010: 6uA */
 998         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
 999         /* Set HP & ZCD bias current optimization */
1000         /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1001         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1002         /* Set HPP/N STB enhance circuits */
1003         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
1004
1005         /* Enable HP aux output stage */
1006         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c);
1007         /* Enable HP aux feedback loop */
1008         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c);
1009         /* Enable HP aux CMFB loop */
1010         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
1011         /* Enable HP driver bias circuits */
1012         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
1013         /* Enable HP driver core circuits */
1014         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
1015         /* Short HP main output to HP aux output stage */
1016         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc);
1017
1018         /* Enable HP main CMFB loop */
1019         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
1020         /* Disable HP aux CMFB loop */
1021         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
1022
1023         /* Select CMFB resistor bulk to AC mode */
1024         /* Selec HS/LO cap size (6.5pF default) */
1025         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1026
1027         /* Enable HP main output stage */
1028         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff);
1029         /* Enable HPR/L main output stage step by step */
1030         hp_main_output_ramp(priv, true);
1031
1032         /* Reduce HP aux feedback loop gain */
1033         hp_aux_feedback_loop_gain_ramp(priv, true);
1034         /* Disable HP aux feedback loop */
1035         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1036
1037         /* apply volume setting */
1038         headset_volume_ramp(priv,
1039                             DL_GAIN_N_10DB,
1040                             priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1041
1042         /* Disable HP aux output stage */
1043         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1044         /* Unshort HP main output to HP aux output stage */
1045         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03);
1046         usleep_range(100, 120);
1047
1048         /* Enable AUD_CLK */
1049         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
1050         /* Enable Audio DAC  */
1051         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff);
1052         /* Enable low-noise mode of DAC */
1053         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201);
1054         usleep_range(100, 120);
1055
1056         /* Switch HPL MUX to audio DAC */
1057         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff);
1058         /* Switch HPR MUX to audio DAC */
1059         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff);
1060
1061         /* Disable Pull-down HPL/R to AVSS28_AUD */
1062         hp_pull_down(priv, false);
1063
1064         return 0;
1065 }
1066
1067 static int mtk_hp_disable(struct mt6358_priv *priv)
1068 {
1069         /* Pull-down HPL/R to AVSS28_AUD */
1070         hp_pull_down(priv, true);
1071
1072         /* HPR/HPL mux to open */
1073         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1074                            0x0f00, 0x0000);
1075
1076         /* Disable low-noise mode of DAC */
1077         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1078                            0x0001, 0x0000);
1079
1080         /* Disable Audio DAC */
1081         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1082                            0x000f, 0x0000);
1083
1084         /* Disable AUD_CLK */
1085         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1086
1087         /* Short HP main output to HP aux output stage */
1088         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1089         /* Enable HP aux output stage */
1090         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1091
1092         /* decrease HPL/R gain to normal gain step by step */
1093         headset_volume_ramp(priv,
1094                             priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1095                             DL_GAIN_N_40DB);
1096
1097         /* Enable HP aux feedback loop */
1098         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1099
1100         /* Reduce HP aux feedback loop gain */
1101         hp_aux_feedback_loop_gain_ramp(priv, false);
1102
1103         /* decrease HPR/L main output stage step by step */
1104         hp_main_output_ramp(priv, false);
1105
1106         /* Disable HP main output stage */
1107         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1108
1109         /* Enable HP aux CMFB loop */
1110         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00);
1111
1112         /* Disable HP main CMFB loop */
1113         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00);
1114
1115         /* Unshort HP main output to HP aux output stage */
1116         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1117                            0x3 << 6, 0x0);
1118
1119         /* Disable HP driver core circuits */
1120         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1121                            0x3 << 4, 0x0);
1122
1123         /* Disable HP driver bias circuits */
1124         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1125                            0x3 << 6, 0x0);
1126
1127         /* Disable HP aux CMFB loop */
1128         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1129
1130         /* Disable HP aux feedback loop */
1131         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1132                            0x3 << 4, 0x0);
1133
1134         /* Disable HP aux output stage */
1135         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1,
1136                            0x3 << 2, 0x0);
1137
1138         /* Disable IBIST */
1139         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1140                            0x1 << 8, 0x1 << 8);
1141
1142         /* Disable NV regulator (-1.2V) */
1143         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1144         /* Disable cap-less LDOs (1.5V) */
1145         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1146                            0x1055, 0x0);
1147         /* Disable NCP */
1148         regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1149                            0x1, 0x1);
1150
1151         /* Increase ESD resistance of AU_REFN */
1152         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2,
1153                            0x1 << 14, 0x0);
1154
1155         /* Set HP CMFB gate rstb */
1156         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1157                            0x1 << 6, 0x0);
1158         /* disable Pull-down HPL/R to AVSS28_AUD */
1159         hp_pull_down(priv, false);
1160
1161         return 0;
1162 }
1163
1164 static int mtk_hp_spk_enable(struct mt6358_priv *priv)
1165 {
1166         /* Pull-down HPL/R to AVSS28_AUD */
1167         hp_pull_down(priv, true);
1168         /* release HP CMFB gate rstb */
1169         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1170                            0x1 << 6, 0x1 << 6);
1171
1172         /* Reduce ESD resistance of AU_REFN */
1173         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1174
1175         /* Set HPR/HPL gain to -10dB */
1176         regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG);
1177
1178         /* Turn on DA_600K_NCP_VA18 */
1179         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1180         /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1181         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1182         /* Toggle RG_DIVCKS_CHG */
1183         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1184         /* Set NCP soft start mode as default mode: 100us */
1185         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1186         /* Enable NCP */
1187         regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1188         usleep_range(250, 270);
1189
1190         /* Enable cap-less LDOs (1.5V) */
1191         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1192                            0x1055, 0x1055);
1193         /* Enable NV regulator (-1.2V) */
1194         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1195         usleep_range(100, 120);
1196
1197         /* Disable AUD_ZCD */
1198         hp_zcd_disable(priv);
1199
1200         /* Disable headphone short-circuit protection */
1201         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000);
1202
1203         /* Enable IBIST */
1204         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1205
1206         /* Set HP DR bias current optimization, 010: 6uA */
1207         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1208         /* Set HP & ZCD bias current optimization */
1209         /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1210         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1211         /* Set HPP/N STB enhance circuits */
1212         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033);
1213
1214         /* Disable Pull-down HPL/R to AVSS28_AUD */
1215         hp_pull_down(priv, false);
1216
1217         /* Enable HP driver bias circuits */
1218         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0);
1219         /* Enable HP driver core circuits */
1220         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0);
1221         /* Enable HP main CMFB loop */
1222         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200);
1223
1224         /* Select CMFB resistor bulk to AC mode */
1225         /* Selec HS/LO cap size (6.5pF default) */
1226         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1227
1228         /* Enable HP main output stage */
1229         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003);
1230         /* Enable HPR/L main output stage step by step */
1231         hp_main_output_ramp(priv, true);
1232
1233         /* Set LO gain as minimum (~ -40dB) */
1234         regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG);
1235         /* apply volume setting */
1236         headset_volume_ramp(priv,
1237                             DL_GAIN_N_10DB,
1238                             priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
1239
1240         /* Set LO STB enhance circuits */
1241         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110);
1242         /* Enable LO driver bias circuits */
1243         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112);
1244         /* Enable LO driver core circuits */
1245         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113);
1246
1247         /* Set LOL gain to normal gain step by step */
1248         regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1249                            RG_AUDLOLGAIN_MASK_SFT,
1250                            priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] <<
1251                            RG_AUDLOLGAIN_SFT);
1252         regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1253                            RG_AUDLORGAIN_MASK_SFT,
1254                            priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] <<
1255                            RG_AUDLORGAIN_SFT);
1256
1257         /* Enable AUD_CLK */
1258         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1);
1259         /* Enable Audio DAC  */
1260         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9);
1261         /* Enable low-noise mode of DAC */
1262         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201);
1263         /* Switch LOL MUX to audio DAC */
1264         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b);
1265         /* Switch HPL/R MUX to Line-out */
1266         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9);
1267
1268         return 0;
1269 }
1270
1271 static int mtk_hp_spk_disable(struct mt6358_priv *priv)
1272 {
1273         /* HPR/HPL mux to open */
1274         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1275                            0x0f00, 0x0000);
1276         /* LOL mux to open */
1277         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1278                            0x3 << 2, 0x0000);
1279
1280         /* Disable Audio DAC */
1281         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1282                            0x000f, 0x0000);
1283
1284         /* Disable AUD_CLK */
1285         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0);
1286
1287         /* decrease HPL/R gain to normal gain step by step */
1288         headset_volume_ramp(priv,
1289                             priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
1290                             DL_GAIN_N_40DB);
1291
1292         /* decrease LOL gain to minimum gain step by step */
1293         regmap_update_bits(priv->regmap, MT6358_ZCD_CON1,
1294                            DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG);
1295
1296         /* decrease HPR/L main output stage step by step */
1297         hp_main_output_ramp(priv, false);
1298
1299         /* Disable HP main output stage */
1300         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0);
1301
1302         /* Short HP main output to HP aux output stage */
1303         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3);
1304         /* Enable HP aux output stage */
1305         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf);
1306
1307         /* Enable HP aux feedback loop */
1308         regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff);
1309
1310         /* Reduce HP aux feedback loop gain */
1311         hp_aux_feedback_loop_gain_ramp(priv, false);
1312
1313         /* Disable HP driver core circuits */
1314         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1315                            0x3 << 4, 0x0);
1316         /* Disable LO driver core circuits */
1317         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1318                            0x1, 0x0);
1319
1320         /* Disable HP driver bias circuits */
1321         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1322                            0x3 << 6, 0x0);
1323         /* Disable LO driver bias circuits */
1324         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
1325                            0x1 << 1, 0x0);
1326
1327         /* Disable HP aux CMFB loop */
1328         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1329                            0xff << 8, 0x0000);
1330
1331         /* Disable IBIST */
1332         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1333                            0x1 << 8, 0x1 << 8);
1334         /* Disable NV regulator (-1.2V) */
1335         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0);
1336         /* Disable cap-less LDOs (1.5V) */
1337         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0);
1338         /* Disable NCP */
1339         regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1);
1340
1341         /* Set HP CMFB gate rstb */
1342         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4,
1343                            0x1 << 6, 0x0);
1344         /* disable Pull-down HPL/R to AVSS28_AUD */
1345         hp_pull_down(priv, false);
1346
1347         return 0;
1348 }
1349
1350 static int mt_hp_event(struct snd_soc_dapm_widget *w,
1351                        struct snd_kcontrol *kcontrol,
1352                        int event)
1353 {
1354         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1355         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1356         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1357         int device = DEVICE_HP;
1358
1359         dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1360                  __func__,
1361                  event,
1362                  priv->dev_counter[device],
1363                  mux);
1364
1365         switch (event) {
1366         case SND_SOC_DAPM_PRE_PMU:
1367                 priv->dev_counter[device]++;
1368                 if (priv->dev_counter[device] > 1)
1369                         break;  /* already enabled, do nothing */
1370                 else if (priv->dev_counter[device] <= 0)
1371                         dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n",
1372                                  __func__,
1373                                  priv->dev_counter[device]);
1374
1375                 priv->mux_select[MUX_HP_L] = mux;
1376
1377                 if (mux == HP_MUX_HP)
1378                         mtk_hp_enable(priv);
1379                 else if (mux == HP_MUX_HPSPK)
1380                         mtk_hp_spk_enable(priv);
1381                 break;
1382         case SND_SOC_DAPM_PRE_PMD:
1383                 priv->dev_counter[device]--;
1384                 if (priv->dev_counter[device] > 0) {
1385                         break;  /* still being used, don't close */
1386                 } else if (priv->dev_counter[device] < 0) {
1387                         dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n",
1388                                  __func__,
1389                                  priv->dev_counter[device]);
1390                         priv->dev_counter[device] = 0;
1391                         break;
1392                 }
1393
1394                 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP)
1395                         mtk_hp_disable(priv);
1396                 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK)
1397                         mtk_hp_spk_disable(priv);
1398
1399                 priv->mux_select[MUX_HP_L] = mux;
1400                 break;
1401         default:
1402                 break;
1403         }
1404
1405         return 0;
1406 }
1407
1408 static int mt_rcv_event(struct snd_soc_dapm_widget *w,
1409                         struct snd_kcontrol *kcontrol,
1410                         int event)
1411 {
1412         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1413         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1414
1415         dev_info(priv->dev, "%s(), event 0x%x, mux %u\n",
1416                  __func__,
1417                  event,
1418                  dapm_kcontrol_get_value(w->kcontrols[0]));
1419
1420         switch (event) {
1421         case SND_SOC_DAPM_PRE_PMU:
1422                 /* Reduce ESD resistance of AU_REFN */
1423                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000);
1424
1425                 /* Turn on DA_600K_NCP_VA18 */
1426                 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001);
1427                 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */
1428                 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c);
1429                 /* Toggle RG_DIVCKS_CHG */
1430                 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001);
1431                 /* Set NCP soft start mode as default mode: 100us */
1432                 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003);
1433                 /* Enable NCP */
1434                 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000);
1435                 usleep_range(250, 270);
1436
1437                 /* Enable cap-less LDOs (1.5V) */
1438                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1439                                    0x1055, 0x1055);
1440                 /* Enable NV regulator (-1.2V) */
1441                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001);
1442                 usleep_range(100, 120);
1443
1444                 /* Disable AUD_ZCD */
1445                 hp_zcd_disable(priv);
1446
1447                 /* Disable handset short-circuit protection */
1448                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010);
1449
1450                 /* Enable IBIST */
1451                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1452                 /* Set HP DR bias current optimization, 010: 6uA */
1453                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900);
1454                 /* Set HP & ZCD bias current optimization */
1455                 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */
1456                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055);
1457                 /* Set HS STB enhance circuits */
1458                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090);
1459
1460                 /* Disable HP main CMFB loop */
1461                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000);
1462                 /* Select CMFB resistor bulk to AC mode */
1463                 /* Selec HS/LO cap size (6.5pF default) */
1464                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000);
1465
1466                 /* Enable HS driver bias circuits */
1467                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092);
1468                 /* Enable HS driver core circuits */
1469                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093);
1470
1471                 /* Enable AUD_CLK */
1472                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1473                                    0x1, 0x1);
1474
1475                 /* Enable Audio DAC  */
1476                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009);
1477                 /* Enable low-noise mode of DAC */
1478                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001);
1479                 /* Switch HS MUX to audio DAC */
1480                 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b);
1481                 break;
1482         case SND_SOC_DAPM_PRE_PMD:
1483                 /* HS mux to open */
1484                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1485                                    RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT,
1486                                    RCV_MUX_OPEN);
1487
1488                 /* Disable Audio DAC */
1489                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
1490                                    0x000f, 0x0000);
1491
1492                 /* Disable AUD_CLK */
1493                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1494                                    0x1, 0x0);
1495
1496                 /* decrease HS gain to minimum gain step by step */
1497                 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB);
1498
1499                 /* Disable HS driver core circuits */
1500                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1501                                    0x1, 0x0);
1502
1503                 /* Disable HS driver bias circuits */
1504                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
1505                                    0x1 << 1, 0x0000);
1506
1507                 /* Disable HP aux CMFB loop */
1508                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1509                                    0xff << 8, 0x0);
1510
1511                 /* Enable HP main CMFB Switch */
1512                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9,
1513                                    0xff << 8, 0x2 << 8);
1514
1515                 /* Disable IBIST */
1516                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12,
1517                                    0x1 << 8, 0x1 << 8);
1518
1519                 /* Disable NV regulator (-1.2V) */
1520                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15,
1521                                    0x1, 0x0);
1522                 /* Disable cap-less LDOs (1.5V) */
1523                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1524                                    0x1055, 0x0);
1525                 /* Disable NCP */
1526                 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3,
1527                                    0x1, 0x1);
1528                 break;
1529         default:
1530                 break;
1531         }
1532
1533         return 0;
1534 }
1535
1536 static int mt_aif_out_event(struct snd_soc_dapm_widget *w,
1537                             struct snd_kcontrol *kcontrol,
1538                             int event)
1539 {
1540         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1541         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1542
1543         dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n",
1544                 __func__, event, priv->ul_rate);
1545
1546         switch (event) {
1547         case SND_SOC_DAPM_PRE_PMU:
1548                 capture_gpio_set(priv);
1549                 break;
1550         case SND_SOC_DAPM_POST_PMD:
1551                 capture_gpio_reset(priv);
1552                 break;
1553         default:
1554                 break;
1555         }
1556
1557         return 0;
1558 }
1559
1560 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w,
1561                                struct snd_kcontrol *kcontrol,
1562                                int event)
1563 {
1564         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1565         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1566
1567         dev_dbg(priv->dev, "%s(), event 0x%x\n",
1568                 __func__, event);
1569
1570         switch (event) {
1571         case SND_SOC_DAPM_PRE_PMU:
1572                 /* Enable audio ADC CLKGEN  */
1573                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1574                                    0x1 << 5, 0x1 << 5);
1575                 /* ADC CLK from CLKGEN (13MHz) */
1576                 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3,
1577                              0x0000);
1578                 /* Enable  LCLDO_ENC 1P8V */
1579                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1580                                    0x2500, 0x0100);
1581                 /* LCLDO_ENC remote sense */
1582                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1583                                    0x2500, 0x2500);
1584                 break;
1585         case SND_SOC_DAPM_POST_PMD:
1586                 /* LCLDO_ENC remote sense off */
1587                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1588                                    0x2500, 0x0100);
1589                 /* disable LCLDO_ENC 1P8V */
1590                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14,
1591                                    0x2500, 0x0000);
1592
1593                 /* ADC CLK from CLKGEN (13MHz) */
1594                 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000);
1595                 /* disable audio ADC CLKGEN  */
1596                 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13,
1597                                    0x1 << 5, 0x0 << 5);
1598                 break;
1599         default:
1600                 break;
1601         }
1602
1603         return 0;
1604 }
1605
1606 static int mt6358_amic_enable(struct mt6358_priv *priv)
1607 {
1608         unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1609         unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1610         unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1611
1612         dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1613                  __func__, mic_type, mux_pga_l, mux_pga_r);
1614
1615         if (IS_DCC_BASE(mic_type)) {
1616                 /* DCC 50k CLK (from 26M) */
1617                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1618                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1619                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1620                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061);
1621                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100);
1622         }
1623
1624         /* mic bias 0 */
1625         if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 ||
1626             mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) {
1627                 switch (mic_type) {
1628                 case MIC_TYPE_MUX_DCC_ECM_DIFF:
1629                         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1630                                            0xff00, 0x7700);
1631                         break;
1632                 case MIC_TYPE_MUX_DCC_ECM_SINGLE:
1633                         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1634                                            0xff00, 0x1100);
1635                         break;
1636                 default:
1637                         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1638                                            0xff00, 0x0000);
1639                         break;
1640                 }
1641                 /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1642                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9,
1643                                    0xff, 0x21);
1644         }
1645
1646         /* mic bias 1 */
1647         if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) {
1648                 /* Enable MICBIAS1, MISBIAS1 = 2P6V */
1649                 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE)
1650                         regmap_write(priv->regmap,
1651                                      MT6358_AUDENC_ANA_CON10, 0x0161);
1652                 else
1653                         regmap_write(priv->regmap,
1654                                      MT6358_AUDENC_ANA_CON10, 0x0061);
1655         }
1656
1657         if (IS_DCC_BASE(mic_type)) {
1658                 /* Audio L/R preamplifier DCC precharge */
1659                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1660                                    0xf8ff, 0x0004);
1661                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1662                                    0xf8ff, 0x0004);
1663         } else {
1664                 /* reset reg */
1665                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1666                                    0xf8ff, 0x0000);
1667                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1668                                    0xf8ff, 0x0000);
1669         }
1670
1671         if (mux_pga_l != PGA_MUX_NONE) {
1672                 /* L preamplifier input sel */
1673                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1674                                    RG_AUDPREAMPLINPUTSEL_MASK_SFT,
1675                                    mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT);
1676
1677                 /* L preamplifier enable */
1678                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1679                                    RG_AUDPREAMPLON_MASK_SFT,
1680                                    0x1 << RG_AUDPREAMPLON_SFT);
1681
1682                 if (IS_DCC_BASE(mic_type)) {
1683                         /* L preamplifier DCCEN */
1684                         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1685                                            RG_AUDPREAMPLDCCEN_MASK_SFT,
1686                                            0x1 << RG_AUDPREAMPLDCCEN_SFT);
1687                 }
1688
1689                 /* L ADC input sel : L PGA. Enable audio L ADC */
1690                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1691                                    RG_AUDADCLINPUTSEL_MASK_SFT,
1692                                    ADC_MUX_PREAMPLIFIER <<
1693                                    RG_AUDADCLINPUTSEL_SFT);
1694                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1695                                    RG_AUDADCLPWRUP_MASK_SFT,
1696                                    0x1 << RG_AUDADCLPWRUP_SFT);
1697         }
1698
1699         if (mux_pga_r != PGA_MUX_NONE) {
1700                 /* R preamplifier input sel */
1701                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1702                                    RG_AUDPREAMPRINPUTSEL_MASK_SFT,
1703                                    mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT);
1704
1705                 /* R preamplifier enable */
1706                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1707                                    RG_AUDPREAMPRON_MASK_SFT,
1708                                    0x1 << RG_AUDPREAMPRON_SFT);
1709
1710                 if (IS_DCC_BASE(mic_type)) {
1711                         /* R preamplifier DCCEN */
1712                         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1713                                            RG_AUDPREAMPRDCCEN_MASK_SFT,
1714                                            0x1 << RG_AUDPREAMPRDCCEN_SFT);
1715                 }
1716
1717                 /* R ADC input sel : R PGA. Enable audio R ADC */
1718                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1719                                    RG_AUDADCRINPUTSEL_MASK_SFT,
1720                                    ADC_MUX_PREAMPLIFIER <<
1721                                    RG_AUDADCRINPUTSEL_SFT);
1722                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1723                                    RG_AUDADCRPWRUP_MASK_SFT,
1724                                    0x1 << RG_AUDADCRPWRUP_SFT);
1725         }
1726
1727         if (IS_DCC_BASE(mic_type)) {
1728                 usleep_range(100, 150);
1729                 /* Audio L preamplifier DCC precharge off */
1730                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1731                                    RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0);
1732                 /* Audio R preamplifier DCC precharge off */
1733                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1734                                    RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0);
1735
1736                 /* Short body to ground in PGA */
1737                 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3,
1738                                    0x1 << 12, 0x0);
1739         }
1740
1741         /* here to set digital part */
1742         mt6358_mtkaif_tx_enable(priv);
1743
1744         /* UL dmic setting off */
1745         regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000);
1746
1747         /* UL turn on */
1748         regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001);
1749
1750         return 0;
1751 }
1752
1753 static void mt6358_amic_disable(struct mt6358_priv *priv)
1754 {
1755         unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE];
1756         unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L];
1757         unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R];
1758
1759         dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n",
1760                  __func__, mic_type, mux_pga_l, mux_pga_r);
1761
1762         /* UL turn off */
1763         regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1764                            0x0001, 0x0000);
1765
1766         /* disable aud_pad TX fifos */
1767         mt6358_mtkaif_tx_disable(priv);
1768
1769         /* L ADC input sel : off, disable L ADC */
1770         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1771                            0xf000, 0x0000);
1772         /* L preamplifier DCCEN */
1773         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1774                            0x1 << 1, 0x0);
1775         /* L preamplifier input sel : off, L PGA 0 dB gain */
1776         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1777                            0xfffb, 0x0000);
1778
1779         /* disable L preamplifier DCC precharge */
1780         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1781                            0x1 << 2, 0x0);
1782
1783         /* R ADC input sel : off, disable R ADC */
1784         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1785                            0xf000, 0x0000);
1786         /* R preamplifier DCCEN */
1787         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1788                            0x1 << 1, 0x0);
1789         /* R preamplifier input sel : off, R PGA 0 dB gain */
1790         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1791                            0x0ffb, 0x0000);
1792
1793         /* disable R preamplifier DCC precharge */
1794         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1795                            0x1 << 2, 0x0);
1796
1797         /* mic bias */
1798         /* Disable MICBIAS0, MISBIAS0 = 1P7V */
1799         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1800
1801         /* Disable MICBIAS1 */
1802         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1803                            0x0001, 0x0000);
1804
1805         if (IS_DCC_BASE(mic_type)) {
1806                 /* dcclk_gen_on=1'b0 */
1807                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060);
1808                 /* dcclk_pdn=1'b1 */
1809                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1810                 /* dcclk_ref_ck_sel=2'b00 */
1811                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1812                 /* dcclk_div=11'b00100000011 */
1813                 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062);
1814         }
1815 }
1816
1817 static int mt6358_dmic_enable(struct mt6358_priv *priv)
1818 {
1819         dev_info(priv->dev, "%s()\n", __func__);
1820
1821         /* mic bias */
1822         /* Enable MICBIAS0, MISBIAS0 = 1P9V */
1823         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021);
1824
1825         /* RG_BANDGAPGEN=1'b0 */
1826         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1827                            0x1 << 12, 0x0);
1828
1829         /* DMIC enable */
1830         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005);
1831
1832         /* here to set digital part */
1833         mt6358_mtkaif_tx_enable(priv);
1834
1835         /* UL dmic setting */
1836         if (priv->dmic_one_wire_mode)
1837                 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0400);
1838         else
1839                 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080);
1840
1841         /* UL turn on */
1842         regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003);
1843
1844         /* Prevent pop noise form dmic hw */
1845         msleep(100);
1846
1847         return 0;
1848 }
1849
1850 static void mt6358_dmic_disable(struct mt6358_priv *priv)
1851 {
1852         dev_info(priv->dev, "%s()\n", __func__);
1853
1854         /* UL turn off */
1855         regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L,
1856                            0x0003, 0x0000);
1857
1858         /* disable aud_pad TX fifos */
1859         mt6358_mtkaif_tx_disable(priv);
1860
1861         /* DMIC disable */
1862         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000);
1863
1864         /* mic bias */
1865         /* MISBIAS0 = 1P7V */
1866         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001);
1867
1868         /* RG_BANDGAPGEN=1'b0 */
1869         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10,
1870                            0x1 << 12, 0x0);
1871
1872         /* MICBIA0 disable */
1873         regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000);
1874 }
1875
1876 static void mt6358_restore_pga(struct mt6358_priv *priv)
1877 {
1878         unsigned int gain_l, gain_r;
1879
1880         gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
1881         gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
1882
1883         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0,
1884                            RG_AUDPREAMPLGAIN_MASK_SFT,
1885                            gain_l << RG_AUDPREAMPLGAIN_SFT);
1886         regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1,
1887                            RG_AUDPREAMPRGAIN_MASK_SFT,
1888                            gain_r << RG_AUDPREAMPRGAIN_SFT);
1889 }
1890
1891 static int mt_mic_type_event(struct snd_soc_dapm_widget *w,
1892                              struct snd_kcontrol *kcontrol,
1893                              int event)
1894 {
1895         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1896         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1897         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1898
1899         dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1900                 __func__, event, mux);
1901
1902         switch (event) {
1903         case SND_SOC_DAPM_WILL_PMU:
1904                 priv->mux_select[MUX_MIC_TYPE] = mux;
1905                 break;
1906         case SND_SOC_DAPM_PRE_PMU:
1907                 switch (mux) {
1908                 case MIC_TYPE_MUX_DMIC:
1909                         mt6358_dmic_enable(priv);
1910                         break;
1911                 default:
1912                         mt6358_amic_enable(priv);
1913                         break;
1914                 }
1915                 mt6358_restore_pga(priv);
1916
1917                 break;
1918         case SND_SOC_DAPM_POST_PMD:
1919                 switch (priv->mux_select[MUX_MIC_TYPE]) {
1920                 case MIC_TYPE_MUX_DMIC:
1921                         mt6358_dmic_disable(priv);
1922                         break;
1923                 default:
1924                         mt6358_amic_disable(priv);
1925                         break;
1926                 }
1927
1928                 priv->mux_select[MUX_MIC_TYPE] = mux;
1929                 break;
1930         default:
1931                 break;
1932         }
1933
1934         return 0;
1935 }
1936
1937 static int mt_adc_l_event(struct snd_soc_dapm_widget *w,
1938                           struct snd_kcontrol *kcontrol,
1939                           int event)
1940 {
1941         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1942         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1943         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1944
1945         dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1946                 __func__, event, mux);
1947
1948         priv->mux_select[MUX_ADC_L] = mux;
1949
1950         return 0;
1951 }
1952
1953 static int mt_adc_r_event(struct snd_soc_dapm_widget *w,
1954                           struct snd_kcontrol *kcontrol,
1955                           int event)
1956 {
1957         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1958         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1959         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1960
1961         dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1962                 __func__, event, mux);
1963
1964         priv->mux_select[MUX_ADC_R] = mux;
1965
1966         return 0;
1967 }
1968
1969 static int mt_pga_left_event(struct snd_soc_dapm_widget *w,
1970                              struct snd_kcontrol *kcontrol,
1971                              int event)
1972 {
1973         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1974         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1975         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1976
1977         dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1978                 __func__, event, mux);
1979
1980         priv->mux_select[MUX_PGA_L] = mux;
1981
1982         return 0;
1983 }
1984
1985 static int mt_pga_right_event(struct snd_soc_dapm_widget *w,
1986                               struct snd_kcontrol *kcontrol,
1987                               int event)
1988 {
1989         struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1990         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
1991         unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1992
1993         dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n",
1994                 __func__, event, mux);
1995
1996         priv->mux_select[MUX_PGA_R] = mux;
1997
1998         return 0;
1999 }
2000
2001 static int mt_delay_250_event(struct snd_soc_dapm_widget *w,
2002                               struct snd_kcontrol *kcontrol,
2003                               int event)
2004 {
2005         switch (event) {
2006         case SND_SOC_DAPM_POST_PMU:
2007                 usleep_range(250, 270);
2008                 break;
2009         case SND_SOC_DAPM_PRE_PMD:
2010                 usleep_range(250, 270);
2011                 break;
2012         default:
2013                 break;
2014         }
2015
2016         return 0;
2017 }
2018
2019 /* DAPM Widgets */
2020 static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = {
2021         /* Global Supply*/
2022         SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF,
2023                               MT6358_DCXO_CW14,
2024                               RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0),
2025         SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB,
2026                               MT6358_AUDDEC_ANA_CON13,
2027                               RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0),
2028         SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ,
2029                               MT6358_AUDENC_ANA_CON6,
2030                               RG_CLKSQ_EN_SFT, 0,
2031                               mt_clksq_event,
2032                               SND_SOC_DAPM_PRE_PMU),
2033         SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK,
2034                               MT6358_AUD_TOP_CKPDN_CON0,
2035                               RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0),
2036         SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK,
2037                               MT6358_AUD_TOP_CKPDN_CON0,
2038                               RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0),
2039         SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST,
2040                               MT6358_AUD_TOP_CKPDN_CON0,
2041                               RG_AUD_CK_PDN_SFT, 1,
2042                               mt_delay_250_event,
2043                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2044         SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK,
2045                               MT6358_AUD_TOP_CKPDN_CON0,
2046                               RG_AUDIF_CK_PDN_SFT, 1, NULL, 0),
2047
2048         /* Digital Clock */
2049         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST,
2050                               MT6358_AUDIO_TOP_CON0,
2051                               PDN_AFE_CTL_SFT, 1,
2052                               mt_delay_250_event,
2053                               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2054         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP,
2055                               MT6358_AUDIO_TOP_CON0,
2056                               PDN_DAC_CTL_SFT, 1, NULL, 0),
2057         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP,
2058                               MT6358_AUDIO_TOP_CON0,
2059                               PDN_ADC_CTL_SFT, 1, NULL, 0),
2060         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP,
2061                               MT6358_AUDIO_TOP_CON0,
2062                               PDN_I2S_DL_CTL_SFT, 1, NULL, 0),
2063         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP,
2064                               MT6358_AUDIO_TOP_CON0,
2065                               PWR_CLK_DIS_CTL_SFT, 1, NULL, 0),
2066         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP,
2067                               MT6358_AUDIO_TOP_CON0,
2068                               PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0),
2069         SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP,
2070                               MT6358_AUDIO_TOP_CON0,
2071                               PDN_RESERVED_SFT, 1, NULL, 0),
2072
2073         SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM,
2074                             0, 0, NULL, 0),
2075
2076         /* AFE ON */
2077         SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE,
2078                               MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0,
2079                               NULL, 0),
2080
2081         /* AIF Rx*/
2082         SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0,
2083                               MT6358_AFE_DL_SRC2_CON0_L,
2084                               DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
2085                               mt_aif_in_event,
2086                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2087
2088         /* DL Supply */
2089         SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM,
2090                             0, 0, NULL, 0),
2091
2092         /* DAC */
2093         SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control),
2094
2095         SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0),
2096
2097         SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0),
2098
2099         /* LOL */
2100         SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control),
2101
2102         SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7,
2103                             RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0),
2104
2105         SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7,
2106                              RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0),
2107
2108         /* Headphone */
2109         SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0,
2110                            &hpl_in_mux_control,
2111                            mt_hp_event,
2112                            SND_SOC_DAPM_PRE_PMU |
2113                            SND_SOC_DAPM_PRE_PMD),
2114
2115         SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0,
2116                            &hpr_in_mux_control,
2117                            mt_hp_event,
2118                            SND_SOC_DAPM_PRE_PMU |
2119                            SND_SOC_DAPM_PRE_PMD),
2120
2121         /* Receiver */
2122         SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0,
2123                            &rcv_in_mux_control,
2124                            mt_rcv_event,
2125                            SND_SOC_DAPM_PRE_PMU |
2126                            SND_SOC_DAPM_PRE_PMD),
2127
2128         /* Outputs */
2129         SND_SOC_DAPM_OUTPUT("Receiver"),
2130         SND_SOC_DAPM_OUTPUT("Headphone L"),
2131         SND_SOC_DAPM_OUTPUT("Headphone R"),
2132         SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"),
2133         SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"),
2134         SND_SOC_DAPM_OUTPUT("LINEOUT L"),
2135         SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"),
2136
2137         /* SGEN */
2138         SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0,
2139                             SGEN_DAC_EN_CTL_SFT, 0, NULL, 0),
2140         SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0,
2141                             SGEN_MUTE_SW_CTL_SFT, 1,
2142                             mt_sgen_event,
2143                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2144         SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L,
2145                             DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0),
2146
2147         SND_SOC_DAPM_INPUT("SGEN DL"),
2148
2149         /* Uplinks */
2150         SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0,
2151                                SND_SOC_NOPM, 0, 0,
2152                                mt_aif_out_event,
2153                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2154
2155         SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY,
2156                               SND_SOC_NOPM, 0, 0,
2157                               mt_adc_supply_event,
2158                               SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2159
2160         /* Uplinks MUX */
2161         SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0,
2162                          &aif_out_mux_control),
2163
2164         SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0,
2165                            &mic_type_mux_control,
2166                            mt_mic_type_event,
2167                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD |
2168                            SND_SOC_DAPM_WILL_PMU),
2169
2170         SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0,
2171                            &adc_left_mux_control,
2172                            mt_adc_l_event,
2173                            SND_SOC_DAPM_WILL_PMU),
2174         SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0,
2175                            &adc_right_mux_control,
2176                            mt_adc_r_event,
2177                            SND_SOC_DAPM_WILL_PMU),
2178
2179         SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2180         SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2181
2182         SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0,
2183                            &pga_left_mux_control,
2184                            mt_pga_left_event,
2185                            SND_SOC_DAPM_WILL_PMU),
2186         SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0,
2187                            &pga_right_mux_control,
2188                            mt_pga_right_event,
2189                            SND_SOC_DAPM_WILL_PMU),
2190
2191         SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0),
2192         SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0),
2193
2194         /* UL input */
2195         SND_SOC_DAPM_INPUT("AIN0"),
2196         SND_SOC_DAPM_INPUT("AIN1"),
2197         SND_SOC_DAPM_INPUT("AIN2"),
2198 };
2199
2200 static const struct snd_soc_dapm_route mt6358_dapm_routes[] = {
2201         /* Capture */
2202         {"AIF1TX", NULL, "AIF Out Mux"},
2203         {"AIF1TX", NULL, "CLK_BUF"},
2204         {"AIF1TX", NULL, "AUDGLB"},
2205         {"AIF1TX", NULL, "CLKSQ Audio"},
2206
2207         {"AIF1TX", NULL, "AUD_CK"},
2208         {"AIF1TX", NULL, "AUDIF_CK"},
2209
2210         {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"},
2211         {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"},
2212         {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"},
2213         {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"},
2214         {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"},
2215
2216         {"AIF1TX", NULL, "AFE_ON"},
2217
2218         {"AIF Out Mux", NULL, "Mic Type Mux"},
2219
2220         {"Mic Type Mux", "ACC", "ADC L"},
2221         {"Mic Type Mux", "ACC", "ADC R"},
2222         {"Mic Type Mux", "DCC", "ADC L"},
2223         {"Mic Type Mux", "DCC", "ADC R"},
2224         {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"},
2225         {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"},
2226         {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"},
2227         {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"},
2228         {"Mic Type Mux", "DMIC", "AIN0"},
2229         {"Mic Type Mux", "DMIC", "AIN2"},
2230
2231         {"ADC L", NULL, "ADC L Mux"},
2232         {"ADC L", NULL, "ADC Supply"},
2233         {"ADC R", NULL, "ADC R Mux"},
2234         {"ADC R", NULL, "ADC Supply"},
2235
2236         {"ADC L Mux", "Left Preamplifier", "PGA L"},
2237
2238         {"ADC R Mux", "Right Preamplifier", "PGA R"},
2239
2240         {"PGA L", NULL, "PGA L Mux"},
2241         {"PGA R", NULL, "PGA R Mux"},
2242
2243         {"PGA L Mux", "AIN0", "AIN0"},
2244         {"PGA L Mux", "AIN1", "AIN1"},
2245         {"PGA L Mux", "AIN2", "AIN2"},
2246
2247         {"PGA R Mux", "AIN0", "AIN0"},
2248         {"PGA R Mux", "AIN1", "AIN1"},
2249         {"PGA R Mux", "AIN2", "AIN2"},
2250
2251         /* DL Supply */
2252         {"DL Power Supply", NULL, "CLK_BUF"},
2253         {"DL Power Supply", NULL, "AUDGLB"},
2254         {"DL Power Supply", NULL, "CLKSQ Audio"},
2255
2256         {"DL Power Supply", NULL, "AUDNCP_CK"},
2257         {"DL Power Supply", NULL, "ZCD13M_CK"},
2258         {"DL Power Supply", NULL, "AUD_CK"},
2259         {"DL Power Supply", NULL, "AUDIF_CK"},
2260
2261         /* DL Digital Supply */
2262         {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"},
2263         {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"},
2264         {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"},
2265
2266         {"DL Digital Clock", NULL, "AFE_ON"},
2267
2268         {"AIF_RX", NULL, "DL Digital Clock"},
2269
2270         /* DL Path */
2271         {"DAC In Mux", "Normal Path", "AIF_RX"},
2272
2273         {"DAC In Mux", "Sgen", "SGEN DL"},
2274         {"SGEN DL", NULL, "SGEN DL SRC"},
2275         {"SGEN DL", NULL, "SGEN MUTE"},
2276         {"SGEN DL", NULL, "SGEN DL Enable"},
2277         {"SGEN DL", NULL, "DL Digital Clock"},
2278         {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"},
2279
2280         {"DACL", NULL, "DAC In Mux"},
2281         {"DACL", NULL, "DL Power Supply"},
2282
2283         {"DACR", NULL, "DAC In Mux"},
2284         {"DACR", NULL, "DL Power Supply"},
2285
2286         /* Lineout Path */
2287         {"LOL Mux", "Playback", "DACL"},
2288
2289         {"LOL Buffer", NULL, "LOL Mux"},
2290         {"LOL Buffer", NULL, "LO Stability Enh"},
2291
2292         {"LINEOUT L", NULL, "LOL Buffer"},
2293
2294         /* Headphone Path */
2295         {"HPL Mux", "Audio Playback", "DACL"},
2296         {"HPR Mux", "Audio Playback", "DACR"},
2297         {"HPL Mux", "HP Impedance", "DACL"},
2298         {"HPR Mux", "HP Impedance", "DACR"},
2299         {"HPL Mux", "LoudSPK Playback", "DACL"},
2300         {"HPR Mux", "LoudSPK Playback", "DACR"},
2301
2302         {"Headphone L", NULL, "HPL Mux"},
2303         {"Headphone R", NULL, "HPR Mux"},
2304         {"Headphone L Ext Spk Amp", NULL, "HPL Mux"},
2305         {"Headphone R Ext Spk Amp", NULL, "HPR Mux"},
2306         {"LINEOUT L HSSPK", NULL, "HPL Mux"},
2307
2308         /* Receiver Path */
2309         {"RCV Mux", "Voice Playback", "DACL"},
2310         {"Receiver", NULL, "RCV Mux"},
2311 };
2312
2313 static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream,
2314                                       struct snd_pcm_hw_params *params,
2315                                       struct snd_soc_dai *dai)
2316 {
2317         struct snd_soc_component *cmpnt = dai->component;
2318         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2319         unsigned int rate = params_rate(params);
2320
2321         dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n",
2322                  __func__,
2323                  substream->stream,
2324                  rate,
2325                  substream->number);
2326
2327         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2328                 priv->dl_rate = rate;
2329         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2330                 priv->ul_rate = rate;
2331
2332         return 0;
2333 }
2334
2335 static const struct snd_soc_dai_ops mt6358_codec_dai_ops = {
2336         .hw_params = mt6358_codec_dai_hw_params,
2337 };
2338
2339 #define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\
2340                         SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\
2341                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\
2342                         SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\
2343                         SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\
2344                         SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE)
2345
2346 static struct snd_soc_dai_driver mt6358_dai_driver[] = {
2347         {
2348                 .name = "mt6358-snd-codec-aif1",
2349                 .playback = {
2350                         .stream_name = "AIF1 Playback",
2351                         .channels_min = 1,
2352                         .channels_max = 2,
2353                         .rates = SNDRV_PCM_RATE_8000_48000 |
2354                                  SNDRV_PCM_RATE_96000 |
2355                                  SNDRV_PCM_RATE_192000,
2356                         .formats = MT6358_FORMATS,
2357                 },
2358                 .capture = {
2359                         .stream_name = "AIF1 Capture",
2360                         .channels_min = 1,
2361                         .channels_max = 2,
2362                         .rates = SNDRV_PCM_RATE_8000 |
2363                                  SNDRV_PCM_RATE_16000 |
2364                                  SNDRV_PCM_RATE_32000 |
2365                                  SNDRV_PCM_RATE_48000,
2366                         .formats = MT6358_FORMATS,
2367                 },
2368                 .ops = &mt6358_codec_dai_ops,
2369         },
2370 };
2371
2372 static void mt6358_codec_init_reg(struct mt6358_priv *priv)
2373 {
2374         /* Disable HeadphoneL/HeadphoneR short circuit protection */
2375         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2376                            RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT,
2377                            0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT);
2378         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0,
2379                            RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT,
2380                            0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT);
2381         /* Disable voice short circuit protection */
2382         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6,
2383                            RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT,
2384                            0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT);
2385         /* disable LO buffer left short circuit protection */
2386         regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7,
2387                            RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT,
2388                            0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT);
2389
2390         /* accdet s/w enable */
2391         regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13,
2392                            0xFFFF, 0x700E);
2393
2394         /* gpio miso driving set to 4mA */
2395         regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888);
2396
2397         /* set gpio */
2398         playback_gpio_reset(priv);
2399         capture_gpio_reset(priv);
2400 }
2401
2402 static int mt6358_codec_probe(struct snd_soc_component *cmpnt)
2403 {
2404         struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt);
2405         int ret;
2406
2407         snd_soc_component_init_regmap(cmpnt, priv->regmap);
2408
2409         mt6358_codec_init_reg(priv);
2410
2411         priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd");
2412         if (IS_ERR(priv->avdd_reg)) {
2413                 dev_err(priv->dev, "%s() have no Avdd supply", __func__);
2414                 return PTR_ERR(priv->avdd_reg);
2415         }
2416
2417         ret = regulator_enable(priv->avdd_reg);
2418         if (ret)
2419                 return  ret;
2420
2421         return 0;
2422 }
2423
2424 static const struct snd_soc_component_driver mt6358_soc_component_driver = {
2425         .probe = mt6358_codec_probe,
2426         .controls = mt6358_snd_controls,
2427         .num_controls = ARRAY_SIZE(mt6358_snd_controls),
2428         .dapm_widgets = mt6358_dapm_widgets,
2429         .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets),
2430         .dapm_routes = mt6358_dapm_routes,
2431         .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes),
2432 };
2433
2434 static void mt6358_parse_dt(struct mt6358_priv *priv)
2435 {
2436         int ret;
2437         struct device *dev = priv->dev;
2438
2439         ret = of_property_read_u32(dev->of_node, "mediatek,dmic-mode",
2440                                    &priv->dmic_one_wire_mode);
2441         if (ret) {
2442                 dev_warn(priv->dev, "%s() failed to read dmic-mode\n",
2443                          __func__);
2444                 priv->dmic_one_wire_mode = 0;
2445         }
2446 }
2447
2448 static int mt6358_platform_driver_probe(struct platform_device *pdev)
2449 {
2450         struct mt6358_priv *priv;
2451         struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
2452
2453         priv = devm_kzalloc(&pdev->dev,
2454                             sizeof(struct mt6358_priv),
2455                             GFP_KERNEL);
2456         if (!priv)
2457                 return -ENOMEM;
2458
2459         dev_set_drvdata(&pdev->dev, priv);
2460
2461         priv->dev = &pdev->dev;
2462
2463         priv->regmap = mt6397->regmap;
2464         if (IS_ERR(priv->regmap))
2465                 return PTR_ERR(priv->regmap);
2466
2467         mt6358_parse_dt(priv);
2468
2469         dev_info(priv->dev, "%s(), dev name %s\n",
2470                  __func__, dev_name(&pdev->dev));
2471
2472         return devm_snd_soc_register_component(&pdev->dev,
2473                                       &mt6358_soc_component_driver,
2474                                       mt6358_dai_driver,
2475                                       ARRAY_SIZE(mt6358_dai_driver));
2476 }
2477
2478 static const struct of_device_id mt6358_of_match[] = {
2479         {.compatible = "mediatek,mt6358-sound",},
2480         {}
2481 };
2482 MODULE_DEVICE_TABLE(of, mt6358_of_match);
2483
2484 static struct platform_driver mt6358_platform_driver = {
2485         .driver = {
2486                 .name = "mt6358-sound",
2487                 .of_match_table = mt6358_of_match,
2488         },
2489         .probe = mt6358_platform_driver_probe,
2490 };
2491
2492 module_platform_driver(mt6358_platform_driver)
2493
2494 /* Module information */
2495 MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver");
2496 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
2497 MODULE_LICENSE("GPL v2");