1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2016, The Linux Foundation. All rights reserved.
4 #include <linux/module.h>
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/types.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <linux/mfd/syscon.h>
14 #include <sound/soc.h>
15 #include <sound/pcm.h>
16 #include <sound/pcm_params.h>
17 #include <sound/tlv.h>
19 #define LPASS_CDC_CLK_RX_RESET_CTL (0x000)
20 #define LPASS_CDC_CLK_TX_RESET_B1_CTL (0x004)
21 #define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK BIT(0)
22 #define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK BIT(1)
23 #define LPASS_CDC_CLK_DMIC_B1_CTL (0x008)
24 #define DMIC_B1_CTL_DMIC0_CLK_SEL_MASK GENMASK(3, 1)
25 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV2 (0x0 << 1)
26 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3 (0x1 << 1)
27 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV4 (0x2 << 1)
28 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV6 (0x3 << 1)
29 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV16 (0x4 << 1)
30 #define DMIC_B1_CTL_DMIC0_CLK_EN_MASK BIT(0)
31 #define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE BIT(0)
33 #define LPASS_CDC_CLK_RX_I2S_CTL (0x00C)
34 #define RX_I2S_CTL_RX_I2S_MODE_MASK BIT(5)
35 #define RX_I2S_CTL_RX_I2S_MODE_16 BIT(5)
36 #define RX_I2S_CTL_RX_I2S_MODE_32 0
37 #define RX_I2S_CTL_RX_I2S_FS_RATE_MASK GENMASK(2, 0)
38 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ 0x0
39 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ 0x1
40 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ 0x2
41 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ 0x3
42 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_96_KHZ 0x4
43 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_192_KHZ 0x5
44 #define LPASS_CDC_CLK_TX_I2S_CTL (0x010)
45 #define TX_I2S_CTL_TX_I2S_MODE_MASK BIT(5)
46 #define TX_I2S_CTL_TX_I2S_MODE_16 BIT(5)
47 #define TX_I2S_CTL_TX_I2S_MODE_32 0
48 #define TX_I2S_CTL_TX_I2S_FS_RATE_MASK GENMASK(2, 0)
49 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ 0x0
50 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ 0x1
51 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ 0x2
52 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ 0x3
53 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_96_KHZ 0x4
54 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_192_KHZ 0x5
56 #define LPASS_CDC_CLK_OTHR_RESET_B1_CTL (0x014)
57 #define LPASS_CDC_CLK_TX_CLK_EN_B1_CTL (0x018)
58 #define LPASS_CDC_CLK_OTHR_CTL (0x01C)
59 #define LPASS_CDC_CLK_RX_B1_CTL (0x020)
60 #define LPASS_CDC_CLK_MCLK_CTL (0x024)
61 #define MCLK_CTL_MCLK_EN_MASK BIT(0)
62 #define MCLK_CTL_MCLK_EN_ENABLE BIT(0)
63 #define MCLK_CTL_MCLK_EN_DISABLE 0
64 #define LPASS_CDC_CLK_PDM_CTL (0x028)
65 #define LPASS_CDC_CLK_PDM_CTL_PDM_EN_MASK BIT(0)
66 #define LPASS_CDC_CLK_PDM_CTL_PDM_EN BIT(0)
67 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK BIT(1)
68 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB BIT(1)
69 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_PDM_CLK 0
71 #define LPASS_CDC_CLK_SD_CTL (0x02C)
72 #define LPASS_CDC_RX1_B1_CTL (0x040)
73 #define LPASS_CDC_RX2_B1_CTL (0x060)
74 #define LPASS_CDC_RX3_B1_CTL (0x080)
75 #define LPASS_CDC_RX1_B2_CTL (0x044)
76 #define LPASS_CDC_RX2_B2_CTL (0x064)
77 #define LPASS_CDC_RX3_B2_CTL (0x084)
78 #define LPASS_CDC_RX1_B3_CTL (0x048)
79 #define LPASS_CDC_RX2_B3_CTL (0x068)
80 #define LPASS_CDC_RX3_B3_CTL (0x088)
81 #define LPASS_CDC_RX1_B4_CTL (0x04C)
82 #define LPASS_CDC_RX2_B4_CTL (0x06C)
83 #define LPASS_CDC_RX3_B4_CTL (0x08C)
84 #define LPASS_CDC_RX1_B5_CTL (0x050)
85 #define LPASS_CDC_RX2_B5_CTL (0x070)
86 #define LPASS_CDC_RX3_B5_CTL (0x090)
87 #define LPASS_CDC_RX1_B6_CTL (0x054)
88 #define RXn_B6_CTL_MUTE_MASK BIT(0)
89 #define RXn_B6_CTL_MUTE_ENABLE BIT(0)
90 #define RXn_B6_CTL_MUTE_DISABLE 0
91 #define LPASS_CDC_RX2_B6_CTL (0x074)
92 #define LPASS_CDC_RX3_B6_CTL (0x094)
93 #define LPASS_CDC_RX1_VOL_CTL_B1_CTL (0x058)
94 #define LPASS_CDC_RX2_VOL_CTL_B1_CTL (0x078)
95 #define LPASS_CDC_RX3_VOL_CTL_B1_CTL (0x098)
96 #define LPASS_CDC_RX1_VOL_CTL_B2_CTL (0x05C)
97 #define LPASS_CDC_RX2_VOL_CTL_B2_CTL (0x07C)
98 #define LPASS_CDC_RX3_VOL_CTL_B2_CTL (0x09C)
99 #define LPASS_CDC_TOP_GAIN_UPDATE (0x0A0)
100 #define LPASS_CDC_TOP_CTL (0x0A4)
101 #define TOP_CTL_DIG_MCLK_FREQ_MASK BIT(0)
102 #define TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ 0
103 #define TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ BIT(0)
105 #define LPASS_CDC_DEBUG_DESER1_CTL (0x0E0)
106 #define LPASS_CDC_DEBUG_DESER2_CTL (0x0E4)
107 #define LPASS_CDC_DEBUG_B1_CTL_CFG (0x0E8)
108 #define LPASS_CDC_DEBUG_B2_CTL_CFG (0x0EC)
109 #define LPASS_CDC_DEBUG_B3_CTL_CFG (0x0F0)
110 #define LPASS_CDC_IIR1_GAIN_B1_CTL (0x100)
111 #define LPASS_CDC_IIR2_GAIN_B1_CTL (0x140)
112 #define LPASS_CDC_IIR1_GAIN_B2_CTL (0x104)
113 #define LPASS_CDC_IIR2_GAIN_B2_CTL (0x144)
114 #define LPASS_CDC_IIR1_GAIN_B3_CTL (0x108)
115 #define LPASS_CDC_IIR2_GAIN_B3_CTL (0x148)
116 #define LPASS_CDC_IIR1_GAIN_B4_CTL (0x10C)
117 #define LPASS_CDC_IIR2_GAIN_B4_CTL (0x14C)
118 #define LPASS_CDC_IIR1_GAIN_B5_CTL (0x110)
119 #define LPASS_CDC_IIR2_GAIN_B5_CTL (0x150)
120 #define LPASS_CDC_IIR1_GAIN_B6_CTL (0x114)
121 #define LPASS_CDC_IIR2_GAIN_B6_CTL (0x154)
122 #define LPASS_CDC_IIR1_GAIN_B7_CTL (0x118)
123 #define LPASS_CDC_IIR2_GAIN_B7_CTL (0x158)
124 #define LPASS_CDC_IIR1_GAIN_B8_CTL (0x11C)
125 #define LPASS_CDC_IIR2_GAIN_B8_CTL (0x15C)
126 #define LPASS_CDC_IIR1_CTL (0x120)
127 #define LPASS_CDC_IIR2_CTL (0x160)
128 #define LPASS_CDC_IIR1_GAIN_TIMER_CTL (0x124)
129 #define LPASS_CDC_IIR2_GAIN_TIMER_CTL (0x164)
130 #define LPASS_CDC_IIR1_COEF_B1_CTL (0x128)
131 #define LPASS_CDC_IIR2_COEF_B1_CTL (0x168)
132 #define LPASS_CDC_IIR1_COEF_B2_CTL (0x12C)
133 #define LPASS_CDC_IIR2_COEF_B2_CTL (0x16C)
134 #define LPASS_CDC_CONN_RX1_B1_CTL (0x180)
135 #define LPASS_CDC_CONN_RX1_B2_CTL (0x184)
136 #define LPASS_CDC_CONN_RX1_B3_CTL (0x188)
137 #define LPASS_CDC_CONN_RX2_B1_CTL (0x18C)
138 #define LPASS_CDC_CONN_RX2_B2_CTL (0x190)
139 #define LPASS_CDC_CONN_RX2_B3_CTL (0x194)
140 #define LPASS_CDC_CONN_RX3_B1_CTL (0x198)
141 #define LPASS_CDC_CONN_RX3_B2_CTL (0x19C)
142 #define LPASS_CDC_CONN_TX_B1_CTL (0x1A0)
143 #define LPASS_CDC_CONN_EQ1_B1_CTL (0x1A8)
144 #define LPASS_CDC_CONN_EQ1_B2_CTL (0x1AC)
145 #define LPASS_CDC_CONN_EQ1_B3_CTL (0x1B0)
146 #define LPASS_CDC_CONN_EQ1_B4_CTL (0x1B4)
147 #define LPASS_CDC_CONN_EQ2_B1_CTL (0x1B8)
148 #define LPASS_CDC_CONN_EQ2_B2_CTL (0x1BC)
149 #define LPASS_CDC_CONN_EQ2_B3_CTL (0x1C0)
150 #define LPASS_CDC_CONN_EQ2_B4_CTL (0x1C4)
151 #define LPASS_CDC_CONN_TX_I2S_SD1_CTL (0x1C8)
152 #define LPASS_CDC_TX1_VOL_CTL_TIMER (0x280)
153 #define LPASS_CDC_TX2_VOL_CTL_TIMER (0x2A0)
154 #define LPASS_CDC_TX1_VOL_CTL_GAIN (0x284)
155 #define LPASS_CDC_TX2_VOL_CTL_GAIN (0x2A4)
156 #define LPASS_CDC_TX1_VOL_CTL_CFG (0x288)
157 #define TX_VOL_CTL_CFG_MUTE_EN_MASK BIT(0)
158 #define TX_VOL_CTL_CFG_MUTE_EN_ENABLE BIT(0)
160 #define LPASS_CDC_TX2_VOL_CTL_CFG (0x2A8)
161 #define LPASS_CDC_TX1_MUX_CTL (0x28C)
162 #define TX_MUX_CTL_CUT_OFF_FREQ_MASK GENMASK(5, 4)
163 #define TX_MUX_CTL_CUT_OFF_FREQ_SHIFT 4
164 #define TX_MUX_CTL_CF_NEG_3DB_4HZ (0x0 << 4)
165 #define TX_MUX_CTL_CF_NEG_3DB_75HZ (0x1 << 4)
166 #define TX_MUX_CTL_CF_NEG_3DB_150HZ (0x2 << 4)
167 #define TX_MUX_CTL_HPF_BP_SEL_MASK BIT(3)
168 #define TX_MUX_CTL_HPF_BP_SEL_BYPASS BIT(3)
169 #define TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS 0
171 #define LPASS_CDC_TX2_MUX_CTL (0x2AC)
172 #define LPASS_CDC_TX1_CLK_FS_CTL (0x290)
173 #define LPASS_CDC_TX2_CLK_FS_CTL (0x2B0)
174 #define LPASS_CDC_TX1_DMIC_CTL (0x294)
175 #define LPASS_CDC_TX2_DMIC_CTL (0x2B4)
176 #define TXN_DMIC_CTL_CLK_SEL_MASK GENMASK(2, 0)
177 #define TXN_DMIC_CTL_CLK_SEL_DIV2 0x0
178 #define TXN_DMIC_CTL_CLK_SEL_DIV3 0x1
179 #define TXN_DMIC_CTL_CLK_SEL_DIV4 0x2
180 #define TXN_DMIC_CTL_CLK_SEL_DIV6 0x3
181 #define TXN_DMIC_CTL_CLK_SEL_DIV16 0x4
183 #define MSM8916_WCD_DIGITAL_RATES (SNDRV_PCM_RATE_8000 | \
184 SNDRV_PCM_RATE_16000 | \
185 SNDRV_PCM_RATE_32000 | \
186 SNDRV_PCM_RATE_48000)
187 #define MSM8916_WCD_DIGITAL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
188 SNDRV_PCM_FMTBIT_S32_LE)
190 /* Codec supports 2 IIR filters */
197 /* Codec supports 5 bands */
207 #define WCD_IIR_FILTER_SIZE (sizeof(u32)*BAND_MAX)
209 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
210 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
211 .info = wcd_iir_filter_info, \
212 .get = msm8x16_wcd_get_iir_band_audio_mixer, \
213 .put = msm8x16_wcd_put_iir_band_audio_mixer, \
214 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
217 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
221 struct wcd_iir_filter_ctl {
222 unsigned int iir_idx;
223 unsigned int band_idx;
224 struct soc_bytes_ext bytes_ext;
227 struct msm8916_wcd_digital_priv {
228 struct clk *ahbclk, *mclk;
231 static const unsigned long rx_gain_reg[] = {
232 LPASS_CDC_RX1_VOL_CTL_B2_CTL,
233 LPASS_CDC_RX2_VOL_CTL_B2_CTL,
234 LPASS_CDC_RX3_VOL_CTL_B2_CTL,
237 static const unsigned long tx_gain_reg[] = {
238 LPASS_CDC_TX1_VOL_CTL_GAIN,
239 LPASS_CDC_TX2_VOL_CTL_GAIN,
242 static const char *const rx_mix1_text[] = {
243 "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
246 static const char *const dec_mux_text[] = {
247 "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2"
250 static const char *const cic_mux_text[] = { "AMIC", "DMIC" };
253 static const struct soc_enum rx_mix1_inp_enum[] = {
254 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 0, 6, rx_mix1_text),
255 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 3, 6, rx_mix1_text),
256 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B2_CTL, 0, 6, rx_mix1_text),
260 static const struct soc_enum rx2_mix1_inp_enum[] = {
261 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text),
262 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 3, 6, rx_mix1_text),
263 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B2_CTL, 0, 6, rx_mix1_text),
267 static const struct soc_enum rx3_mix1_inp_enum[] = {
268 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text),
269 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 3, 6, rx_mix1_text),
270 SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B2_CTL, 0, 6, rx_mix1_text),
274 static const struct soc_enum dec1_mux_enum = SOC_ENUM_SINGLE(
275 LPASS_CDC_CONN_TX_B1_CTL, 0, 6, dec_mux_text);
276 static const struct soc_enum dec2_mux_enum = SOC_ENUM_SINGLE(
277 LPASS_CDC_CONN_TX_B1_CTL, 3, 6, dec_mux_text);
280 static const struct soc_enum cic1_mux_enum = SOC_ENUM_SINGLE(
281 LPASS_CDC_TX1_MUX_CTL, 0, 2, cic_mux_text);
282 static const struct soc_enum cic2_mux_enum = SOC_ENUM_SINGLE(
283 LPASS_CDC_TX2_MUX_CTL, 0, 2, cic_mux_text);
286 static const struct snd_kcontrol_new dec1_mux = SOC_DAPM_ENUM(
287 "DEC1 MUX Mux", dec1_mux_enum);
288 static const struct snd_kcontrol_new dec2_mux = SOC_DAPM_ENUM(
289 "DEC2 MUX Mux", dec2_mux_enum);
290 static const struct snd_kcontrol_new cic1_mux = SOC_DAPM_ENUM(
291 "CIC1 MUX Mux", cic1_mux_enum);
292 static const struct snd_kcontrol_new cic2_mux = SOC_DAPM_ENUM(
293 "CIC2 MUX Mux", cic2_mux_enum);
294 static const struct snd_kcontrol_new rx_mix1_inp1_mux = SOC_DAPM_ENUM(
295 "RX1 MIX1 INP1 Mux", rx_mix1_inp_enum[0]);
296 static const struct snd_kcontrol_new rx_mix1_inp2_mux = SOC_DAPM_ENUM(
297 "RX1 MIX1 INP2 Mux", rx_mix1_inp_enum[1]);
298 static const struct snd_kcontrol_new rx_mix1_inp3_mux = SOC_DAPM_ENUM(
299 "RX1 MIX1 INP3 Mux", rx_mix1_inp_enum[2]);
300 static const struct snd_kcontrol_new rx2_mix1_inp1_mux = SOC_DAPM_ENUM(
301 "RX2 MIX1 INP1 Mux", rx2_mix1_inp_enum[0]);
302 static const struct snd_kcontrol_new rx2_mix1_inp2_mux = SOC_DAPM_ENUM(
303 "RX2 MIX1 INP2 Mux", rx2_mix1_inp_enum[1]);
304 static const struct snd_kcontrol_new rx2_mix1_inp3_mux = SOC_DAPM_ENUM(
305 "RX2 MIX1 INP3 Mux", rx2_mix1_inp_enum[2]);
306 static const struct snd_kcontrol_new rx3_mix1_inp1_mux = SOC_DAPM_ENUM(
307 "RX3 MIX1 INP1 Mux", rx3_mix1_inp_enum[0]);
308 static const struct snd_kcontrol_new rx3_mix1_inp2_mux = SOC_DAPM_ENUM(
309 "RX3 MIX1 INP2 Mux", rx3_mix1_inp_enum[1]);
310 static const struct snd_kcontrol_new rx3_mix1_inp3_mux = SOC_DAPM_ENUM(
311 "RX3 MIX1 INP3 Mux", rx3_mix1_inp_enum[2]);
313 /* Digital Gain control -38.4 dB to +38.4 dB in 0.3 dB steps */
314 static const DECLARE_TLV_DB_SCALE(digital_gain, -3840, 30, 0);
316 /* Cutoff Freq for High Pass Filter at -3dB */
317 static const char * const hpf_cutoff_text[] = {
318 "4Hz", "75Hz", "150Hz",
321 static SOC_ENUM_SINGLE_DECL(tx1_hpf_cutoff_enum, LPASS_CDC_TX1_MUX_CTL, 4,
323 static SOC_ENUM_SINGLE_DECL(tx2_hpf_cutoff_enum, LPASS_CDC_TX2_MUX_CTL, 4,
326 /* cut off for dc blocker inside rx chain */
327 static const char * const dc_blocker_cutoff_text[] = {
328 "4Hz", "75Hz", "150Hz",
331 static SOC_ENUM_SINGLE_DECL(rx1_dcb_cutoff_enum, LPASS_CDC_RX1_B4_CTL, 0,
332 dc_blocker_cutoff_text);
333 static SOC_ENUM_SINGLE_DECL(rx2_dcb_cutoff_enum, LPASS_CDC_RX2_B4_CTL, 0,
334 dc_blocker_cutoff_text);
335 static SOC_ENUM_SINGLE_DECL(rx3_dcb_cutoff_enum, LPASS_CDC_RX3_B4_CTL, 0,
336 dc_blocker_cutoff_text);
338 static int msm8x16_wcd_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
339 struct snd_kcontrol *kcontrol, int event)
341 struct snd_soc_component *component =
342 snd_soc_dapm_to_component(w->dapm);
343 int value = 0, reg = 0;
346 case SND_SOC_DAPM_POST_PMU:
348 reg = LPASS_CDC_IIR1_GAIN_B1_CTL;
349 else if (w->shift == 1)
350 reg = LPASS_CDC_IIR2_GAIN_B1_CTL;
351 value = snd_soc_component_read32(component, reg);
352 snd_soc_component_write(component, reg, value);
360 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
361 int iir_idx, int band_idx,
366 /* Address does not automatically update if reading */
367 snd_soc_component_write(component,
368 (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
369 ((band_idx * BAND_MAX + coeff_idx)
370 * sizeof(uint32_t)) & 0x7F);
372 value |= snd_soc_component_read32(component,
373 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx));
375 snd_soc_component_write(component,
376 (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
377 ((band_idx * BAND_MAX + coeff_idx)
378 * sizeof(uint32_t) + 1) & 0x7F);
380 value |= (snd_soc_component_read32(component,
381 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 8);
383 snd_soc_component_write(component,
384 (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
385 ((band_idx * BAND_MAX + coeff_idx)
386 * sizeof(uint32_t) + 2) & 0x7F);
388 value |= (snd_soc_component_read32(component,
389 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 16);
391 snd_soc_component_write(component,
392 (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
393 ((band_idx * BAND_MAX + coeff_idx)
394 * sizeof(uint32_t) + 3) & 0x7F);
396 /* Mask bits top 2 bits since they are reserved */
397 value |= ((snd_soc_component_read32(component,
398 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) & 0x3f) << 24);
403 static int msm8x16_wcd_get_iir_band_audio_mixer(
404 struct snd_kcontrol *kcontrol,
405 struct snd_ctl_elem_value *ucontrol)
408 struct snd_soc_component *component =
409 snd_soc_kcontrol_component(kcontrol);
410 struct wcd_iir_filter_ctl *ctl =
411 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
412 struct soc_bytes_ext *params = &ctl->bytes_ext;
413 int iir_idx = ctl->iir_idx;
414 int band_idx = ctl->band_idx;
417 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
418 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
419 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
420 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
421 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
423 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
428 static void set_iir_band_coeff(struct snd_soc_component *component,
429 int iir_idx, int band_idx,
432 snd_soc_component_write(component,
433 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
436 snd_soc_component_write(component,
437 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
438 (value >> 8) & 0xFF);
440 snd_soc_component_write(component,
441 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
442 (value >> 16) & 0xFF);
444 /* Mask top 2 bits, 7-8 are reserved */
445 snd_soc_component_write(component,
446 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
447 (value >> 24) & 0x3F);
450 static int msm8x16_wcd_put_iir_band_audio_mixer(
451 struct snd_kcontrol *kcontrol,
452 struct snd_ctl_elem_value *ucontrol)
454 struct snd_soc_component *component =
455 snd_soc_kcontrol_component(kcontrol);
456 struct wcd_iir_filter_ctl *ctl =
457 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
458 struct soc_bytes_ext *params = &ctl->bytes_ext;
459 int iir_idx = ctl->iir_idx;
460 int band_idx = ctl->band_idx;
463 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
465 /* Mask top bit it is reserved */
466 /* Updates addr automatically for each B2 write */
467 snd_soc_component_write(component,
468 (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
469 (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F);
471 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
472 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
473 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
474 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
475 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
480 static int wcd_iir_filter_info(struct snd_kcontrol *kcontrol,
481 struct snd_ctl_elem_info *ucontrol)
483 struct wcd_iir_filter_ctl *ctl =
484 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
485 struct soc_bytes_ext *params = &ctl->bytes_ext;
487 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
488 ucontrol->count = params->max;
493 static const struct snd_kcontrol_new msm8916_wcd_digital_snd_controls[] = {
494 SOC_SINGLE_S8_TLV("RX1 Digital Volume", LPASS_CDC_RX1_VOL_CTL_B2_CTL,
495 -128, 127, digital_gain),
496 SOC_SINGLE_S8_TLV("RX2 Digital Volume", LPASS_CDC_RX2_VOL_CTL_B2_CTL,
497 -128, 127, digital_gain),
498 SOC_SINGLE_S8_TLV("RX3 Digital Volume", LPASS_CDC_RX3_VOL_CTL_B2_CTL,
499 -128, 127, digital_gain),
500 SOC_SINGLE_S8_TLV("TX1 Digital Volume", LPASS_CDC_TX1_VOL_CTL_GAIN,
501 -128, 127, digital_gain),
502 SOC_SINGLE_S8_TLV("TX2 Digital Volume", LPASS_CDC_TX2_VOL_CTL_GAIN,
503 -128, 127, digital_gain),
504 SOC_ENUM("TX1 HPF Cutoff", tx1_hpf_cutoff_enum),
505 SOC_ENUM("TX2 HPF Cutoff", tx2_hpf_cutoff_enum),
506 SOC_SINGLE("TX1 HPF Switch", LPASS_CDC_TX1_MUX_CTL, 3, 1, 0),
507 SOC_SINGLE("TX2 HPF Switch", LPASS_CDC_TX2_MUX_CTL, 3, 1, 0),
508 SOC_ENUM("RX1 DCB Cutoff", rx1_dcb_cutoff_enum),
509 SOC_ENUM("RX2 DCB Cutoff", rx2_dcb_cutoff_enum),
510 SOC_ENUM("RX3 DCB Cutoff", rx3_dcb_cutoff_enum),
511 SOC_SINGLE("RX1 DCB Switch", LPASS_CDC_RX1_B5_CTL, 2, 1, 0),
512 SOC_SINGLE("RX2 DCB Switch", LPASS_CDC_RX2_B5_CTL, 2, 1, 0),
513 SOC_SINGLE("RX3 DCB Switch", LPASS_CDC_RX3_B5_CTL, 2, 1, 0),
514 SOC_SINGLE("RX1 Mute Switch", LPASS_CDC_RX1_B6_CTL, 0, 1, 0),
515 SOC_SINGLE("RX2 Mute Switch", LPASS_CDC_RX2_B6_CTL, 0, 1, 0),
516 SOC_SINGLE("RX3 Mute Switch", LPASS_CDC_RX3_B6_CTL, 0, 1, 0),
518 SOC_SINGLE("IIR1 Band1 Switch", LPASS_CDC_IIR1_CTL, 0, 1, 0),
519 SOC_SINGLE("IIR1 Band2 Switch", LPASS_CDC_IIR1_CTL, 1, 1, 0),
520 SOC_SINGLE("IIR1 Band3 Switch", LPASS_CDC_IIR1_CTL, 2, 1, 0),
521 SOC_SINGLE("IIR1 Band4 Switch", LPASS_CDC_IIR1_CTL, 3, 1, 0),
522 SOC_SINGLE("IIR1 Band5 Switch", LPASS_CDC_IIR1_CTL, 4, 1, 0),
523 SOC_SINGLE("IIR2 Band1 Switch", LPASS_CDC_IIR2_CTL, 0, 1, 0),
524 SOC_SINGLE("IIR2 Band2 Switch", LPASS_CDC_IIR2_CTL, 1, 1, 0),
525 SOC_SINGLE("IIR2 Band3 Switch", LPASS_CDC_IIR2_CTL, 2, 1, 0),
526 SOC_SINGLE("IIR2 Band4 Switch", LPASS_CDC_IIR2_CTL, 3, 1, 0),
527 SOC_SINGLE("IIR2 Band5 Switch", LPASS_CDC_IIR2_CTL, 4, 1, 0),
528 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
529 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
530 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
531 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
532 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
533 WCD_IIR_FILTER_CTL("IIR2 Band1", IIR2, BAND1),
534 WCD_IIR_FILTER_CTL("IIR2 Band2", IIR2, BAND2),
535 WCD_IIR_FILTER_CTL("IIR2 Band3", IIR2, BAND3),
536 WCD_IIR_FILTER_CTL("IIR2 Band4", IIR2, BAND4),
537 WCD_IIR_FILTER_CTL("IIR2 Band5", IIR2, BAND5),
538 SOC_SINGLE_SX_TLV("IIR1 INP1 Volume", LPASS_CDC_IIR1_GAIN_B1_CTL,
539 0, -84, 40, digital_gain),
540 SOC_SINGLE_SX_TLV("IIR1 INP2 Volume", LPASS_CDC_IIR1_GAIN_B2_CTL,
541 0, -84, 40, digital_gain),
542 SOC_SINGLE_SX_TLV("IIR1 INP3 Volume", LPASS_CDC_IIR1_GAIN_B3_CTL,
543 0, -84, 40, digital_gain),
544 SOC_SINGLE_SX_TLV("IIR1 INP4 Volume", LPASS_CDC_IIR1_GAIN_B4_CTL,
545 0, -84, 40, digital_gain),
546 SOC_SINGLE_SX_TLV("IIR2 INP1 Volume", LPASS_CDC_IIR2_GAIN_B1_CTL,
547 0, -84, 40, digital_gain),
548 SOC_SINGLE_SX_TLV("IIR2 INP2 Volume", LPASS_CDC_IIR2_GAIN_B2_CTL,
549 0, -84, 40, digital_gain),
550 SOC_SINGLE_SX_TLV("IIR2 INP3 Volume", LPASS_CDC_IIR2_GAIN_B3_CTL,
551 0, -84, 40, digital_gain),
552 SOC_SINGLE_SX_TLV("IIR2 INP4 Volume", LPASS_CDC_IIR2_GAIN_B4_CTL,
553 0, -84, 40, digital_gain),
557 static int msm8916_wcd_digital_enable_interpolator(
558 struct snd_soc_dapm_widget *w,
559 struct snd_kcontrol *kcontrol,
562 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
565 case SND_SOC_DAPM_POST_PMU:
566 /* apply the digital gain after the interpolator is enabled */
567 usleep_range(10000, 10100);
568 snd_soc_component_write(component, rx_gain_reg[w->shift],
569 snd_soc_component_read32(component, rx_gain_reg[w->shift]));
575 static int msm8916_wcd_digital_enable_dec(struct snd_soc_dapm_widget *w,
576 struct snd_kcontrol *kcontrol,
579 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
580 unsigned int decimator = w->shift + 1;
581 u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
582 u8 dec_hpf_cut_of_freq;
584 dec_reset_reg = LPASS_CDC_CLK_TX_RESET_B1_CTL;
585 tx_vol_ctl_reg = LPASS_CDC_TX1_VOL_CTL_CFG + 32 * (decimator - 1);
586 tx_mux_ctl_reg = LPASS_CDC_TX1_MUX_CTL + 32 * (decimator - 1);
589 case SND_SOC_DAPM_PRE_PMU:
590 /* Enable TX digital mute */
591 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
592 TX_VOL_CTL_CFG_MUTE_EN_MASK,
593 TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
594 dec_hpf_cut_of_freq = snd_soc_component_read32(component, tx_mux_ctl_reg) &
595 TX_MUX_CTL_CUT_OFF_FREQ_MASK;
596 dec_hpf_cut_of_freq >>= TX_MUX_CTL_CUT_OFF_FREQ_SHIFT;
597 if (dec_hpf_cut_of_freq != TX_MUX_CTL_CF_NEG_3DB_150HZ) {
598 /* set cut of freq to CF_MIN_3DB_150HZ (0x1) */
599 snd_soc_component_update_bits(component, tx_mux_ctl_reg,
600 TX_MUX_CTL_CUT_OFF_FREQ_MASK,
601 TX_MUX_CTL_CF_NEG_3DB_150HZ);
604 case SND_SOC_DAPM_POST_PMU:
606 snd_soc_component_update_bits(component, tx_mux_ctl_reg,
607 TX_MUX_CTL_HPF_BP_SEL_MASK,
608 TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS);
609 /* apply the digital gain after the decimator is enabled */
610 snd_soc_component_write(component, tx_gain_reg[w->shift],
611 snd_soc_component_read32(component, tx_gain_reg[w->shift]));
612 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
613 TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
615 case SND_SOC_DAPM_PRE_PMD:
616 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
617 TX_VOL_CTL_CFG_MUTE_EN_MASK,
618 TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
619 snd_soc_component_update_bits(component, tx_mux_ctl_reg,
620 TX_MUX_CTL_HPF_BP_SEL_MASK,
621 TX_MUX_CTL_HPF_BP_SEL_BYPASS);
623 case SND_SOC_DAPM_POST_PMD:
624 snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift,
626 snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift, 0x0);
627 snd_soc_component_update_bits(component, tx_mux_ctl_reg,
628 TX_MUX_CTL_HPF_BP_SEL_MASK,
629 TX_MUX_CTL_HPF_BP_SEL_BYPASS);
630 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
631 TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
638 static int msm8916_wcd_digital_enable_dmic(struct snd_soc_dapm_widget *w,
639 struct snd_kcontrol *kcontrol,
642 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
645 /* get dmic number out of widget name */
646 char *dmic_num = strpbrk(w->name, "12");
648 if (dmic_num == NULL) {
649 dev_err(component->dev, "Invalid DMIC\n");
652 ret = kstrtouint(dmic_num, 10, &dmic);
653 if (ret < 0 || dmic > 2) {
654 dev_err(component->dev, "Invalid DMIC line on the component\n");
659 case SND_SOC_DAPM_PRE_PMU:
660 snd_soc_component_update_bits(component, LPASS_CDC_CLK_DMIC_B1_CTL,
661 DMIC_B1_CTL_DMIC0_CLK_SEL_MASK,
662 DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3);
665 snd_soc_component_update_bits(component, LPASS_CDC_TX1_DMIC_CTL,
666 TXN_DMIC_CTL_CLK_SEL_MASK,
667 TXN_DMIC_CTL_CLK_SEL_DIV3);
670 snd_soc_component_update_bits(component, LPASS_CDC_TX2_DMIC_CTL,
671 TXN_DMIC_CTL_CLK_SEL_MASK,
672 TXN_DMIC_CTL_CLK_SEL_DIV3);
681 static const char * const iir_inp1_text[] = {
682 "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
685 static const struct soc_enum iir1_inp1_mux_enum =
686 SOC_ENUM_SINGLE(LPASS_CDC_CONN_EQ1_B1_CTL,
687 0, 6, iir_inp1_text);
689 static const struct soc_enum iir2_inp1_mux_enum =
690 SOC_ENUM_SINGLE(LPASS_CDC_CONN_EQ2_B1_CTL,
691 0, 6, iir_inp1_text);
693 static const struct snd_kcontrol_new iir1_inp1_mux =
694 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
696 static const struct snd_kcontrol_new iir2_inp1_mux =
697 SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum);
699 static const struct snd_soc_dapm_widget msm8916_wcd_digital_dapm_widgets[] = {
701 SND_SOC_DAPM_AIF_IN("I2S RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
702 SND_SOC_DAPM_AIF_IN("I2S RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
703 SND_SOC_DAPM_AIF_IN("I2S RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
705 SND_SOC_DAPM_OUTPUT("PDM_RX1"),
706 SND_SOC_DAPM_OUTPUT("PDM_RX2"),
707 SND_SOC_DAPM_OUTPUT("PDM_RX3"),
709 SND_SOC_DAPM_INPUT("LPASS_PDM_TX"),
711 SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
712 SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
713 SND_SOC_DAPM_MIXER("RX3 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
716 SND_SOC_DAPM_MIXER_E("RX1 INT", LPASS_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
717 0, msm8916_wcd_digital_enable_interpolator,
718 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
719 SND_SOC_DAPM_MIXER_E("RX2 INT", LPASS_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
720 0, msm8916_wcd_digital_enable_interpolator,
721 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
722 SND_SOC_DAPM_MIXER_E("RX3 INT", LPASS_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
723 0, msm8916_wcd_digital_enable_interpolator,
724 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
725 SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
727 SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
729 SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
731 SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
733 SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
735 SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0,
737 SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
739 SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
741 SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0,
744 SND_SOC_DAPM_MUX("CIC1 MUX", SND_SOC_NOPM, 0, 0, &cic1_mux),
745 SND_SOC_DAPM_MUX("CIC2 MUX", SND_SOC_NOPM, 0, 0, &cic2_mux),
747 SND_SOC_DAPM_MIXER("ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
748 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
749 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
751 SND_SOC_DAPM_MUX_E("DEC1 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
752 &dec1_mux, msm8916_wcd_digital_enable_dec,
753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
754 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
755 SND_SOC_DAPM_MUX_E("DEC2 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
756 &dec2_mux, msm8916_wcd_digital_enable_dec,
757 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
758 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
759 SND_SOC_DAPM_AIF_OUT("I2S TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
760 SND_SOC_DAPM_AIF_OUT("I2S TX2", NULL, 0, SND_SOC_NOPM, 0, 0),
761 SND_SOC_DAPM_AIF_OUT("I2S TX3", NULL, 0, SND_SOC_NOPM, 0, 0),
763 /* Digital Mic Inputs */
764 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
765 msm8916_wcd_digital_enable_dmic,
766 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
767 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
768 msm8916_wcd_digital_enable_dmic,
769 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
770 SND_SOC_DAPM_SUPPLY("DMIC_CLK", LPASS_CDC_CLK_DMIC_B1_CTL, 0, 0,
772 SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", LPASS_CDC_CLK_RX_I2S_CTL,
774 SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", LPASS_CDC_CLK_TX_I2S_CTL, 4, 0,
777 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
778 SND_SOC_DAPM_SUPPLY("PDM_CLK", LPASS_CDC_CLK_PDM_CTL, 0, 0, NULL, 0),
779 /* Connectivity Clock */
780 SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, LPASS_CDC_CLK_OTHR_CTL, 2, 0,
782 SND_SOC_DAPM_MIC("Digital Mic1", NULL),
783 SND_SOC_DAPM_MIC("Digital Mic2", NULL),
786 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
787 SND_SOC_DAPM_PGA_E("IIR1", LPASS_CDC_CLK_SD_CTL, 0, 0, NULL, 0,
788 msm8x16_wcd_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU),
790 SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux),
791 SND_SOC_DAPM_PGA_E("IIR2", LPASS_CDC_CLK_SD_CTL, 1, 0, NULL, 0,
792 msm8x16_wcd_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU),
796 static int msm8916_wcd_digital_get_clks(struct platform_device *pdev,
797 struct msm8916_wcd_digital_priv *priv)
799 struct device *dev = &pdev->dev;
801 priv->ahbclk = devm_clk_get(dev, "ahbix-clk");
802 if (IS_ERR(priv->ahbclk)) {
803 dev_err(dev, "failed to get ahbix clk\n");
804 return PTR_ERR(priv->ahbclk);
807 priv->mclk = devm_clk_get(dev, "mclk");
808 if (IS_ERR(priv->mclk)) {
809 dev_err(dev, "failed to get mclk\n");
810 return PTR_ERR(priv->mclk);
816 static int msm8916_wcd_digital_component_probe(struct snd_soc_component *component)
818 struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(component->dev);
820 snd_soc_component_set_drvdata(component, priv);
825 static int msm8916_wcd_digital_component_set_sysclk(struct snd_soc_component *component,
826 int clk_id, int source,
827 unsigned int freq, int dir)
829 struct msm8916_wcd_digital_priv *p = dev_get_drvdata(component->dev);
831 return clk_set_rate(p->mclk, freq);
834 static int msm8916_wcd_digital_hw_params(struct snd_pcm_substream *substream,
835 struct snd_pcm_hw_params *params,
836 struct snd_soc_dai *dai)
841 switch (params_rate(params)) {
843 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ;
844 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ;
847 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ;
848 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ;
851 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ;
852 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ;
855 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ;
856 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ;
859 dev_err(dai->component->dev, "Invalid sampling rate %d\n",
860 params_rate(params));
864 switch (substream->stream) {
865 case SNDRV_PCM_STREAM_CAPTURE:
866 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
867 TX_I2S_CTL_TX_I2S_FS_RATE_MASK, tx_fs_rate);
869 case SNDRV_PCM_STREAM_PLAYBACK:
870 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
871 RX_I2S_CTL_RX_I2S_FS_RATE_MASK, rx_fs_rate);
877 switch (params_format(params)) {
878 case SNDRV_PCM_FORMAT_S16_LE:
879 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
880 TX_I2S_CTL_TX_I2S_MODE_MASK,
881 TX_I2S_CTL_TX_I2S_MODE_16);
882 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
883 RX_I2S_CTL_RX_I2S_MODE_MASK,
884 RX_I2S_CTL_RX_I2S_MODE_16);
887 case SNDRV_PCM_FORMAT_S32_LE:
888 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
889 TX_I2S_CTL_TX_I2S_MODE_MASK,
890 TX_I2S_CTL_TX_I2S_MODE_32);
891 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
892 RX_I2S_CTL_RX_I2S_MODE_MASK,
893 RX_I2S_CTL_RX_I2S_MODE_32);
896 dev_err(dai->dev, "%s: wrong format selected\n", __func__);
903 static const struct snd_soc_dapm_route msm8916_wcd_digital_audio_map[] = {
905 {"I2S RX1", NULL, "AIF1 Playback"},
906 {"I2S RX2", NULL, "AIF1 Playback"},
907 {"I2S RX3", NULL, "AIF1 Playback"},
909 {"AIF1 Capture", NULL, "I2S TX1"},
910 {"AIF1 Capture", NULL, "I2S TX2"},
911 {"AIF1 Capture", NULL, "I2S TX3"},
913 {"CIC1 MUX", "DMIC", "DEC1 MUX"},
914 {"CIC1 MUX", "AMIC", "DEC1 MUX"},
915 {"CIC2 MUX", "DMIC", "DEC2 MUX"},
916 {"CIC2 MUX", "AMIC", "DEC2 MUX"},
918 /* Decimator Inputs */
919 {"DEC1 MUX", "DMIC1", "DMIC1"},
920 {"DEC1 MUX", "DMIC2", "DMIC2"},
921 {"DEC1 MUX", "ADC1", "ADC1"},
922 {"DEC1 MUX", "ADC2", "ADC2"},
923 {"DEC1 MUX", "ADC3", "ADC3"},
924 {"DEC1 MUX", NULL, "CDC_CONN"},
926 {"DEC2 MUX", "DMIC1", "DMIC1"},
927 {"DEC2 MUX", "DMIC2", "DMIC2"},
928 {"DEC2 MUX", "ADC1", "ADC1"},
929 {"DEC2 MUX", "ADC2", "ADC2"},
930 {"DEC2 MUX", "ADC3", "ADC3"},
931 {"DEC2 MUX", NULL, "CDC_CONN"},
933 {"DMIC1", NULL, "DMIC_CLK"},
934 {"DMIC2", NULL, "DMIC_CLK"},
936 {"I2S TX1", NULL, "CIC1 MUX"},
937 {"I2S TX2", NULL, "CIC2 MUX"},
939 {"I2S TX1", NULL, "TX_I2S_CLK"},
940 {"I2S TX2", NULL, "TX_I2S_CLK"},
942 {"TX_I2S_CLK", NULL, "MCLK"},
943 {"TX_I2S_CLK", NULL, "PDM_CLK"},
945 {"ADC1", NULL, "LPASS_PDM_TX"},
946 {"ADC2", NULL, "LPASS_PDM_TX"},
947 {"ADC3", NULL, "LPASS_PDM_TX"},
949 {"I2S RX1", NULL, "RX_I2S_CLK"},
950 {"I2S RX2", NULL, "RX_I2S_CLK"},
951 {"I2S RX3", NULL, "RX_I2S_CLK"},
953 {"RX_I2S_CLK", NULL, "PDM_CLK"},
954 {"RX_I2S_CLK", NULL, "MCLK"},
955 {"RX_I2S_CLK", NULL, "CDC_CONN"},
958 {"PDM_RX1", NULL, "RX1 INT"},
959 {"RX1 INT", NULL, "RX1 MIX1"},
961 {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
962 {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
963 {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
965 {"RX1 MIX1 INP1", "RX1", "I2S RX1"},
966 {"RX1 MIX1 INP1", "RX2", "I2S RX2"},
967 {"RX1 MIX1 INP1", "RX3", "I2S RX3"},
968 {"RX1 MIX1 INP1", "IIR1", "IIR1"},
969 {"RX1 MIX1 INP1", "IIR2", "IIR2"},
971 {"RX1 MIX1 INP2", "RX1", "I2S RX1"},
972 {"RX1 MIX1 INP2", "RX2", "I2S RX2"},
973 {"RX1 MIX1 INP2", "RX3", "I2S RX3"},
974 {"RX1 MIX1 INP2", "IIR1", "IIR1"},
975 {"RX1 MIX1 INP2", "IIR2", "IIR2"},
977 {"RX1 MIX1 INP3", "RX1", "I2S RX1"},
978 {"RX1 MIX1 INP3", "RX2", "I2S RX2"},
979 {"RX1 MIX1 INP3", "RX3", "I2S RX3"},
982 {"PDM_RX2", NULL, "RX2 INT"},
983 {"RX2 INT", NULL, "RX2 MIX1"},
985 {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
986 {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
987 {"RX2 MIX1", NULL, "RX2 MIX1 INP3"},
989 {"RX2 MIX1 INP1", "RX1", "I2S RX1"},
990 {"RX2 MIX1 INP1", "RX2", "I2S RX2"},
991 {"RX2 MIX1 INP1", "RX3", "I2S RX3"},
992 {"RX2 MIX1 INP1", "IIR1", "IIR1"},
993 {"RX2 MIX1 INP1", "IIR2", "IIR2"},
995 {"RX2 MIX1 INP2", "RX1", "I2S RX1"},
996 {"RX2 MIX1 INP2", "RX2", "I2S RX2"},
997 {"RX2 MIX1 INP2", "RX3", "I2S RX3"},
998 {"RX2 MIX1 INP1", "IIR1", "IIR1"},
999 {"RX2 MIX1 INP1", "IIR2", "IIR2"},
1001 {"RX2 MIX1 INP3", "RX1", "I2S RX1"},
1002 {"RX2 MIX1 INP3", "RX2", "I2S RX2"},
1003 {"RX2 MIX1 INP3", "RX3", "I2S RX3"},
1006 {"PDM_RX3", NULL, "RX3 INT"},
1007 {"RX3 INT", NULL, "RX3 MIX1"},
1009 {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
1010 {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
1011 {"RX3 MIX1", NULL, "RX3 MIX1 INP3"},
1013 {"RX3 MIX1 INP1", "RX1", "I2S RX1"},
1014 {"RX3 MIX1 INP1", "RX2", "I2S RX2"},
1015 {"RX3 MIX1 INP1", "RX3", "I2S RX3"},
1016 {"RX3 MIX1 INP1", "IIR1", "IIR1"},
1017 {"RX3 MIX1 INP1", "IIR2", "IIR2"},
1019 {"RX3 MIX1 INP2", "RX1", "I2S RX1"},
1020 {"RX3 MIX1 INP2", "RX2", "I2S RX2"},
1021 {"RX3 MIX1 INP2", "RX3", "I2S RX3"},
1022 {"RX3 MIX1 INP2", "IIR1", "IIR1"},
1023 {"RX3 MIX1 INP2", "IIR2", "IIR2"},
1025 {"RX1 MIX2 INP1", "IIR1", "IIR1"},
1026 {"RX2 MIX2 INP1", "IIR1", "IIR1"},
1027 {"RX1 MIX2 INP1", "IIR2", "IIR2"},
1028 {"RX2 MIX2 INP1", "IIR2", "IIR2"},
1030 {"IIR1", NULL, "IIR1 INP1 MUX"},
1031 {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
1032 {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
1034 {"IIR2", NULL, "IIR2 INP1 MUX"},
1035 {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"},
1036 {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"},
1038 {"RX3 MIX1 INP3", "RX1", "I2S RX1"},
1039 {"RX3 MIX1 INP3", "RX2", "I2S RX2"},
1040 {"RX3 MIX1 INP3", "RX3", "I2S RX3"},
1044 static int msm8916_wcd_digital_startup(struct snd_pcm_substream *substream,
1045 struct snd_soc_dai *dai)
1047 struct snd_soc_component *component = dai->component;
1048 struct msm8916_wcd_digital_priv *msm8916_wcd;
1049 unsigned long mclk_rate;
1051 msm8916_wcd = snd_soc_component_get_drvdata(component);
1052 snd_soc_component_update_bits(component, LPASS_CDC_CLK_MCLK_CTL,
1053 MCLK_CTL_MCLK_EN_MASK,
1054 MCLK_CTL_MCLK_EN_ENABLE);
1055 snd_soc_component_update_bits(component, LPASS_CDC_CLK_PDM_CTL,
1056 LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK,
1057 LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB);
1059 mclk_rate = clk_get_rate(msm8916_wcd->mclk);
1060 switch (mclk_rate) {
1062 snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
1063 TOP_CTL_DIG_MCLK_FREQ_MASK,
1064 TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ);
1067 snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
1068 TOP_CTL_DIG_MCLK_FREQ_MASK,
1069 TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ);
1072 dev_err(component->dev, "Invalid mclk rate %ld\n", mclk_rate);
1078 static void msm8916_wcd_digital_shutdown(struct snd_pcm_substream *substream,
1079 struct snd_soc_dai *dai)
1081 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_PDM_CTL,
1082 LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK, 0);
1085 static const struct snd_soc_dai_ops msm8916_wcd_digital_dai_ops = {
1086 .startup = msm8916_wcd_digital_startup,
1087 .shutdown = msm8916_wcd_digital_shutdown,
1088 .hw_params = msm8916_wcd_digital_hw_params,
1091 static struct snd_soc_dai_driver msm8916_wcd_digital_dai[] = {
1093 .name = "msm8916_wcd_digital_i2s_rx1",
1096 .stream_name = "AIF1 Playback",
1097 .rates = MSM8916_WCD_DIGITAL_RATES,
1098 .formats = MSM8916_WCD_DIGITAL_FORMATS,
1102 .ops = &msm8916_wcd_digital_dai_ops,
1105 .name = "msm8916_wcd_digital_i2s_tx1",
1108 .stream_name = "AIF1 Capture",
1109 .rates = MSM8916_WCD_DIGITAL_RATES,
1110 .formats = MSM8916_WCD_DIGITAL_FORMATS,
1114 .ops = &msm8916_wcd_digital_dai_ops,
1118 static const struct snd_soc_component_driver msm8916_wcd_digital = {
1119 .probe = msm8916_wcd_digital_component_probe,
1120 .set_sysclk = msm8916_wcd_digital_component_set_sysclk,
1121 .controls = msm8916_wcd_digital_snd_controls,
1122 .num_controls = ARRAY_SIZE(msm8916_wcd_digital_snd_controls),
1123 .dapm_widgets = msm8916_wcd_digital_dapm_widgets,
1124 .num_dapm_widgets = ARRAY_SIZE(msm8916_wcd_digital_dapm_widgets),
1125 .dapm_routes = msm8916_wcd_digital_audio_map,
1126 .num_dapm_routes = ARRAY_SIZE(msm8916_wcd_digital_audio_map),
1128 .use_pmdown_time = 1,
1130 .non_legacy_dai_naming = 1,
1133 static const struct regmap_config msm8916_codec_regmap_config = {
1137 .max_register = LPASS_CDC_TX2_DMIC_CTL,
1138 .cache_type = REGCACHE_FLAT,
1141 static int msm8916_wcd_digital_probe(struct platform_device *pdev)
1143 struct msm8916_wcd_digital_priv *priv;
1144 struct device *dev = &pdev->dev;
1146 struct regmap *digital_map;
1149 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1153 base = devm_platform_ioremap_resource(pdev, 0);
1155 return PTR_ERR(base);
1158 devm_regmap_init_mmio(&pdev->dev, base,
1159 &msm8916_codec_regmap_config);
1160 if (IS_ERR(digital_map))
1161 return PTR_ERR(digital_map);
1163 ret = msm8916_wcd_digital_get_clks(pdev, priv);
1167 ret = clk_prepare_enable(priv->ahbclk);
1169 dev_err(dev, "failed to enable ahbclk %d\n", ret);
1173 ret = clk_prepare_enable(priv->mclk);
1175 dev_err(dev, "failed to enable mclk %d\n", ret);
1179 dev_set_drvdata(dev, priv);
1181 return devm_snd_soc_register_component(dev, &msm8916_wcd_digital,
1182 msm8916_wcd_digital_dai,
1183 ARRAY_SIZE(msm8916_wcd_digital_dai));
1186 static int msm8916_wcd_digital_remove(struct platform_device *pdev)
1188 struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(&pdev->dev);
1190 clk_disable_unprepare(priv->mclk);
1191 clk_disable_unprepare(priv->ahbclk);
1196 static const struct of_device_id msm8916_wcd_digital_match_table[] = {
1197 { .compatible = "qcom,msm8916-wcd-digital-codec" },
1201 MODULE_DEVICE_TABLE(of, msm8916_wcd_digital_match_table);
1203 static struct platform_driver msm8916_wcd_digital_driver = {
1205 .name = "msm8916-wcd-digital-codec",
1206 .of_match_table = msm8916_wcd_digital_match_table,
1208 .probe = msm8916_wcd_digital_probe,
1209 .remove = msm8916_wcd_digital_remove,
1212 module_platform_driver(msm8916_wcd_digital_driver);
1214 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
1215 MODULE_DESCRIPTION("MSM8916 WCD Digital Codec driver");
1216 MODULE_LICENSE("GPL v2");