sound/soc/codecs/msm8916-wcd-digital.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2016, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/module.h>
   5 #include <linux/err.h>
   6 #include <linux/kernel.h>
   7 #include <linux/delay.h>
   8 #include <linux/types.h>
   9 #include <linux/clk.h>
  10 #include <linux/of.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/regmap.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <sound/soc.h>
  15 #include <sound/pcm.h>
  16 #include <sound/pcm_params.h>
  17 #include <sound/tlv.h>
  18
  19 #define LPASS_CDC_CLK_RX_RESET_CTL              (0x000)
  20 #define LPASS_CDC_CLK_TX_RESET_B1_CTL           (0x004)
  21 #define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK      BIT(0)
  22 #define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK      BIT(1)
  23 #define LPASS_CDC_CLK_DMIC_B1_CTL               (0x008)
  24 #define DMIC_B1_CTL_DMIC0_CLK_SEL_MASK          GENMASK(3, 1)
  25 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV2          (0x0 << 1)
  26 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3          (0x1 << 1)
  27 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV4          (0x2 << 1)
  28 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV6          (0x3 << 1)
  29 #define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV16         (0x4 << 1)
  30 #define DMIC_B1_CTL_DMIC0_CLK_EN_MASK           BIT(0)
  31 #define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE         BIT(0)
  32
  33 #define LPASS_CDC_CLK_RX_I2S_CTL                (0x00C)
  34 #define RX_I2S_CTL_RX_I2S_MODE_MASK             BIT(5)
  35 #define RX_I2S_CTL_RX_I2S_MODE_16               BIT(5)
  36 #define RX_I2S_CTL_RX_I2S_MODE_32               0
  37 #define RX_I2S_CTL_RX_I2S_FS_RATE_MASK          GENMASK(2, 0)
  38 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ       0x0
  39 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ      0x1
  40 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ      0x2
  41 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ      0x3
  42 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_96_KHZ      0x4
  43 #define RX_I2S_CTL_RX_I2S_FS_RATE_F_192_KHZ     0x5
  44 #define LPASS_CDC_CLK_TX_I2S_CTL                (0x010)
  45 #define TX_I2S_CTL_TX_I2S_MODE_MASK             BIT(5)
  46 #define TX_I2S_CTL_TX_I2S_MODE_16               BIT(5)
  47 #define TX_I2S_CTL_TX_I2S_MODE_32               0
  48 #define TX_I2S_CTL_TX_I2S_FS_RATE_MASK          GENMASK(2, 0)
  49 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ       0x0
  50 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ      0x1
  51 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ      0x2
  52 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ      0x3
  53 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_96_KHZ      0x4
  54 #define TX_I2S_CTL_TX_I2S_FS_RATE_F_192_KHZ     0x5
  55
  56 #define LPASS_CDC_CLK_OTHR_RESET_B1_CTL         (0x014)
  57 #define LPASS_CDC_CLK_TX_CLK_EN_B1_CTL          (0x018)
  58 #define LPASS_CDC_CLK_OTHR_CTL                  (0x01C)
  59 #define LPASS_CDC_CLK_RX_B1_CTL                 (0x020)
  60 #define LPASS_CDC_CLK_MCLK_CTL                  (0x024)
  61 #define MCLK_CTL_MCLK_EN_MASK                   BIT(0)
  62 #define MCLK_CTL_MCLK_EN_ENABLE                 BIT(0)
  63 #define MCLK_CTL_MCLK_EN_DISABLE                0
  64 #define LPASS_CDC_CLK_PDM_CTL                   (0x028)
  65 #define LPASS_CDC_CLK_PDM_CTL_PDM_EN_MASK       BIT(0)
  66 #define LPASS_CDC_CLK_PDM_CTL_PDM_EN            BIT(0)
  67 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK  BIT(1)
  68 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB    BIT(1)
  69 #define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_PDM_CLK   0
  70
  71 #define LPASS_CDC_CLK_SD_CTL                    (0x02C)
  72 #define LPASS_CDC_RX1_B1_CTL                    (0x040)
  73 #define LPASS_CDC_RX2_B1_CTL                    (0x060)
  74 #define LPASS_CDC_RX3_B1_CTL                    (0x080)
  75 #define LPASS_CDC_RX1_B2_CTL                    (0x044)
  76 #define LPASS_CDC_RX2_B2_CTL                    (0x064)
  77 #define LPASS_CDC_RX3_B2_CTL                    (0x084)
  78 #define LPASS_CDC_RX1_B3_CTL                    (0x048)
  79 #define LPASS_CDC_RX2_B3_CTL                    (0x068)
  80 #define LPASS_CDC_RX3_B3_CTL                    (0x088)
  81 #define LPASS_CDC_RX1_B4_CTL                    (0x04C)
  82 #define LPASS_CDC_RX2_B4_CTL                    (0x06C)
  83 #define LPASS_CDC_RX3_B4_CTL                    (0x08C)
  84 #define LPASS_CDC_RX1_B5_CTL                    (0x050)
  85 #define LPASS_CDC_RX2_B5_CTL                    (0x070)
  86 #define LPASS_CDC_RX3_B5_CTL                    (0x090)
  87 #define LPASS_CDC_RX1_B6_CTL                    (0x054)
  88 #define RXn_B6_CTL_MUTE_MASK                    BIT(0)
  89 #define RXn_B6_CTL_MUTE_ENABLE                  BIT(0)
  90 #define RXn_B6_CTL_MUTE_DISABLE                 0
  91 #define LPASS_CDC_RX2_B6_CTL                    (0x074)
  92 #define LPASS_CDC_RX3_B6_CTL                    (0x094)
  93 #define LPASS_CDC_RX1_VOL_CTL_B1_CTL            (0x058)
  94 #define LPASS_CDC_RX2_VOL_CTL_B1_CTL            (0x078)
  95 #define LPASS_CDC_RX3_VOL_CTL_B1_CTL            (0x098)
  96 #define LPASS_CDC_RX1_VOL_CTL_B2_CTL            (0x05C)
  97 #define LPASS_CDC_RX2_VOL_CTL_B2_CTL            (0x07C)
  98 #define LPASS_CDC_RX3_VOL_CTL_B2_CTL            (0x09C)
  99 #define LPASS_CDC_TOP_GAIN_UPDATE               (0x0A0)
 100 #define LPASS_CDC_TOP_CTL                       (0x0A4)
 101 #define TOP_CTL_DIG_MCLK_FREQ_MASK              BIT(0)
 102 #define TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ       0
 103 #define TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ          BIT(0)
 104
 105 #define LPASS_CDC_DEBUG_DESER1_CTL              (0x0E0)
 106 #define LPASS_CDC_DEBUG_DESER2_CTL              (0x0E4)
 107 #define LPASS_CDC_DEBUG_B1_CTL_CFG              (0x0E8)
 108 #define LPASS_CDC_DEBUG_B2_CTL_CFG              (0x0EC)
 109 #define LPASS_CDC_DEBUG_B3_CTL_CFG              (0x0F0)
 110 #define LPASS_CDC_IIR1_GAIN_B1_CTL              (0x100)
 111 #define LPASS_CDC_IIR2_GAIN_B1_CTL              (0x140)
 112 #define LPASS_CDC_IIR1_GAIN_B2_CTL              (0x104)
 113 #define LPASS_CDC_IIR2_GAIN_B2_CTL              (0x144)
 114 #define LPASS_CDC_IIR1_GAIN_B3_CTL              (0x108)
 115 #define LPASS_CDC_IIR2_GAIN_B3_CTL              (0x148)
 116 #define LPASS_CDC_IIR1_GAIN_B4_CTL              (0x10C)
 117 #define LPASS_CDC_IIR2_GAIN_B4_CTL              (0x14C)
 118 #define LPASS_CDC_IIR1_GAIN_B5_CTL              (0x110)
 119 #define LPASS_CDC_IIR2_GAIN_B5_CTL              (0x150)
 120 #define LPASS_CDC_IIR1_GAIN_B6_CTL              (0x114)
 121 #define LPASS_CDC_IIR2_GAIN_B6_CTL              (0x154)
 122 #define LPASS_CDC_IIR1_GAIN_B7_CTL              (0x118)
 123 #define LPASS_CDC_IIR2_GAIN_B7_CTL              (0x158)
 124 #define LPASS_CDC_IIR1_GAIN_B8_CTL              (0x11C)
 125 #define LPASS_CDC_IIR2_GAIN_B8_CTL              (0x15C)
 126 #define LPASS_CDC_IIR1_CTL                      (0x120)
 127 #define LPASS_CDC_IIR2_CTL                      (0x160)
 128 #define LPASS_CDC_IIR1_GAIN_TIMER_CTL           (0x124)
 129 #define LPASS_CDC_IIR2_GAIN_TIMER_CTL           (0x164)
 130 #define LPASS_CDC_IIR1_COEF_B1_CTL              (0x128)
 131 #define LPASS_CDC_IIR2_COEF_B1_CTL              (0x168)
 132 #define LPASS_CDC_IIR1_COEF_B2_CTL              (0x12C)
 133 #define LPASS_CDC_IIR2_COEF_B2_CTL              (0x16C)
 134 #define LPASS_CDC_CONN_RX1_B1_CTL               (0x180)
 135 #define LPASS_CDC_CONN_RX1_B2_CTL               (0x184)
 136 #define LPASS_CDC_CONN_RX1_B3_CTL               (0x188)
 137 #define LPASS_CDC_CONN_RX2_B1_CTL               (0x18C)
 138 #define LPASS_CDC_CONN_RX2_B2_CTL               (0x190)
 139 #define LPASS_CDC_CONN_RX2_B3_CTL               (0x194)
 140 #define LPASS_CDC_CONN_RX3_B1_CTL               (0x198)
 141 #define LPASS_CDC_CONN_RX3_B2_CTL               (0x19C)
 142 #define LPASS_CDC_CONN_TX_B1_CTL                (0x1A0)
 143 #define LPASS_CDC_CONN_EQ1_B1_CTL               (0x1A8)
 144 #define LPASS_CDC_CONN_EQ1_B2_CTL               (0x1AC)
 145 #define LPASS_CDC_CONN_EQ1_B3_CTL               (0x1B0)
 146 #define LPASS_CDC_CONN_EQ1_B4_CTL               (0x1B4)
 147 #define LPASS_CDC_CONN_EQ2_B1_CTL               (0x1B8)
 148 #define LPASS_CDC_CONN_EQ2_B2_CTL               (0x1BC)
 149 #define LPASS_CDC_CONN_EQ2_B3_CTL               (0x1C0)
 150 #define LPASS_CDC_CONN_EQ2_B4_CTL               (0x1C4)
 151 #define LPASS_CDC_CONN_TX_I2S_SD1_CTL           (0x1C8)
 152 #define LPASS_CDC_TX1_VOL_CTL_TIMER             (0x280)
 153 #define LPASS_CDC_TX2_VOL_CTL_TIMER             (0x2A0)
 154 #define LPASS_CDC_TX1_VOL_CTL_GAIN              (0x284)
 155 #define LPASS_CDC_TX2_VOL_CTL_GAIN              (0x2A4)
 156 #define LPASS_CDC_TX1_VOL_CTL_CFG               (0x288)
 157 #define TX_VOL_CTL_CFG_MUTE_EN_MASK             BIT(0)
 158 #define TX_VOL_CTL_CFG_MUTE_EN_ENABLE           BIT(0)
 159
 160 #define LPASS_CDC_TX2_VOL_CTL_CFG               (0x2A8)
 161 #define LPASS_CDC_TX1_MUX_CTL                   (0x28C)
 162 #define TX_MUX_CTL_CUT_OFF_FREQ_MASK            GENMASK(5, 4)
 163 #define TX_MUX_CTL_CUT_OFF_FREQ_SHIFT           4
 164 #define TX_MUX_CTL_CF_NEG_3DB_4HZ               (0x0 << 4)
 165 #define TX_MUX_CTL_CF_NEG_3DB_75HZ              (0x1 << 4)
 166 #define TX_MUX_CTL_CF_NEG_3DB_150HZ             (0x2 << 4)
 167 #define TX_MUX_CTL_HPF_BP_SEL_MASK              BIT(3)
 168 #define TX_MUX_CTL_HPF_BP_SEL_BYPASS            BIT(3)
 169 #define TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS         0
 170
 171 #define LPASS_CDC_TX2_MUX_CTL                   (0x2AC)
 172 #define LPASS_CDC_TX1_CLK_FS_CTL                (0x290)
 173 #define LPASS_CDC_TX2_CLK_FS_CTL                (0x2B0)
 174 #define LPASS_CDC_TX1_DMIC_CTL                  (0x294)
 175 #define LPASS_CDC_TX2_DMIC_CTL                  (0x2B4)
 176 #define TXN_DMIC_CTL_CLK_SEL_MASK               GENMASK(2, 0)
 177 #define TXN_DMIC_CTL_CLK_SEL_DIV2               0x0
 178 #define TXN_DMIC_CTL_CLK_SEL_DIV3               0x1
 179 #define TXN_DMIC_CTL_CLK_SEL_DIV4               0x2
 180 #define TXN_DMIC_CTL_CLK_SEL_DIV6               0x3
 181 #define TXN_DMIC_CTL_CLK_SEL_DIV16              0x4
 182
 183 #define MSM8916_WCD_DIGITAL_RATES (SNDRV_PCM_RATE_8000 | \
 184                                    SNDRV_PCM_RATE_16000 | \
 185                                    SNDRV_PCM_RATE_32000 | \
 186                                    SNDRV_PCM_RATE_48000)
 187 #define MSM8916_WCD_DIGITAL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 188                                      SNDRV_PCM_FMTBIT_S32_LE)
 189
 190 /* Codec supports 2 IIR filters */
 191 enum {
 192         IIR1 = 0,
 193         IIR2,
 194         IIR_MAX,
 195 };
 196
 197 /* Codec supports 5 bands */
 198 enum {
 199         BAND1 = 0,
 200         BAND2,
 201         BAND3,
 202         BAND4,
 203         BAND5,
 204         BAND_MAX,
 205 };
 206
 207 #define WCD_IIR_FILTER_SIZE     (sizeof(u32)*BAND_MAX)
 208
 209 #define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
 210 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 211         .info = wcd_iir_filter_info, \
 212         .get = msm8x16_wcd_get_iir_band_audio_mixer, \
 213         .put = msm8x16_wcd_put_iir_band_audio_mixer, \
 214         .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
 215                 .iir_idx = iidx, \
 216                 .band_idx = bidx, \
 217                 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
 218         } \
 219 }
 220
 221 struct wcd_iir_filter_ctl {
 222         unsigned int iir_idx;
 223         unsigned int band_idx;
 224         struct soc_bytes_ext bytes_ext;
 225 };
 226
 227 struct msm8916_wcd_digital_priv {
 228         struct clk *ahbclk, *mclk;
 229 };
 230
 231 static const unsigned long rx_gain_reg[] = {
 232         LPASS_CDC_RX1_VOL_CTL_B2_CTL,
 233         LPASS_CDC_RX2_VOL_CTL_B2_CTL,
 234         LPASS_CDC_RX3_VOL_CTL_B2_CTL,
 235 };
 236
 237 static const unsigned long tx_gain_reg[] = {
 238         LPASS_CDC_TX1_VOL_CTL_GAIN,
 239         LPASS_CDC_TX2_VOL_CTL_GAIN,
 240 };
 241
 242 static const char *const rx_mix1_text[] = {
 243         "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3"
 244 };
 245
 246 static const char * const rx_mix2_text[] = {
 247         "ZERO", "IIR1", "IIR2"
 248 };
 249
 250 static const char *const dec_mux_text[] = {
 251         "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2"
 252 };
 253
 254 static const char *const cic_mux_text[] = { "AMIC", "DMIC" };
 255
 256 /* RX1 MIX1 */
 257 static const struct soc_enum rx_mix1_inp_enum[] = {
 258         SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 0, 6, rx_mix1_text),
 259         SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 3, 6, rx_mix1_text),
 260         SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B2_CTL, 0, 6, rx_mix1_text),
 261 };
 262
 263 /* RX2 MIX1 */
 264 static const struct soc_enum rx2_mix1_inp_enum[] = {
 265         SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text),
 266         SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 3, 6, rx_mix1_text),
 267         SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B2_CTL, 0, 6, rx_mix1_text),
 268 };
 269
 270 /* RX3 MIX1 */
 271 static const struct soc_enum rx3_mix1_inp_enum[] = {
 272         SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text),
 273         SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 3, 6, rx_mix1_text),
 274         SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B2_CTL, 0, 6, rx_mix1_text),
 275 };
 276
 277 /* RX1 MIX2 */
 278 static const struct soc_enum rx_mix2_inp1_chain_enum =
 279         SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B3_CTL,
 280                 0, 3, rx_mix2_text);
 281
 282 /* RX2 MIX2 */
 283 static const struct soc_enum rx2_mix2_inp1_chain_enum =
 284         SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B3_CTL,
 285                 0, 3, rx_mix2_text);
 286
 287 /* DEC */
 288 static const struct soc_enum dec1_mux_enum = SOC_ENUM_SINGLE(
 289                                 LPASS_CDC_CONN_TX_B1_CTL, 0, 6, dec_mux_text);
 290 static const struct soc_enum dec2_mux_enum = SOC_ENUM_SINGLE(
 291                                 LPASS_CDC_CONN_TX_B1_CTL, 3, 6, dec_mux_text);
 292
 293 /* CIC */
 294 static const struct soc_enum cic1_mux_enum = SOC_ENUM_SINGLE(
 295                                 LPASS_CDC_TX1_MUX_CTL, 0, 2, cic_mux_text);
 296 static const struct soc_enum cic2_mux_enum = SOC_ENUM_SINGLE(
 297                                 LPASS_CDC_TX2_MUX_CTL, 0, 2, cic_mux_text);
 298
 299 /* RDAC2 MUX */
 300 static const struct snd_kcontrol_new dec1_mux = SOC_DAPM_ENUM(
 301                                 "DEC1 MUX Mux", dec1_mux_enum);
 302 static const struct snd_kcontrol_new dec2_mux = SOC_DAPM_ENUM(
 303                                 "DEC2 MUX Mux", dec2_mux_enum);
 304 static const struct snd_kcontrol_new cic1_mux = SOC_DAPM_ENUM(
 305                                 "CIC1 MUX Mux", cic1_mux_enum);
 306 static const struct snd_kcontrol_new cic2_mux = SOC_DAPM_ENUM(
 307                                 "CIC2 MUX Mux", cic2_mux_enum);
 308 static const struct snd_kcontrol_new rx_mix1_inp1_mux = SOC_DAPM_ENUM(
 309                                 "RX1 MIX1 INP1 Mux", rx_mix1_inp_enum[0]);
 310 static const struct snd_kcontrol_new rx_mix1_inp2_mux = SOC_DAPM_ENUM(
 311                                 "RX1 MIX1 INP2 Mux", rx_mix1_inp_enum[1]);
 312 static const struct snd_kcontrol_new rx_mix1_inp3_mux = SOC_DAPM_ENUM(
 313                                 "RX1 MIX1 INP3 Mux", rx_mix1_inp_enum[2]);
 314 static const struct snd_kcontrol_new rx2_mix1_inp1_mux = SOC_DAPM_ENUM(
 315                                 "RX2 MIX1 INP1 Mux", rx2_mix1_inp_enum[0]);
 316 static const struct snd_kcontrol_new rx2_mix1_inp2_mux = SOC_DAPM_ENUM(
 317                                 "RX2 MIX1 INP2 Mux", rx2_mix1_inp_enum[1]);
 318 static const struct snd_kcontrol_new rx2_mix1_inp3_mux = SOC_DAPM_ENUM(
 319                                 "RX2 MIX1 INP3 Mux", rx2_mix1_inp_enum[2]);
 320 static const struct snd_kcontrol_new rx3_mix1_inp1_mux = SOC_DAPM_ENUM(
 321                                 "RX3 MIX1 INP1 Mux", rx3_mix1_inp_enum[0]);
 322 static const struct snd_kcontrol_new rx3_mix1_inp2_mux = SOC_DAPM_ENUM(
 323                                 "RX3 MIX1 INP2 Mux", rx3_mix1_inp_enum[1]);
 324 static const struct snd_kcontrol_new rx3_mix1_inp3_mux = SOC_DAPM_ENUM(
 325                                 "RX3 MIX1 INP3 Mux", rx3_mix1_inp_enum[2]);
 326 static const struct snd_kcontrol_new rx1_mix2_inp1_mux = SOC_DAPM_ENUM(
 327                                 "RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum);
 328 static const struct snd_kcontrol_new rx2_mix2_inp1_mux = SOC_DAPM_ENUM(
 329                                 "RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum);
 330
 331 /* Digital Gain control -38.4 dB to +38.4 dB in 0.3 dB steps */
 332 static const DECLARE_TLV_DB_SCALE(digital_gain, -3840, 30, 0);
 333
 334 /* Cutoff Freq for High Pass Filter at -3dB */
 335 static const char * const hpf_cutoff_text[] = {
 336         "4Hz", "75Hz", "150Hz",
 337 };
 338
 339 static SOC_ENUM_SINGLE_DECL(tx1_hpf_cutoff_enum, LPASS_CDC_TX1_MUX_CTL, 4,
 340                             hpf_cutoff_text);
 341 static SOC_ENUM_SINGLE_DECL(tx2_hpf_cutoff_enum, LPASS_CDC_TX2_MUX_CTL, 4,
 342                             hpf_cutoff_text);
 343
 344 /* cut off for dc blocker inside rx chain */
 345 static const char * const dc_blocker_cutoff_text[] = {
 346         "4Hz", "75Hz", "150Hz",
 347 };
 348
 349 static SOC_ENUM_SINGLE_DECL(rx1_dcb_cutoff_enum, LPASS_CDC_RX1_B4_CTL, 0,
 350                             dc_blocker_cutoff_text);
 351 static SOC_ENUM_SINGLE_DECL(rx2_dcb_cutoff_enum, LPASS_CDC_RX2_B4_CTL, 0,
 352                             dc_blocker_cutoff_text);
 353 static SOC_ENUM_SINGLE_DECL(rx3_dcb_cutoff_enum, LPASS_CDC_RX3_B4_CTL, 0,
 354                             dc_blocker_cutoff_text);
 355
 356 static int msm8x16_wcd_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
 357                 struct snd_kcontrol *kcontrol, int event)
 358 {
 359         struct snd_soc_component *component =
 360                         snd_soc_dapm_to_component(w->dapm);
 361         int value = 0, reg = 0;
 362
 363         switch (event) {
 364         case SND_SOC_DAPM_POST_PMU:
 365                 if (w->shift == 0)
 366                         reg = LPASS_CDC_IIR1_GAIN_B1_CTL;
 367                 else if (w->shift == 1)
 368                         reg = LPASS_CDC_IIR2_GAIN_B1_CTL;
 369                 value = snd_soc_component_read(component, reg);
 370                 snd_soc_component_write(component, reg, value);
 371                 break;
 372         default:
 373                 break;
 374         }
 375         return 0;
 376 }
 377
 378 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
 379                                    int iir_idx, int band_idx,
 380                                    int coeff_idx)
 381 {
 382         uint32_t value = 0;
 383
 384         /* Address does not automatically update if reading */
 385         snd_soc_component_write(component,
 386                 (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
 387                 ((band_idx * BAND_MAX + coeff_idx)
 388                 * sizeof(uint32_t)) & 0x7F);
 389
 390         value |= snd_soc_component_read(component,
 391                 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx));
 392
 393         snd_soc_component_write(component,
 394                 (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
 395                 ((band_idx * BAND_MAX + coeff_idx)
 396                 * sizeof(uint32_t) + 1) & 0x7F);
 397
 398         value |= (snd_soc_component_read(component,
 399                 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 8);
 400
 401         snd_soc_component_write(component,
 402                 (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
 403                 ((band_idx * BAND_MAX + coeff_idx)
 404                 * sizeof(uint32_t) + 2) & 0x7F);
 405
 406         value |= (snd_soc_component_read(component,
 407                 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 16);
 408
 409         snd_soc_component_write(component,
 410                 (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
 411                 ((band_idx * BAND_MAX + coeff_idx)
 412                 * sizeof(uint32_t) + 3) & 0x7F);
 413
 414         /* Mask bits top 2 bits since they are reserved */
 415         value |= ((snd_soc_component_read(component,
 416                  (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx)) & 0x3f) << 24);
 417         return value;
 418
 419 }
 420
 421 static int msm8x16_wcd_get_iir_band_audio_mixer(
 422                                         struct snd_kcontrol *kcontrol,
 423                                         struct snd_ctl_elem_value *ucontrol)
 424 {
 425
 426         struct snd_soc_component *component =
 427                         snd_soc_kcontrol_component(kcontrol);
 428         struct wcd_iir_filter_ctl *ctl =
 429                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
 430         struct soc_bytes_ext *params = &ctl->bytes_ext;
 431         int iir_idx = ctl->iir_idx;
 432         int band_idx = ctl->band_idx;
 433         u32 coeff[BAND_MAX];
 434
 435         coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
 436         coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
 437         coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
 438         coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
 439         coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
 440
 441         memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
 442
 443         return 0;
 444 }
 445
 446 static void set_iir_band_coeff(struct snd_soc_component *component,
 447                                 int iir_idx, int band_idx,
 448                                 uint32_t value)
 449 {
 450         snd_soc_component_write(component,
 451                 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
 452                 (value & 0xFF));
 453
 454         snd_soc_component_write(component,
 455                 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
 456                 (value >> 8) & 0xFF);
 457
 458         snd_soc_component_write(component,
 459                 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
 460                 (value >> 16) & 0xFF);
 461
 462         /* Mask top 2 bits, 7-8 are reserved */
 463         snd_soc_component_write(component,
 464                 (LPASS_CDC_IIR1_COEF_B2_CTL + 64 * iir_idx),
 465                 (value >> 24) & 0x3F);
 466 }
 467
 468 static int msm8x16_wcd_put_iir_band_audio_mixer(
 469                                         struct snd_kcontrol *kcontrol,
 470                                         struct snd_ctl_elem_value *ucontrol)
 471 {
 472         struct snd_soc_component *component =
 473                         snd_soc_kcontrol_component(kcontrol);
 474         struct wcd_iir_filter_ctl *ctl =
 475                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
 476         struct soc_bytes_ext *params = &ctl->bytes_ext;
 477         int iir_idx = ctl->iir_idx;
 478         int band_idx = ctl->band_idx;
 479         u32 coeff[BAND_MAX];
 480
 481         memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
 482
 483         /* Mask top bit it is reserved */
 484         /* Updates addr automatically for each B2 write */
 485         snd_soc_component_write(component,
 486                 (LPASS_CDC_IIR1_COEF_B1_CTL + 64 * iir_idx),
 487                 (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F);
 488
 489         set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
 490         set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
 491         set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
 492         set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
 493         set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
 494
 495         return 0;
 496 }
 497
 498 static int wcd_iir_filter_info(struct snd_kcontrol *kcontrol,
 499                                 struct snd_ctl_elem_info *ucontrol)
 500 {
 501         struct wcd_iir_filter_ctl *ctl =
 502                 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
 503         struct soc_bytes_ext *params = &ctl->bytes_ext;
 504
 505         ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 506         ucontrol->count = params->max;
 507
 508         return 0;
 509 }
 510
 511 static const struct snd_kcontrol_new msm8916_wcd_digital_snd_controls[] = {
 512         SOC_SINGLE_S8_TLV("RX1 Digital Volume", LPASS_CDC_RX1_VOL_CTL_B2_CTL,
 513                           -128, 127, digital_gain),
 514         SOC_SINGLE_S8_TLV("RX2 Digital Volume", LPASS_CDC_RX2_VOL_CTL_B2_CTL,
 515                           -128, 127, digital_gain),
 516         SOC_SINGLE_S8_TLV("RX3 Digital Volume", LPASS_CDC_RX3_VOL_CTL_B2_CTL,
 517                           -128, 127, digital_gain),
 518         SOC_SINGLE_S8_TLV("TX1 Digital Volume", LPASS_CDC_TX1_VOL_CTL_GAIN,
 519                           -128, 127, digital_gain),
 520         SOC_SINGLE_S8_TLV("TX2 Digital Volume", LPASS_CDC_TX2_VOL_CTL_GAIN,
 521                           -128, 127, digital_gain),
 522         SOC_ENUM("TX1 HPF Cutoff", tx1_hpf_cutoff_enum),
 523         SOC_ENUM("TX2 HPF Cutoff", tx2_hpf_cutoff_enum),
 524         SOC_SINGLE("TX1 HPF Switch", LPASS_CDC_TX1_MUX_CTL, 3, 1, 0),
 525         SOC_SINGLE("TX2 HPF Switch", LPASS_CDC_TX2_MUX_CTL, 3, 1, 0),
 526         SOC_ENUM("RX1 DCB Cutoff", rx1_dcb_cutoff_enum),
 527         SOC_ENUM("RX2 DCB Cutoff", rx2_dcb_cutoff_enum),
 528         SOC_ENUM("RX3 DCB Cutoff", rx3_dcb_cutoff_enum),
 529         SOC_SINGLE("RX1 DCB Switch", LPASS_CDC_RX1_B5_CTL, 2, 1, 0),
 530         SOC_SINGLE("RX2 DCB Switch", LPASS_CDC_RX2_B5_CTL, 2, 1, 0),
 531         SOC_SINGLE("RX3 DCB Switch", LPASS_CDC_RX3_B5_CTL, 2, 1, 0),
 532         SOC_SINGLE("RX1 Mute Switch", LPASS_CDC_RX1_B6_CTL, 0, 1, 0),
 533         SOC_SINGLE("RX2 Mute Switch", LPASS_CDC_RX2_B6_CTL, 0, 1, 0),
 534         SOC_SINGLE("RX3 Mute Switch", LPASS_CDC_RX3_B6_CTL, 0, 1, 0),
 535
 536         SOC_SINGLE("IIR1 Band1 Switch", LPASS_CDC_IIR1_CTL, 0, 1, 0),
 537         SOC_SINGLE("IIR1 Band2 Switch", LPASS_CDC_IIR1_CTL, 1, 1, 0),
 538         SOC_SINGLE("IIR1 Band3 Switch", LPASS_CDC_IIR1_CTL, 2, 1, 0),
 539         SOC_SINGLE("IIR1 Band4 Switch", LPASS_CDC_IIR1_CTL, 3, 1, 0),
 540         SOC_SINGLE("IIR1 Band5 Switch", LPASS_CDC_IIR1_CTL, 4, 1, 0),
 541         SOC_SINGLE("IIR2 Band1 Switch", LPASS_CDC_IIR2_CTL, 0, 1, 0),
 542         SOC_SINGLE("IIR2 Band2 Switch", LPASS_CDC_IIR2_CTL, 1, 1, 0),
 543         SOC_SINGLE("IIR2 Band3 Switch", LPASS_CDC_IIR2_CTL, 2, 1, 0),
 544         SOC_SINGLE("IIR2 Band4 Switch", LPASS_CDC_IIR2_CTL, 3, 1, 0),
 545         SOC_SINGLE("IIR2 Band5 Switch", LPASS_CDC_IIR2_CTL, 4, 1, 0),
 546         WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
 547         WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
 548         WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
 549         WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
 550         WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
 551         WCD_IIR_FILTER_CTL("IIR2 Band1", IIR2, BAND1),
 552         WCD_IIR_FILTER_CTL("IIR2 Band2", IIR2, BAND2),
 553         WCD_IIR_FILTER_CTL("IIR2 Band3", IIR2, BAND3),
 554         WCD_IIR_FILTER_CTL("IIR2 Band4", IIR2, BAND4),
 555         WCD_IIR_FILTER_CTL("IIR2 Band5", IIR2, BAND5),
 556         SOC_SINGLE_SX_TLV("IIR1 INP1 Volume", LPASS_CDC_IIR1_GAIN_B1_CTL,
 557                         0,  -84, 40, digital_gain),
 558         SOC_SINGLE_SX_TLV("IIR1 INP2 Volume", LPASS_CDC_IIR1_GAIN_B2_CTL,
 559                         0,  -84, 40, digital_gain),
 560         SOC_SINGLE_SX_TLV("IIR1 INP3 Volume", LPASS_CDC_IIR1_GAIN_B3_CTL,
 561                         0,  -84, 40, digital_gain),
 562         SOC_SINGLE_SX_TLV("IIR1 INP4 Volume", LPASS_CDC_IIR1_GAIN_B4_CTL,
 563                         0,  -84,        40, digital_gain),
 564         SOC_SINGLE_SX_TLV("IIR2 INP1 Volume", LPASS_CDC_IIR2_GAIN_B1_CTL,
 565                         0,  -84, 40, digital_gain),
 566         SOC_SINGLE_SX_TLV("IIR2 INP2 Volume", LPASS_CDC_IIR2_GAIN_B2_CTL,
 567                         0,  -84, 40, digital_gain),
 568         SOC_SINGLE_SX_TLV("IIR2 INP3 Volume", LPASS_CDC_IIR2_GAIN_B3_CTL,
 569                         0,  -84, 40, digital_gain),
 570         SOC_SINGLE_SX_TLV("IIR2 INP4 Volume", LPASS_CDC_IIR2_GAIN_B4_CTL,
 571                         0,  -84, 40, digital_gain),
 572
 573 };
 574
 575 static int msm8916_wcd_digital_enable_interpolator(
 576                                                 struct snd_soc_dapm_widget *w,
 577                                                 struct snd_kcontrol *kcontrol,
 578                                                 int event)
 579 {
 580         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 581
 582         switch (event) {
 583         case SND_SOC_DAPM_POST_PMU:
 584                 /* apply the digital gain after the interpolator is enabled */
 585                 usleep_range(10000, 10100);
 586                 snd_soc_component_write(component, rx_gain_reg[w->shift],
 587                               snd_soc_component_read(component, rx_gain_reg[w->shift]));
 588                 break;
 589         case SND_SOC_DAPM_POST_PMD:
 590                 snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL,
 591                                               1 << w->shift, 1 << w->shift);
 592                 snd_soc_component_update_bits(component, LPASS_CDC_CLK_RX_RESET_CTL,
 593                                               1 << w->shift, 0x0);
 594                 break;
 595         }
 596         return 0;
 597 }
 598
 599 static int msm8916_wcd_digital_enable_dec(struct snd_soc_dapm_widget *w,
 600                                           struct snd_kcontrol *kcontrol,
 601                                           int event)
 602 {
 603         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 604         unsigned int decimator = w->shift + 1;
 605         u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg;
 606         u8 dec_hpf_cut_of_freq;
 607
 608         dec_reset_reg = LPASS_CDC_CLK_TX_RESET_B1_CTL;
 609         tx_vol_ctl_reg = LPASS_CDC_TX1_VOL_CTL_CFG + 32 * (decimator - 1);
 610         tx_mux_ctl_reg = LPASS_CDC_TX1_MUX_CTL + 32 * (decimator - 1);
 611
 612         switch (event) {
 613         case SND_SOC_DAPM_PRE_PMU:
 614                 /* Enable TX digital mute */
 615                 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
 616                                     TX_VOL_CTL_CFG_MUTE_EN_MASK,
 617                                     TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
 618                 dec_hpf_cut_of_freq = snd_soc_component_read(component, tx_mux_ctl_reg) &
 619                                         TX_MUX_CTL_CUT_OFF_FREQ_MASK;
 620                 dec_hpf_cut_of_freq >>= TX_MUX_CTL_CUT_OFF_FREQ_SHIFT;
 621                 if (dec_hpf_cut_of_freq != TX_MUX_CTL_CF_NEG_3DB_150HZ) {
 622                         /* set cut of freq to CF_MIN_3DB_150HZ (0x1) */
 623                         snd_soc_component_update_bits(component, tx_mux_ctl_reg,
 624                                             TX_MUX_CTL_CUT_OFF_FREQ_MASK,
 625                                             TX_MUX_CTL_CF_NEG_3DB_150HZ);
 626                 }
 627                 break;
 628         case SND_SOC_DAPM_POST_PMU:
 629                 /* enable HPF */
 630                 snd_soc_component_update_bits(component, tx_mux_ctl_reg,
 631                                     TX_MUX_CTL_HPF_BP_SEL_MASK,
 632                                     TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS);
 633                 /* apply the digital gain after the decimator is enabled */
 634                 snd_soc_component_write(component, tx_gain_reg[w->shift],
 635                               snd_soc_component_read(component, tx_gain_reg[w->shift]));
 636                 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
 637                                     TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
 638                 break;
 639         case SND_SOC_DAPM_PRE_PMD:
 640                 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
 641                                     TX_VOL_CTL_CFG_MUTE_EN_MASK,
 642                                     TX_VOL_CTL_CFG_MUTE_EN_ENABLE);
 643                 snd_soc_component_update_bits(component, tx_mux_ctl_reg,
 644                                     TX_MUX_CTL_HPF_BP_SEL_MASK,
 645                                     TX_MUX_CTL_HPF_BP_SEL_BYPASS);
 646                 break;
 647         case SND_SOC_DAPM_POST_PMD:
 648                 snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift,
 649                                     1 << w->shift);
 650                 snd_soc_component_update_bits(component, dec_reset_reg, 1 << w->shift, 0x0);
 651                 snd_soc_component_update_bits(component, tx_mux_ctl_reg,
 652                                     TX_MUX_CTL_HPF_BP_SEL_MASK,
 653                                     TX_MUX_CTL_HPF_BP_SEL_BYPASS);
 654                 snd_soc_component_update_bits(component, tx_vol_ctl_reg,
 655                                     TX_VOL_CTL_CFG_MUTE_EN_MASK, 0);
 656                 break;
 657         }
 658
 659         return 0;
 660 }
 661
 662 static int msm8916_wcd_digital_enable_dmic(struct snd_soc_dapm_widget *w,
 663                                            struct snd_kcontrol *kcontrol,
 664                                            int event)
 665 {
 666         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 667         unsigned int dmic;
 668         int ret;
 669         /* get dmic number out of widget name */
 670         char *dmic_num = strpbrk(w->name, "12");
 671
 672         if (dmic_num == NULL) {
 673                 dev_err(component->dev, "Invalid DMIC\n");
 674                 return -EINVAL;
 675         }
 676         ret = kstrtouint(dmic_num, 10, &dmic);
 677         if (ret < 0 || dmic > 2) {
 678                 dev_err(component->dev, "Invalid DMIC line on the component\n");
 679                 return -EINVAL;
 680         }
 681
 682         switch (event) {
 683         case SND_SOC_DAPM_PRE_PMU:
 684                 snd_soc_component_update_bits(component, LPASS_CDC_CLK_DMIC_B1_CTL,
 685                                     DMIC_B1_CTL_DMIC0_CLK_SEL_MASK,
 686                                     DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3);
 687                 switch (dmic) {
 688                 case 1:
 689                         snd_soc_component_update_bits(component, LPASS_CDC_TX1_DMIC_CTL,
 690                                             TXN_DMIC_CTL_CLK_SEL_MASK,
 691                                             TXN_DMIC_CTL_CLK_SEL_DIV3);
 692                         break;
 693                 case 2:
 694                         snd_soc_component_update_bits(component, LPASS_CDC_TX2_DMIC_CTL,
 695                                             TXN_DMIC_CTL_CLK_SEL_MASK,
 696                                             TXN_DMIC_CTL_CLK_SEL_DIV3);
 697                         break;
 698                 }
 699                 break;
 700         }
 701
 702         return 0;
 703 }
 704
 705 static const char * const iir_inp1_text[] = {
 706         "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3"
 707 };
 708
 709 static const struct soc_enum iir1_inp1_mux_enum =
 710         SOC_ENUM_SINGLE(LPASS_CDC_CONN_EQ1_B1_CTL,
 711                 0, 6, iir_inp1_text);
 712
 713 static const struct soc_enum iir2_inp1_mux_enum =
 714         SOC_ENUM_SINGLE(LPASS_CDC_CONN_EQ2_B1_CTL,
 715                 0, 6, iir_inp1_text);
 716
 717 static const struct snd_kcontrol_new iir1_inp1_mux =
 718         SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
 719
 720 static const struct snd_kcontrol_new iir2_inp1_mux =
 721         SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum);
 722
 723 static const struct snd_soc_dapm_widget msm8916_wcd_digital_dapm_widgets[] = {
 724         /*RX stuff */
 725         SND_SOC_DAPM_AIF_IN("I2S RX1", NULL, 0, SND_SOC_NOPM, 0, 0),
 726         SND_SOC_DAPM_AIF_IN("I2S RX2", NULL, 0, SND_SOC_NOPM, 0, 0),
 727         SND_SOC_DAPM_AIF_IN("I2S RX3", NULL, 0, SND_SOC_NOPM, 0, 0),
 728
 729         SND_SOC_DAPM_OUTPUT("PDM_RX1"),
 730         SND_SOC_DAPM_OUTPUT("PDM_RX2"),
 731         SND_SOC_DAPM_OUTPUT("PDM_RX3"),
 732
 733         SND_SOC_DAPM_INPUT("LPASS_PDM_TX"),
 734
 735         SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
 736         SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
 737         SND_SOC_DAPM_MIXER("RX3 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
 738
 739         /* Interpolator */
 740         SND_SOC_DAPM_MIXER_E("RX1 INT", LPASS_CDC_CLK_RX_B1_CTL, 0, 0, NULL,
 741                              0, msm8916_wcd_digital_enable_interpolator,
 742                              SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 743         SND_SOC_DAPM_MIXER_E("RX2 INT", LPASS_CDC_CLK_RX_B1_CTL, 1, 0, NULL,
 744                              0, msm8916_wcd_digital_enable_interpolator,
 745                              SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 746         SND_SOC_DAPM_MIXER_E("RX3 INT", LPASS_CDC_CLK_RX_B1_CTL, 2, 0, NULL,
 747                              0, msm8916_wcd_digital_enable_interpolator,
 748                              SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 749         SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
 750                          &rx_mix1_inp1_mux),
 751         SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
 752                          &rx_mix1_inp2_mux),
 753         SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0,
 754                          &rx_mix1_inp3_mux),
 755         SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0,
 756                          &rx2_mix1_inp1_mux),
 757         SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0,
 758                          &rx2_mix1_inp2_mux),
 759         SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0,
 760                          &rx2_mix1_inp3_mux),
 761         SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0,
 762                          &rx3_mix1_inp1_mux),
 763         SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0,
 764                          &rx3_mix1_inp2_mux),
 765         SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0,
 766                          &rx3_mix1_inp3_mux),
 767         SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0,
 768                          &rx1_mix2_inp1_mux),
 769         SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0,
 770                          &rx2_mix2_inp1_mux),
 771
 772         SND_SOC_DAPM_MUX("CIC1 MUX", SND_SOC_NOPM, 0, 0, &cic1_mux),
 773         SND_SOC_DAPM_MUX("CIC2 MUX", SND_SOC_NOPM, 0, 0, &cic2_mux),
 774         /* TX */
 775         SND_SOC_DAPM_MIXER("ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 776         SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 777         SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
 778
 779         SND_SOC_DAPM_MUX_E("DEC1 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0,
 780                            &dec1_mux, msm8916_wcd_digital_enable_dec,
 781                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 782                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 783         SND_SOC_DAPM_MUX_E("DEC2 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0,
 784                            &dec2_mux, msm8916_wcd_digital_enable_dec,
 785                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
 786                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
 787         SND_SOC_DAPM_AIF_OUT("I2S TX1", NULL, 0, SND_SOC_NOPM, 0, 0),
 788         SND_SOC_DAPM_AIF_OUT("I2S TX2", NULL, 0, SND_SOC_NOPM, 0, 0),
 789         SND_SOC_DAPM_AIF_OUT("I2S TX3", NULL, 0, SND_SOC_NOPM, 0, 0),
 790
 791         /* Digital Mic Inputs */
 792         SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
 793                            msm8916_wcd_digital_enable_dmic,
 794                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 795         SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
 796                            msm8916_wcd_digital_enable_dmic,
 797                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
 798         SND_SOC_DAPM_SUPPLY("DMIC_CLK", LPASS_CDC_CLK_DMIC_B1_CTL, 0, 0,
 799                             NULL, 0),
 800         SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", LPASS_CDC_CLK_RX_I2S_CTL,
 801                             4, 0, NULL, 0),
 802         SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", LPASS_CDC_CLK_TX_I2S_CTL, 4, 0,
 803                             NULL, 0),
 804
 805         SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
 806         SND_SOC_DAPM_SUPPLY("PDM_CLK", LPASS_CDC_CLK_PDM_CTL, 0, 0, NULL, 0),
 807         /* Connectivity Clock */
 808         SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, LPASS_CDC_CLK_OTHR_CTL, 2, 0,
 809                               NULL, 0),
 810         SND_SOC_DAPM_MIC("Digital Mic1", NULL),
 811         SND_SOC_DAPM_MIC("Digital Mic2", NULL),
 812
 813         /* Sidetone */
 814         SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
 815         SND_SOC_DAPM_PGA_E("IIR1", LPASS_CDC_CLK_SD_CTL, 0, 0, NULL, 0,
 816                 msm8x16_wcd_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU),
 817
 818         SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux),
 819         SND_SOC_DAPM_PGA_E("IIR2", LPASS_CDC_CLK_SD_CTL, 1, 0, NULL, 0,
 820                 msm8x16_wcd_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU),
 821
 822 };
 823
 824 static int msm8916_wcd_digital_get_clks(struct platform_device *pdev,
 825                                         struct msm8916_wcd_digital_priv *priv)
 826 {
 827         struct device *dev = &pdev->dev;
 828
 829         priv->ahbclk = devm_clk_get(dev, "ahbix-clk");
 830         if (IS_ERR(priv->ahbclk)) {
 831                 dev_err(dev, "failed to get ahbix clk\n");
 832                 return PTR_ERR(priv->ahbclk);
 833         }
 834
 835         priv->mclk = devm_clk_get(dev, "mclk");
 836         if (IS_ERR(priv->mclk)) {
 837                 dev_err(dev, "failed to get mclk\n");
 838                 return PTR_ERR(priv->mclk);
 839         }
 840
 841         return 0;
 842 }
 843
 844 static int msm8916_wcd_digital_component_probe(struct snd_soc_component *component)
 845 {
 846         struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(component->dev);
 847
 848         snd_soc_component_set_drvdata(component, priv);
 849
 850         return 0;
 851 }
 852
 853 static int msm8916_wcd_digital_component_set_sysclk(struct snd_soc_component *component,
 854                                                 int clk_id, int source,
 855                                                 unsigned int freq, int dir)
 856 {
 857         struct msm8916_wcd_digital_priv *p = dev_get_drvdata(component->dev);
 858
 859         return clk_set_rate(p->mclk, freq);
 860 }
 861
 862 static int msm8916_wcd_digital_hw_params(struct snd_pcm_substream *substream,
 863                                          struct snd_pcm_hw_params *params,
 864                                          struct snd_soc_dai *dai)
 865 {
 866         u8 tx_fs_rate;
 867         u8 rx_fs_rate;
 868
 869         switch (params_rate(params)) {
 870         case 8000:
 871                 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ;
 872                 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ;
 873                 break;
 874         case 16000:
 875                 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ;
 876                 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ;
 877                 break;
 878         case 32000:
 879                 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ;
 880                 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ;
 881                 break;
 882         case 48000:
 883                 tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ;
 884                 rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ;
 885                 break;
 886         default:
 887                 dev_err(dai->component->dev, "Invalid sampling rate %d\n",
 888                         params_rate(params));
 889                 return -EINVAL;
 890         }
 891
 892         switch (substream->stream) {
 893         case SNDRV_PCM_STREAM_CAPTURE:
 894                 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
 895                                     TX_I2S_CTL_TX_I2S_FS_RATE_MASK, tx_fs_rate);
 896                 break;
 897         case SNDRV_PCM_STREAM_PLAYBACK:
 898                 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
 899                                     RX_I2S_CTL_RX_I2S_FS_RATE_MASK, rx_fs_rate);
 900                 break;
 901         default:
 902                 return -EINVAL;
 903         }
 904
 905         switch (params_format(params)) {
 906         case SNDRV_PCM_FORMAT_S16_LE:
 907                 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
 908                                     TX_I2S_CTL_TX_I2S_MODE_MASK,
 909                                     TX_I2S_CTL_TX_I2S_MODE_16);
 910                 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
 911                                     RX_I2S_CTL_RX_I2S_MODE_MASK,
 912                                     RX_I2S_CTL_RX_I2S_MODE_16);
 913                 break;
 914
 915         case SNDRV_PCM_FORMAT_S32_LE:
 916                 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_TX_I2S_CTL,
 917                                     TX_I2S_CTL_TX_I2S_MODE_MASK,
 918                                     TX_I2S_CTL_TX_I2S_MODE_32);
 919                 snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_RX_I2S_CTL,
 920                                     RX_I2S_CTL_RX_I2S_MODE_MASK,
 921                                     RX_I2S_CTL_RX_I2S_MODE_32);
 922                 break;
 923         default:
 924                 dev_err(dai->dev, "%s: wrong format selected\n", __func__);
 925                 return -EINVAL;
 926         }
 927
 928         return 0;
 929 }
 930
 931 static const struct snd_soc_dapm_route msm8916_wcd_digital_audio_map[] = {
 932
 933         {"I2S RX1",  NULL, "AIF1 Playback"},
 934         {"I2S RX2",  NULL, "AIF1 Playback"},
 935         {"I2S RX3",  NULL, "AIF1 Playback"},
 936
 937         {"AIF1 Capture", NULL, "I2S TX1"},
 938         {"AIF1 Capture", NULL, "I2S TX2"},
 939         {"AIF1 Capture", NULL, "I2S TX3"},
 940
 941         {"CIC1 MUX", "DMIC", "DEC1 MUX"},
 942         {"CIC1 MUX", "AMIC", "DEC1 MUX"},
 943         {"CIC2 MUX", "DMIC", "DEC2 MUX"},
 944         {"CIC2 MUX", "AMIC", "DEC2 MUX"},
 945
 946         /* Decimator Inputs */
 947         {"DEC1 MUX", "DMIC1", "DMIC1"},
 948         {"DEC1 MUX", "DMIC2", "DMIC2"},
 949         {"DEC1 MUX", "ADC1", "ADC1"},
 950         {"DEC1 MUX", "ADC2", "ADC2"},
 951         {"DEC1 MUX", "ADC3", "ADC3"},
 952         {"DEC1 MUX", NULL, "CDC_CONN"},
 953
 954         {"DEC2 MUX", "DMIC1", "DMIC1"},
 955         {"DEC2 MUX", "DMIC2", "DMIC2"},
 956         {"DEC2 MUX", "ADC1", "ADC1"},
 957         {"DEC2 MUX", "ADC2", "ADC2"},
 958         {"DEC2 MUX", "ADC3", "ADC3"},
 959         {"DEC2 MUX", NULL, "CDC_CONN"},
 960
 961         {"DMIC1", NULL, "DMIC_CLK"},
 962         {"DMIC2", NULL, "DMIC_CLK"},
 963
 964         {"I2S TX1", NULL, "CIC1 MUX"},
 965         {"I2S TX2", NULL, "CIC2 MUX"},
 966
 967         {"I2S TX1", NULL, "TX_I2S_CLK"},
 968         {"I2S TX2", NULL, "TX_I2S_CLK"},
 969
 970         {"TX_I2S_CLK", NULL, "MCLK"},
 971         {"TX_I2S_CLK", NULL, "PDM_CLK"},
 972
 973         {"ADC1", NULL, "LPASS_PDM_TX"},
 974         {"ADC2", NULL, "LPASS_PDM_TX"},
 975         {"ADC3", NULL, "LPASS_PDM_TX"},
 976
 977         {"I2S RX1", NULL, "RX_I2S_CLK"},
 978         {"I2S RX2", NULL, "RX_I2S_CLK"},
 979         {"I2S RX3", NULL, "RX_I2S_CLK"},
 980
 981         {"RX_I2S_CLK", NULL, "PDM_CLK"},
 982         {"RX_I2S_CLK", NULL, "MCLK"},
 983         {"RX_I2S_CLK", NULL, "CDC_CONN"},
 984
 985         /* RX1 PATH.. */
 986         {"PDM_RX1", NULL, "RX1 INT"},
 987         {"RX1 INT", NULL, "RX1 MIX1"},
 988
 989         {"RX1 MIX1", NULL, "RX1 MIX1 INP1"},
 990         {"RX1 MIX1", NULL, "RX1 MIX1 INP2"},
 991         {"RX1 MIX1", NULL, "RX1 MIX1 INP3"},
 992
 993         {"RX1 MIX1 INP1", "RX1", "I2S RX1"},
 994         {"RX1 MIX1 INP1", "RX2", "I2S RX2"},
 995         {"RX1 MIX1 INP1", "RX3", "I2S RX3"},
 996         {"RX1 MIX1 INP1", "IIR1", "IIR1"},
 997         {"RX1 MIX1 INP1", "IIR2", "IIR2"},
 998
 999         {"RX1 MIX1 INP2", "RX1", "I2S RX1"},
1000         {"RX1 MIX1 INP2", "RX2", "I2S RX2"},
1001         {"RX1 MIX1 INP2", "RX3", "I2S RX3"},
1002         {"RX1 MIX1 INP2", "IIR1", "IIR1"},
1003         {"RX1 MIX1 INP2", "IIR2", "IIR2"},
1004
1005         {"RX1 MIX1 INP3", "RX1", "I2S RX1"},
1006         {"RX1 MIX1 INP3", "RX2", "I2S RX2"},
1007         {"RX1 MIX1 INP3", "RX3", "I2S RX3"},
1008
1009         /* RX2 PATH */
1010         {"PDM_RX2", NULL, "RX2 INT"},
1011         {"RX2 INT", NULL, "RX2 MIX1"},
1012
1013         {"RX2 MIX1", NULL, "RX2 MIX1 INP1"},
1014         {"RX2 MIX1", NULL, "RX2 MIX1 INP2"},
1015         {"RX2 MIX1", NULL, "RX2 MIX1 INP3"},
1016
1017         {"RX2 MIX1 INP1", "RX1", "I2S RX1"},
1018         {"RX2 MIX1 INP1", "RX2", "I2S RX2"},
1019         {"RX2 MIX1 INP1", "RX3", "I2S RX3"},
1020         {"RX2 MIX1 INP1", "IIR1", "IIR1"},
1021         {"RX2 MIX1 INP1", "IIR2", "IIR2"},
1022
1023         {"RX2 MIX1 INP2", "RX1", "I2S RX1"},
1024         {"RX2 MIX1 INP2", "RX2", "I2S RX2"},
1025         {"RX2 MIX1 INP2", "RX3", "I2S RX3"},
1026         {"RX2 MIX1 INP1", "IIR1", "IIR1"},
1027         {"RX2 MIX1 INP1", "IIR2", "IIR2"},
1028
1029         {"RX2 MIX1 INP3", "RX1", "I2S RX1"},
1030         {"RX2 MIX1 INP3", "RX2", "I2S RX2"},
1031         {"RX2 MIX1 INP3", "RX3", "I2S RX3"},
1032
1033         /* RX3 PATH */
1034         {"PDM_RX3", NULL, "RX3 INT"},
1035         {"RX3 INT", NULL, "RX3 MIX1"},
1036
1037         {"RX3 MIX1", NULL, "RX3 MIX1 INP1"},
1038         {"RX3 MIX1", NULL, "RX3 MIX1 INP2"},
1039         {"RX3 MIX1", NULL, "RX3 MIX1 INP3"},
1040
1041         {"RX3 MIX1 INP1", "RX1", "I2S RX1"},
1042         {"RX3 MIX1 INP1", "RX2", "I2S RX2"},
1043         {"RX3 MIX1 INP1", "RX3", "I2S RX3"},
1044         {"RX3 MIX1 INP1", "IIR1", "IIR1"},
1045         {"RX3 MIX1 INP1", "IIR2", "IIR2"},
1046
1047         {"RX3 MIX1 INP2", "RX1", "I2S RX1"},
1048         {"RX3 MIX1 INP2", "RX2", "I2S RX2"},
1049         {"RX3 MIX1 INP2", "RX3", "I2S RX3"},
1050         {"RX3 MIX1 INP2", "IIR1", "IIR1"},
1051         {"RX3 MIX1 INP2", "IIR2", "IIR2"},
1052
1053         {"RX1 MIX2 INP1", "IIR1", "IIR1"},
1054         {"RX2 MIX2 INP1", "IIR1", "IIR1"},
1055         {"RX1 MIX2 INP1", "IIR2", "IIR2"},
1056         {"RX2 MIX2 INP1", "IIR2", "IIR2"},
1057
1058         {"IIR1", NULL, "IIR1 INP1 MUX"},
1059         {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"},
1060         {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"},
1061
1062         {"IIR2", NULL, "IIR2 INP1 MUX"},
1063         {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"},
1064         {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"},
1065
1066         {"RX3 MIX1 INP3", "RX1", "I2S RX1"},
1067         {"RX3 MIX1 INP3", "RX2", "I2S RX2"},
1068         {"RX3 MIX1 INP3", "RX3", "I2S RX3"},
1069
1070 };
1071
1072 static int msm8916_wcd_digital_startup(struct snd_pcm_substream *substream,
1073                                        struct snd_soc_dai *dai)
1074 {
1075         struct snd_soc_component *component = dai->component;
1076         struct msm8916_wcd_digital_priv *msm8916_wcd;
1077         unsigned long mclk_rate;
1078
1079         msm8916_wcd = snd_soc_component_get_drvdata(component);
1080         snd_soc_component_update_bits(component, LPASS_CDC_CLK_MCLK_CTL,
1081                             MCLK_CTL_MCLK_EN_MASK,
1082                             MCLK_CTL_MCLK_EN_ENABLE);
1083         snd_soc_component_update_bits(component, LPASS_CDC_CLK_PDM_CTL,
1084                             LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK,
1085                             LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB);
1086
1087         mclk_rate = clk_get_rate(msm8916_wcd->mclk);
1088         switch (mclk_rate) {
1089         case 12288000:
1090                 snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
1091                                     TOP_CTL_DIG_MCLK_FREQ_MASK,
1092                                     TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ);
1093                 break;
1094         case 9600000:
1095                 snd_soc_component_update_bits(component, LPASS_CDC_TOP_CTL,
1096                                     TOP_CTL_DIG_MCLK_FREQ_MASK,
1097                                     TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ);
1098                 break;
1099         default:
1100                 dev_err(component->dev, "Invalid mclk rate %ld\n", mclk_rate);
1101                 break;
1102         }
1103         return 0;
1104 }
1105
1106 static void msm8916_wcd_digital_shutdown(struct snd_pcm_substream *substream,
1107                                          struct snd_soc_dai *dai)
1108 {
1109         snd_soc_component_update_bits(dai->component, LPASS_CDC_CLK_PDM_CTL,
1110                             LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK, 0);
1111 }
1112
1113 static const struct snd_soc_dai_ops msm8916_wcd_digital_dai_ops = {
1114         .startup = msm8916_wcd_digital_startup,
1115         .shutdown = msm8916_wcd_digital_shutdown,
1116         .hw_params = msm8916_wcd_digital_hw_params,
1117 };
1118
1119 static struct snd_soc_dai_driver msm8916_wcd_digital_dai[] = {
1120         [0] = {
1121                .name = "msm8916_wcd_digital_i2s_rx1",
1122                .id = 0,
1123                .playback = {
1124                             .stream_name = "AIF1 Playback",
1125                             .rates = MSM8916_WCD_DIGITAL_RATES,
1126                             .formats = MSM8916_WCD_DIGITAL_FORMATS,
1127                             .channels_min = 1,
1128                             .channels_max = 3,
1129                             },
1130                .ops = &msm8916_wcd_digital_dai_ops,
1131                },
1132         [1] = {
1133                .name = "msm8916_wcd_digital_i2s_tx1",
1134                .id = 1,
1135                .capture = {
1136                            .stream_name = "AIF1 Capture",
1137                            .rates = MSM8916_WCD_DIGITAL_RATES,
1138                            .formats = MSM8916_WCD_DIGITAL_FORMATS,
1139                            .channels_min = 1,
1140                            .channels_max = 4,
1141                            },
1142                .ops = &msm8916_wcd_digital_dai_ops,
1143                },
1144 };
1145
1146 static const struct snd_soc_component_driver msm8916_wcd_digital = {
1147         .probe                  = msm8916_wcd_digital_component_probe,
1148         .set_sysclk             = msm8916_wcd_digital_component_set_sysclk,
1149         .controls               = msm8916_wcd_digital_snd_controls,
1150         .num_controls           = ARRAY_SIZE(msm8916_wcd_digital_snd_controls),
1151         .dapm_widgets           = msm8916_wcd_digital_dapm_widgets,
1152         .num_dapm_widgets       = ARRAY_SIZE(msm8916_wcd_digital_dapm_widgets),
1153         .dapm_routes            = msm8916_wcd_digital_audio_map,
1154         .num_dapm_routes        = ARRAY_SIZE(msm8916_wcd_digital_audio_map),
1155         .idle_bias_on           = 1,
1156         .use_pmdown_time        = 1,
1157         .endianness             = 1,
1158         .non_legacy_dai_naming  = 1,
1159 };
1160
1161 static const struct regmap_config msm8916_codec_regmap_config = {
1162         .reg_bits = 32,
1163         .reg_stride = 4,
1164         .val_bits = 32,
1165         .max_register = LPASS_CDC_TX2_DMIC_CTL,
1166         .cache_type = REGCACHE_FLAT,
1167 };
1168
1169 static int msm8916_wcd_digital_probe(struct platform_device *pdev)
1170 {
1171         struct msm8916_wcd_digital_priv *priv;
1172         struct device *dev = &pdev->dev;
1173         void __iomem *base;
1174         struct regmap *digital_map;
1175         int ret;
1176
1177         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1178         if (!priv)
1179                 return -ENOMEM;
1180
1181         base = devm_platform_ioremap_resource(pdev, 0);
1182         if (IS_ERR(base))
1183                 return PTR_ERR(base);
1184
1185         digital_map =
1186             devm_regmap_init_mmio(&pdev->dev, base,
1187                                   &msm8916_codec_regmap_config);
1188         if (IS_ERR(digital_map))
1189                 return PTR_ERR(digital_map);
1190
1191         ret = msm8916_wcd_digital_get_clks(pdev, priv);
1192         if (ret < 0)
1193                 return ret;
1194
1195         ret = clk_prepare_enable(priv->ahbclk);
1196         if (ret < 0) {
1197                 dev_err(dev, "failed to enable ahbclk %d\n", ret);
1198                 return ret;
1199         }
1200
1201         ret = clk_prepare_enable(priv->mclk);
1202         if (ret < 0) {
1203                 dev_err(dev, "failed to enable mclk %d\n", ret);
1204                 return ret;
1205         }
1206
1207         dev_set_drvdata(dev, priv);
1208
1209         return devm_snd_soc_register_component(dev, &msm8916_wcd_digital,
1210                                       msm8916_wcd_digital_dai,
1211                                       ARRAY_SIZE(msm8916_wcd_digital_dai));
1212 }
1213
1214 static int msm8916_wcd_digital_remove(struct platform_device *pdev)
1215 {
1216         struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(&pdev->dev);
1217
1218         clk_disable_unprepare(priv->mclk);
1219         clk_disable_unprepare(priv->ahbclk);
1220
1221         return 0;
1222 }
1223
1224 static const struct of_device_id msm8916_wcd_digital_match_table[] = {
1225         { .compatible = "qcom,msm8916-wcd-digital-codec" },
1226         { }
1227 };
1228
1229 MODULE_DEVICE_TABLE(of, msm8916_wcd_digital_match_table);
1230
1231 static struct platform_driver msm8916_wcd_digital_driver = {
1232         .driver = {
1233                    .name = "msm8916-wcd-digital-codec",
1234                    .of_match_table = msm8916_wcd_digital_match_table,
1235         },
1236         .probe = msm8916_wcd_digital_probe,
1237         .remove = msm8916_wcd_digital_remove,
1238 };
1239
1240 module_platform_driver(msm8916_wcd_digital_driver);
1241
1242 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
1243 MODULE_DESCRIPTION("MSM8916 WCD Digital Codec driver");
1244 MODULE_LICENSE("GPL v2");