1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
6 #include <linux/module.h>
7 #include <linux/moduleparam.h>
8 #include <linux/init.h>
9 #include <linux/delay.h>
11 #include <linux/i2c.h>
12 #include <linux/slab.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <sound/core.h>
16 #include <sound/pcm.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc.h>
19 #include <sound/tlv.h>
22 #define DVOL_CTL_DVMUTE_ON BIT(4) /* Digital volume MUTE On */
23 #define DVOL_CTL_DVMUTE_OFF 0 /* Digital volume MUTE Off */
24 #define ML26124_SAI_NO_DELAY BIT(1)
25 #define ML26124_SAI_FRAME_SYNC (BIT(5) | BIT(0)) /* For mono (Telecodec) */
26 #define ML26134_CACHESIZE 212
27 #define ML26124_VMID BIT(1)
28 #define ML26124_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 |\
30 #define ML26124_FORMATS (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |\
31 SNDRV_PCM_FMTBIT_S32_LE)
32 #define ML26124_NUM_REGISTER ML26134_CACHESIZE
37 struct regmap *regmap;
39 struct snd_pcm_substream *substream;
52 /* ML26124 configuration */
53 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7150, 50, 0);
55 static const DECLARE_TLV_DB_SCALE(alclvl, -2250, 150, 0);
56 static const DECLARE_TLV_DB_SCALE(mingain, -1200, 600, 0);
57 static const DECLARE_TLV_DB_SCALE(maxgain, -675, 600, 0);
58 static const DECLARE_TLV_DB_SCALE(boost_vol, -1200, 75, 0);
59 static const DECLARE_TLV_DB_SCALE(ngth, -7650, 150, 0);
61 static const char * const ml26124_companding[] = {"16bit PCM", "u-law",
64 static SOC_ENUM_SINGLE_DECL(ml26124_adc_companding_enum,
65 ML26124_SAI_TRANS_CTL, 6, ml26124_companding);
67 static SOC_ENUM_SINGLE_DECL(ml26124_dac_companding_enum,
68 ML26124_SAI_RCV_CTL, 6, ml26124_companding);
70 static const struct snd_kcontrol_new ml26124_snd_controls[] = {
71 SOC_SINGLE_TLV("Capture Digital Volume", ML26124_RECORD_DIG_VOL, 0,
72 0xff, 1, digital_tlv),
73 SOC_SINGLE_TLV("Playback Digital Volume", ML26124_PLBAK_DIG_VOL, 0,
74 0xff, 1, digital_tlv),
75 SOC_SINGLE_TLV("Digital Boost Volume", ML26124_DIGI_BOOST_VOL, 0,
77 SOC_SINGLE_TLV("EQ Band0 Volume", ML26124_EQ_GAIN_BRAND0, 0,
78 0xff, 1, digital_tlv),
79 SOC_SINGLE_TLV("EQ Band1 Volume", ML26124_EQ_GAIN_BRAND1, 0,
80 0xff, 1, digital_tlv),
81 SOC_SINGLE_TLV("EQ Band2 Volume", ML26124_EQ_GAIN_BRAND2, 0,
82 0xff, 1, digital_tlv),
83 SOC_SINGLE_TLV("EQ Band3 Volume", ML26124_EQ_GAIN_BRAND3, 0,
84 0xff, 1, digital_tlv),
85 SOC_SINGLE_TLV("EQ Band4 Volume", ML26124_EQ_GAIN_BRAND4, 0,
86 0xff, 1, digital_tlv),
87 SOC_SINGLE_TLV("ALC Target Level", ML26124_ALC_TARGET_LEV, 0,
89 SOC_SINGLE_TLV("ALC Min Input Volume", ML26124_ALC_MAXMIN_GAIN, 0,
91 SOC_SINGLE_TLV("ALC Max Input Volume", ML26124_ALC_MAXMIN_GAIN, 4,
93 SOC_SINGLE_TLV("Playback Limiter Min Input Volume",
94 ML26124_PL_MAXMIN_GAIN, 0, 7, 0, mingain),
95 SOC_SINGLE_TLV("Playback Limiter Max Input Volume",
96 ML26124_PL_MAXMIN_GAIN, 4, 7, 1, maxgain),
97 SOC_SINGLE_TLV("Playback Boost Volume", ML26124_PLYBAK_BOST_VOL, 0,
99 SOC_SINGLE("DC High Pass Filter Switch", ML26124_FILTER_EN, 0, 1, 0),
100 SOC_SINGLE("Noise High Pass Filter Switch", ML26124_FILTER_EN, 1, 1, 0),
101 SOC_SINGLE("ZC Switch", ML26124_PW_ZCCMP_PW_MNG, 1,
103 SOC_SINGLE("EQ Band0 Switch", ML26124_FILTER_EN, 2, 1, 0),
104 SOC_SINGLE("EQ Band1 Switch", ML26124_FILTER_EN, 3, 1, 0),
105 SOC_SINGLE("EQ Band2 Switch", ML26124_FILTER_EN, 4, 1, 0),
106 SOC_SINGLE("EQ Band3 Switch", ML26124_FILTER_EN, 5, 1, 0),
107 SOC_SINGLE("EQ Band4 Switch", ML26124_FILTER_EN, 6, 1, 0),
108 SOC_SINGLE("Play Limiter", ML26124_DVOL_CTL, 0, 1, 0),
109 SOC_SINGLE("Capture Limiter", ML26124_DVOL_CTL, 1, 1, 0),
110 SOC_SINGLE("Digital Volume Fade Switch", ML26124_DVOL_CTL, 3, 1, 0),
111 SOC_SINGLE("Digital Switch", ML26124_DVOL_CTL, 4, 1, 0),
112 SOC_ENUM("DAC Companding", ml26124_dac_companding_enum),
113 SOC_ENUM("ADC Companding", ml26124_adc_companding_enum),
116 static const struct snd_kcontrol_new ml26124_output_mixer_controls[] = {
117 SOC_DAPM_SINGLE("DAC Switch", ML26124_SPK_AMP_OUT, 1, 1, 0),
118 SOC_DAPM_SINGLE("Line in loopback Switch", ML26124_SPK_AMP_OUT, 3, 1,
120 SOC_DAPM_SINGLE("PGA Switch", ML26124_SPK_AMP_OUT, 5, 1, 0),
124 static const char * const ml26124_input_select[] = {"Analog MIC SingleEnded in",
125 "Digital MIC in", "Analog MIC Differential in"};
127 static SOC_ENUM_SINGLE_DECL(ml26124_insel_enum,
128 ML26124_MIC_IF_CTL, 0, ml26124_input_select);
130 static const struct snd_kcontrol_new ml26124_input_mux_controls =
131 SOC_DAPM_ENUM("Input Select", ml26124_insel_enum);
133 static const struct snd_kcontrol_new ml26124_line_control =
134 SOC_DAPM_SINGLE("Switch", ML26124_PW_LOUT_PW_MNG, 1, 1, 0);
136 static const struct snd_soc_dapm_widget ml26124_dapm_widgets[] = {
137 SND_SOC_DAPM_SUPPLY("MCLKEN", ML26124_CLK_EN, 0, 0, NULL, 0),
138 SND_SOC_DAPM_SUPPLY("PLLEN", ML26124_CLK_EN, 1, 0, NULL, 0),
139 SND_SOC_DAPM_SUPPLY("PLLOE", ML26124_CLK_EN, 2, 0, NULL, 0),
140 SND_SOC_DAPM_SUPPLY("MICBIAS", ML26124_PW_REF_PW_MNG, 2, 0, NULL, 0),
141 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
142 &ml26124_output_mixer_controls[0],
143 ARRAY_SIZE(ml26124_output_mixer_controls)),
144 SND_SOC_DAPM_DAC("DAC", "Playback", ML26124_PW_DAC_PW_MNG, 1, 0),
145 SND_SOC_DAPM_ADC("ADC", "Capture", ML26124_PW_IN_PW_MNG, 1, 0),
146 SND_SOC_DAPM_PGA("PGA", ML26124_PW_IN_PW_MNG, 3, 0, NULL, 0),
147 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
148 &ml26124_input_mux_controls),
149 SND_SOC_DAPM_SWITCH("Line Out Enable", SND_SOC_NOPM, 0, 0,
150 &ml26124_line_control),
151 SND_SOC_DAPM_INPUT("MDIN"),
152 SND_SOC_DAPM_INPUT("MIN"),
153 SND_SOC_DAPM_INPUT("LIN"),
154 SND_SOC_DAPM_OUTPUT("SPOUT"),
155 SND_SOC_DAPM_OUTPUT("LOUT"),
158 static const struct snd_soc_dapm_route ml26124_intercon[] = {
160 {"DAC", NULL, "MCLKEN"},
161 {"ADC", NULL, "MCLKEN"},
162 {"DAC", NULL, "PLLEN"},
163 {"ADC", NULL, "PLLEN"},
164 {"DAC", NULL, "PLLOE"},
165 {"ADC", NULL, "PLLOE"},
168 {"Output Mixer", "DAC Switch", "DAC"},
169 {"Output Mixer", "Line in loopback Switch", "LIN"},
172 {"LOUT", NULL, "Output Mixer"},
173 {"SPOUT", NULL, "Output Mixer"},
174 {"Line Out Enable", NULL, "LOUT"},
177 {"ADC", NULL, "Input Mux"},
178 {"Input Mux", "Analog MIC SingleEnded in", "PGA"},
179 {"Input Mux", "Analog MIC Differential in", "PGA"},
180 {"PGA", NULL, "MIN"},
183 /* PLLOutputFreq(Hz) = InputMclkFreq(Hz) * PLLM / (PLLN * PLLDIV) */
184 static const struct clk_coeff coeff_div[] = {
185 {12288000, 16000, 0xc, 0x0, 0x20, 0x0, 0x4},
186 {12288000, 32000, 0xc, 0x0, 0x20, 0x0, 0x4},
187 {12288000, 48000, 0xc, 0x0, 0x30, 0x0, 0x4},
190 static const struct reg_default ml26124_reg[] = {
191 /* CLOCK control Register */
192 {0x00, 0x00 }, /* Sampling Rate */
193 {0x02, 0x00}, /* PLL NL */
194 {0x04, 0x00}, /* PLLNH */
195 {0x06, 0x00}, /* PLLML */
196 {0x08, 0x00}, /* MLLMH */
197 {0x0a, 0x00}, /* PLLDIV */
198 {0x0c, 0x00}, /* Clock Enable */
199 {0x0e, 0x00}, /* CLK Input/Output Control */
201 /* System Control Register */
202 {0x10, 0x00}, /* Software RESET */
203 {0x12, 0x00}, /* Record/Playback Run */
204 {0x14, 0x00}, /* Mic Input/Output control */
206 /* Power Management Register */
207 {0x20, 0x00}, /* Reference Power Management */
208 {0x22, 0x00}, /* Input Power Management */
209 {0x24, 0x00}, /* DAC Power Management */
210 {0x26, 0x00}, /* SP-AMP Power Management */
211 {0x28, 0x00}, /* LINEOUT Power Management */
212 {0x2a, 0x00}, /* VIDEO Power Management */
213 {0x2e, 0x00}, /* AC-CMP Power Management */
215 /* Analog reference Control Register */
216 {0x30, 0x04}, /* MICBIAS Voltage Control */
218 /* Input/Output Amplifier Control Register */
219 {0x32, 0x10}, /* MIC Input Volume */
220 {0x38, 0x00}, /* Mic Boost Volume */
221 {0x3a, 0x33}, /* Speaker AMP Volume */
222 {0x48, 0x00}, /* AMP Volume Control Function Enable */
223 {0x4a, 0x00}, /* Amplifier Volume Fader Control */
225 /* Analog Path Control Register */
226 {0x54, 0x00}, /* Speaker AMP Output Control */
227 {0x5a, 0x00}, /* Mic IF Control */
228 {0xe8, 0x01}, /* Mic Select Control */
230 /* Audio Interface Control Register */
231 {0x60, 0x00}, /* SAI-Trans Control */
232 {0x62, 0x00}, /* SAI-Receive Control */
233 {0x64, 0x00}, /* SAI Mode select */
235 /* DSP Control Register */
236 {0x66, 0x01}, /* Filter Func Enable */
237 {0x68, 0x00}, /* Volume Control Func Enable */
238 {0x6A, 0x00}, /* Mixer & Volume Control*/
239 {0x6C, 0xff}, /* Record Digital Volume */
240 {0x70, 0xff}, /* Playback Digital Volume */
241 {0x72, 0x10}, /* Digital Boost Volume */
242 {0x74, 0xe7}, /* EQ gain Band0 */
243 {0x76, 0xe7}, /* EQ gain Band1 */
244 {0x78, 0xe7}, /* EQ gain Band2 */
245 {0x7A, 0xe7}, /* EQ gain Band3 */
246 {0x7C, 0xe7}, /* EQ gain Band4 */
247 {0x7E, 0x00}, /* HPF2 CutOff*/
248 {0x80, 0x00}, /* EQ Band0 Coef0L */
249 {0x82, 0x00}, /* EQ Band0 Coef0H */
250 {0x84, 0x00}, /* EQ Band0 Coef0L */
251 {0x86, 0x00}, /* EQ Band0 Coef0H */
252 {0x88, 0x00}, /* EQ Band1 Coef0L */
253 {0x8A, 0x00}, /* EQ Band1 Coef0H */
254 {0x8C, 0x00}, /* EQ Band1 Coef0L */
255 {0x8E, 0x00}, /* EQ Band1 Coef0H */
256 {0x90, 0x00}, /* EQ Band2 Coef0L */
257 {0x92, 0x00}, /* EQ Band2 Coef0H */
258 {0x94, 0x00}, /* EQ Band2 Coef0L */
259 {0x96, 0x00}, /* EQ Band2 Coef0H */
260 {0x98, 0x00}, /* EQ Band3 Coef0L */
261 {0x9A, 0x00}, /* EQ Band3 Coef0H */
262 {0x9C, 0x00}, /* EQ Band3 Coef0L */
263 {0x9E, 0x00}, /* EQ Band3 Coef0H */
264 {0xA0, 0x00}, /* EQ Band4 Coef0L */
265 {0xA2, 0x00}, /* EQ Band4 Coef0H */
266 {0xA4, 0x00}, /* EQ Band4 Coef0L */
267 {0xA6, 0x00}, /* EQ Band4 Coef0H */
269 /* ALC Control Register */
270 {0xb0, 0x00}, /* ALC Mode */
271 {0xb2, 0x02}, /* ALC Attack Time */
272 {0xb4, 0x03}, /* ALC Decay Time */
273 {0xb6, 0x00}, /* ALC Hold Time */
274 {0xb8, 0x0b}, /* ALC Target Level */
275 {0xba, 0x70}, /* ALC Max/Min Gain */
276 {0xbc, 0x00}, /* Noise Gate Threshold */
277 {0xbe, 0x00}, /* ALC ZeroCross TimeOut */
279 /* Playback Limiter Control Register */
280 {0xc0, 0x04}, /* PL Attack Time */
281 {0xc2, 0x05}, /* PL Decay Time */
282 {0xc4, 0x0d}, /* PL Target Level */
283 {0xc6, 0x70}, /* PL Max/Min Gain */
284 {0xc8, 0x10}, /* Playback Boost Volume */
285 {0xca, 0x00}, /* PL ZeroCross TimeOut */
287 /* Video Amplifier Control Register */
288 {0xd0, 0x01}, /* VIDEO AMP Gain Control */
289 {0xd2, 0x01}, /* VIDEO AMP Setup 1 */
290 {0xd4, 0x01}, /* VIDEO AMP Control2 */
293 /* Get sampling rate value of sampling rate setting register (0x0) */
294 static inline int get_srate(int rate)
314 static inline int get_coeff(int mclk, int rate)
318 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
319 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
325 static int ml26124_hw_params(struct snd_pcm_substream *substream,
326 struct snd_pcm_hw_params *hw_params,
327 struct snd_soc_dai *dai)
329 struct snd_soc_component *component = dai->component;
330 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
331 int i = get_coeff(priv->mclk, params_rate(hw_params));
336 priv->substream = substream;
337 priv->rate = params_rate(hw_params);
340 switch (priv->mclk / params_rate(hw_params)) {
342 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
346 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
350 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
354 dev_err(component->dev, "Unsupported MCLKI\n");
358 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
362 srate = get_srate(params_rate(hw_params));
366 snd_soc_component_update_bits(component, ML26124_SMPLING_RATE, 0xf, srate);
367 snd_soc_component_update_bits(component, ML26124_PLLNL, 0xff, coeff_div[i].pllnl);
368 snd_soc_component_update_bits(component, ML26124_PLLNH, 0x1, coeff_div[i].pllnh);
369 snd_soc_component_update_bits(component, ML26124_PLLML, 0xff, coeff_div[i].pllml);
370 snd_soc_component_update_bits(component, ML26124_PLLMH, 0x3f, coeff_div[i].pllmh);
371 snd_soc_component_update_bits(component, ML26124_PLLDIV, 0x1f, coeff_div[i].plldiv);
376 static int ml26124_mute(struct snd_soc_dai *dai, int mute)
378 struct snd_soc_component *component = dai->component;
379 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
381 switch (priv->substream->stream) {
382 case SNDRV_PCM_STREAM_CAPTURE:
383 snd_soc_component_update_bits(component, ML26124_REC_PLYBAK_RUN, BIT(0), 1);
385 case SNDRV_PCM_STREAM_PLAYBACK:
386 snd_soc_component_update_bits(component, ML26124_REC_PLYBAK_RUN, BIT(1), 2);
391 snd_soc_component_update_bits(component, ML26124_DVOL_CTL, BIT(4),
394 snd_soc_component_update_bits(component, ML26124_DVOL_CTL, BIT(4),
395 DVOL_CTL_DVMUTE_OFF);
400 static int ml26124_set_dai_fmt(struct snd_soc_dai *codec_dai,
404 struct snd_soc_component *component = codec_dai->component;
406 /* set master/slave audio interface */
407 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
408 case SND_SOC_DAIFMT_CBM_CFM:
411 case SND_SOC_DAIFMT_CBS_CFS:
417 snd_soc_component_update_bits(component, ML26124_SAI_MODE_SEL, BIT(0), mode);
419 /* interface format */
420 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
421 case SND_SOC_DAIFMT_I2S:
427 /* clock inversion */
428 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
429 case SND_SOC_DAIFMT_NB_NF:
438 static int ml26124_set_dai_sysclk(struct snd_soc_dai *codec_dai,
439 int clk_id, unsigned int freq, int dir)
441 struct snd_soc_component *component = codec_dai->component;
442 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
445 case ML26124_USE_PLLOUT:
446 priv->clk_in = ML26124_USE_PLLOUT;
448 case ML26124_USE_MCLKI:
449 priv->clk_in = ML26124_USE_MCLKI;
460 static int ml26124_set_bias_level(struct snd_soc_component *component,
461 enum snd_soc_bias_level level)
463 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
466 case SND_SOC_BIAS_ON:
467 snd_soc_component_update_bits(component, ML26124_PW_SPAMP_PW_MNG,
468 ML26124_R26_MASK, ML26124_BLT_PREAMP_ON);
470 snd_soc_component_update_bits(component, ML26124_PW_SPAMP_PW_MNG,
472 ML26124_MICBEN_ON | ML26124_BLT_ALL_ON);
474 case SND_SOC_BIAS_PREPARE:
476 case SND_SOC_BIAS_STANDBY:
478 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
479 snd_soc_component_update_bits(component, ML26124_PW_REF_PW_MNG,
480 ML26124_VMID, ML26124_VMID);
482 regcache_sync(priv->regmap);
485 case SND_SOC_BIAS_OFF:
487 snd_soc_component_update_bits(component, ML26124_PW_REF_PW_MNG,
494 static const struct snd_soc_dai_ops ml26124_dai_ops = {
495 .hw_params = ml26124_hw_params,
496 .digital_mute = ml26124_mute,
497 .set_fmt = ml26124_set_dai_fmt,
498 .set_sysclk = ml26124_set_dai_sysclk,
501 static struct snd_soc_dai_driver ml26124_dai = {
502 .name = "ml26124-hifi",
504 .stream_name = "Playback",
507 .rates = ML26124_RATES,
508 .formats = ML26124_FORMATS,},
510 .stream_name = "Capture",
513 .rates = ML26124_RATES,
514 .formats = ML26124_FORMATS,},
515 .ops = &ml26124_dai_ops,
516 .symmetric_rates = 1,
519 static int ml26124_probe(struct snd_soc_component *component)
522 snd_soc_component_update_bits(component, ML26124_SW_RST, 0x01, 1);
523 snd_soc_component_update_bits(component, ML26124_SW_RST, 0x01, 0);
528 static const struct snd_soc_component_driver soc_component_dev_ml26124 = {
529 .probe = ml26124_probe,
530 .set_bias_level = ml26124_set_bias_level,
531 .controls = ml26124_snd_controls,
532 .num_controls = ARRAY_SIZE(ml26124_snd_controls),
533 .dapm_widgets = ml26124_dapm_widgets,
534 .num_dapm_widgets = ARRAY_SIZE(ml26124_dapm_widgets),
535 .dapm_routes = ml26124_intercon,
536 .num_dapm_routes = ARRAY_SIZE(ml26124_intercon),
537 .suspend_bias_off = 1,
539 .use_pmdown_time = 1,
541 .non_legacy_dai_naming = 1,
544 static const struct regmap_config ml26124_i2c_regmap = {
547 .max_register = ML26124_NUM_REGISTER,
548 .reg_defaults = ml26124_reg,
549 .num_reg_defaults = ARRAY_SIZE(ml26124_reg),
550 .cache_type = REGCACHE_RBTREE,
551 .write_flag_mask = 0x01,
554 static int ml26124_i2c_probe(struct i2c_client *i2c,
555 const struct i2c_device_id *id)
557 struct ml26124_priv *priv;
560 priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
564 i2c_set_clientdata(i2c, priv);
566 priv->regmap = devm_regmap_init_i2c(i2c, &ml26124_i2c_regmap);
567 if (IS_ERR(priv->regmap)) {
568 ret = PTR_ERR(priv->regmap);
569 dev_err(&i2c->dev, "regmap_init_i2c() failed: %d\n", ret);
573 return devm_snd_soc_register_component(&i2c->dev,
574 &soc_component_dev_ml26124, &ml26124_dai, 1);
577 static const struct i2c_device_id ml26124_i2c_id[] = {
581 MODULE_DEVICE_TABLE(i2c, ml26124_i2c_id);
583 static struct i2c_driver ml26124_i2c_driver = {
587 .probe = ml26124_i2c_probe,
588 .id_table = ml26124_i2c_id,
591 module_i2c_driver(ml26124_i2c_driver);
593 MODULE_AUTHOR("Tomoya MORINAGA <tomoya.rohm@gmail.com>");
594 MODULE_DESCRIPTION("LAPIS Semiconductor ML26124 ALSA SoC codec driver");
595 MODULE_LICENSE("GPL");