1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2021, Maxim Integrated
4 #include <linux/acpi.h>
5 #include <linux/delay.h>
7 #include <linux/module.h>
8 #include <linux/regmap.h>
9 #include <linux/slab.h>
10 #include <linux/cdev.h>
11 #include <sound/pcm.h>
12 #include <sound/pcm_params.h>
13 #include <sound/soc.h>
14 #include <linux/gpio.h>
15 #include <linux/gpio/consumer.h>
17 #include <linux/of_gpio.h>
18 #include <sound/tlv.h>
21 static struct reg_default max98520_reg[] = {
22 {MAX98520_R2000_SW_RESET, 0x00},
23 {MAX98520_R2001_STATUS_1, 0x00},
24 {MAX98520_R2002_STATUS_2, 0x00},
25 {MAX98520_R2020_THERM_WARN_THRESH, 0x46},
26 {MAX98520_R2021_THERM_SHDN_THRESH, 0x64},
27 {MAX98520_R2022_THERM_HYSTERESIS, 0x02},
28 {MAX98520_R2023_THERM_FOLDBACK_SET, 0x31},
29 {MAX98520_R2027_THERM_FOLDBACK_EN, 0x01},
30 {MAX98520_R2030_CLK_MON_CTRL, 0x00},
31 {MAX98520_R2037_ERR_MON_CTRL, 0x01},
32 {MAX98520_R2040_PCM_MODE_CFG, 0xC0},
33 {MAX98520_R2041_PCM_CLK_SETUP, 0x04},
34 {MAX98520_R2042_PCM_SR_SETUP, 0x08},
35 {MAX98520_R2043_PCM_RX_SRC1, 0x00},
36 {MAX98520_R2044_PCM_RX_SRC2, 0x00},
37 {MAX98520_R204F_PCM_RX_EN, 0x00},
38 {MAX98520_R2090_AMP_VOL_CTRL, 0x00},
39 {MAX98520_R2091_AMP_PATH_GAIN, 0x03},
40 {MAX98520_R2092_AMP_DSP_CFG, 0x02},
41 {MAX98520_R2094_SSM_CFG, 0x01},
42 {MAX98520_R2095_AMP_CFG, 0xF0},
43 {MAX98520_R209F_AMP_EN, 0x00},
44 {MAX98520_R20B0_ADC_SR, 0x00},
45 {MAX98520_R20B1_ADC_RESOLUTION, 0x00},
46 {MAX98520_R20B2_ADC_PVDD0_CFG, 0x02},
47 {MAX98520_R20B3_ADC_THERMAL_CFG, 0x02},
48 {MAX98520_R20B4_ADC_READBACK_CTRL, 0x00},
49 {MAX98520_R20B5_ADC_READBACK_UPDATE, 0x00},
50 {MAX98520_R20B6_ADC_PVDD_READBACK_MSB, 0x00},
51 {MAX98520_R20B7_ADC_PVDD_READBACK_LSB, 0x00},
52 {MAX98520_R20B8_ADC_TEMP_READBACK_MSB, 0x00},
53 {MAX98520_R20B9_ADC_TEMP_READBACK_LSB, 0x00},
54 {MAX98520_R20BA_ADC_LOW_PVDD_READBACK_MSB, 0xFF},
55 {MAX98520_R20BB_ADC_LOW_READBACK_LSB, 0x01},
56 {MAX98520_R20BC_ADC_HIGH_TEMP_READBACK_MSB, 0x00},
57 {MAX98520_R20BD_ADC_HIGH_TEMP_READBACK_LSB, 0x00},
58 {MAX98520_R20CF_MEAS_ADC_CFG, 0x00},
59 {MAX98520_R20D0_DHT_CFG1, 0x00},
60 {MAX98520_R20D1_LIMITER_CFG1, 0x08},
61 {MAX98520_R20D2_LIMITER_CFG2, 0x00},
62 {MAX98520_R20D3_DHT_CFG2, 0x14},
63 {MAX98520_R20D4_DHT_CFG3, 0x02},
64 {MAX98520_R20D5_DHT_CFG4, 0x04},
65 {MAX98520_R20D6_DHT_HYSTERESIS_CFG, 0x07},
66 {MAX98520_R20D8_DHT_EN, 0x00},
67 {MAX98520_R210E_AUTO_RESTART_BEHAVIOR, 0x00},
68 {MAX98520_R210F_GLOBAL_EN, 0x00},
69 {MAX98520_R21FF_REVISION_ID, 0x00},
72 static int max98520_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
74 struct snd_soc_component *component = codec_dai->component;
75 struct max98520_priv *max98520 =
76 snd_soc_component_get_drvdata(component);
77 unsigned int format = 0;
78 unsigned int invert = 0;
80 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
82 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
83 case SND_SOC_DAIFMT_NB_NF:
85 case SND_SOC_DAIFMT_IB_NF:
86 invert = MAX98520_PCM_MODE_CFG_PCM_BCLKEDGE;
89 dev_err(component->dev, "DAI invert mode unsupported\n");
93 regmap_update_bits(max98520->regmap,
94 MAX98520_R2041_PCM_CLK_SETUP,
95 MAX98520_PCM_MODE_CFG_PCM_BCLKEDGE,
98 /* interface format */
99 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
100 case SND_SOC_DAIFMT_I2S:
101 format = MAX98520_PCM_FORMAT_I2S;
103 case SND_SOC_DAIFMT_LEFT_J:
104 format = MAX98520_PCM_FORMAT_LJ;
106 case SND_SOC_DAIFMT_DSP_A:
107 format = MAX98520_PCM_FORMAT_TDM_MODE1;
109 case SND_SOC_DAIFMT_DSP_B:
110 format = MAX98520_PCM_FORMAT_TDM_MODE0;
116 regmap_update_bits(max98520->regmap,
117 MAX98520_R2040_PCM_MODE_CFG,
118 MAX98520_PCM_MODE_CFG_FORMAT_MASK,
119 format << MAX98520_PCM_MODE_CFG_FORMAT_SHIFT);
124 /* BCLKs per LRCLK */
125 static const int bclk_sel_table[] = {
126 32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
129 static int max98520_get_bclk_sel(int bclk)
132 /* match BCLKs per LRCLK */
133 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
134 if (bclk_sel_table[i] == bclk)
140 static int max98520_set_clock(struct snd_soc_component *component,
141 struct snd_pcm_hw_params *params)
143 struct max98520_priv *max98520 =
144 snd_soc_component_get_drvdata(component);
145 /* BCLK/LRCLK ratio calculation */
146 int blr_clk_ratio = params_channels(params) * max98520->ch_size;
149 if (!max98520->tdm_mode) {
150 /* BCLK configuration */
151 value = max98520_get_bclk_sel(blr_clk_ratio);
153 dev_err(component->dev, "format unsupported %d\n",
154 params_format(params));
158 regmap_update_bits(max98520->regmap,
159 MAX98520_R2041_PCM_CLK_SETUP,
160 MAX98520_PCM_CLK_SETUP_BSEL_MASK,
163 dev_dbg(component->dev, "%s tdm_mode:%d out\n", __func__, max98520->tdm_mode);
167 static int max98520_dai_hw_params(struct snd_pcm_substream *substream,
168 struct snd_pcm_hw_params *params,
169 struct snd_soc_dai *dai)
171 struct snd_soc_component *component = dai->component;
172 struct max98520_priv *max98520 =
173 snd_soc_component_get_drvdata(component);
174 unsigned int sampling_rate = 0;
175 unsigned int chan_sz = 0;
177 /* pcm mode configuration */
178 switch (snd_pcm_format_width(params_format(params))) {
180 chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_16;
183 chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_24;
186 chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_32;
189 dev_err(component->dev, "format unsupported %d\n",
190 params_format(params));
194 max98520->ch_size = snd_pcm_format_width(params_format(params));
196 regmap_update_bits(max98520->regmap,
197 MAX98520_R2040_PCM_MODE_CFG,
198 MAX98520_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
200 dev_dbg(component->dev, "format supported %d",
201 params_format(params));
203 /* sampling rate configuration */
204 switch (params_rate(params)) {
206 sampling_rate = MAX98520_PCM_SR_8000;
209 sampling_rate = MAX98520_PCM_SR_11025;
212 sampling_rate = MAX98520_PCM_SR_12000;
215 sampling_rate = MAX98520_PCM_SR_16000;
218 sampling_rate = MAX98520_PCM_SR_22050;
221 sampling_rate = MAX98520_PCM_SR_24000;
224 sampling_rate = MAX98520_PCM_SR_32000;
227 sampling_rate = MAX98520_PCM_SR_44100;
230 sampling_rate = MAX98520_PCM_SR_48000;
233 sampling_rate = MAX98520_PCM_SR_88200;
236 sampling_rate = MAX98520_PCM_SR_96000;
239 sampling_rate = MAX98520_PCM_SR_176400;
242 sampling_rate = MAX98520_PCM_SR_192000;
245 dev_err(component->dev, "rate %d not supported\n",
246 params_rate(params));
250 dev_dbg(component->dev, " %s ch_size: %d, sampling rate : %d out\n", __func__,
251 snd_pcm_format_width(params_format(params)), params_rate(params));
252 /* set DAI_SR to correct LRCLK frequency */
253 regmap_update_bits(max98520->regmap,
254 MAX98520_R2042_PCM_SR_SETUP,
255 MAX98520_PCM_SR_MASK,
258 return max98520_set_clock(component, params);
260 dev_dbg(component->dev, "%s out error", __func__);
264 static int max98520_dai_tdm_slot(struct snd_soc_dai *dai,
265 unsigned int tx_mask, unsigned int rx_mask,
266 int slots, int slot_width)
268 struct snd_soc_component *component = dai->component;
269 struct max98520_priv *max98520 =
270 snd_soc_component_get_drvdata(component);
272 unsigned int chan_sz = 0;
274 if (!tx_mask && !rx_mask && !slots && !slot_width)
275 max98520->tdm_mode = false;
277 max98520->tdm_mode = true;
279 /* BCLK configuration */
280 bsel = max98520_get_bclk_sel(slots * slot_width);
282 dev_err(component->dev, "BCLK %d not supported\n",
287 regmap_update_bits(max98520->regmap,
288 MAX98520_R2041_PCM_CLK_SETUP,
289 MAX98520_PCM_CLK_SETUP_BSEL_MASK,
292 /* Channel size configuration */
293 switch (slot_width) {
295 chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_16;
298 chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_24;
301 chan_sz = MAX98520_PCM_MODE_CFG_CHANSZ_32;
304 dev_err(component->dev, "format unsupported %d\n",
309 regmap_update_bits(max98520->regmap,
310 MAX98520_R2040_PCM_MODE_CFG,
311 MAX98520_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
313 /* Rx slot configuration */
314 regmap_update_bits(max98520->regmap,
315 MAX98520_R2044_PCM_RX_SRC2,
316 MAX98520_PCM_DMIX_CH0_SRC_MASK,
318 regmap_update_bits(max98520->regmap,
319 MAX98520_R2044_PCM_RX_SRC2,
320 MAX98520_PCM_DMIX_CH1_SRC_MASK,
321 rx_mask << MAX98520_PCM_DMIX_CH1_SHIFT);
326 #define MAX98520_RATES SNDRV_PCM_RATE_8000_192000
328 #define MAX98520_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
329 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
331 static const struct snd_soc_dai_ops max98520_dai_ops = {
332 .set_fmt = max98520_dai_set_fmt,
333 .hw_params = max98520_dai_hw_params,
334 .set_tdm_slot = max98520_dai_tdm_slot,
337 static int max98520_dac_event(struct snd_soc_dapm_widget *w,
338 struct snd_kcontrol *kcontrol, int event)
340 struct snd_soc_component *component =
341 snd_soc_dapm_to_component(w->dapm);
342 struct max98520_priv *max98520 =
343 snd_soc_component_get_drvdata(component);
346 case SND_SOC_DAPM_POST_PMU:
347 dev_dbg(component->dev, " AMP ON\n");
349 regmap_write(max98520->regmap, MAX98520_R209F_AMP_EN, 1);
350 regmap_write(max98520->regmap, MAX98520_R210F_GLOBAL_EN, 1);
351 usleep_range(30000, 31000);
353 case SND_SOC_DAPM_POST_PMD:
354 dev_dbg(component->dev, " AMP OFF\n");
356 regmap_write(max98520->regmap, MAX98520_R210F_GLOBAL_EN, 0);
357 regmap_write(max98520->regmap, MAX98520_R209F_AMP_EN, 0);
358 usleep_range(30000, 31000);
366 static const char * const max98520_switch_text[] = {
367 "Left", "Right", "LeftRight"};
369 static const struct soc_enum dai_sel_enum =
370 SOC_ENUM_SINGLE(MAX98520_R2043_PCM_RX_SRC1,
371 0, 3, max98520_switch_text);
373 static const struct snd_kcontrol_new max98520_dai_controls =
374 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
376 static const struct snd_kcontrol_new max98520_left_input_mixer_controls[] = {
377 SOC_DAPM_SINGLE("PCM_INPUT_CH0", MAX98520_R2044_PCM_RX_SRC2, 0, 0x0, 0),
378 SOC_DAPM_SINGLE("PCM_INPUT_CH1", MAX98520_R2044_PCM_RX_SRC2, 0, 0x1, 0),
379 SOC_DAPM_SINGLE("PCM_INPUT_CH2", MAX98520_R2044_PCM_RX_SRC2, 0, 0x2, 0),
380 SOC_DAPM_SINGLE("PCM_INPUT_CH3", MAX98520_R2044_PCM_RX_SRC2, 0, 0x3, 0),
381 SOC_DAPM_SINGLE("PCM_INPUT_CH4", MAX98520_R2044_PCM_RX_SRC2, 0, 0x4, 0),
382 SOC_DAPM_SINGLE("PCM_INPUT_CH5", MAX98520_R2044_PCM_RX_SRC2, 0, 0x5, 0),
383 SOC_DAPM_SINGLE("PCM_INPUT_CH6", MAX98520_R2044_PCM_RX_SRC2, 0, 0x6, 0),
384 SOC_DAPM_SINGLE("PCM_INPUT_CH7", MAX98520_R2044_PCM_RX_SRC2, 0, 0x7, 0),
385 SOC_DAPM_SINGLE("PCM_INPUT_CH8", MAX98520_R2044_PCM_RX_SRC2, 0, 0x8, 0),
386 SOC_DAPM_SINGLE("PCM_INPUT_CH9", MAX98520_R2044_PCM_RX_SRC2, 0, 0x9, 0),
387 SOC_DAPM_SINGLE("PCM_INPUT_CH10", MAX98520_R2044_PCM_RX_SRC2, 0, 0xa, 0),
388 SOC_DAPM_SINGLE("PCM_INPUT_CH11", MAX98520_R2044_PCM_RX_SRC2, 0, 0xb, 0),
389 SOC_DAPM_SINGLE("PCM_INPUT_CH12", MAX98520_R2044_PCM_RX_SRC2, 0, 0xc, 0),
390 SOC_DAPM_SINGLE("PCM_INPUT_CH13", MAX98520_R2044_PCM_RX_SRC2, 0, 0xd, 0),
391 SOC_DAPM_SINGLE("PCM_INPUT_CH14", MAX98520_R2044_PCM_RX_SRC2, 0, 0xe, 0),
392 SOC_DAPM_SINGLE("PCM_INPUT_CH15", MAX98520_R2044_PCM_RX_SRC2, 0, 0xf, 0),
395 static const struct snd_kcontrol_new max98520_right_input_mixer_controls[] = {
396 SOC_DAPM_SINGLE("PCM_INPUT_CH0", MAX98520_R2044_PCM_RX_SRC2, 4, 0x0, 0),
397 SOC_DAPM_SINGLE("PCM_INPUT_CH1", MAX98520_R2044_PCM_RX_SRC2, 4, 0x1, 0),
398 SOC_DAPM_SINGLE("PCM_INPUT_CH2", MAX98520_R2044_PCM_RX_SRC2, 4, 0x2, 0),
399 SOC_DAPM_SINGLE("PCM_INPUT_CH3", MAX98520_R2044_PCM_RX_SRC2, 4, 0x3, 0),
400 SOC_DAPM_SINGLE("PCM_INPUT_CH4", MAX98520_R2044_PCM_RX_SRC2, 4, 0x4, 0),
401 SOC_DAPM_SINGLE("PCM_INPUT_CH5", MAX98520_R2044_PCM_RX_SRC2, 4, 0x5, 0),
402 SOC_DAPM_SINGLE("PCM_INPUT_CH6", MAX98520_R2044_PCM_RX_SRC2, 4, 0x6, 0),
403 SOC_DAPM_SINGLE("PCM_INPUT_CH7", MAX98520_R2044_PCM_RX_SRC2, 4, 0x7, 0),
404 SOC_DAPM_SINGLE("PCM_INPUT_CH8", MAX98520_R2044_PCM_RX_SRC2, 4, 0x8, 0),
405 SOC_DAPM_SINGLE("PCM_INPUT_CH9", MAX98520_R2044_PCM_RX_SRC2, 4, 0x9, 0),
406 SOC_DAPM_SINGLE("PCM_INPUT_CH10", MAX98520_R2044_PCM_RX_SRC2, 4, 0xa, 0),
407 SOC_DAPM_SINGLE("PCM_INPUT_CH11", MAX98520_R2044_PCM_RX_SRC2, 4, 0xb, 0),
408 SOC_DAPM_SINGLE("PCM_INPUT_CH12", MAX98520_R2044_PCM_RX_SRC2, 4, 0xc, 0),
409 SOC_DAPM_SINGLE("PCM_INPUT_CH13", MAX98520_R2044_PCM_RX_SRC2, 4, 0xd, 0),
410 SOC_DAPM_SINGLE("PCM_INPUT_CH14", MAX98520_R2044_PCM_RX_SRC2, 4, 0xe, 0),
411 SOC_DAPM_SINGLE("PCM_INPUT_CH15", MAX98520_R2044_PCM_RX_SRC2, 4, 0xf, 0),
414 static const struct snd_soc_dapm_widget max98520_dapm_widgets[] = {
415 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
416 SND_SOC_NOPM, 0, 0, max98520_dac_event,
417 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
418 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, &max98520_dai_controls),
419 SND_SOC_DAPM_OUTPUT("BE_OUT"),
420 /* Left Input Selection */
421 SND_SOC_DAPM_MIXER("Left Input Selection", SND_SOC_NOPM, 0, 0,
422 &max98520_left_input_mixer_controls[0],
423 ARRAY_SIZE(max98520_left_input_mixer_controls)),
424 /* Right Input Selection */
425 SND_SOC_DAPM_MIXER("Right Input Selection", SND_SOC_NOPM, 0, 0,
426 &max98520_right_input_mixer_controls[0],
427 ARRAY_SIZE(max98520_right_input_mixer_controls)),
430 static const DECLARE_TLV_DB_SCALE(max98520_digital_tlv, -6300, 50, 1);
431 static const DECLARE_TLV_DB_SCALE(max98520_spk_tlv, -600, 300, 0);
433 static const DECLARE_TLV_DB_RANGE(max98520_dht_lim_thresh_tlv,
434 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
437 static const DECLARE_TLV_DB_RANGE(max98520_dht_hysteresis_tlv,
438 0, 3, TLV_DB_SCALE_ITEM(100, 100, 0),
439 4, 7, TLV_DB_SCALE_ITEM(600, 200, 0),
442 static const DECLARE_TLV_DB_RANGE(max98520_dht_rotation_point_tlv,
443 0, 1, TLV_DB_SCALE_ITEM(-1500, 300, 0),
444 2, 4, TLV_DB_SCALE_ITEM(-1000, 200, 0),
445 5, 10, TLV_DB_SCALE_ITEM(-500, 100, 0),
448 static const DECLARE_TLV_DB_RANGE(max98520_dht_supply_hr_tlv,
449 0, 16, TLV_DB_SCALE_ITEM(-2000, 250, 0),
452 static const DECLARE_TLV_DB_RANGE(max98520_dht_max_atten_tlv,
453 1, 20, TLV_DB_SCALE_ITEM(-2000, 100, 0),
456 static const char * const max98520_dht_attack_rate_text[] = {
457 "20us", "40us", "80us", "160us", "320us", "640us",
458 "1.28ms", "2.56ms", "5.12ms", "10.24ms", "20.48ms", "40.96ms",
459 "81.92ms", "163.84ms"
462 static SOC_ENUM_SINGLE_DECL(max98520_dht_attack_rate_enum,
463 MAX98520_R20D4_DHT_CFG3, 0,
464 max98520_dht_attack_rate_text);
466 static const char * const max98520_dht_release_rate_text[] = {
467 "2ms", "4ms", "8ms", "16ms", "32ms", "64ms", "128ms", "256ms", "512ms",
468 "1.024s", "2.048s", "4.096s", "8.192s", "16.384s"
471 static SOC_ENUM_SINGLE_DECL(max98520_dht_release_rate_enum,
472 MAX98520_R20D5_DHT_CFG4, 0,
473 max98520_dht_release_rate_text);
475 static bool max98520_readable_register(struct device *dev, unsigned int reg)
478 case MAX98520_R2000_SW_RESET:
479 case MAX98520_R2027_THERM_FOLDBACK_EN:
480 case MAX98520_R2030_CLK_MON_CTRL:
481 case MAX98520_R2037_ERR_MON_CTRL:
482 case MAX98520_R204F_PCM_RX_EN:
483 case MAX98520_R209F_AMP_EN:
484 case MAX98520_R20CF_MEAS_ADC_CFG:
485 case MAX98520_R20D8_DHT_EN:
486 case MAX98520_R21FF_REVISION_ID:
487 case MAX98520_R2001_STATUS_1... MAX98520_R2002_STATUS_2:
488 case MAX98520_R2020_THERM_WARN_THRESH... MAX98520_R2023_THERM_FOLDBACK_SET:
489 case MAX98520_R2040_PCM_MODE_CFG... MAX98520_R2044_PCM_RX_SRC2:
490 case MAX98520_R2090_AMP_VOL_CTRL... MAX98520_R2092_AMP_DSP_CFG:
491 case MAX98520_R2094_SSM_CFG... MAX98520_R2095_AMP_CFG:
492 case MAX98520_R20B0_ADC_SR... MAX98520_R20BD_ADC_HIGH_TEMP_READBACK_LSB:
493 case MAX98520_R20D0_DHT_CFG1... MAX98520_R20D6_DHT_HYSTERESIS_CFG:
494 case MAX98520_R210E_AUTO_RESTART_BEHAVIOR... MAX98520_R210F_GLOBAL_EN:
495 case MAX98520_R2161_BOOST_TM1... MAX98520_R2163_BOOST_TM3:
502 static bool max98520_volatile_reg(struct device *dev, unsigned int reg)
505 case MAX98520_R210F_GLOBAL_EN:
506 case MAX98520_R21FF_REVISION_ID:
507 case MAX98520_R2000_SW_RESET:
508 case MAX98520_R2001_STATUS_1 ... MAX98520_R2002_STATUS_2:
509 case MAX98520_R20B4_ADC_READBACK_CTRL
510 ... MAX98520_R20BD_ADC_HIGH_TEMP_READBACK_LSB:
517 static const struct snd_kcontrol_new max98520_snd_controls[] = {
519 SOC_SINGLE_TLV("Digital Volume", MAX98520_R2090_AMP_VOL_CTRL,
520 0, 0x7F, 1, max98520_digital_tlv),
521 SOC_SINGLE_TLV("Speaker Volume", MAX98520_R2091_AMP_PATH_GAIN,
522 0, 0x5, 0, max98520_spk_tlv),
523 /* Volume Ramp Up/Down Enable*/
524 SOC_SINGLE("Ramp Up Switch", MAX98520_R2092_AMP_DSP_CFG,
525 MAX98520_DSP_SPK_VOL_RMPUP_SHIFT, 1, 0),
526 SOC_SINGLE("Ramp Down Switch", MAX98520_R2092_AMP_DSP_CFG,
527 MAX98520_DSP_SPK_VOL_RMPDN_SHIFT, 1, 0),
528 /* Clock Monitor Enable */
529 SOC_SINGLE("CLK Monitor Switch", MAX98520_R2037_ERR_MON_CTRL,
530 MAX98520_CTRL_CMON_EN_SHIFT, 1, 0),
531 /* Clock Monitor Config */
532 SOC_SINGLE("CLKMON Autorestart Switch", MAX98520_R2030_CLK_MON_CTRL,
533 MAX98520_CMON_AUTORESTART_SHIFT, 1, 0),
535 SOC_SINGLE("Dither Switch", MAX98520_R2092_AMP_DSP_CFG,
536 MAX98520_DSP_SPK_DITH_EN_SHIFT, 1, 0),
537 /* DC Blocker Enable */
538 SOC_SINGLE("DC Blocker Switch", MAX98520_R2092_AMP_DSP_CFG,
539 MAX98520_DSP_SPK_DCBLK_EN_SHIFT, 1, 0),
540 /* Speaker Safe Mode Enable */
541 SOC_SINGLE("Speaker Safemode Switch", MAX98520_R2092_AMP_DSP_CFG,
542 MAX98520_DSP_SPK_SAFE_EN_SHIFT, 1, 0),
544 SOC_SINGLE("CP Bypass Switch", MAX98520_R2094_SSM_CFG,
545 MAX98520_SSM_RCVR_MODE_SHIFT, 1, 0),
546 /* Dynamic Headroom Tracking */
547 SOC_SINGLE("DHT Switch", MAX98520_R20D8_DHT_EN, 0, 1, 0),
548 SOC_SINGLE("DHT Limiter Mode", MAX98520_R20D2_LIMITER_CFG2,
549 MAX98520_DHT_LIMITER_MODE_SHIFT, 1, 0),
550 SOC_SINGLE("DHT Hysteresis Switch", MAX98520_R20D6_DHT_HYSTERESIS_CFG,
551 MAX98520_DHT_HYSTERESIS_SWITCH_SHIFT, 1, 0),
552 SOC_SINGLE_TLV("DHT Rot Pnt", MAX98520_R20D0_DHT_CFG1,
553 MAX98520_DHT_VROT_PNT_SHIFT, 10, 1, max98520_dht_rotation_point_tlv),
554 SOC_SINGLE_TLV("DHT Supply Headroom", MAX98520_R20D1_LIMITER_CFG1,
555 MAX98520_DHT_SUPPLY_HR_SHIFT, 16, 0, max98520_dht_supply_hr_tlv),
556 SOC_SINGLE_TLV("DHT Limiter Threshold", MAX98520_R20D2_LIMITER_CFG2,
557 MAX98520_DHT_LIMITER_THRESHOLD_SHIFT, 0xF, 1, max98520_dht_lim_thresh_tlv),
558 SOC_SINGLE_TLV("DHT Max Attenuation", MAX98520_R20D3_DHT_CFG2,
559 MAX98520_DHT_MAX_ATTEN_SHIFT, 20, 1, max98520_dht_max_atten_tlv),
560 SOC_SINGLE_TLV("DHT Hysteresis", MAX98520_R20D6_DHT_HYSTERESIS_CFG,
561 MAX98520_DHT_HYSTERESIS_SHIFT, 0x7, 0, max98520_dht_hysteresis_tlv),
562 SOC_ENUM("DHT Attack Rate", max98520_dht_attack_rate_enum),
563 SOC_ENUM("DHT Release Rate", max98520_dht_release_rate_enum),
564 /* ADC configuration */
565 SOC_SINGLE("ADC PVDD CH Switch", MAX98520_R20CF_MEAS_ADC_CFG, 0, 1, 0),
566 SOC_SINGLE("ADC PVDD FLT Switch", MAX98520_R20B2_ADC_PVDD0_CFG, MAX98520_FLT_EN_SHIFT, 1, 0),
567 SOC_SINGLE("ADC TEMP FLT Switch", MAX98520_R20B3_ADC_THERMAL_CFG, MAX98520_FLT_EN_SHIFT, 1, 0),
568 SOC_SINGLE("ADC PVDD MSB", MAX98520_R20B6_ADC_PVDD_READBACK_MSB, 0, 0xFF, 0),
569 SOC_SINGLE("ADC PVDD LSB", MAX98520_R20B7_ADC_PVDD_READBACK_LSB, 0, 0x01, 0),
570 SOC_SINGLE("ADC TEMP MSB", MAX98520_R20B8_ADC_TEMP_READBACK_MSB, 0, 0xFF, 0),
571 SOC_SINGLE("ADC TEMP LSB", MAX98520_R20B9_ADC_TEMP_READBACK_LSB, 0, 0x01, 0),
574 static const struct snd_soc_dapm_route max98520_audio_map[] = {
576 {"DAI Sel Mux", "Left", "Amp Enable"},
577 {"DAI Sel Mux", "Right", "Amp Enable"},
578 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
579 {"BE_OUT", NULL, "DAI Sel Mux"},
582 static struct snd_soc_dai_driver max98520_dai[] = {
584 .name = "max98520-aif1",
586 .stream_name = "HiFi Playback",
589 .rates = MAX98520_RATES,
590 .formats = MAX98520_FORMATS,
592 .ops = &max98520_dai_ops,
597 static int max98520_probe(struct snd_soc_component *component)
599 struct max98520_priv *max98520 =
600 snd_soc_component_get_drvdata(component);
603 regmap_write(max98520->regmap, MAX98520_R2000_SW_RESET, 1);
605 /* L/R mono mix configuration : "DAI Sel" for 0x2043 */
606 regmap_write(max98520->regmap, MAX98520_R2043_PCM_RX_SRC1, 0x2);
608 /* PCM input channles configuration : "Left Input Selection" for 0x2044 */
609 /* PCM input channles configuration : "Right Input Selection" for 0x2044 */
610 regmap_write(max98520->regmap, MAX98520_R2044_PCM_RX_SRC2, 0x10);
612 /* Enable DC blocker */
613 regmap_update_bits(max98520->regmap, MAX98520_R2092_AMP_DSP_CFG, 1, 1);
614 /* Enable Clock Monitor Auto-restart */
615 regmap_write(max98520->regmap, MAX98520_R2030_CLK_MON_CTRL, 0x1);
618 regmap_update_bits(max98520->regmap,
619 MAX98520_R204F_PCM_RX_EN,
620 MAX98520_PCM_RX_EN_MASK,
626 static int __maybe_unused max98520_suspend(struct device *dev)
628 struct max98520_priv *max98520 = dev_get_drvdata(dev);
630 regcache_cache_only(max98520->regmap, true);
631 regcache_mark_dirty(max98520->regmap);
635 static int __maybe_unused max98520_resume(struct device *dev)
637 struct max98520_priv *max98520 = dev_get_drvdata(dev);
639 regcache_cache_only(max98520->regmap, false);
640 regmap_write(max98520->regmap, MAX98520_R2000_SW_RESET, 1);
641 regcache_sync(max98520->regmap);
645 static const struct dev_pm_ops max98520_pm = {
646 SET_SYSTEM_SLEEP_PM_OPS(max98520_suspend, max98520_resume)
649 static const struct snd_soc_component_driver soc_codec_dev_max98520 = {
650 .probe = max98520_probe,
651 .controls = max98520_snd_controls,
652 .num_controls = ARRAY_SIZE(max98520_snd_controls),
653 .dapm_widgets = max98520_dapm_widgets,
654 .num_dapm_widgets = ARRAY_SIZE(max98520_dapm_widgets),
655 .dapm_routes = max98520_audio_map,
656 .num_dapm_routes = ARRAY_SIZE(max98520_audio_map),
658 .use_pmdown_time = 1,
660 .non_legacy_dai_naming = 1,
663 static const struct regmap_config max98520_regmap = {
666 .max_register = MAX98520_R21FF_REVISION_ID,
667 .reg_defaults = max98520_reg,
668 .num_reg_defaults = ARRAY_SIZE(max98520_reg),
669 .readable_reg = max98520_readable_register,
670 .volatile_reg = max98520_volatile_reg,
671 .cache_type = REGCACHE_RBTREE,
674 static void max98520_power_on(struct max98520_priv *max98520, bool poweron)
676 if (max98520->reset_gpio)
677 gpiod_set_value_cansleep(max98520->reset_gpio, !poweron);
680 static int max98520_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
684 struct max98520_priv *max98520;
685 struct i2c_adapter *adapter = to_i2c_adapter(i2c->dev.parent);
687 ret = i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA);
689 dev_err(&i2c->dev, "I2C check functionality failed\n");
693 max98520 = devm_kzalloc(&i2c->dev, sizeof(*max98520), GFP_KERNEL);
698 i2c_set_clientdata(i2c, max98520);
700 /* regmap initialization */
701 max98520->regmap = devm_regmap_init_i2c(i2c, &max98520_regmap);
702 if (IS_ERR(max98520->regmap)) {
703 ret = PTR_ERR(max98520->regmap);
704 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
708 /* Power on device */
709 max98520->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset", GPIOD_OUT_HIGH);
710 if (max98520->reset_gpio) {
711 if (IS_ERR(max98520->reset_gpio)) {
712 ret = PTR_ERR(max98520->reset_gpio);
713 dev_err(&i2c->dev, "Unable to request GPIO pin: %d.\n", ret);
717 max98520_power_on(max98520, 1);
720 /* Check Revision ID */
721 ret = regmap_read(max98520->regmap, MAX98520_R21FF_REVISION_ID, ®);
724 "Failed to read: 0x%02X\n", MAX98520_R21FF_REVISION_ID);
727 dev_info(&i2c->dev, "MAX98520 revisionID: 0x%02X\n", reg);
729 /* codec registration */
730 ret = devm_snd_soc_register_component(&i2c->dev,
731 &soc_codec_dev_max98520,
732 max98520_dai, ARRAY_SIZE(max98520_dai));
734 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
739 static const struct i2c_device_id max98520_i2c_id[] = {
744 MODULE_DEVICE_TABLE(i2c, max98520_i2c_id);
746 #if defined(CONFIG_OF)
747 static const struct of_device_id max98520_of_match[] = {
748 { .compatible = "maxim,max98520", },
751 MODULE_DEVICE_TABLE(of, max98520_of_match);
754 static struct i2c_driver max98520_i2c_driver = {
757 .of_match_table = of_match_ptr(max98520_of_match),
760 .probe = max98520_i2c_probe,
761 .id_table = max98520_i2c_id,
764 module_i2c_driver(max98520_i2c_driver)
766 MODULE_DESCRIPTION("ALSA SoC MAX98520 driver");
767 MODULE_AUTHOR("George Song <george.song@maximintegrated.com>");
768 MODULE_LICENSE("GPL");