1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2017, Maxim Integrated */
4 #include <linux/acpi.h>
6 #include <linux/module.h>
7 #include <linux/regmap.h>
8 #include <linux/slab.h>
9 #include <linux/cdev.h>
10 #include <sound/pcm.h>
11 #include <sound/pcm_params.h>
12 #include <sound/soc.h>
13 #include <linux/gpio.h>
14 #include <linux/of_gpio.h>
15 #include <sound/tlv.h>
18 static struct reg_default max98373_reg[] = {
19 {MAX98373_R2000_SW_RESET, 0x00},
20 {MAX98373_R2001_INT_RAW1, 0x00},
21 {MAX98373_R2002_INT_RAW2, 0x00},
22 {MAX98373_R2003_INT_RAW3, 0x00},
23 {MAX98373_R2004_INT_STATE1, 0x00},
24 {MAX98373_R2005_INT_STATE2, 0x00},
25 {MAX98373_R2006_INT_STATE3, 0x00},
26 {MAX98373_R2007_INT_FLAG1, 0x00},
27 {MAX98373_R2008_INT_FLAG2, 0x00},
28 {MAX98373_R2009_INT_FLAG3, 0x00},
29 {MAX98373_R200A_INT_EN1, 0x00},
30 {MAX98373_R200B_INT_EN2, 0x00},
31 {MAX98373_R200C_INT_EN3, 0x00},
32 {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
33 {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
34 {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
35 {MAX98373_R2010_IRQ_CTRL, 0x00},
36 {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
37 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
38 {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
39 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
40 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
41 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
42 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
43 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
44 {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
45 {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
46 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
47 {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
48 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
49 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
50 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
51 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
52 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
53 {MAX98373_R202B_PCM_RX_EN, 0x00},
54 {MAX98373_R202C_PCM_TX_EN, 0x00},
55 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
56 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
57 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
58 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
59 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
60 {MAX98373_R2034_ICC_TX_CNTL, 0x00},
61 {MAX98373_R2035_ICC_TX_EN, 0x00},
62 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
63 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
64 {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
65 {MAX98373_R203F_AMP_DSP_CFG, 0x02},
66 {MAX98373_R2040_TONE_GEN_CFG, 0x00},
67 {MAX98373_R2041_AMP_CFG, 0x03},
68 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
69 {MAX98373_R2043_AMP_EN, 0x00},
70 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
71 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
72 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
73 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
74 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
75 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
76 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
77 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
78 {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
79 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
80 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
81 {MAX98373_R2097_BDE_L1_THRESH, 0x00},
82 {MAX98373_R2098_BDE_L2_THRESH, 0x00},
83 {MAX98373_R2099_BDE_L3_THRESH, 0x00},
84 {MAX98373_R209A_BDE_L4_THRESH, 0x00},
85 {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
86 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
87 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
88 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
89 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
90 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
91 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
92 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
93 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
94 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
95 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
96 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
97 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
98 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
99 {MAX98373_R20B5_BDE_EN, 0x00},
100 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
101 {MAX98373_R20D1_DHT_CFG, 0x01},
102 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
103 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
104 {MAX98373_R20D4_DHT_EN, 0x00},
105 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
106 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
107 {MAX98373_R20E2_LIMITER_EN, 0x00},
108 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
109 {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
110 {MAX98373_R21FF_REV_ID, 0x42},
113 static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
115 struct snd_soc_codec *codec = codec_dai->codec;
116 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
117 unsigned int format = 0;
118 unsigned int invert = 0;
120 dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
122 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
123 case SND_SOC_DAIFMT_NB_NF:
125 case SND_SOC_DAIFMT_IB_NF:
126 invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE;
129 dev_err(codec->dev, "DAI invert mode unsupported\n");
133 regmap_update_bits(max98373->regmap,
134 MAX98373_R2026_PCM_CLOCK_RATIO,
135 MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE,
138 /* interface format */
139 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
140 case SND_SOC_DAIFMT_I2S:
141 format = MAX98373_PCM_FORMAT_I2S;
143 case SND_SOC_DAIFMT_LEFT_J:
144 format = MAX98373_PCM_FORMAT_LJ;
146 case SND_SOC_DAIFMT_DSP_A:
147 format = MAX98373_PCM_FORMAT_TDM_MODE1;
149 case SND_SOC_DAIFMT_DSP_B:
150 format = MAX98373_PCM_FORMAT_TDM_MODE0;
156 regmap_update_bits(max98373->regmap,
157 MAX98373_R2024_PCM_DATA_FMT_CFG,
158 MAX98373_PCM_MODE_CFG_FORMAT_MASK,
159 format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT);
164 /* BCLKs per LRCLK */
165 static const int bclk_sel_table[] = {
166 32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
169 static int max98373_get_bclk_sel(int bclk)
172 /* match BCLKs per LRCLK */
173 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
174 if (bclk_sel_table[i] == bclk)
180 static int max98373_set_clock(struct snd_soc_codec *codec,
181 struct snd_pcm_hw_params *params)
183 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
184 /* BCLK/LRCLK ratio calculation */
185 int blr_clk_ratio = params_channels(params) * max98373->ch_size;
188 if (!max98373->tdm_mode) {
189 /* BCLK configuration */
190 value = max98373_get_bclk_sel(blr_clk_ratio);
192 dev_err(codec->dev, "format unsupported %d\n",
193 params_format(params));
197 regmap_update_bits(max98373->regmap,
198 MAX98373_R2026_PCM_CLOCK_RATIO,
199 MAX98373_PCM_CLK_SETUP_BSEL_MASK,
205 static int max98373_dai_hw_params(struct snd_pcm_substream *substream,
206 struct snd_pcm_hw_params *params,
207 struct snd_soc_dai *dai)
209 struct snd_soc_codec *codec = dai->codec;
210 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
211 unsigned int sampling_rate = 0;
212 unsigned int chan_sz = 0;
214 /* pcm mode configuration */
215 switch (snd_pcm_format_width(params_format(params))) {
217 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
220 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
223 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
226 dev_err(codec->dev, "format unsupported %d\n",
227 params_format(params));
231 max98373->ch_size = snd_pcm_format_width(params_format(params));
233 regmap_update_bits(max98373->regmap,
234 MAX98373_R2024_PCM_DATA_FMT_CFG,
235 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
237 dev_dbg(codec->dev, "format supported %d",
238 params_format(params));
240 /* sampling rate configuration */
241 switch (params_rate(params)) {
243 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
246 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
249 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
252 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
255 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
258 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
261 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
264 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
267 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
270 dev_err(codec->dev, "rate %d not supported\n",
271 params_rate(params));
275 /* set DAI_SR to correct LRCLK frequency */
276 regmap_update_bits(max98373->regmap,
277 MAX98373_R2027_PCM_SR_SETUP_1,
278 MAX98373_PCM_SR_SET1_SR_MASK,
280 regmap_update_bits(max98373->regmap,
281 MAX98373_R2028_PCM_SR_SETUP_2,
282 MAX98373_PCM_SR_SET2_SR_MASK,
283 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
285 /* set sampling rate of IV */
286 if (max98373->interleave_mode &&
287 sampling_rate > MAX98373_PCM_SR_SET1_SR_16000)
288 regmap_update_bits(max98373->regmap,
289 MAX98373_R2028_PCM_SR_SETUP_2,
290 MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
293 regmap_update_bits(max98373->regmap,
294 MAX98373_R2028_PCM_SR_SETUP_2,
295 MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
298 return max98373_set_clock(codec, params);
303 static int max98373_dai_tdm_slot(struct snd_soc_dai *dai,
304 unsigned int tx_mask, unsigned int rx_mask,
305 int slots, int slot_width)
307 struct snd_soc_codec *codec = dai->codec;
308 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
310 unsigned int chan_sz = 0;
314 if (!tx_mask && !rx_mask && !slots && !slot_width)
315 max98373->tdm_mode = false;
317 max98373->tdm_mode = true;
319 /* BCLK configuration */
320 bsel = max98373_get_bclk_sel(slots * slot_width);
322 dev_err(codec->dev, "BCLK %d not supported\n",
327 regmap_update_bits(max98373->regmap,
328 MAX98373_R2026_PCM_CLOCK_RATIO,
329 MAX98373_PCM_CLK_SETUP_BSEL_MASK,
332 /* Channel size configuration */
333 switch (slot_width) {
335 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
338 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
341 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
344 dev_err(codec->dev, "format unsupported %d\n",
349 regmap_update_bits(max98373->regmap,
350 MAX98373_R2024_PCM_DATA_FMT_CFG,
351 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
353 /* Rx slot configuration */
356 for (x = 0 ; x < 16 ; x++, mask >>= 1) {
359 regmap_update_bits(max98373->regmap,
360 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
361 MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x);
363 regmap_write(max98373->regmap,
364 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
372 /* Tx slot Hi-Z configuration */
373 regmap_write(max98373->regmap,
374 MAX98373_R2020_PCM_TX_HIZ_EN_1,
376 regmap_write(max98373->regmap,
377 MAX98373_R2021_PCM_TX_HIZ_EN_2,
378 (~tx_mask & 0xFF00) >> 8);
383 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
385 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
386 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
388 static const struct snd_soc_dai_ops max98373_dai_ops = {
389 .set_fmt = max98373_dai_set_fmt,
390 .hw_params = max98373_dai_hw_params,
391 .set_tdm_slot = max98373_dai_tdm_slot,
394 static int max98373_dac_event(struct snd_soc_dapm_widget *w,
395 struct snd_kcontrol *kcontrol, int event)
397 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
398 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
401 case SND_SOC_DAPM_POST_PMU:
402 regmap_update_bits(max98373->regmap,
403 MAX98373_R20FF_GLOBAL_SHDN,
404 MAX98373_GLOBAL_EN_MASK, 1);
406 case SND_SOC_DAPM_POST_PMD:
407 regmap_update_bits(max98373->regmap,
408 MAX98373_R20FF_GLOBAL_SHDN,
409 MAX98373_GLOBAL_EN_MASK, 0);
410 max98373->tdm_mode = 0;
418 static const char * const max98373_switch_text[] = {
419 "Left", "Right", "LeftRight"};
421 static const struct soc_enum dai_sel_enum =
422 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
423 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
424 3, max98373_switch_text);
426 static const struct snd_kcontrol_new max98373_dai_controls =
427 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
429 static const struct snd_kcontrol_new max98373_vi_control =
430 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
432 static const struct snd_kcontrol_new max98373_spkfb_control =
433 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
435 static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
436 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
437 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
438 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
439 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
440 &max98373_dai_controls),
441 SND_SOC_DAPM_OUTPUT("BE_OUT"),
442 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
443 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
444 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
445 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
446 SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
448 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
449 &max98373_vi_control),
450 SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
451 &max98373_spkfb_control),
452 SND_SOC_DAPM_SIGGEN("VMON"),
453 SND_SOC_DAPM_SIGGEN("IMON"),
454 SND_SOC_DAPM_SIGGEN("FBMON"),
457 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, 0, -50, 0);
458 static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
459 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
460 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
462 static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
463 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
465 static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
466 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
467 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
469 static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
470 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
472 static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
473 0, 1, TLV_DB_SCALE_ITEM(-50, -50, 0),
474 2, 7, TLV_DB_SCALE_ITEM(-200, -100, 0),
475 8, 9, TLV_DB_SCALE_ITEM(-1000, -200, 0),
476 10, 11, TLV_DB_SCALE_ITEM(-1500, -300, 0),
477 12, 13, TLV_DB_SCALE_ITEM(-2000, -200, 0),
478 14, 15, TLV_DB_SCALE_ITEM(-2500, -500, 0),
480 static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
481 0, 15, TLV_DB_SCALE_ITEM(0, -100, 0),
484 static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
485 0, 60, TLV_DB_SCALE_ITEM(0, -25, 0),
488 static bool max98373_readable_register(struct device *dev, unsigned int reg)
491 case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3:
492 case MAX98373_R2010_IRQ_CTRL:
493 case MAX98373_R2014_THERM_WARN_THRESH
494 ... MAX98373_R2018_THERM_FOLDBACK_EN:
495 case MAX98373_R201E_PIN_DRIVE_STRENGTH
496 ... MAX98373_R2036_SOUNDWIRE_CTRL:
497 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
498 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
499 ... MAX98373_R2047_IV_SENSE_ADC_EN:
500 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
501 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
502 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
503 case MAX98373_R2097_BDE_L1_THRESH
504 ... MAX98373_R209B_BDE_THRESH_HYST:
505 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
506 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
507 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
508 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
509 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
510 ... MAX98373_R20FF_GLOBAL_SHDN:
511 case MAX98373_R21FF_REV_ID:
518 static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
521 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
522 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
523 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
524 case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
525 case MAX98373_R21FF_REV_ID:
532 static const char * const max98373_output_voltage_lvl_text[] = {
533 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
534 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
537 static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
538 MAX98373_R203E_AMP_PATH_GAIN, 0,
539 max98373_output_voltage_lvl_text);
541 static const char * const max98373_dht_attack_rate_text[] = {
542 "17.5us", "35us", "70us", "140us",
543 "280us", "560us", "1120us", "2240us"
546 static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
547 MAX98373_R20D2_DHT_ATTACK_CFG, 0,
548 max98373_dht_attack_rate_text);
550 static const char * const max98373_dht_release_rate_text[] = {
551 "45ms", "225ms", "450ms", "1150ms",
552 "2250ms", "3100ms", "4500ms", "6750ms"
555 static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
556 MAX98373_R20D3_DHT_RELEASE_CFG, 0,
557 max98373_dht_release_rate_text);
559 static const char * const max98373_limiter_attack_rate_text[] = {
560 "10us", "20us", "40us", "80us",
561 "160us", "320us", "640us", "1.28ms",
562 "2.56ms", "5.12ms", "10.24ms", "20.48ms",
563 "40.96ms", "81.92ms", "16.384ms", "32.768ms"
566 static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
567 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
568 max98373_limiter_attack_rate_text);
570 static const char * const max98373_limiter_release_rate_text[] = {
571 "40us", "80us", "160us", "320us",
572 "640us", "1.28ms", "2.56ms", "5.120ms",
573 "10.24ms", "20.48ms", "40.96ms", "81.92ms",
574 "163.84ms", "327.68ms", "655.36ms", "1310.72ms"
577 static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
578 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
579 max98373_limiter_release_rate_text);
581 static const char * const max98373_ADC_samplerate_text[] = {
582 "333kHz", "192kHz", "64kHz", "48kHz"
585 static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
586 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
587 max98373_ADC_samplerate_text);
589 static const struct snd_kcontrol_new max98373_snd_controls[] = {
590 SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
591 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
592 SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
593 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
594 SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
595 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
596 SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
597 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
598 SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
599 MAX98373_CLOCK_MON_SHIFT, 1, 0),
600 SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
601 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
602 SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
603 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
604 SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
605 0, 0x7F, 0, max98373_digital_tlv),
606 SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
607 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
608 SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
609 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
610 SOC_ENUM("Output Voltage", max98373_out_volt_enum),
611 /* Dynamic Headroom Tracking */
612 SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
613 MAX98373_DHT_EN_SHIFT, 1, 0),
614 SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
615 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
616 SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
617 MAX98373_DHT_ROT_PNT_SHIFT, 15, 0, max98373_dht_rotation_point_tlv),
618 SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
619 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
620 SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
621 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
622 SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
623 SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
624 /* ADC configuration */
625 SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
626 SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
627 MAX98373_FLT_EN_SHIFT, 1, 0),
628 SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
629 MAX98373_FLT_EN_SHIFT, 1, 0),
630 SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0),
631 SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0),
632 SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
634 SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
636 SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
637 /* Brownout Detection Engine */
638 SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
639 SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
640 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
641 SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
642 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
643 SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
644 SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
645 SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
646 SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
647 SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0),
648 SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
649 SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
650 SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
651 SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
652 SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
653 SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
654 0, 0x3C, 0, max98373_bde_gain_tlv),
655 SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
656 0, 0x3C, 0, max98373_bde_gain_tlv),
657 SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
658 0, 0x3C, 0, max98373_bde_gain_tlv),
659 SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
660 0, 0x3C, 0, max98373_bde_gain_tlv),
661 SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
662 0, 0x3C, 0, max98373_bde_gain_tlv),
663 SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
664 0, 0x3C, 0, max98373_bde_gain_tlv),
665 SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
666 0, 0x3C, 0, max98373_bde_gain_tlv),
667 SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
668 0, 0x3C, 0, max98373_bde_gain_tlv),
669 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
670 0, 0xF, 0, max98373_limiter_thresh_tlv),
671 SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
672 0, 0xF, 0, max98373_limiter_thresh_tlv),
673 SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
674 0, 0xF, 0, max98373_limiter_thresh_tlv),
675 SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
676 0, 0xF, 0, max98373_limiter_thresh_tlv),
678 SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
679 MAX98373_LIMITER_EN_SHIFT, 1, 0),
680 SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
681 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
682 SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
683 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
684 SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
685 SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
688 static const struct snd_soc_dapm_route max98373_audio_map[] = {
690 {"DAI Sel Mux", "Left", "Amp Enable"},
691 {"DAI Sel Mux", "Right", "Amp Enable"},
692 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
693 {"BE_OUT", NULL, "DAI Sel Mux"},
695 { "VI Sense", "Switch", "VMON" },
696 { "VI Sense", "Switch", "IMON" },
697 { "SpkFB Sense", "Switch", "FBMON" },
698 { "Voltage Sense", NULL, "VI Sense" },
699 { "Current Sense", NULL, "VI Sense" },
700 { "Speaker FB Sense", NULL, "SpkFB Sense" },
703 static struct snd_soc_dai_driver max98373_dai[] = {
705 .name = "max98373-aif1",
707 .stream_name = "HiFi Playback",
710 .rates = MAX98373_RATES,
711 .formats = MAX98373_FORMATS,
714 .stream_name = "HiFi Capture",
717 .rates = MAX98373_RATES,
718 .formats = MAX98373_FORMATS,
720 .ops = &max98373_dai_ops,
724 static int max98373_probe(struct snd_soc_codec *codec)
726 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
728 codec->control_data = max98373->regmap;
731 regmap_write(max98373->regmap,
732 MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
734 /* IV default slot configuration */
735 regmap_write(max98373->regmap,
736 MAX98373_R2020_PCM_TX_HIZ_EN_1,
738 regmap_write(max98373->regmap,
739 MAX98373_R2021_PCM_TX_HIZ_EN_2,
741 /* L/R mix configuration */
742 regmap_write(max98373->regmap,
743 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
745 regmap_write(max98373->regmap,
746 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
748 /* Set inital volume (0dB) */
749 regmap_write(max98373->regmap,
750 MAX98373_R203D_AMP_DIG_VOL_CTRL,
752 regmap_write(max98373->regmap,
753 MAX98373_R203E_AMP_PATH_GAIN,
755 /* Enable DC blocker */
756 regmap_write(max98373->regmap,
757 MAX98373_R203F_AMP_DSP_CFG,
759 /* Enable IMON VMON DC blocker */
760 regmap_write(max98373->regmap,
761 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
763 /* voltage, current slot configuration */
764 regmap_write(max98373->regmap,
765 MAX98373_R2022_PCM_TX_SRC_1,
766 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
767 max98373->v_slot) & 0xFF);
768 if (max98373->v_slot < 8)
769 regmap_update_bits(max98373->regmap,
770 MAX98373_R2020_PCM_TX_HIZ_EN_1,
771 1 << max98373->v_slot, 0);
773 regmap_update_bits(max98373->regmap,
774 MAX98373_R2021_PCM_TX_HIZ_EN_2,
775 1 << (max98373->v_slot - 8), 0);
777 if (max98373->i_slot < 8)
778 regmap_update_bits(max98373->regmap,
779 MAX98373_R2020_PCM_TX_HIZ_EN_1,
780 1 << max98373->i_slot, 0);
782 regmap_update_bits(max98373->regmap,
783 MAX98373_R2021_PCM_TX_HIZ_EN_2,
784 1 << (max98373->i_slot - 8), 0);
786 /* speaker feedback slot configuration */
787 regmap_write(max98373->regmap,
788 MAX98373_R2023_PCM_TX_SRC_2,
789 max98373->spkfb_slot & 0xFF);
791 /* Set interleave mode */
792 if (max98373->interleave_mode)
793 regmap_update_bits(max98373->regmap,
794 MAX98373_R2024_PCM_DATA_FMT_CFG,
795 MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
796 MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
799 regmap_update_bits(max98373->regmap,
800 MAX98373_R2043_AMP_EN,
801 MAX98373_SPK_EN_MASK, 1);
806 #ifdef CONFIG_PM_SLEEP
807 static int max98373_suspend(struct device *dev)
809 struct max98373_priv *max98373 = dev_get_drvdata(dev);
811 regcache_cache_only(max98373->regmap, true);
812 regcache_mark_dirty(max98373->regmap);
815 static int max98373_resume(struct device *dev)
817 struct max98373_priv *max98373 = dev_get_drvdata(dev);
819 regmap_write(max98373->regmap,
820 MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
821 regcache_cache_only(max98373->regmap, false);
822 regcache_sync(max98373->regmap);
827 static const struct dev_pm_ops max98373_pm = {
828 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
831 static const struct snd_soc_codec_driver soc_codec_dev_max98373 = {
832 .probe = max98373_probe,
833 .component_driver = {
834 .controls = max98373_snd_controls,
835 .num_controls = ARRAY_SIZE(max98373_snd_controls),
836 .dapm_widgets = max98373_dapm_widgets,
837 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
838 .dapm_routes = max98373_audio_map,
839 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
843 static const struct regmap_config max98373_regmap = {
846 .max_register = MAX98373_R21FF_REV_ID,
847 .reg_defaults = max98373_reg,
848 .num_reg_defaults = ARRAY_SIZE(max98373_reg),
849 .readable_reg = max98373_readable_register,
850 .volatile_reg = max98373_volatile_reg,
851 .cache_type = REGCACHE_RBTREE,
854 static void max98373_slot_config(struct i2c_client *i2c,
855 struct max98373_priv *max98373)
858 struct device *dev = &i2c->dev;
860 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
861 max98373->v_slot = value & 0xF;
863 max98373->v_slot = 0;
865 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
866 max98373->i_slot = value & 0xF;
868 max98373->i_slot = 1;
870 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
871 max98373->spkfb_slot = value & 0xF;
873 max98373->spkfb_slot = 2;
876 static int max98373_i2c_probe(struct i2c_client *i2c,
877 const struct i2c_device_id *id)
882 struct max98373_priv *max98373 = NULL;
884 max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL);
890 i2c_set_clientdata(i2c, max98373);
892 /* update interleave mode info */
893 if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode"))
894 max98373->interleave_mode = 1;
896 max98373->interleave_mode = 0;
899 /* regmap initialization */
901 = devm_regmap_init_i2c(i2c, &max98373_regmap);
902 if (IS_ERR(max98373->regmap)) {
903 ret = PTR_ERR(max98373->regmap);
905 "Failed to allocate regmap: %d\n", ret);
909 /* Check Revision ID */
910 ret = regmap_read(max98373->regmap,
911 MAX98373_R21FF_REV_ID, ®);
914 "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID);
917 dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg);
919 /* voltage/current slot configuration */
920 max98373_slot_config(i2c, max98373);
922 /* codec registeration */
923 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98373,
924 max98373_dai, ARRAY_SIZE(max98373_dai));
926 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
931 static int max98373_i2c_remove(struct i2c_client *client)
933 snd_soc_unregister_codec(&client->dev);
937 static const struct i2c_device_id max98373_i2c_id[] = {
942 MODULE_DEVICE_TABLE(i2c, max98373_i2c_id);
944 #if defined(CONFIG_OF)
945 static const struct of_device_id max98373_of_match[] = {
946 { .compatible = "maxim,max98373", },
949 MODULE_DEVICE_TABLE(of, max98373_of_match);
953 static const struct acpi_device_id max98373_acpi_match[] = {
957 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
960 static struct i2c_driver max98373_i2c_driver = {
963 .of_match_table = of_match_ptr(max98373_of_match),
964 .acpi_match_table = ACPI_PTR(max98373_acpi_match),
967 .probe = max98373_i2c_probe,
968 .remove = max98373_i2c_remove,
969 .id_table = max98373_i2c_id,
972 module_i2c_driver(max98373_i2c_driver)
974 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
975 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
976 MODULE_LICENSE("GPL");