sound/soc/codecs/max98373-sdw.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // Copyright (c) 2020, Maxim Integrated
   3
   4 #include <linux/acpi.h>
   5 #include <linux/delay.h>
   6 #include <linux/module.h>
   7 #include <linux/mod_devicetable.h>
   8 #include <linux/pm_runtime.h>
   9 #include <linux/regmap.h>
  10 #include <linux/slab.h>
  11 #include <sound/pcm.h>
  12 #include <sound/pcm_params.h>
  13 #include <sound/soc.h>
  14 #include <sound/tlv.h>
  15 #include <linux/of.h>
  16 #include <linux/soundwire/sdw.h>
  17 #include <linux/soundwire/sdw_type.h>
  18 #include "max98373.h"
  19 #include "max98373-sdw.h"
  20
  21 struct sdw_stream_data {
  22         struct sdw_stream_runtime *sdw_stream;
  23 };
  24
  25 static struct reg_default max98373_reg[] = {
  26         {MAX98373_R0040_SCP_INIT_STAT_1, 0x00},
  27         {MAX98373_R0041_SCP_INIT_MASK_1, 0x00},
  28         {MAX98373_R0042_SCP_INIT_STAT_2, 0x00},
  29         {MAX98373_R0044_SCP_CTRL, 0x00},
  30         {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00},
  31         {MAX98373_R0046_SCP_DEV_NUMBER, 0x00},
  32         {MAX98373_R0050_SCP_DEV_ID_0, 0x21},
  33         {MAX98373_R0051_SCP_DEV_ID_1, 0x01},
  34         {MAX98373_R0052_SCP_DEV_ID_2, 0x9F},
  35         {MAX98373_R0053_SCP_DEV_ID_3, 0x87},
  36         {MAX98373_R0054_SCP_DEV_ID_4, 0x08},
  37         {MAX98373_R0055_SCP_DEV_ID_5, 0x00},
  38         {MAX98373_R0060_SCP_FRAME_CTLR, 0x00},
  39         {MAX98373_R0070_SCP_FRAME_CTLR, 0x00},
  40         {MAX98373_R0100_DP1_INIT_STAT, 0x00},
  41         {MAX98373_R0101_DP1_INIT_MASK, 0x00},
  42         {MAX98373_R0102_DP1_PORT_CTRL, 0x00},
  43         {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00},
  44         {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00},
  45         {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00},
  46         {MAX98373_R0120_DP1_CHANNEL_EN, 0x00},
  47         {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00},
  48         {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00},
  49         {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00},
  50         {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00},
  51         {MAX98373_R0126_DP1_HCTRL, 0x00},
  52         {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00},
  53         {MAX98373_R0130_DP1_CHANNEL_EN, 0x00},
  54         {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00},
  55         {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00},
  56         {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00},
  57         {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00},
  58         {MAX98373_R0136_DP1_HCTRL, 0x0136},
  59         {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00},
  60         {MAX98373_R0300_DP3_INIT_STAT, 0x00},
  61         {MAX98373_R0301_DP3_INIT_MASK, 0x00},
  62         {MAX98373_R0302_DP3_PORT_CTRL, 0x00},
  63         {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00},
  64         {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00},
  65         {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00},
  66         {MAX98373_R0320_DP3_CHANNEL_EN, 0x00},
  67         {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00},
  68         {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00},
  69         {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00},
  70         {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00},
  71         {MAX98373_R0326_DP3_HCTRL, 0x00},
  72         {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00},
  73         {MAX98373_R0330_DP3_CHANNEL_EN, 0x00},
  74         {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00},
  75         {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00},
  76         {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00},
  77         {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00},
  78         {MAX98373_R0336_DP3_HCTRL, 0x00},
  79         {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00},
  80         {MAX98373_R2000_SW_RESET, 0x00},
  81         {MAX98373_R2001_INT_RAW1, 0x00},
  82         {MAX98373_R2002_INT_RAW2, 0x00},
  83         {MAX98373_R2003_INT_RAW3, 0x00},
  84         {MAX98373_R2004_INT_STATE1, 0x00},
  85         {MAX98373_R2005_INT_STATE2, 0x00},
  86         {MAX98373_R2006_INT_STATE3, 0x00},
  87         {MAX98373_R2007_INT_FLAG1, 0x00},
  88         {MAX98373_R2008_INT_FLAG2, 0x00},
  89         {MAX98373_R2009_INT_FLAG3, 0x00},
  90         {MAX98373_R200A_INT_EN1, 0x00},
  91         {MAX98373_R200B_INT_EN2, 0x00},
  92         {MAX98373_R200C_INT_EN3, 0x00},
  93         {MAX98373_R200D_INT_FLAG_CLR1, 0x00},
  94         {MAX98373_R200E_INT_FLAG_CLR2, 0x00},
  95         {MAX98373_R200F_INT_FLAG_CLR3, 0x00},
  96         {MAX98373_R2010_IRQ_CTRL, 0x00},
  97         {MAX98373_R2014_THERM_WARN_THRESH, 0x10},
  98         {MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
  99         {MAX98373_R2016_THERM_HYSTERESIS, 0x01},
 100         {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
 101         {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
 102         {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
 103         {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
 104         {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
 105         {MAX98373_R2022_PCM_TX_SRC_1, 0x00},
 106         {MAX98373_R2023_PCM_TX_SRC_2, 0x00},
 107         {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
 108         {MAX98373_R2025_AUDIO_IF_MODE, 0x00},
 109         {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
 110         {MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
 111         {MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
 112         {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
 113         {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
 114         {MAX98373_R202B_PCM_RX_EN, 0x00},
 115         {MAX98373_R202C_PCM_TX_EN, 0x00},
 116         {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
 117         {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
 118         {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
 119         {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
 120         {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
 121         {MAX98373_R2034_ICC_TX_CNTL, 0x00},
 122         {MAX98373_R2035_ICC_TX_EN, 0x00},
 123         {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
 124         {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
 125         {MAX98373_R203E_AMP_PATH_GAIN, 0x08},
 126         {MAX98373_R203F_AMP_DSP_CFG, 0x02},
 127         {MAX98373_R2040_TONE_GEN_CFG, 0x00},
 128         {MAX98373_R2041_AMP_CFG, 0x03},
 129         {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
 130         {MAX98373_R2043_AMP_EN, 0x00},
 131         {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
 132         {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
 133         {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
 134         {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
 135         {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
 136         {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
 137         {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
 138         {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
 139         {MAX98373_R2090_BDE_LVL_HOLD, 0x00},
 140         {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
 141         {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
 142         {MAX98373_R2097_BDE_L1_THRESH, 0x00},
 143         {MAX98373_R2098_BDE_L2_THRESH, 0x00},
 144         {MAX98373_R2099_BDE_L3_THRESH, 0x00},
 145         {MAX98373_R209A_BDE_L4_THRESH, 0x00},
 146         {MAX98373_R209B_BDE_THRESH_HYST, 0x00},
 147         {MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
 148         {MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
 149         {MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
 150         {MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
 151         {MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
 152         {MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
 153         {MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
 154         {MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
 155         {MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
 156         {MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
 157         {MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
 158         {MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
 159         {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
 160         {MAX98373_R20B5_BDE_EN, 0x00},
 161         {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
 162         {MAX98373_R20D1_DHT_CFG, 0x01},
 163         {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
 164         {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
 165         {MAX98373_R20D4_DHT_EN, 0x00},
 166         {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
 167         {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
 168         {MAX98373_R20E2_LIMITER_EN, 0x00},
 169         {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
 170         {MAX98373_R20FF_GLOBAL_SHDN, 0x00},
 171         {MAX98373_R21FF_REV_ID, 0x42},
 172 };
 173
 174 static bool max98373_readable_register(struct device *dev, unsigned int reg)
 175 {
 176         switch (reg) {
 177         case MAX98373_R21FF_REV_ID:
 178         case MAX98373_R2010_IRQ_CTRL:
 179         /* SoundWire Control Port Registers */
 180         case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
 181         /* Soundwire Data Port 1 Registers */
 182         case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
 183         /* Soundwire Data Port 3 Registers */
 184         case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
 185         case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3:
 186         case MAX98373_R2014_THERM_WARN_THRESH
 187                 ... MAX98373_R2018_THERM_FOLDBACK_EN:
 188         case MAX98373_R201E_PIN_DRIVE_STRENGTH
 189                 ... MAX98373_R2036_SOUNDWIRE_CTRL:
 190         case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
 191         case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
 192                 ... MAX98373_R2047_IV_SENSE_ADC_EN:
 193         case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
 194                 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
 195         case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
 196         case MAX98373_R2097_BDE_L1_THRESH
 197                 ... MAX98373_R209B_BDE_THRESH_HYST:
 198         case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
 199         case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 200         case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
 201         case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
 202         case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
 203                 ... MAX98373_R20FF_GLOBAL_SHDN:
 204                 return true;
 205         default:
 206                 return false;
 207         }
 208 };
 209
 210 static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
 211 {
 212         switch (reg) {
 213         case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
 214         case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
 215         case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
 216         case MAX98373_R21FF_REV_ID:
 217         /* SoundWire Control Port Registers */
 218         case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR:
 219         /* Soundwire Data Port 1 Registers */
 220         case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3:
 221         /* Soundwire Data Port 3 Registers */
 222         case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3:
 223         case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
 224                 return true;
 225         default:
 226                 return false;
 227         }
 228 }
 229
 230 static const struct regmap_config max98373_sdw_regmap = {
 231         .reg_bits = 32,
 232         .val_bits = 8,
 233         .max_register = MAX98373_R21FF_REV_ID,
 234         .reg_defaults  = max98373_reg,
 235         .num_reg_defaults = ARRAY_SIZE(max98373_reg),
 236         .readable_reg = max98373_readable_register,
 237         .volatile_reg = max98373_volatile_reg,
 238         .cache_type = REGCACHE_RBTREE,
 239         .use_single_read = true,
 240         .use_single_write = true,
 241 };
 242
 243 /* Power management functions and structure */
 244 static __maybe_unused int max98373_suspend(struct device *dev)
 245 {
 246         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 247
 248         regcache_cache_only(max98373->regmap, true);
 249         regcache_mark_dirty(max98373->regmap);
 250         return 0;
 251 }
 252
 253 static __maybe_unused int max98373_resume(struct device *dev)
 254 {
 255         struct sdw_slave *slave = dev_to_sdw_dev(dev);
 256         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 257         unsigned long time;
 258
 259         if (!slave->unattach_request)
 260                 goto regmap_sync;
 261
 262         time = wait_for_completion_timeout(&slave->initialization_complete,
 263                                            msecs_to_jiffies(2000));
 264         if (!time) {
 265                 dev_err(dev, "Initialization not complete, timed out\n");
 266                 return -ETIMEDOUT;
 267         }
 268
 269 regmap_sync:
 270         slave->unattach_request = 0;
 271         regcache_cache_only(max98373->regmap, false);
 272         regcache_sync(max98373->regmap);
 273
 274         return 0;
 275 }
 276
 277 static const struct dev_pm_ops max98373_pm = {
 278         SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
 279         SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL)
 280 };
 281
 282 static int max98373_read_prop(struct sdw_slave *slave)
 283 {
 284         struct sdw_slave_prop *prop = &slave->prop;
 285         int nval, i, num_of_ports;
 286         u32 bit;
 287         unsigned long addr;
 288         struct sdw_dpn_prop *dpn;
 289
 290         /* BITMAP: 00001000  Dataport 3 is active */
 291         prop->source_ports = BIT(3);
 292         /* BITMAP: 00000010  Dataport 1 is active */
 293         prop->sink_ports = BIT(1);
 294         prop->paging_support = true;
 295         prop->clk_stop_timeout = 20;
 296
 297         nval = hweight32(prop->source_ports);
 298         num_of_ports = nval;
 299         prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
 300                                           sizeof(*prop->src_dpn_prop),
 301                                           GFP_KERNEL);
 302         if (!prop->src_dpn_prop)
 303                 return -ENOMEM;
 304
 305         i = 0;
 306         dpn = prop->src_dpn_prop;
 307         addr = prop->source_ports;
 308         for_each_set_bit(bit, &addr, 32) {
 309                 dpn[i].num = bit;
 310                 dpn[i].type = SDW_DPN_FULL;
 311                 dpn[i].simple_ch_prep_sm = true;
 312                 dpn[i].ch_prep_timeout = 10;
 313                 i++;
 314         }
 315
 316         /* do this again for sink now */
 317         nval = hweight32(prop->sink_ports);
 318         num_of_ports += nval;
 319         prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
 320                                            sizeof(*prop->sink_dpn_prop),
 321                                            GFP_KERNEL);
 322         if (!prop->sink_dpn_prop)
 323                 return -ENOMEM;
 324
 325         i = 0;
 326         dpn = prop->sink_dpn_prop;
 327         addr = prop->sink_ports;
 328         for_each_set_bit(bit, &addr, 32) {
 329                 dpn[i].num = bit;
 330                 dpn[i].type = SDW_DPN_FULL;
 331                 dpn[i].simple_ch_prep_sm = true;
 332                 dpn[i].ch_prep_timeout = 10;
 333                 i++;
 334         }
 335
 336         /* Allocate port_ready based on num_of_ports */
 337         slave->port_ready = devm_kcalloc(&slave->dev, num_of_ports,
 338                                          sizeof(*slave->port_ready),
 339                                          GFP_KERNEL);
 340         if (!slave->port_ready)
 341                 return -ENOMEM;
 342
 343         /* Initialize completion */
 344         for (i = 0; i < num_of_ports; i++)
 345                 init_completion(&slave->port_ready[i]);
 346
 347         /* set the timeout values */
 348         prop->clk_stop_timeout = 20;
 349
 350         return 0;
 351 }
 352
 353 static int max98373_io_init(struct sdw_slave *slave)
 354 {
 355         struct device *dev = &slave->dev;
 356         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 357
 358         if (max98373->pm_init_once) {
 359                 regcache_cache_only(max98373->regmap, false);
 360                 regcache_cache_bypass(max98373->regmap, true);
 361         }
 362
 363         /*
 364          * PM runtime is only enabled when a Slave reports as Attached
 365          */
 366         if (!max98373->pm_init_once) {
 367                 /* set autosuspend parameters */
 368                 pm_runtime_set_autosuspend_delay(dev, 3000);
 369                 pm_runtime_use_autosuspend(dev);
 370
 371                 /* update count of parent 'active' children */
 372                 pm_runtime_set_active(dev);
 373
 374                 /* make sure the device does not suspend immediately */
 375                 pm_runtime_mark_last_busy(dev);
 376
 377                 pm_runtime_enable(dev);
 378         }
 379
 380         pm_runtime_get_noresume(dev);
 381
 382         /* Software Reset */
 383         max98373_reset(max98373, dev);
 384
 385         /* Set soundwire mode */
 386         regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3);
 387         /* Enable ADC */
 388         regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3);
 389         /* Set default Soundwire clock */
 390         regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5);
 391         /* Set default sampling rate for speaker and IVDAC */
 392         regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
 393         /* IV default slot configuration */
 394         regmap_write(max98373->regmap,
 395                      MAX98373_R2020_PCM_TX_HIZ_EN_1,
 396                      0xFF);
 397         regmap_write(max98373->regmap,
 398                      MAX98373_R2021_PCM_TX_HIZ_EN_2,
 399                      0xFF);
 400         /* L/R mix configuration */
 401         regmap_write(max98373->regmap,
 402                      MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
 403                      0x80);
 404         regmap_write(max98373->regmap,
 405                      MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
 406                      0x1);
 407         /* Enable DC blocker */
 408         regmap_write(max98373->regmap,
 409                      MAX98373_R203F_AMP_DSP_CFG,
 410                      0x3);
 411         /* Enable IMON VMON DC blocker */
 412         regmap_write(max98373->regmap,
 413                      MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
 414                      0x7);
 415         /* voltage, current slot configuration */
 416         regmap_write(max98373->regmap,
 417                      MAX98373_R2022_PCM_TX_SRC_1,
 418                      (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
 419                      max98373->v_slot) & 0xFF);
 420         if (max98373->v_slot < 8)
 421                 regmap_update_bits(max98373->regmap,
 422                                    MAX98373_R2020_PCM_TX_HIZ_EN_1,
 423                                    1 << max98373->v_slot, 0);
 424         else
 425                 regmap_update_bits(max98373->regmap,
 426                                    MAX98373_R2021_PCM_TX_HIZ_EN_2,
 427                                    1 << (max98373->v_slot - 8), 0);
 428
 429         if (max98373->i_slot < 8)
 430                 regmap_update_bits(max98373->regmap,
 431                                    MAX98373_R2020_PCM_TX_HIZ_EN_1,
 432                                    1 << max98373->i_slot, 0);
 433         else
 434                 regmap_update_bits(max98373->regmap,
 435                                    MAX98373_R2021_PCM_TX_HIZ_EN_2,
 436                                    1 << (max98373->i_slot - 8), 0);
 437
 438         /* speaker feedback slot configuration */
 439         regmap_write(max98373->regmap,
 440                      MAX98373_R2023_PCM_TX_SRC_2,
 441                      max98373->spkfb_slot & 0xFF);
 442
 443         /* Set interleave mode */
 444         if (max98373->interleave_mode)
 445                 regmap_update_bits(max98373->regmap,
 446                                    MAX98373_R2024_PCM_DATA_FMT_CFG,
 447                                    MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
 448                                    MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
 449
 450         /* Speaker enable */
 451         regmap_update_bits(max98373->regmap,
 452                            MAX98373_R2043_AMP_EN,
 453                            MAX98373_SPK_EN_MASK, 1);
 454
 455         regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1);
 456         regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1);
 457
 458         if (max98373->pm_init_once) {
 459                 regcache_cache_bypass(max98373->regmap, false);
 460                 regcache_mark_dirty(max98373->regmap);
 461         }
 462
 463         max98373->pm_init_once = true;
 464         max98373->hw_init = true;
 465
 466         pm_runtime_mark_last_busy(dev);
 467         pm_runtime_put_autosuspend(dev);
 468
 469         return 0;
 470 }
 471
 472 static int max98373_clock_calculate(struct sdw_slave *slave,
 473                                     unsigned int clk_freq)
 474 {
 475         int x, y;
 476         static const int max98373_clk_family[] = {
 477                 7680000, 8400000, 9600000, 11289600,
 478                 12000000, 12288000, 13000000
 479         };
 480
 481         for (x = 0; x < 4; x++)
 482                 for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++)
 483                         if (clk_freq == (max98373_clk_family[y] >> x))
 484                                 return (x << 3) + y;
 485
 486         /* Set default clock (12.288 Mhz) if the value is not in the list */
 487         dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n",
 488                 clk_freq);
 489         return 0x5;
 490 }
 491
 492 static int max98373_clock_config(struct sdw_slave *slave,
 493                                  struct sdw_bus_params *params)
 494 {
 495         struct device *dev = &slave->dev;
 496         struct max98373_priv *max98373 = dev_get_drvdata(dev);
 497         unsigned int clk_freq, value;
 498
 499         clk_freq = (params->curr_dr_freq >> 1);
 500
 501         /*
 502          *      Select the proper value for the register based on the
 503          *      requested clock. If the value is not in the list,
 504          *      use reasonable default - 12.288 Mhz
 505          */
 506         value = max98373_clock_calculate(slave, clk_freq);
 507
 508         /* SWCLK */
 509         regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value);
 510
 511         /* The default Sampling Rate value for IV is 48KHz*/
 512         regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88);
 513
 514         return 0;
 515 }
 516
 517 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
 518 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
 519
 520 static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream,
 521                                       struct snd_pcm_hw_params *params,
 522                                       struct snd_soc_dai *dai)
 523 {
 524         struct snd_soc_component *component = dai->component;
 525         struct max98373_priv *max98373 =
 526                 snd_soc_component_get_drvdata(component);
 527
 528         struct sdw_stream_config stream_config;
 529         struct sdw_port_config port_config;
 530         enum sdw_data_direction direction;
 531         struct sdw_stream_data *stream;
 532         int ret, chan_sz, sampling_rate;
 533
 534         stream = snd_soc_dai_get_dma_data(dai, substream);
 535
 536         if (!stream)
 537                 return -EINVAL;
 538
 539         if (!max98373->slave)
 540                 return -EINVAL;
 541
 542         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 543                 direction = SDW_DATA_DIR_RX;
 544                 port_config.num = 1;
 545         } else {
 546                 direction = SDW_DATA_DIR_TX;
 547                 port_config.num = 3;
 548         }
 549
 550         stream_config.frame_rate = params_rate(params);
 551         stream_config.bps = snd_pcm_format_width(params_format(params));
 552         stream_config.direction = direction;
 553
 554         if (max98373->slot && direction == SDW_DATA_DIR_RX) {
 555                 stream_config.ch_count = max98373->slot;
 556                 port_config.ch_mask = max98373->rx_mask;
 557         } else {
 558                 /* only IV are supported by capture */
 559                 if (direction == SDW_DATA_DIR_TX)
 560                         stream_config.ch_count = 2;
 561                 else
 562                         stream_config.ch_count = params_channels(params);
 563
 564                 port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0);
 565         }
 566
 567         ret = sdw_stream_add_slave(max98373->slave, &stream_config,
 568                                    &port_config, 1, stream->sdw_stream);
 569         if (ret) {
 570                 dev_err(dai->dev, "Unable to configure port\n");
 571                 return ret;
 572         }
 573
 574         if (params_channels(params) > 16) {
 575                 dev_err(component->dev, "Unsupported channels %d\n",
 576                         params_channels(params));
 577                 return -EINVAL;
 578         }
 579
 580         /* Channel size configuration */
 581         switch (snd_pcm_format_width(params_format(params))) {
 582         case 16:
 583                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
 584                 break;
 585         case 24:
 586                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
 587                 break;
 588         case 32:
 589                 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
 590                 break;
 591         default:
 592                 dev_err(component->dev, "Channel size unsupported %d\n",
 593                         params_format(params));
 594                 return -EINVAL;
 595         }
 596
 597         max98373->ch_size = snd_pcm_format_width(params_format(params));
 598
 599         regmap_update_bits(max98373->regmap,
 600                            MAX98373_R2024_PCM_DATA_FMT_CFG,
 601                            MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
 602
 603         dev_dbg(component->dev, "Format supported %d", params_format(params));
 604
 605         /* Sampling rate configuration */
 606         switch (params_rate(params)) {
 607         case 8000:
 608                 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
 609                 break;
 610         case 11025:
 611                 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
 612                 break;
 613         case 12000:
 614                 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
 615                 break;
 616         case 16000:
 617                 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
 618                 break;
 619         case 22050:
 620                 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
 621                 break;
 622         case 24000:
 623                 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
 624                 break;
 625         case 32000:
 626                 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
 627                 break;
 628         case 44100:
 629                 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
 630                 break;
 631         case 48000:
 632                 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
 633                 break;
 634         case 88200:
 635                 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200;
 636                 break;
 637         case 96000:
 638                 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000;
 639                 break;
 640         default:
 641                 dev_err(component->dev, "Rate %d is not supported\n",
 642                         params_rate(params));
 643                 return -EINVAL;
 644         }
 645
 646         /* set correct sampling frequency */
 647         regmap_update_bits(max98373->regmap,
 648                            MAX98373_R2028_PCM_SR_SETUP_2,
 649                            MAX98373_PCM_SR_SET2_SR_MASK,
 650                            sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
 651
 652         /* set sampling rate of IV */
 653         regmap_update_bits(max98373->regmap,
 654                            MAX98373_R2028_PCM_SR_SETUP_2,
 655                            MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
 656                            sampling_rate);
 657
 658         return 0;
 659 }
 660
 661 static int max98373_pcm_hw_free(struct snd_pcm_substream *substream,
 662                                 struct snd_soc_dai *dai)
 663 {
 664         struct snd_soc_component *component = dai->component;
 665         struct max98373_priv *max98373 =
 666                 snd_soc_component_get_drvdata(component);
 667         struct sdw_stream_data *stream =
 668                 snd_soc_dai_get_dma_data(dai, substream);
 669
 670         if (!max98373->slave)
 671                 return -EINVAL;
 672
 673         sdw_stream_remove_slave(max98373->slave, stream->sdw_stream);
 674         return 0;
 675 }
 676
 677 static int max98373_set_sdw_stream(struct snd_soc_dai *dai,
 678                                    void *sdw_stream, int direction)
 679 {
 680         struct sdw_stream_data *stream;
 681
 682         if (!sdw_stream)
 683                 return 0;
 684
 685         stream = kzalloc(sizeof(*stream), GFP_KERNEL);
 686         if (!stream)
 687                 return -ENOMEM;
 688
 689         stream->sdw_stream = sdw_stream;
 690
 691         /* Use tx_mask or rx_mask to configure stream tag and set dma_data */
 692         if (direction == SNDRV_PCM_STREAM_PLAYBACK)
 693                 dai->playback_dma_data = stream;
 694         else
 695                 dai->capture_dma_data = stream;
 696
 697         return 0;
 698 }
 699
 700 static void max98373_shutdown(struct snd_pcm_substream *substream,
 701                               struct snd_soc_dai *dai)
 702 {
 703         struct sdw_stream_data *stream;
 704
 705         stream = snd_soc_dai_get_dma_data(dai, substream);
 706         snd_soc_dai_set_dma_data(dai, substream, NULL);
 707         kfree(stream);
 708 }
 709
 710 static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai,
 711                                      unsigned int tx_mask,
 712                                      unsigned int rx_mask,
 713                                      int slots, int slot_width)
 714 {
 715         struct snd_soc_component *component = dai->component;
 716         struct max98373_priv *max98373 =
 717                 snd_soc_component_get_drvdata(component);
 718
 719         /* tx_mask is unused since it's irrelevant for I/V feedback */
 720         if (tx_mask)
 721                 return -EINVAL;
 722
 723         if (!rx_mask && !slots && !slot_width)
 724                 max98373->tdm_mode = false;
 725         else
 726                 max98373->tdm_mode = true;
 727
 728         max98373->rx_mask = rx_mask;
 729         max98373->slot = slots;
 730
 731         return 0;
 732 }
 733
 734 static const struct snd_soc_dai_ops max98373_dai_sdw_ops = {
 735         .hw_params = max98373_sdw_dai_hw_params,
 736         .hw_free = max98373_pcm_hw_free,
 737         .set_sdw_stream = max98373_set_sdw_stream,
 738         .shutdown = max98373_shutdown,
 739         .set_tdm_slot = max98373_sdw_set_tdm_slot,
 740 };
 741
 742 static struct snd_soc_dai_driver max98373_sdw_dai[] = {
 743         {
 744                 .name = "max98373-aif1",
 745                 .playback = {
 746                         .stream_name = "HiFi Playback",
 747                         .channels_min = 1,
 748                         .channels_max = 2,
 749                         .rates = MAX98373_RATES,
 750                         .formats = MAX98373_FORMATS,
 751                 },
 752                 .capture = {
 753                         .stream_name = "HiFi Capture",
 754                         .channels_min = 1,
 755                         .channels_max = 2,
 756                         .rates = MAX98373_RATES,
 757                         .formats = MAX98373_FORMATS,
 758                 },
 759                 .ops = &max98373_dai_sdw_ops,
 760         }
 761 };
 762
 763 static int max98373_init(struct sdw_slave *slave, struct regmap *regmap)
 764 {
 765         struct max98373_priv *max98373;
 766         int ret;
 767         struct device *dev = &slave->dev;
 768
 769         /*  Allocate and assign private driver data structure  */
 770         max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL);
 771         if (!max98373)
 772                 return -ENOMEM;
 773
 774         dev_set_drvdata(dev, max98373);
 775         max98373->regmap = regmap;
 776         max98373->slave = slave;
 777
 778         /* Read voltage and slot configuration */
 779         max98373_slot_config(dev, max98373);
 780
 781         max98373->hw_init = false;
 782         max98373->pm_init_once = false;
 783
 784         /* codec registration  */
 785         ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw,
 786                                               max98373_sdw_dai,
 787                                               ARRAY_SIZE(max98373_sdw_dai));
 788         if (ret < 0)
 789                 dev_err(dev, "Failed to register codec: %d\n", ret);
 790
 791         return ret;
 792 }
 793
 794 static int max98373_update_status(struct sdw_slave *slave,
 795                                   enum sdw_slave_status status)
 796 {
 797         struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev);
 798
 799         if (status == SDW_SLAVE_UNATTACHED)
 800                 max98373->hw_init = false;
 801
 802         /*
 803          * Perform initialization only if slave status is SDW_SLAVE_ATTACHED
 804          */
 805         if (max98373->hw_init || status != SDW_SLAVE_ATTACHED)
 806                 return 0;
 807
 808         /* perform I/O transfers required for Slave initialization */
 809         return max98373_io_init(slave);
 810 }
 811
 812 static int max98373_bus_config(struct sdw_slave *slave,
 813                                struct sdw_bus_params *params)
 814 {
 815         int ret;
 816
 817         ret = max98373_clock_config(slave, params);
 818         if (ret < 0)
 819                 dev_err(&slave->dev, "Invalid clk config");
 820
 821         return ret;
 822 }
 823
 824 /*
 825  * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
 826  * port_prep are not defined for now
 827  */
 828 static struct sdw_slave_ops max98373_slave_ops = {
 829         .read_prop = max98373_read_prop,
 830         .update_status = max98373_update_status,
 831         .bus_config = max98373_bus_config,
 832 };
 833
 834 static int max98373_sdw_probe(struct sdw_slave *slave,
 835                               const struct sdw_device_id *id)
 836 {
 837         struct regmap *regmap;
 838
 839         /* Regmap Initialization */
 840         regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap);
 841         if (!regmap)
 842                 return -EINVAL;
 843
 844         return max98373_init(slave, regmap);
 845 }
 846
 847 #if defined(CONFIG_OF)
 848 static const struct of_device_id max98373_of_match[] = {
 849         { .compatible = "maxim,max98373", },
 850         {},
 851 };
 852 MODULE_DEVICE_TABLE(of, max98373_of_match);
 853 #endif
 854
 855 #ifdef CONFIG_ACPI
 856 static const struct acpi_device_id max98373_acpi_match[] = {
 857         { "MX98373", 0 },
 858         {},
 859 };
 860 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
 861 #endif
 862
 863 static const struct sdw_device_id max98373_id[] = {
 864         SDW_SLAVE_ENTRY(0x019F, 0x8373, 0),
 865         {},
 866 };
 867 MODULE_DEVICE_TABLE(sdw, max98373_id);
 868
 869 static struct sdw_driver max98373_sdw_driver = {
 870         .driver = {
 871                 .name = "max98373",
 872                 .owner = THIS_MODULE,
 873                 .of_match_table = of_match_ptr(max98373_of_match),
 874                 .acpi_match_table = ACPI_PTR(max98373_acpi_match),
 875                 .pm = &max98373_pm,
 876         },
 877         .probe = max98373_sdw_probe,
 878         .remove = NULL,
 879         .ops = &max98373_slave_ops,
 880         .id_table = max98373_id,
 881 };
 882
 883 module_sdw_driver(max98373_sdw_driver);
 884
 885 MODULE_DESCRIPTION("ASoC MAX98373 driver SDW");
 886 MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>");
 887 MODULE_LICENSE("GPL v2");