1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
8 #include <linux/acpi.h>
10 #include <linux/delay.h>
11 #include <linux/i2c.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 #include <sound/jack.h>
20 #include <sound/max98090.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/soc.h>
24 #include <sound/tlv.h>
27 static void max98090_shdn_save_locked(struct max98090_priv *max98090)
31 /* saved_shdn, saved_count, SHDN are protected by card->dapm_mutex */
32 regmap_read(max98090->regmap, M98090_REG_DEVICE_SHUTDOWN, &shdn);
33 max98090->saved_shdn |= shdn;
34 ++max98090->saved_count;
37 regmap_write(max98090->regmap, M98090_REG_DEVICE_SHUTDOWN, 0x0);
40 static void max98090_shdn_restore_locked(struct max98090_priv *max98090)
42 /* saved_shdn, saved_count, SHDN are protected by card->dapm_mutex */
43 if (--max98090->saved_count == 0) {
44 if (max98090->saved_shdn) {
45 regmap_write(max98090->regmap,
46 M98090_REG_DEVICE_SHUTDOWN,
48 max98090->saved_shdn = 0;
53 static void max98090_shdn_save(struct max98090_priv *max98090)
55 mutex_lock_nested(&max98090->component->card->dapm_mutex,
56 SND_SOC_DAPM_CLASS_RUNTIME);
57 max98090_shdn_save_locked(max98090);
60 static void max98090_shdn_restore(struct max98090_priv *max98090)
62 max98090_shdn_restore_locked(max98090);
63 mutex_unlock(&max98090->component->card->dapm_mutex);
66 static int max98090_put_volsw(struct snd_kcontrol *kcontrol,
67 struct snd_ctl_elem_value *ucontrol)
69 struct snd_soc_component *component =
70 snd_soc_kcontrol_component(kcontrol);
71 struct max98090_priv *max98090 =
72 snd_soc_component_get_drvdata(component);
75 max98090_shdn_save(max98090);
76 ret = snd_soc_put_volsw(kcontrol, ucontrol);
77 max98090_shdn_restore(max98090);
82 static int max98090_dapm_put_enum_double(struct snd_kcontrol *kcontrol,
83 struct snd_ctl_elem_value *ucontrol)
85 struct snd_soc_component *component =
86 snd_soc_dapm_kcontrol_component(kcontrol);
87 struct max98090_priv *max98090 =
88 snd_soc_component_get_drvdata(component);
91 max98090_shdn_save(max98090);
92 ret = snd_soc_dapm_put_enum_double_locked(kcontrol, ucontrol);
93 max98090_shdn_restore(max98090);
98 static int max98090_put_enum_double(struct snd_kcontrol *kcontrol,
99 struct snd_ctl_elem_value *ucontrol)
101 struct snd_soc_component *component =
102 snd_soc_kcontrol_component(kcontrol);
103 struct max98090_priv *max98090 =
104 snd_soc_component_get_drvdata(component);
107 max98090_shdn_save(max98090);
108 ret = snd_soc_put_enum_double(kcontrol, ucontrol);
109 max98090_shdn_restore(max98090);
114 static int max98090_bytes_put(struct snd_kcontrol *kcontrol,
115 struct snd_ctl_elem_value *ucontrol)
117 struct snd_soc_component *component =
118 snd_soc_kcontrol_component(kcontrol);
119 struct max98090_priv *max98090 =
120 snd_soc_component_get_drvdata(component);
123 max98090_shdn_save(max98090);
124 ret = snd_soc_bytes_put(kcontrol, ucontrol);
125 max98090_shdn_restore(max98090);
130 static int max98090_dapm_event(struct snd_soc_dapm_widget *w,
131 struct snd_kcontrol *kcontrol, int event)
133 struct snd_soc_component *component =
134 snd_soc_dapm_to_component(w->dapm);
135 struct max98090_priv *max98090 =
136 snd_soc_component_get_drvdata(component);
139 case SND_SOC_DAPM_PRE_PMU:
140 case SND_SOC_DAPM_PRE_PMD:
141 max98090_shdn_save_locked(max98090);
143 case SND_SOC_DAPM_POST_PMU:
144 case SND_SOC_DAPM_POST_PMD:
145 max98090_shdn_restore_locked(max98090);
152 /* Allows for sparsely populated register maps */
153 static const struct reg_default max98090_reg[] = {
154 { 0x00, 0x00 }, /* 00 Software Reset */
155 { 0x03, 0x04 }, /* 03 Interrupt Masks */
156 { 0x04, 0x00 }, /* 04 System Clock Quick */
157 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
158 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
159 { 0x07, 0x00 }, /* 07 DAC Path Quick */
160 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
161 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
162 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
163 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
164 { 0x0C, 0x00 }, /* 0C Reserved */
165 { 0x0D, 0x00 }, /* 0D Input Config */
166 { 0x0E, 0x1B }, /* 0E Line Input Level */
167 { 0x0F, 0x00 }, /* 0F Line Config */
169 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
170 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
171 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
172 { 0x13, 0x00 }, /* 13 Digital Mic Config */
173 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
174 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
175 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
176 { 0x17, 0x03 }, /* 17 Left ADC Level */
177 { 0x18, 0x03 }, /* 18 Right ADC Level */
178 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
179 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
180 { 0x1B, 0x00 }, /* 1B System Clock */
181 { 0x1C, 0x00 }, /* 1C Clock Mode */
182 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
183 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
184 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
186 { 0x20, 0x00 }, /* 20 Any Clock 4 */
187 { 0x21, 0x00 }, /* 21 Master Mode */
188 { 0x22, 0x00 }, /* 22 Interface Format */
189 { 0x23, 0x00 }, /* 23 TDM Format 1*/
190 { 0x24, 0x00 }, /* 24 TDM Format 2*/
191 { 0x25, 0x00 }, /* 25 I/O Configuration */
192 { 0x26, 0x80 }, /* 26 Filter Config */
193 { 0x27, 0x00 }, /* 27 DAI Playback Level */
194 { 0x28, 0x00 }, /* 28 EQ Playback Level */
195 { 0x29, 0x00 }, /* 29 Left HP Mixer */
196 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
197 { 0x2B, 0x00 }, /* 2B HP Control */
198 { 0x2C, 0x1A }, /* 2C Left HP Volume */
199 { 0x2D, 0x1A }, /* 2D Right HP Volume */
200 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
201 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
203 { 0x30, 0x00 }, /* 30 Spk Control */
204 { 0x31, 0x2C }, /* 31 Left Spk Volume */
205 { 0x32, 0x2C }, /* 32 Right Spk Volume */
206 { 0x33, 0x00 }, /* 33 ALC Timing */
207 { 0x34, 0x00 }, /* 34 ALC Compressor */
208 { 0x35, 0x00 }, /* 35 ALC Expander */
209 { 0x36, 0x00 }, /* 36 ALC Gain */
210 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
211 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
212 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
213 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
214 { 0x3B, 0x00 }, /* 3B Line OutR Control */
215 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
216 { 0x3D, 0x00 }, /* 3D Jack Detect */
217 { 0x3E, 0x00 }, /* 3E Input Enable */
218 { 0x3F, 0x00 }, /* 3F Output Enable */
220 { 0x40, 0x00 }, /* 40 Level Control */
221 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
222 { 0x42, 0x00 }, /* 42 Bias Control */
223 { 0x43, 0x00 }, /* 43 DAC Control */
224 { 0x44, 0x06 }, /* 44 ADC Control */
225 { 0x45, 0x00 }, /* 45 Device Shutdown */
226 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
227 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
228 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
229 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
230 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
231 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
232 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
233 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
234 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
235 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
237 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
238 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
239 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
240 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
241 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
242 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
243 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
244 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
245 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
246 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
247 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
248 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
249 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
250 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
251 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
252 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
254 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
255 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
256 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
257 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
258 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
259 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
260 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
261 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
262 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
263 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
264 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
265 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
266 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
267 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
268 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
269 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
271 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
272 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
273 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
274 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
275 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
276 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
277 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
278 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
279 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
280 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
281 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
282 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
283 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
284 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
285 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
286 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
288 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
289 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
290 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
291 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
292 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
293 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
294 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
295 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
296 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
297 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
298 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
299 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
300 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
301 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
302 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
303 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
305 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
306 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
307 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
308 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
309 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
310 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
311 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
312 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
313 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
314 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
315 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
316 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
317 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
318 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
319 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
320 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
322 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
323 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
324 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
325 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
326 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
327 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
328 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
329 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
330 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
331 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
332 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
333 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
334 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
335 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
336 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
337 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
339 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
340 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
341 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
342 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
343 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
344 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
345 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
346 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
347 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
348 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
349 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
350 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
351 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
352 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
353 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
354 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
356 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
357 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
358 { 0xC2, 0x00 }, /* C2 Sample Rate */
359 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
360 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
361 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
362 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
363 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
364 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
365 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
366 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
367 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
368 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
369 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
370 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
371 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
373 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
374 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
377 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
380 case M98090_REG_SOFTWARE_RESET:
381 case M98090_REG_DEVICE_STATUS:
382 case M98090_REG_JACK_STATUS:
383 case M98090_REG_REVISION_ID:
390 static bool max98090_readable_register(struct device *dev, unsigned int reg)
393 case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S:
394 case M98090_REG_LINE_INPUT_CONFIG ... 0xD1:
395 case M98090_REG_REVISION_ID:
402 static int max98090_reset(struct max98090_priv *max98090)
406 /* Reset the codec by writing to this write-only reset register */
407 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
408 M98090_SWRESET_MASK);
410 dev_err(max98090->component->dev,
411 "Failed to reset codec: %d\n", ret);
419 static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv,
420 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
421 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
424 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
426 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
429 static const DECLARE_TLV_DB_RANGE(max98090_line_tlv,
430 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
431 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0)
434 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
435 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
437 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
438 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
440 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
441 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
442 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
443 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
445 static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv,
446 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
447 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
450 static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv,
451 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
452 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
453 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
454 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
455 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
458 static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv,
459 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
460 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
461 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
462 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
463 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0)
466 static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv,
467 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
468 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
469 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
470 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
471 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
474 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
475 struct snd_ctl_elem_value *ucontrol)
477 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
478 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
479 struct soc_mixer_control *mc =
480 (struct soc_mixer_control *)kcontrol->private_value;
481 unsigned int mask = (1 << fls(mc->max)) - 1;
482 unsigned int val = snd_soc_component_read32(component, mc->reg);
483 unsigned int *select;
486 case M98090_REG_MIC1_INPUT_LEVEL:
487 select = &(max98090->pa1en);
489 case M98090_REG_MIC2_INPUT_LEVEL:
490 select = &(max98090->pa2en);
492 case M98090_REG_ADC_SIDETONE:
493 select = &(max98090->sidetone);
499 val = (val >> mc->shift) & mask;
502 /* If on, return the volume */
506 /* If off, return last stored value */
510 ucontrol->value.integer.value[0] = val;
514 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
515 struct snd_ctl_elem_value *ucontrol)
517 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
518 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
519 struct soc_mixer_control *mc =
520 (struct soc_mixer_control *)kcontrol->private_value;
521 unsigned int mask = (1 << fls(mc->max)) - 1;
522 unsigned int sel = ucontrol->value.integer.value[0];
523 unsigned int val = snd_soc_component_read32(component, mc->reg);
524 unsigned int *select;
527 case M98090_REG_MIC1_INPUT_LEVEL:
528 select = &(max98090->pa1en);
530 case M98090_REG_MIC2_INPUT_LEVEL:
531 select = &(max98090->pa2en);
533 case M98090_REG_ADC_SIDETONE:
534 select = &(max98090->sidetone);
540 val = (val >> mc->shift) & mask;
544 /* Setting a volume is only valid if it is already On */
548 /* Write what was already there */
552 snd_soc_component_update_bits(component, mc->reg,
559 static const char *max98090_perf_pwr_text[] =
560 { "High Performance", "Low Power" };
561 static const char *max98090_pwr_perf_text[] =
562 { "Low Power", "High Performance" };
564 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
565 M98090_REG_BIAS_CONTROL,
566 M98090_VCM_MODE_SHIFT,
567 max98090_pwr_perf_text);
569 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
571 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
572 M98090_REG_ADC_CONTROL,
574 max98090_osr128_text);
576 static const char *max98090_mode_text[] = { "Voice", "Music" };
578 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
579 M98090_REG_FILTER_CONFIG,
583 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
584 M98090_REG_FILTER_CONFIG,
585 M98090_FLT_DMIC34MODE_SHIFT,
588 static const char *max98090_drcatk_text[] =
589 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
591 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
592 M98090_REG_DRC_TIMING,
594 max98090_drcatk_text);
596 static const char *max98090_drcrls_text[] =
597 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
599 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
600 M98090_REG_DRC_TIMING,
602 max98090_drcrls_text);
604 static const char *max98090_alccmp_text[] =
605 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
607 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
608 M98090_REG_DRC_COMPRESSOR,
610 max98090_alccmp_text);
612 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
614 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
615 M98090_REG_DRC_EXPANDER,
617 max98090_drcexp_text);
619 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
620 M98090_REG_DAC_CONTROL,
621 M98090_PERFMODE_SHIFT,
622 max98090_perf_pwr_text);
624 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
625 M98090_REG_DAC_CONTROL,
627 max98090_pwr_perf_text);
629 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
630 M98090_REG_ADC_CONTROL,
632 max98090_pwr_perf_text);
634 static const struct snd_kcontrol_new max98090_snd_controls[] = {
635 SOC_ENUM_EXT("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum,
636 snd_soc_get_enum_double, max98090_put_enum_double),
638 SOC_SINGLE_EXT("DMIC MIC Comp Filter Config",
639 M98090_REG_DIGITAL_MIC_CONFIG,
640 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0,
641 snd_soc_get_volsw, max98090_put_volsw),
643 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
644 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
645 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
646 max98090_put_enab_tlv, max98090_micboost_tlv),
648 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
649 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
650 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
651 max98090_put_enab_tlv, max98090_micboost_tlv),
653 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
654 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
657 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
658 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
661 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
662 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
663 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
665 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
666 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
667 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
669 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
670 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
673 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
674 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
677 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
678 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
679 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
680 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
682 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
683 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
685 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
686 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
689 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
690 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
692 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
693 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
696 SOC_ENUM_EXT("ADC Oversampling Rate", max98090_osr128_enum,
697 snd_soc_get_enum_double, max98090_put_enum_double),
698 SOC_SINGLE_EXT("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
699 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0,
700 snd_soc_get_volsw, max98090_put_volsw),
701 SOC_ENUM_EXT("ADC High Performance Mode", max98090_adchp_enum,
702 snd_soc_get_enum_double, max98090_put_enum_double),
704 SOC_SINGLE_EXT("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
705 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0,
706 snd_soc_get_volsw, max98090_put_volsw),
707 SOC_SINGLE_EXT("SDIN Mode", M98090_REG_IO_CONFIGURATION,
708 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0,
709 snd_soc_get_volsw, max98090_put_volsw),
710 SOC_SINGLE_EXT("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
711 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0,
712 snd_soc_get_volsw, max98090_put_volsw),
713 SOC_SINGLE_EXT("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
714 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1,
715 snd_soc_get_volsw, max98090_put_volsw),
716 SOC_ENUM_EXT("Filter Mode", max98090_mode_enum,
717 snd_soc_get_enum_double, max98090_put_enum_double),
718 SOC_SINGLE_EXT("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
719 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0,
720 snd_soc_get_volsw, max98090_put_volsw),
721 SOC_SINGLE_EXT("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
722 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0,
723 snd_soc_get_volsw, max98090_put_volsw),
724 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
725 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
726 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
727 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
728 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
729 max98090_put_enab_tlv, max98090_sdg_tlv),
730 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
731 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
733 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
734 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
736 SND_SOC_BYTES_E("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105,
737 snd_soc_bytes_get, max98090_bytes_put),
738 SOC_SINGLE_EXT("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
739 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0,
740 snd_soc_get_volsw, max98090_put_volsw),
741 SOC_SINGLE_EXT("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
742 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0,
743 snd_soc_get_volsw, max98090_put_volsw),
744 SOC_SINGLE_EXT("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
745 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0,
746 snd_soc_get_volsw, max98090_put_volsw),
747 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
748 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
750 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
751 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
754 SOC_SINGLE_EXT("ALC Enable", M98090_REG_DRC_TIMING,
755 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0,
756 snd_soc_get_volsw, max98090_put_volsw),
757 SOC_ENUM_EXT("ALC Attack Time", max98090_drcatk_enum,
758 snd_soc_get_enum_double, max98090_put_enum_double),
759 SOC_ENUM_EXT("ALC Release Time", max98090_drcrls_enum,
760 snd_soc_get_enum_double, max98090_put_enum_double),
761 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
762 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
763 max98090_alcmakeup_tlv),
764 SOC_ENUM_EXT("ALC Compression Ratio", max98090_alccmp_enum,
765 snd_soc_get_enum_double, max98090_put_enum_double),
766 SOC_ENUM_EXT("ALC Expansion Ratio", max98090_drcexp_enum,
767 snd_soc_get_enum_double, max98090_put_enum_double),
768 SOC_SINGLE_EXT_TLV("ALC Compression Threshold Volume",
769 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
770 M98090_DRCTHC_NUM - 1, 1,
771 snd_soc_get_volsw, max98090_put_volsw, max98090_alccomp_tlv),
772 SOC_SINGLE_EXT_TLV("ALC Expansion Threshold Volume",
773 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
774 M98090_DRCTHE_NUM - 1, 1,
775 snd_soc_get_volsw, max98090_put_volsw, max98090_drcexp_tlv),
777 SOC_ENUM_EXT("DAC HP Playback Performance Mode",
778 max98090_dac_perfmode_enum,
779 snd_soc_get_enum_double, max98090_put_enum_double),
780 SOC_ENUM_EXT("DAC High Performance Mode", max98090_dachp_enum,
781 snd_soc_get_enum_double, max98090_put_enum_double),
783 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
784 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
785 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
786 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
787 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
788 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
790 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
791 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
792 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
793 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
794 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
795 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
797 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
798 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
799 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
800 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
801 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
802 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
804 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
805 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
806 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
808 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
809 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
810 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
811 0, max98090_spk_tlv),
813 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
814 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
815 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
817 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
818 M98090_HPLM_SHIFT, 1, 1),
819 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
820 M98090_HPRM_SHIFT, 1, 1),
822 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
823 M98090_SPLM_SHIFT, 1, 1),
824 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
825 M98090_SPRM_SHIFT, 1, 1),
827 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
828 M98090_RCVLM_SHIFT, 1, 1),
829 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
830 M98090_RCVRM_SHIFT, 1, 1),
832 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
833 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
834 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
835 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
836 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
837 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
839 SND_SOC_BYTES_E("Biquad Coefficients",
840 M98090_REG_RECORD_BIQUAD_BASE, 15,
841 snd_soc_bytes_get, max98090_bytes_put),
842 SOC_SINGLE_EXT("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
843 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0,
844 snd_soc_get_volsw, max98090_put_volsw),
847 static const struct snd_kcontrol_new max98091_snd_controls[] = {
849 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
850 M98090_DMIC34_ZEROPAD_SHIFT,
851 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
853 SOC_ENUM_EXT("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum,
854 snd_soc_get_enum_double, max98090_put_enum_double),
855 SOC_SINGLE_EXT("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
856 M98090_FLT_DMIC34HPF_SHIFT,
857 M98090_FLT_DMIC34HPF_NUM - 1, 0,
858 snd_soc_get_volsw, max98090_put_volsw),
860 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
861 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
863 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
864 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
867 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
868 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
870 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
871 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
874 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
875 M98090_REG_DMIC34_BIQUAD_BASE, 15),
876 SOC_SINGLE_EXT("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
877 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0,
878 snd_soc_get_volsw, max98090_put_volsw),
880 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
881 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
882 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
885 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
886 struct snd_kcontrol *kcontrol, int event)
888 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
889 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
891 unsigned int val = snd_soc_component_read32(component, w->reg);
893 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
894 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
896 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
899 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
900 max98090->pa1en = val - 1; /* Update for volatile */
902 max98090->pa2en = val - 1; /* Update for volatile */
907 case SND_SOC_DAPM_POST_PMU:
908 /* If turning on, set to most recently selected volume */
909 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
910 val = max98090->pa1en + 1;
912 val = max98090->pa2en + 1;
914 case SND_SOC_DAPM_POST_PMD:
915 /* If turning off, turn off */
922 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
923 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK,
924 val << M98090_MIC_PA1EN_SHIFT);
926 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK,
927 val << M98090_MIC_PA2EN_SHIFT);
932 static const char *mic1_mux_text[] = { "IN12", "IN56" };
934 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
935 M98090_REG_INPUT_MODE,
936 M98090_EXTMIC1_SHIFT,
939 static const struct snd_kcontrol_new max98090_mic1_mux =
940 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
942 static const char *mic2_mux_text[] = { "IN34", "IN56" };
944 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
945 M98090_REG_INPUT_MODE,
946 M98090_EXTMIC2_SHIFT,
949 static const struct snd_kcontrol_new max98090_mic2_mux =
950 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
952 static const char *dmic_mux_text[] = { "ADC", "DMIC" };
954 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
956 static const struct snd_kcontrol_new max98090_dmic_mux =
957 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
959 /* LINEA mixer switch */
960 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
961 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
962 M98090_IN1SEEN_SHIFT, 1, 0),
963 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
964 M98090_IN3SEEN_SHIFT, 1, 0),
965 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
966 M98090_IN5SEEN_SHIFT, 1, 0),
967 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
968 M98090_IN34DIFF_SHIFT, 1, 0),
971 /* LINEB mixer switch */
972 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
973 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
974 M98090_IN2SEEN_SHIFT, 1, 0),
975 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
976 M98090_IN4SEEN_SHIFT, 1, 0),
977 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
978 M98090_IN6SEEN_SHIFT, 1, 0),
979 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
980 M98090_IN56DIFF_SHIFT, 1, 0),
983 /* Left ADC mixer switch */
984 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
985 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
986 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
987 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
988 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
989 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
990 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
991 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
992 M98090_MIXADL_LINEA_SHIFT, 1, 0),
993 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
994 M98090_MIXADL_LINEB_SHIFT, 1, 0),
995 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
996 M98090_MIXADL_MIC1_SHIFT, 1, 0),
997 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
998 M98090_MIXADL_MIC2_SHIFT, 1, 0),
1001 /* Right ADC mixer switch */
1002 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
1003 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
1004 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
1005 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
1006 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
1007 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
1008 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
1009 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
1010 M98090_MIXADR_LINEA_SHIFT, 1, 0),
1011 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
1012 M98090_MIXADR_LINEB_SHIFT, 1, 0),
1013 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
1014 M98090_MIXADR_MIC1_SHIFT, 1, 0),
1015 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
1016 M98090_MIXADR_MIC2_SHIFT, 1, 0),
1019 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
1021 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
1022 M98090_REG_IO_CONFIGURATION,
1026 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
1027 M98090_REG_IO_CONFIGURATION,
1031 static const struct snd_kcontrol_new max98090_ltenl_mux =
1032 SOC_DAPM_ENUM_EXT("LTENL Mux", ltenl_mux_enum,
1033 snd_soc_dapm_get_enum_double,
1034 max98090_dapm_put_enum_double);
1036 static const struct snd_kcontrol_new max98090_ltenr_mux =
1037 SOC_DAPM_ENUM_EXT("LTENR Mux", ltenr_mux_enum,
1038 snd_soc_dapm_get_enum_double,
1039 max98090_dapm_put_enum_double);
1041 static const char *lben_mux_text[] = { "Normal", "Loopback" };
1043 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
1044 M98090_REG_IO_CONFIGURATION,
1048 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
1049 M98090_REG_IO_CONFIGURATION,
1053 static const struct snd_kcontrol_new max98090_lbenl_mux =
1054 SOC_DAPM_ENUM_EXT("LBENL Mux", lbenl_mux_enum,
1055 snd_soc_dapm_get_enum_double,
1056 max98090_dapm_put_enum_double);
1058 static const struct snd_kcontrol_new max98090_lbenr_mux =
1059 SOC_DAPM_ENUM_EXT("LBENR Mux", lbenr_mux_enum,
1060 snd_soc_dapm_get_enum_double,
1061 max98090_dapm_put_enum_double);
1063 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
1065 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
1067 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
1068 M98090_REG_ADC_SIDETONE,
1072 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
1073 M98090_REG_ADC_SIDETONE,
1077 static const struct snd_kcontrol_new max98090_stenl_mux =
1078 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
1080 static const struct snd_kcontrol_new max98090_stenr_mux =
1081 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
1083 /* Left speaker mixer switch */
1085 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
1086 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1087 M98090_MIXSPL_DACL_SHIFT, 1, 0),
1088 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1089 M98090_MIXSPL_DACR_SHIFT, 1, 0),
1090 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
1091 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
1092 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
1093 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
1094 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
1095 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
1096 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
1097 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
1100 /* Right speaker mixer switch */
1102 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
1103 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1104 M98090_MIXSPR_DACL_SHIFT, 1, 0),
1105 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1106 M98090_MIXSPR_DACR_SHIFT, 1, 0),
1107 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
1108 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
1109 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
1110 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
1111 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
1112 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
1113 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
1114 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
1117 /* Left headphone mixer switch */
1118 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
1119 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
1120 M98090_MIXHPL_DACL_SHIFT, 1, 0),
1121 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
1122 M98090_MIXHPL_DACR_SHIFT, 1, 0),
1123 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
1124 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
1125 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
1126 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
1127 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
1128 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1129 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1130 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1133 /* Right headphone mixer switch */
1134 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1135 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1136 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1137 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1138 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1139 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1140 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1141 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1142 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1143 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1144 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1145 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1146 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1149 /* Left receiver mixer switch */
1150 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1151 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1152 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1153 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1154 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1155 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1156 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1157 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1158 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1159 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1160 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1161 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1162 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1165 /* Right receiver mixer switch */
1166 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1167 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1168 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1169 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1170 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1171 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1172 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1173 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1174 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1175 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1176 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1177 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1178 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1181 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1183 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1184 M98090_REG_LOUTR_MIXER,
1185 M98090_LINMOD_SHIFT,
1188 static const struct snd_kcontrol_new max98090_linmod_mux =
1189 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1191 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1194 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1196 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1197 M98090_REG_HP_CONTROL,
1198 M98090_MIXHPLSEL_SHIFT,
1201 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1202 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1204 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1205 M98090_REG_HP_CONTROL,
1206 M98090_MIXHPRSEL_SHIFT,
1209 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1210 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1212 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1213 SND_SOC_DAPM_INPUT("MIC1"),
1214 SND_SOC_DAPM_INPUT("MIC2"),
1215 SND_SOC_DAPM_INPUT("DMICL"),
1216 SND_SOC_DAPM_INPUT("DMICR"),
1217 SND_SOC_DAPM_INPUT("IN1"),
1218 SND_SOC_DAPM_INPUT("IN2"),
1219 SND_SOC_DAPM_INPUT("IN3"),
1220 SND_SOC_DAPM_INPUT("IN4"),
1221 SND_SOC_DAPM_INPUT("IN5"),
1222 SND_SOC_DAPM_INPUT("IN6"),
1223 SND_SOC_DAPM_INPUT("IN12"),
1224 SND_SOC_DAPM_INPUT("IN34"),
1225 SND_SOC_DAPM_INPUT("IN56"),
1227 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1228 M98090_MBEN_SHIFT, 0, max98090_dapm_event,
1229 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1230 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1231 M98090_SHDNN_SHIFT, 0, NULL, 0),
1232 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1233 M98090_SDIEN_SHIFT, 0, max98090_dapm_event,
1234 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1235 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1236 M98090_SDOEN_SHIFT, 0, max98090_dapm_event,
1237 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1238 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1239 M98090_DIGMICL_SHIFT, 0, max98090_dapm_event,
1240 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1241 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1242 M98090_DIGMICR_SHIFT, 0, max98090_dapm_event,
1243 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1244 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1245 M98090_AHPF_SHIFT, 0, max98090_dapm_event,
1246 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1249 * Note: Sysclk and misc power supplies are taken care of by SHDN
1252 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1253 0, 0, &max98090_mic1_mux),
1255 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1256 0, 0, &max98090_mic2_mux),
1258 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
1260 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1261 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1262 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1264 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1265 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1266 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1268 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1269 &max98090_linea_mixer_controls[0],
1270 ARRAY_SIZE(max98090_linea_mixer_controls)),
1272 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1273 &max98090_lineb_mixer_controls[0],
1274 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1276 SND_SOC_DAPM_PGA_E("LINEA Input", M98090_REG_INPUT_ENABLE,
1277 M98090_LINEAEN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1278 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1279 SND_SOC_DAPM_PGA_E("LINEB Input", M98090_REG_INPUT_ENABLE,
1280 M98090_LINEBEN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1281 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1283 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1284 &max98090_left_adc_mixer_controls[0],
1285 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1287 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1288 &max98090_right_adc_mixer_controls[0],
1289 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1291 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1292 M98090_ADLEN_SHIFT, 0, max98090_dapm_event,
1293 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1294 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1295 M98090_ADREN_SHIFT, 0, max98090_dapm_event,
1296 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1298 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1299 SND_SOC_NOPM, 0, 0),
1300 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1301 SND_SOC_NOPM, 0, 0),
1303 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1304 0, 0, &max98090_lbenl_mux),
1306 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1307 0, 0, &max98090_lbenr_mux),
1309 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1310 0, 0, &max98090_ltenl_mux),
1312 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1313 0, 0, &max98090_ltenr_mux),
1315 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1316 0, 0, &max98090_stenl_mux),
1318 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1319 0, 0, &max98090_stenr_mux),
1321 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1322 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1324 SND_SOC_DAPM_DAC_E("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1325 M98090_DALEN_SHIFT, 0, max98090_dapm_event,
1326 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1327 SND_SOC_DAPM_DAC_E("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1328 M98090_DAREN_SHIFT, 0, max98090_dapm_event,
1329 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1331 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1332 &max98090_left_hp_mixer_controls[0],
1333 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1335 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1336 &max98090_right_hp_mixer_controls[0],
1337 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1339 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1340 &max98090_left_speaker_mixer_controls[0],
1341 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1343 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1344 &max98090_right_speaker_mixer_controls[0],
1345 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1347 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1348 &max98090_left_rcv_mixer_controls[0],
1349 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1351 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1352 &max98090_right_rcv_mixer_controls[0],
1353 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1355 SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0,
1356 &max98090_linmod_mux),
1358 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0,
1359 &max98090_mixhplsel_mux),
1361 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0,
1362 &max98090_mixhprsel_mux),
1364 SND_SOC_DAPM_PGA_E("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1365 M98090_HPLEN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1366 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1367 SND_SOC_DAPM_PGA_E("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1368 M98090_HPREN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1369 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1371 SND_SOC_DAPM_PGA_E("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1372 M98090_SPLEN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1373 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1374 SND_SOC_DAPM_PGA_E("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1375 M98090_SPREN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1376 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1378 SND_SOC_DAPM_PGA_E("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1379 M98090_RCVLEN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1380 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1381 SND_SOC_DAPM_PGA_E("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1382 M98090_RCVREN_SHIFT, 0, NULL, 0, max98090_dapm_event,
1383 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1385 SND_SOC_DAPM_OUTPUT("HPL"),
1386 SND_SOC_DAPM_OUTPUT("HPR"),
1387 SND_SOC_DAPM_OUTPUT("SPKL"),
1388 SND_SOC_DAPM_OUTPUT("SPKR"),
1389 SND_SOC_DAPM_OUTPUT("RCVL"),
1390 SND_SOC_DAPM_OUTPUT("RCVR"),
1393 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1394 SND_SOC_DAPM_INPUT("DMIC3"),
1395 SND_SOC_DAPM_INPUT("DMIC4"),
1397 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1398 M98090_DIGMIC3_SHIFT, 0, max98090_dapm_event,
1399 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1400 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1401 M98090_DIGMIC4_SHIFT, 0, max98090_dapm_event,
1402 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD),
1405 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1406 {"MIC1 Input", NULL, "MIC1"},
1407 {"MIC2 Input", NULL, "MIC2"},
1409 {"DMICL", NULL, "DMICL_ENA"},
1410 {"DMICL", NULL, "DMICR_ENA"},
1411 {"DMICR", NULL, "DMICL_ENA"},
1412 {"DMICR", NULL, "DMICR_ENA"},
1413 {"DMICL", NULL, "AHPF"},
1414 {"DMICR", NULL, "AHPF"},
1416 /* MIC1 input mux */
1417 {"MIC1 Mux", "IN12", "IN12"},
1418 {"MIC1 Mux", "IN56", "IN56"},
1420 /* MIC2 input mux */
1421 {"MIC2 Mux", "IN34", "IN34"},
1422 {"MIC2 Mux", "IN56", "IN56"},
1424 {"MIC1 Input", NULL, "MIC1 Mux"},
1425 {"MIC2 Input", NULL, "MIC2 Mux"},
1427 /* Left ADC input mixer */
1428 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1429 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1430 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1431 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1432 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1433 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1434 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1436 /* Right ADC input mixer */
1437 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1438 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1439 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1440 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1441 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1442 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1443 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1445 /* Line A input mixer */
1446 {"LINEA Mixer", "IN1 Switch", "IN1"},
1447 {"LINEA Mixer", "IN3 Switch", "IN3"},
1448 {"LINEA Mixer", "IN5 Switch", "IN5"},
1449 {"LINEA Mixer", "IN34 Switch", "IN34"},
1451 /* Line B input mixer */
1452 {"LINEB Mixer", "IN2 Switch", "IN2"},
1453 {"LINEB Mixer", "IN4 Switch", "IN4"},
1454 {"LINEB Mixer", "IN6 Switch", "IN6"},
1455 {"LINEB Mixer", "IN56 Switch", "IN56"},
1457 {"LINEA Input", NULL, "LINEA Mixer"},
1458 {"LINEB Input", NULL, "LINEB Mixer"},
1461 {"ADCL", NULL, "Left ADC Mixer"},
1462 {"ADCR", NULL, "Right ADC Mixer"},
1463 {"ADCL", NULL, "SHDN"},
1464 {"ADCR", NULL, "SHDN"},
1466 {"DMIC Mux", "ADC", "ADCL"},
1467 {"DMIC Mux", "ADC", "ADCR"},
1468 {"DMIC Mux", "DMIC", "DMICL"},
1469 {"DMIC Mux", "DMIC", "DMICR"},
1471 {"LBENL Mux", "Normal", "DMIC Mux"},
1472 {"LBENL Mux", "Loopback", "LTENL Mux"},
1473 {"LBENR Mux", "Normal", "DMIC Mux"},
1474 {"LBENR Mux", "Loopback", "LTENR Mux"},
1476 {"AIFOUTL", NULL, "LBENL Mux"},
1477 {"AIFOUTR", NULL, "LBENR Mux"},
1478 {"AIFOUTL", NULL, "SHDN"},
1479 {"AIFOUTR", NULL, "SHDN"},
1480 {"AIFOUTL", NULL, "SDOEN"},
1481 {"AIFOUTR", NULL, "SDOEN"},
1483 {"LTENL Mux", "Normal", "AIFINL"},
1484 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1485 {"LTENR Mux", "Normal", "AIFINR"},
1486 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1488 {"DACL", NULL, "LTENL Mux"},
1489 {"DACR", NULL, "LTENR Mux"},
1491 {"STENL Mux", "Sidetone Left", "ADCL"},
1492 {"STENL Mux", "Sidetone Left", "DMICL"},
1493 {"STENR Mux", "Sidetone Right", "ADCR"},
1494 {"STENR Mux", "Sidetone Right", "DMICR"},
1495 {"DACL", NULL, "STENL Mux"},
1496 {"DACR", NULL, "STENR Mux"},
1498 {"AIFINL", NULL, "SHDN"},
1499 {"AIFINR", NULL, "SHDN"},
1500 {"AIFINL", NULL, "SDIEN"},
1501 {"AIFINR", NULL, "SDIEN"},
1502 {"DACL", NULL, "SHDN"},
1503 {"DACR", NULL, "SHDN"},
1505 /* Left headphone output mixer */
1506 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1507 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1508 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1509 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1510 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1511 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1513 /* Right headphone output mixer */
1514 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1515 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1516 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1517 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1518 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1519 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1521 /* Left speaker output mixer */
1522 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1523 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1524 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1525 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1526 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1527 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1529 /* Right speaker output mixer */
1530 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1531 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1532 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1533 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1534 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1535 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1537 /* Left Receiver output mixer */
1538 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1539 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1540 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1541 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1542 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1543 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1545 /* Right Receiver output mixer */
1546 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1547 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1548 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1549 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1550 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1551 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1553 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1556 * Disable this for lowest power if bypassing
1557 * the DAC with an analog signal
1559 {"HP Left Out", NULL, "DACL"},
1560 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1562 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1565 * Disable this for lowest power if bypassing
1566 * the DAC with an analog signal
1568 {"HP Right Out", NULL, "DACR"},
1569 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1571 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1572 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1573 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1575 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1576 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1577 {"RCV Right Out", NULL, "LINMOD Mux"},
1579 {"HPL", NULL, "HP Left Out"},
1580 {"HPR", NULL, "HP Right Out"},
1581 {"SPKL", NULL, "SPK Left Out"},
1582 {"SPKR", NULL, "SPK Right Out"},
1583 {"RCVL", NULL, "RCV Left Out"},
1584 {"RCVR", NULL, "RCV Right Out"},
1587 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1589 {"DMIC3", NULL, "DMIC3_ENA"},
1590 {"DMIC4", NULL, "DMIC4_ENA"},
1591 {"DMIC3", NULL, "AHPF"},
1592 {"DMIC4", NULL, "AHPF"},
1595 static int max98090_add_widgets(struct snd_soc_component *component)
1597 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1598 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1600 snd_soc_add_component_controls(component, max98090_snd_controls,
1601 ARRAY_SIZE(max98090_snd_controls));
1603 if (max98090->devtype == MAX98091) {
1604 snd_soc_add_component_controls(component, max98091_snd_controls,
1605 ARRAY_SIZE(max98091_snd_controls));
1608 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1609 ARRAY_SIZE(max98090_dapm_widgets));
1611 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1612 ARRAY_SIZE(max98090_dapm_routes));
1614 if (max98090->devtype == MAX98091) {
1615 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1616 ARRAY_SIZE(max98091_dapm_widgets));
1618 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1619 ARRAY_SIZE(max98091_dapm_routes));
1625 static const int pclk_rates[] = {
1626 12000000, 12000000, 13000000, 13000000,
1627 16000000, 16000000, 19200000, 19200000
1630 static const int lrclk_rates[] = {
1631 8000, 16000, 8000, 16000,
1632 8000, 16000, 8000, 16000
1635 static const int user_pclk_rates[] = {
1636 13000000, 13000000, 19200000, 19200000,
1639 static const int user_lrclk_rates[] = {
1640 44100, 48000, 44100, 48000,
1643 static const unsigned long long ni_value[] = {
1647 static const unsigned long long mi_value[] = {
1648 8125, 1625, 1500, 25
1651 static void max98090_configure_bclk(struct snd_soc_component *component)
1653 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1654 unsigned long long ni;
1657 if (!max98090->sysclk) {
1658 dev_err(component->dev, "No SYSCLK configured\n");
1662 if (!max98090->bclk || !max98090->lrclk) {
1663 dev_err(component->dev, "No audio clocks configured\n");
1667 /* Skip configuration when operating as slave */
1668 if (!(snd_soc_component_read32(component, M98090_REG_MASTER_MODE) &
1674 * Master mode: no need to save and restore SHDN for the following
1675 * sensitive registers.
1678 /* Check for supported PCLK to LRCLK ratios */
1679 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1680 if ((pclk_rates[i] == max98090->sysclk) &&
1681 (lrclk_rates[i] == max98090->lrclk)) {
1682 dev_dbg(component->dev,
1683 "Found supported PCLK to LRCLK rates 0x%x\n",
1686 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1688 (i + 0x8) << M98090_FREQ_SHIFT);
1689 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1690 M98090_USE_M1_MASK, 0);
1695 /* Check for user calculated MI and NI ratios */
1696 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1697 if ((user_pclk_rates[i] == max98090->sysclk) &&
1698 (user_lrclk_rates[i] == max98090->lrclk)) {
1699 dev_dbg(component->dev,
1700 "Found user supported PCLK to LRCLK rates\n");
1701 dev_dbg(component->dev, "i %d ni %lld mi %lld\n",
1702 i, ni_value[i], mi_value[i]);
1704 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1705 M98090_FREQ_MASK, 0);
1706 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1708 1 << M98090_USE_M1_SHIFT);
1710 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
1711 (ni_value[i] >> 8) & 0x7F);
1712 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB,
1713 ni_value[i] & 0xFF);
1714 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB,
1715 (mi_value[i] >> 8) & 0x7F);
1716 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB,
1717 mi_value[i] & 0xFF);
1724 * Calculate based on MI = 65536 (not as good as either method above)
1726 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1727 M98090_FREQ_MASK, 0);
1728 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1729 M98090_USE_M1_MASK, 0);
1732 * Configure NI when operating as master
1733 * Note: There is a small, but significant audio quality improvement
1734 * by calculating ni and mi.
1736 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1737 * (unsigned long long int)max98090->lrclk;
1738 do_div(ni, (unsigned long long int)max98090->sysclk);
1739 dev_info(component->dev, "No better method found\n");
1740 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni);
1741 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB,
1743 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1746 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1749 struct snd_soc_component *component = codec_dai->component;
1750 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1751 struct max98090_cdata *cdata;
1754 max98090->dai_fmt = fmt;
1755 cdata = &max98090->dai[0];
1757 if (fmt != cdata->fmt) {
1761 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1762 case SND_SOC_DAIFMT_CBS_CFS:
1763 /* Set to slave mode PLL - MAS mode off */
1764 max98090_shdn_save(max98090);
1765 snd_soc_component_write(component,
1766 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1767 snd_soc_component_write(component,
1768 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1769 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE,
1770 M98090_USE_M1_MASK, 0);
1771 max98090_shdn_restore(max98090);
1772 max98090->master = false;
1774 case SND_SOC_DAIFMT_CBM_CFM:
1775 /* Set to master mode */
1776 if (max98090->tdm_slots == 4) {
1778 regval |= M98090_MAS_MASK |
1780 } else if (max98090->tdm_slots == 3) {
1782 regval |= M98090_MAS_MASK |
1785 /* Few TDM slots, or No TDM */
1786 regval |= M98090_MAS_MASK |
1789 max98090->master = true;
1791 case SND_SOC_DAIFMT_CBS_CFM:
1792 case SND_SOC_DAIFMT_CBM_CFS:
1794 dev_err(component->dev, "DAI clock mode unsupported");
1797 max98090_shdn_save(max98090);
1798 snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval);
1799 max98090_shdn_restore(max98090);
1802 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1803 case SND_SOC_DAIFMT_I2S:
1804 regval |= M98090_DLY_MASK;
1806 case SND_SOC_DAIFMT_LEFT_J:
1808 case SND_SOC_DAIFMT_RIGHT_J:
1809 regval |= M98090_RJ_MASK;
1811 case SND_SOC_DAIFMT_DSP_A:
1812 /* Not supported mode */
1814 dev_err(component->dev, "DAI format unsupported");
1818 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1819 case SND_SOC_DAIFMT_NB_NF:
1821 case SND_SOC_DAIFMT_NB_IF:
1822 regval |= M98090_WCI_MASK;
1824 case SND_SOC_DAIFMT_IB_NF:
1825 regval |= M98090_BCI_MASK;
1827 case SND_SOC_DAIFMT_IB_IF:
1828 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1831 dev_err(component->dev, "DAI invert mode unsupported");
1836 * This accommodates an inverted logic in the MAX98090 chip
1837 * for Bit Clock Invert (BCI). The inverted logic is only
1838 * seen for the case of TDM mode. The remaining cases have
1841 if (max98090->tdm_slots > 1)
1842 regval ^= M98090_BCI_MASK;
1844 max98090_shdn_save(max98090);
1845 snd_soc_component_write(component,
1846 M98090_REG_INTERFACE_FORMAT, regval);
1847 max98090_shdn_restore(max98090);
1853 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1854 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1856 struct snd_soc_component *component = codec_dai->component;
1857 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1858 struct max98090_cdata *cdata;
1860 cdata = &max98090->dai[0];
1862 if (slots < 0 || slots > 4)
1865 max98090->tdm_slots = slots;
1866 max98090->tdm_width = slot_width;
1868 if (max98090->tdm_slots > 1) {
1869 max98090_shdn_save(max98090);
1870 /* SLOTL SLOTR SLOTDLY */
1871 snd_soc_component_write(component, M98090_REG_TDM_FORMAT,
1872 0 << M98090_TDM_SLOTL_SHIFT |
1873 1 << M98090_TDM_SLOTR_SHIFT |
1874 0 << M98090_TDM_SLOTDLY_SHIFT);
1877 snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL,
1880 max98090_shdn_restore(max98090);
1884 * Normally advisable to set TDM first, but this permits either order
1887 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1892 static int max98090_set_bias_level(struct snd_soc_component *component,
1893 enum snd_soc_bias_level level)
1895 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
1899 case SND_SOC_BIAS_ON:
1902 case SND_SOC_BIAS_PREPARE:
1904 * SND_SOC_BIAS_PREPARE is called while preparing for a
1905 * transition to ON or away from ON. If current bias_level
1906 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1907 * away from ON. Disable the clock in that case, otherwise
1910 if (IS_ERR(max98090->mclk))
1913 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
1914 clk_disable_unprepare(max98090->mclk);
1916 ret = clk_prepare_enable(max98090->mclk);
1922 case SND_SOC_BIAS_STANDBY:
1923 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1924 ret = regcache_sync(max98090->regmap);
1926 dev_err(component->dev,
1927 "Failed to sync cache: %d\n", ret);
1933 case SND_SOC_BIAS_OFF:
1934 /* Set internal pull-up to lowest power mode */
1935 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
1936 M98090_JDWK_MASK, M98090_JDWK_MASK);
1937 regcache_mark_dirty(max98090->regmap);
1943 static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
1945 static const int comp_lrclk_rates[] = {
1946 8000, 16000, 32000, 44100, 48000, 96000
1953 int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
1954 } settings[6]; /* One for each dmic divisor. */
1957 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1961 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1962 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1963 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1964 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1965 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1966 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1972 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1973 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1974 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1975 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1976 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1977 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1983 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1984 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1985 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1986 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1987 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1988 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1994 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1995 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1996 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1997 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1998 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1999 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
2005 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
2006 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
2007 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
2008 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
2009 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
2010 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
2015 static int max98090_find_divisor(int target_freq, int pclk)
2017 int current_diff = INT_MAX;
2018 int test_diff = INT_MAX;
2019 int divisor_index = 0;
2022 for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
2023 test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
2024 if (test_diff < current_diff) {
2025 current_diff = test_diff;
2030 return divisor_index;
2033 static int max98090_find_closest_pclk(int pclk)
2039 for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
2040 if (pclk == dmic_table[i].pclk)
2042 if (pclk < dmic_table[i].pclk) {
2045 m1 = pclk - dmic_table[i-1].pclk;
2046 m2 = dmic_table[i].pclk - pclk;
2057 static int max98090_configure_dmic(struct max98090_priv *max98090,
2058 int target_dmic_clk, int pclk, int fs)
2066 pclk_index = max98090_find_closest_pclk(pclk);
2070 micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
2072 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
2073 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
2077 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
2078 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
2080 max98090_shdn_save(max98090);
2081 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
2083 micclk_index << M98090_MICCLK_SHIFT);
2085 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
2086 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
2087 dmic_comp << M98090_DMIC_COMP_SHIFT |
2088 dmic_freq << M98090_DMIC_FREQ_SHIFT);
2089 max98090_shdn_restore(max98090);
2094 static int max98090_dai_startup(struct snd_pcm_substream *substream,
2095 struct snd_soc_dai *dai)
2097 struct snd_soc_component *component = dai->component;
2098 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2099 unsigned int fmt = max98090->dai_fmt;
2101 /* Remove 24-bit format support if it is not in right justified mode. */
2102 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) {
2103 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
2104 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16);
2109 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
2110 struct snd_pcm_hw_params *params,
2111 struct snd_soc_dai *dai)
2113 struct snd_soc_component *component = dai->component;
2114 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2115 struct max98090_cdata *cdata;
2117 cdata = &max98090->dai[0];
2118 max98090->bclk = snd_soc_params_to_bclk(params);
2119 if (params_channels(params) == 1)
2120 max98090->bclk *= 2;
2122 max98090->lrclk = params_rate(params);
2124 switch (params_width(params)) {
2126 max98090_shdn_save(max98090);
2127 snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT,
2129 max98090_shdn_restore(max98090);
2135 if (max98090->master)
2136 max98090_configure_bclk(component);
2138 cdata->rate = max98090->lrclk;
2140 max98090_shdn_save(max98090);
2141 /* Update filter mode */
2142 if (max98090->lrclk < 24000)
2143 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
2144 M98090_MODE_MASK, 0);
2146 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
2147 M98090_MODE_MASK, M98090_MODE_MASK);
2149 /* Update sample rate mode */
2150 if (max98090->lrclk < 50000)
2151 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
2152 M98090_DHF_MASK, 0);
2154 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG,
2155 M98090_DHF_MASK, M98090_DHF_MASK);
2156 max98090_shdn_restore(max98090);
2158 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
2167 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
2168 int clk_id, unsigned int freq, int dir)
2170 struct snd_soc_component *component = dai->component;
2171 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2173 /* Requested clock frequency is already setup */
2174 if (freq == max98090->sysclk)
2177 if (!IS_ERR(max98090->mclk)) {
2178 freq = clk_round_rate(max98090->mclk, freq);
2179 clk_set_rate(max98090->mclk, freq);
2182 /* Setup clocks for slave mode, and using the PLL
2183 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
2184 * 0x02 (when master clk is 20MHz to 40MHz)..
2185 * 0x03 (when master clk is 40MHz to 60MHz)..
2187 max98090_shdn_save(max98090);
2188 if ((freq >= 10000000) && (freq <= 20000000)) {
2189 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2191 max98090->pclk = freq;
2192 } else if ((freq > 20000000) && (freq <= 40000000)) {
2193 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2195 max98090->pclk = freq >> 1;
2196 } else if ((freq > 40000000) && (freq <= 60000000)) {
2197 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK,
2199 max98090->pclk = freq >> 2;
2201 dev_err(component->dev, "Invalid master clock frequency\n");
2202 max98090_shdn_restore(max98090);
2205 max98090_shdn_restore(max98090);
2207 max98090->sysclk = freq;
2212 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2214 struct snd_soc_component *component = codec_dai->component;
2217 regval = mute ? M98090_DVM_MASK : 0;
2218 snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL,
2219 M98090_DVM_MASK, regval);
2224 static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
2225 struct snd_soc_dai *dai)
2227 struct snd_soc_component *component = dai->component;
2228 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2231 case SNDRV_PCM_TRIGGER_START:
2232 case SNDRV_PCM_TRIGGER_RESUME:
2233 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2234 if (!max98090->master && dai->active == 1)
2235 queue_delayed_work(system_power_efficient_wq,
2236 &max98090->pll_det_enable_work,
2237 msecs_to_jiffies(10));
2239 case SNDRV_PCM_TRIGGER_STOP:
2240 case SNDRV_PCM_TRIGGER_SUSPEND:
2241 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2242 if (!max98090->master && dai->active == 1)
2243 schedule_work(&max98090->pll_det_disable_work);
2252 static void max98090_pll_det_enable_work(struct work_struct *work)
2254 struct max98090_priv *max98090 =
2255 container_of(work, struct max98090_priv,
2256 pll_det_enable_work.work);
2257 struct snd_soc_component *component = max98090->component;
2258 unsigned int status, mask;
2261 * Clear status register in order to clear possibly already occurred
2262 * PLL unlock. If PLL hasn't still locked, the status will be set
2263 * again and PLL unlock interrupt will occur.
2264 * Note this will clear all status bits
2266 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2269 * Queue jack work in case jack state has just changed but handler
2272 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2274 if (status & M98090_JDET_MASK)
2275 queue_delayed_work(system_power_efficient_wq,
2276 &max98090->jack_work,
2277 msecs_to_jiffies(100));
2279 /* Enable PLL unlock interrupt */
2280 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2282 1 << M98090_IULK_SHIFT);
2285 static void max98090_pll_det_disable_work(struct work_struct *work)
2287 struct max98090_priv *max98090 =
2288 container_of(work, struct max98090_priv, pll_det_disable_work);
2289 struct snd_soc_component *component = max98090->component;
2291 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2293 /* Disable PLL unlock interrupt */
2294 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2295 M98090_IULK_MASK, 0);
2298 static void max98090_pll_work(struct max98090_priv *max98090)
2300 struct snd_soc_component *component = max98090->component;
2304 if (!snd_soc_component_is_active(component))
2307 dev_info_ratelimited(component->dev, "PLL unlocked\n");
2310 * As the datasheet suggested, the maximum PLL lock time should be
2311 * 7 msec. The workaround resets the codec softly by toggling SHDN
2312 * off and on if PLL failed to lock for 10 msec. Notably, there is
2313 * no suggested hold time for SHDN off.
2316 /* Toggle shutdown OFF then ON */
2317 mutex_lock(&component->card->dapm_mutex);
2318 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2319 M98090_SHDNN_MASK, 0);
2320 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN,
2321 M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2322 mutex_unlock(&component->card->dapm_mutex);
2324 for (i = 0; i < 10; ++i) {
2325 /* Give PLL time to lock */
2326 usleep_range(1000, 1200);
2328 /* Check lock status */
2329 pll = snd_soc_component_read32(
2330 component, M98090_REG_DEVICE_STATUS);
2331 if (!(pll & M98090_ULK_MASK))
2336 static void max98090_jack_work(struct work_struct *work)
2338 struct max98090_priv *max98090 = container_of(work,
2339 struct max98090_priv,
2341 struct snd_soc_component *component = max98090->component;
2345 /* Read a second time */
2346 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
2348 /* Strong pull up allows mic detection */
2349 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
2350 M98090_JDWK_MASK, 0);
2354 reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS);
2356 /* Weak pull up allows only insertion detection */
2357 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT,
2358 M98090_JDWK_MASK, M98090_JDWK_MASK);
2360 reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS);
2363 reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS);
2365 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2366 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2367 dev_dbg(component->dev, "No Headset Detected\n");
2369 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2376 if (max98090->jack_state ==
2377 M98090_JACK_STATE_HEADSET) {
2379 dev_dbg(component->dev,
2380 "Headset Button Down Detected\n");
2383 * max98090_headset_button_event(codec)
2384 * could be defined, then called here.
2387 status |= SND_JACK_HEADSET;
2388 status |= SND_JACK_BTN_0;
2393 /* Line is reported as Headphone */
2394 /* Nokia Headset is reported as Headphone */
2395 /* Mono Headphone is reported as Headphone */
2396 dev_dbg(component->dev, "Headphone Detected\n");
2398 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2400 status |= SND_JACK_HEADPHONE;
2404 case M98090_JKSNS_MASK:
2405 dev_dbg(component->dev, "Headset Detected\n");
2407 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2409 status |= SND_JACK_HEADSET;
2414 dev_dbg(component->dev, "Unrecognized Jack Status\n");
2418 snd_soc_jack_report(max98090->jack, status,
2419 SND_JACK_HEADSET | SND_JACK_BTN_0);
2422 static irqreturn_t max98090_interrupt(int irq, void *data)
2424 struct max98090_priv *max98090 = data;
2425 struct snd_soc_component *component = max98090->component;
2428 unsigned int active;
2430 /* Treat interrupt before codec is initialized as spurious */
2431 if (component == NULL)
2434 dev_dbg(component->dev, "***** max98090_interrupt *****\n");
2436 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2439 dev_err(component->dev,
2440 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2445 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2448 dev_err(component->dev,
2449 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2454 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2455 active, mask, active & mask);
2462 if (active & M98090_CLD_MASK)
2463 dev_err(component->dev, "M98090_CLD_MASK\n");
2465 if (active & M98090_SLD_MASK)
2466 dev_dbg(component->dev, "M98090_SLD_MASK\n");
2468 if (active & M98090_ULK_MASK) {
2469 dev_dbg(component->dev, "M98090_ULK_MASK\n");
2470 max98090_pll_work(max98090);
2473 if (active & M98090_JDET_MASK) {
2474 dev_dbg(component->dev, "M98090_JDET_MASK\n");
2476 pm_wakeup_event(component->dev, 100);
2478 queue_delayed_work(system_power_efficient_wq,
2479 &max98090->jack_work,
2480 msecs_to_jiffies(100));
2483 if (active & M98090_DRCACT_MASK)
2484 dev_dbg(component->dev, "M98090_DRCACT_MASK\n");
2486 if (active & M98090_DRCCLP_MASK)
2487 dev_err(component->dev, "M98090_DRCCLP_MASK\n");
2493 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2495 * @component: MAX98090 component
2496 * @jack: jack to report detection events on
2498 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2499 * being used to bring out signals to the processor then only platform
2500 * data configuration is needed for MAX98090 and processor GPIOs should
2501 * be configured using snd_soc_jack_add_gpios() instead.
2503 * If no jack is supplied detection will be disabled.
2505 int max98090_mic_detect(struct snd_soc_component *component,
2506 struct snd_soc_jack *jack)
2508 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2510 dev_dbg(component->dev, "max98090_mic_detect\n");
2512 max98090->jack = jack;
2514 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2516 1 << M98090_IJDET_SHIFT);
2518 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S,
2523 /* Send an initial empty report */
2524 snd_soc_jack_report(max98090->jack, 0,
2525 SND_JACK_HEADSET | SND_JACK_BTN_0);
2527 queue_delayed_work(system_power_efficient_wq,
2528 &max98090->jack_work,
2529 msecs_to_jiffies(100));
2533 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2535 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2536 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2538 static const struct snd_soc_dai_ops max98090_dai_ops = {
2539 .startup = max98090_dai_startup,
2540 .set_sysclk = max98090_dai_set_sysclk,
2541 .set_fmt = max98090_dai_set_fmt,
2542 .set_tdm_slot = max98090_set_tdm_slot,
2543 .hw_params = max98090_dai_hw_params,
2544 .digital_mute = max98090_dai_digital_mute,
2545 .trigger = max98090_dai_trigger,
2548 static struct snd_soc_dai_driver max98090_dai[] = {
2552 .stream_name = "HiFi Playback",
2555 .rates = MAX98090_RATES,
2556 .formats = MAX98090_FORMATS,
2559 .stream_name = "HiFi Capture",
2562 .rates = MAX98090_RATES,
2563 .formats = MAX98090_FORMATS,
2565 .ops = &max98090_dai_ops,
2569 static int max98090_probe(struct snd_soc_component *component)
2571 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2572 struct max98090_cdata *cdata;
2573 enum max98090_type devtype;
2576 unsigned int micbias;
2578 dev_dbg(component->dev, "max98090_probe\n");
2580 max98090->mclk = devm_clk_get(component->dev, "mclk");
2581 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2582 return -EPROBE_DEFER;
2584 max98090->component = component;
2586 /* Reset the codec, the DSP core, and disable all interrupts */
2587 max98090_reset(max98090);
2589 /* Initialize private data */
2591 max98090->sysclk = (unsigned)-1;
2592 max98090->pclk = (unsigned)-1;
2593 max98090->master = false;
2595 cdata = &max98090->dai[0];
2596 cdata->rate = (unsigned)-1;
2597 cdata->fmt = (unsigned)-1;
2599 max98090->lin_state = 0;
2600 max98090->pa1en = 0;
2601 max98090->pa2en = 0;
2603 ret = snd_soc_component_read32(component, M98090_REG_REVISION_ID);
2605 dev_err(component->dev, "Failed to read device revision: %d\n",
2610 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2612 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret);
2613 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2615 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret);
2618 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret);
2621 if (max98090->devtype != devtype) {
2622 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n");
2623 max98090->devtype = devtype;
2626 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2628 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2629 INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
2630 max98090_pll_det_enable_work);
2631 INIT_WORK(&max98090->pll_det_disable_work,
2632 max98090_pll_det_disable_work);
2634 /* Enable jack detection */
2635 snd_soc_component_write(component, M98090_REG_JACK_DETECT,
2636 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2639 * Clear any old interrupts.
2640 * An old interrupt ocurring prior to installing the ISR
2641 * can keep a new interrupt from generating a trigger.
2643 snd_soc_component_read32(component, M98090_REG_DEVICE_STATUS);
2646 * SHDN should be 0 at the point, no need to save/restore for the
2647 * following registers.
2649 * High Performance is default
2651 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2653 1 << M98090_DACHP_SHIFT);
2654 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL,
2655 M98090_PERFMODE_MASK,
2656 0 << M98090_PERFMODE_SHIFT);
2657 snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL,
2659 1 << M98090_ADCHP_SHIFT);
2662 * SHDN should be 0 at the point, no need to save/restore for the
2663 * following registers.
2665 * Turn on VCM bandgap reference
2667 snd_soc_component_write(component, M98090_REG_BIAS_CONTROL,
2668 M98090_VCM_MODE_MASK);
2670 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias);
2672 micbias = M98090_MBVSEL_2V8;
2673 dev_info(component->dev, "use default 2.8v micbias\n");
2674 } else if (micbias > M98090_MBVSEL_2V8) {
2675 dev_err(component->dev, "micbias out of range 0x%x\n", micbias);
2676 micbias = M98090_MBVSEL_2V8;
2679 snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE,
2680 M98090_MBVSEL_MASK, micbias);
2682 max98090_add_widgets(component);
2688 static void max98090_remove(struct snd_soc_component *component)
2690 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component);
2692 cancel_delayed_work_sync(&max98090->jack_work);
2693 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2694 cancel_work_sync(&max98090->pll_det_disable_work);
2695 max98090->component = NULL;
2698 static const struct snd_soc_component_driver soc_component_dev_max98090 = {
2699 .probe = max98090_probe,
2700 .remove = max98090_remove,
2701 .set_bias_level = max98090_set_bias_level,
2703 .use_pmdown_time = 1,
2705 .non_legacy_dai_naming = 1,
2708 static const struct regmap_config max98090_regmap = {
2712 .max_register = MAX98090_MAX_REGISTER,
2713 .reg_defaults = max98090_reg,
2714 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2715 .volatile_reg = max98090_volatile_register,
2716 .readable_reg = max98090_readable_register,
2717 .cache_type = REGCACHE_RBTREE,
2720 static int max98090_i2c_probe(struct i2c_client *i2c,
2721 const struct i2c_device_id *i2c_id)
2723 struct max98090_priv *max98090;
2724 const struct acpi_device_id *acpi_id;
2725 kernel_ulong_t driver_data = 0;
2728 pr_debug("max98090_i2c_probe\n");
2730 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2732 if (max98090 == NULL)
2735 if (ACPI_HANDLE(&i2c->dev)) {
2736 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2739 dev_err(&i2c->dev, "No driver data\n");
2742 driver_data = acpi_id->driver_data;
2743 } else if (i2c_id) {
2744 driver_data = i2c_id->driver_data;
2747 max98090->devtype = driver_data;
2748 i2c_set_clientdata(i2c, max98090);
2749 max98090->pdata = i2c->dev.platform_data;
2751 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
2752 &max98090->dmic_freq);
2754 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
2756 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2757 if (IS_ERR(max98090->regmap)) {
2758 ret = PTR_ERR(max98090->regmap);
2759 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2763 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2764 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2765 "max98090_interrupt", max98090);
2767 dev_err(&i2c->dev, "request_irq failed: %d\n",
2772 ret = devm_snd_soc_register_component(&i2c->dev,
2773 &soc_component_dev_max98090, max98090_dai,
2774 ARRAY_SIZE(max98090_dai));
2779 static void max98090_i2c_shutdown(struct i2c_client *i2c)
2781 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
2784 * Enable volume smoothing, disable zero cross. This will cause
2785 * a quick 40ms ramp to mute on shutdown.
2787 regmap_write(max98090->regmap,
2788 M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK);
2789 regmap_write(max98090->regmap,
2790 M98090_REG_DEVICE_SHUTDOWN, 0x00);
2794 static int max98090_i2c_remove(struct i2c_client *client)
2796 max98090_i2c_shutdown(client);
2802 static int max98090_runtime_resume(struct device *dev)
2804 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2806 regcache_cache_only(max98090->regmap, false);
2808 max98090_reset(max98090);
2810 regcache_sync(max98090->regmap);
2815 static int max98090_runtime_suspend(struct device *dev)
2817 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2819 regcache_cache_only(max98090->regmap, true);
2825 #ifdef CONFIG_PM_SLEEP
2826 static int max98090_resume(struct device *dev)
2828 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2829 unsigned int status;
2831 regcache_mark_dirty(max98090->regmap);
2833 max98090_reset(max98090);
2835 /* clear IRQ status */
2836 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2838 regcache_sync(max98090->regmap);
2844 static const struct dev_pm_ops max98090_pm = {
2845 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2846 max98090_runtime_resume, NULL)
2847 SET_SYSTEM_SLEEP_PM_OPS(NULL, max98090_resume)
2850 static const struct i2c_device_id max98090_i2c_id[] = {
2851 { "max98090", MAX98090 },
2852 { "max98091", MAX98091 },
2855 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2857 static const struct of_device_id max98090_of_match[] = {
2858 { .compatible = "maxim,max98090", },
2859 { .compatible = "maxim,max98091", },
2862 MODULE_DEVICE_TABLE(of, max98090_of_match);
2865 static const struct acpi_device_id max98090_acpi_match[] = {
2866 { "193C9890", MAX98090 },
2869 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2872 static struct i2c_driver max98090_i2c_driver = {
2876 .of_match_table = of_match_ptr(max98090_of_match),
2877 .acpi_match_table = ACPI_PTR(max98090_acpi_match),
2879 .probe = max98090_i2c_probe,
2880 .shutdown = max98090_i2c_shutdown,
2881 .remove = max98090_i2c_remove,
2882 .id_table = max98090_i2c_id,
2885 module_i2c_driver(max98090_i2c_driver);
2887 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2888 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2889 MODULE_LICENSE("GPL");