sound/soc/codecs/lpass-rx-macro.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
   3
   4 #include <linux/module.h>
   5 #include <linux/init.h>
   6 #include <linux/io.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/clk.h>
   9 #include <sound/soc.h>
  10 #include <sound/pcm.h>
  11 #include <sound/pcm_params.h>
  12 #include <sound/soc-dapm.h>
  13 #include <sound/tlv.h>
  14 #include <linux/of_clk.h>
  15 #include <linux/clk-provider.h>
  16
  17 #define CDC_RX_TOP_TOP_CFG0             (0x0000)
  18 #define CDC_RX_TOP_SWR_CTRL             (0x0008)
  19 #define CDC_RX_TOP_DEBUG                (0x000C)
  20 #define CDC_RX_TOP_DEBUG_BUS            (0x0010)
  21 #define CDC_RX_TOP_DEBUG_EN0            (0x0014)
  22 #define CDC_RX_TOP_DEBUG_EN1            (0x0018)
  23 #define CDC_RX_TOP_DEBUG_EN2            (0x001C)
  24 #define CDC_RX_TOP_HPHL_COMP_WR_LSB     (0x0020)
  25 #define CDC_RX_TOP_HPHL_COMP_WR_MSB     (0x0024)
  26 #define CDC_RX_TOP_HPHL_COMP_LUT        (0x0028)
  27 #define CDC_RX_TOP_HPH_LUT_BYPASS_MASK  BIT(7)
  28 #define CDC_RX_TOP_HPHL_COMP_RD_LSB     (0x002C)
  29 #define CDC_RX_TOP_HPHL_COMP_RD_MSB     (0x0030)
  30 #define CDC_RX_TOP_HPHR_COMP_WR_LSB     (0x0034)
  31 #define CDC_RX_TOP_HPHR_COMP_WR_MSB     (0x0038)
  32 #define CDC_RX_TOP_HPHR_COMP_LUT        (0x003C)
  33 #define CDC_RX_TOP_HPHR_COMP_RD_LSB     (0x0040)
  34 #define CDC_RX_TOP_HPHR_COMP_RD_MSB     (0x0044)
  35 #define CDC_RX_TOP_DSD0_DEBUG_CFG0      (0x0070)
  36 #define CDC_RX_TOP_DSD0_DEBUG_CFG1      (0x0074)
  37 #define CDC_RX_TOP_DSD0_DEBUG_CFG2      (0x0078)
  38 #define CDC_RX_TOP_DSD0_DEBUG_CFG3      (0x007C)
  39 #define CDC_RX_TOP_DSD1_DEBUG_CFG0      (0x0080)
  40 #define CDC_RX_TOP_DSD1_DEBUG_CFG1      (0x0084)
  41 #define CDC_RX_TOP_DSD1_DEBUG_CFG2      (0x0088)
  42 #define CDC_RX_TOP_DSD1_DEBUG_CFG3      (0x008C)
  43 #define CDC_RX_TOP_RX_I2S_CTL           (0x0090)
  44 #define CDC_RX_TOP_TX_I2S2_CTL          (0x0094)
  45 #define CDC_RX_TOP_I2S_CLK              (0x0098)
  46 #define CDC_RX_TOP_I2S_RESET            (0x009C)
  47 #define CDC_RX_TOP_I2S_MUX              (0x00A0)
  48 #define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL        (0x0100)
  49 #define CDC_RX_CLK_MCLK_EN_MASK         BIT(0)
  50 #define CDC_RX_CLK_MCLK_ENABLE          BIT(0)
  51 #define CDC_RX_CLK_MCLK2_EN_MASK        BIT(1)
  52 #define CDC_RX_CLK_MCLK2_ENABLE         BIT(1)
  53 #define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL      (0x0104)
  54 #define CDC_RX_FS_MCLK_CNT_EN_MASK      BIT(0)
  55 #define CDC_RX_FS_MCLK_CNT_ENABLE       BIT(0)
  56 #define CDC_RX_FS_MCLK_CNT_CLR_MASK     BIT(1)
  57 #define CDC_RX_FS_MCLK_CNT_CLR          BIT(1)
  58 #define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108)
  59 #define CDC_RX_SWR_CLK_EN_MASK          BIT(0)
  60 #define CDC_RX_SWR_RESET_MASK           BIT(1)
  61 #define CDC_RX_SWR_RESET                BIT(1)
  62 #define CDC_RX_CLK_RST_CTRL_DSD_CONTROL (0x010C)
  63 #define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL  (0x0110)
  64 #define CDC_RX_SOFTCLIP_CRC             (0x0140)
  65 #define CDC_RX_SOFTCLIP_CLK_EN_MASK     BIT(0)
  66 #define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL   (0x0144)
  67 #define CDC_RX_SOFTCLIP_EN_MASK         BIT(0)
  68 #define CDC_RX_INP_MUX_RX_INT0_CFG0     (0x0180)
  69 #define CDC_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(3, 0)
  70 #define CDC_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(7, 4)
  71 #define CDC_RX_INP_MUX_RX_INT0_CFG1     (0x0184)
  72 #define CDC_RX_INTX_2_SEL_MASK          GENMASK(3, 0)
  73 #define CDC_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(7, 4)
  74 #define CDC_RX_INP_MUX_RX_INT1_CFG0     (0x0188)
  75 #define CDC_RX_INP_MUX_RX_INT1_CFG1     (0x018C)
  76 #define CDC_RX_INP_MUX_RX_INT2_CFG0     (0x0190)
  77 #define CDC_RX_INP_MUX_RX_INT2_CFG1     (0x0194)
  78 #define CDC_RX_INP_MUX_RX_MIX_CFG4      (0x0198)
  79 #define CDC_RX_INP_MUX_RX_MIX_CFG5      (0x019C)
  80 #define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0        (0x01A0)
  81 #define CDC_RX_CLSH_CRC                 (0x0200)
  82 #define CDC_RX_CLSH_CLK_EN_MASK         BIT(0)
  83 #define CDC_RX_CLSH_DLY_CTRL            (0x0204)
  84 #define CDC_RX_CLSH_DECAY_CTRL          (0x0208)
  85 #define CDC_RX_CLSH_DECAY_RATE_MASK     GENMASK(2, 0)
  86 #define CDC_RX_CLSH_HPH_V_PA            (0x020C)
  87 #define CDC_RX_CLSH_HPH_V_PA_MIN_MASK   GENMASK(5, 0)
  88 #define CDC_RX_CLSH_EAR_V_PA            (0x0210)
  89 #define CDC_RX_CLSH_HPH_V_HD            (0x0214)
  90 #define CDC_RX_CLSH_EAR_V_HD            (0x0218)
  91 #define CDC_RX_CLSH_K1_MSB              (0x021C)
  92 #define CDC_RX_CLSH_K1_MSB_COEFF_MASK   GENMASK(3, 0)
  93 #define CDC_RX_CLSH_K1_LSB              (0x0220)
  94 #define CDC_RX_CLSH_K2_MSB              (0x0224)
  95 #define CDC_RX_CLSH_K2_LSB              (0x0228)
  96 #define CDC_RX_CLSH_IDLE_CTRL           (0x022C)
  97 #define CDC_RX_CLSH_IDLE_HPH            (0x0230)
  98 #define CDC_RX_CLSH_IDLE_EAR            (0x0234)
  99 #define CDC_RX_CLSH_TEST0               (0x0238)
 100 #define CDC_RX_CLSH_TEST1               (0x023C)
 101 #define CDC_RX_CLSH_OVR_VREF            (0x0240)
 102 #define CDC_RX_CLSH_CLSG_CTL            (0x0244)
 103 #define CDC_RX_CLSH_CLSG_CFG1           (0x0248)
 104 #define CDC_RX_CLSH_CLSG_CFG2           (0x024C)
 105 #define CDC_RX_BCL_VBAT_PATH_CTL        (0x0280)
 106 #define CDC_RX_BCL_VBAT_CFG             (0x0284)
 107 #define CDC_RX_BCL_VBAT_ADC_CAL1        (0x0288)
 108 #define CDC_RX_BCL_VBAT_ADC_CAL2        (0x028C)
 109 #define CDC_RX_BCL_VBAT_ADC_CAL3        (0x0290)
 110 #define CDC_RX_BCL_VBAT_PK_EST1         (0x0294)
 111 #define CDC_RX_BCL_VBAT_PK_EST2         (0x0298)
 112 #define CDC_RX_BCL_VBAT_PK_EST3         (0x029C)
 113 #define CDC_RX_BCL_VBAT_RF_PROC1        (0x02A0)
 114 #define CDC_RX_BCL_VBAT_RF_PROC2        (0x02A4)
 115 #define CDC_RX_BCL_VBAT_TAC1            (0x02A8)
 116 #define CDC_RX_BCL_VBAT_TAC2            (0x02AC)
 117 #define CDC_RX_BCL_VBAT_TAC3            (0x02B0)
 118 #define CDC_RX_BCL_VBAT_TAC4            (0x02B4)
 119 #define CDC_RX_BCL_VBAT_GAIN_UPD1       (0x02B8)
 120 #define CDC_RX_BCL_VBAT_GAIN_UPD2       (0x02BC)
 121 #define CDC_RX_BCL_VBAT_GAIN_UPD3       (0x02C0)
 122 #define CDC_RX_BCL_VBAT_GAIN_UPD4       (0x02C4)
 123 #define CDC_RX_BCL_VBAT_GAIN_UPD5       (0x02C8)
 124 #define CDC_RX_BCL_VBAT_DEBUG1          (0x02CC)
 125 #define CDC_RX_BCL_VBAT_GAIN_UPD_MON    (0x02D0)
 126 #define CDC_RX_BCL_VBAT_GAIN_MON_VAL    (0x02D4)
 127 #define CDC_RX_BCL_VBAT_BAN             (0x02D8)
 128 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1   (0x02DC)
 129 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2   (0x02E0)
 130 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3   (0x02E4)
 131 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4   (0x02E8)
 132 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5   (0x02EC)
 133 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6   (0x02F0)
 134 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7   (0x02F4)
 135 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8   (0x02F8)
 136 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9   (0x02FC)
 137 #define CDC_RX_BCL_VBAT_ATTN1           (0x0300)
 138 #define CDC_RX_BCL_VBAT_ATTN2           (0x0304)
 139 #define CDC_RX_BCL_VBAT_ATTN3           (0x0308)
 140 #define CDC_RX_BCL_VBAT_DECODE_CTL1     (0x030C)
 141 #define CDC_RX_BCL_VBAT_DECODE_CTL2     (0x0310)
 142 #define CDC_RX_BCL_VBAT_DECODE_CFG1     (0x0314)
 143 #define CDC_RX_BCL_VBAT_DECODE_CFG2     (0x0318)
 144 #define CDC_RX_BCL_VBAT_DECODE_CFG3     (0x031C)
 145 #define CDC_RX_BCL_VBAT_DECODE_CFG4     (0x0320)
 146 #define CDC_RX_BCL_VBAT_DECODE_ST       (0x0324)
 147 #define CDC_RX_INTR_CTRL_CFG            (0x0340)
 148 #define CDC_RX_INTR_CTRL_CLR_COMMIT     (0x0344)
 149 #define CDC_RX_INTR_CTRL_PIN1_MASK0     (0x0360)
 150 #define CDC_RX_INTR_CTRL_PIN1_STATUS0   (0x0368)
 151 #define CDC_RX_INTR_CTRL_PIN1_CLEAR0    (0x0370)
 152 #define CDC_RX_INTR_CTRL_PIN2_MASK0     (0x0380)
 153 #define CDC_RX_INTR_CTRL_PIN2_STATUS0   (0x0388)
 154 #define CDC_RX_INTR_CTRL_PIN2_CLEAR0    (0x0390)
 155 #define CDC_RX_INTR_CTRL_LEVEL0         (0x03C0)
 156 #define CDC_RX_INTR_CTRL_BYPASS0        (0x03C8)
 157 #define CDC_RX_INTR_CTRL_SET0           (0x03D0)
 158 #define CDC_RX_RXn_RX_PATH_CTL(n)       (0x0400 + 0x80 * n)
 159 #define CDC_RX_RX0_RX_PATH_CTL          (0x0400)
 160 #define CDC_RX_PATH_RESET_EN_MASK       BIT(6)
 161 #define CDC_RX_PATH_CLK_EN_MASK         BIT(5)
 162 #define CDC_RX_PATH_CLK_ENABLE          BIT(5)
 163 #define CDC_RX_PATH_PGA_MUTE_MASK       BIT(4)
 164 #define CDC_RX_PATH_PGA_MUTE_ENABLE     BIT(4)
 165 #define CDC_RX_PATH_PCM_RATE_MASK       GENMASK(3, 0)
 166 #define CDC_RX_RXn_RX_PATH_CFG0(n)      (0x0404 + 0x80 * n)
 167 #define CDC_RX_RXn_COMP_EN_MASK         BIT(1)
 168 #define CDC_RX_RX0_RX_PATH_CFG0         (0x0404)
 169 #define CDC_RX_RXn_CLSH_EN_MASK         BIT(6)
 170 #define CDC_RX_DLY_ZN_EN_MASK           BIT(3)
 171 #define CDC_RX_DLY_ZN_ENABLE            BIT(3)
 172 #define CDC_RX_RXn_HD2_EN_MASK          BIT(2)
 173 #define CDC_RX_RXn_RX_PATH_CFG1(n)      (0x0408 + 0x80 * n)
 174 #define CDC_RX_RXn_SIDETONE_EN_MASK     BIT(4)
 175 #define CDC_RX_RX0_RX_PATH_CFG1         (0x0408)
 176 #define CDC_RX_RX0_HPH_L_EAR_SEL_MASK   BIT(1)
 177 #define CDC_RX_RXn_RX_PATH_CFG2(n)      (0x040C + 0x80 * n)
 178 #define CDC_RX_RXn_HPF_CUT_FREQ_MASK    GENMASK(1, 0)
 179 #define CDC_RX_RX0_RX_PATH_CFG2         (0x040C)
 180 #define CDC_RX_RXn_RX_PATH_CFG3(n)      (0x0410 + 0x80 * n)
 181 #define CDC_RX_RX0_RX_PATH_CFG3         (0x0410)
 182 #define CDC_RX_DC_COEFF_SEL_MASK        GENMASK(1, 0)
 183 #define CDC_RX_DC_COEFF_SEL_TWO         0x2
 184 #define CDC_RX_RXn_RX_VOL_CTL(n)        (0x0414 + 0x80 * n)
 185 #define CDC_RX_RX0_RX_VOL_CTL           (0x0414)
 186 #define CDC_RX_RXn_RX_PATH_MIX_CTL(n)   (0x0418 + 0x80 * n)
 187 #define CDC_RX_RXn_MIX_PCM_RATE_MASK    GENMASK(3, 0)
 188 #define CDC_RX_RXn_MIX_RESET_MASK       BIT(6)
 189 #define CDC_RX_RXn_MIX_RESET            BIT(6)
 190 #define CDC_RX_RXn_MIX_CLK_EN_MASK      BIT(5)
 191 #define CDC_RX_RX0_RX_PATH_MIX_CTL      (0x0418)
 192 #define CDC_RX_RX0_RX_PATH_MIX_CFG      (0x041C)
 193 #define CDC_RX_RXn_RX_VOL_MIX_CTL(n)    (0x0420 + 0x80 * n)
 194 #define CDC_RX_RX0_RX_VOL_MIX_CTL       (0x0420)
 195 #define CDC_RX_RX0_RX_PATH_SEC1         (0x0424)
 196 #define CDC_RX_RX0_RX_PATH_SEC2         (0x0428)
 197 #define CDC_RX_RX0_RX_PATH_SEC3         (0x042C)
 198 #define CDC_RX_RX0_RX_PATH_SEC4         (0x0430)
 199 #define CDC_RX_RX0_RX_PATH_SEC7         (0x0434)
 200 #define CDC_RX_DSM_OUT_DELAY_SEL_MASK   GENMASK(2, 0)
 201 #define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE 0x2
 202 #define CDC_RX_RX0_RX_PATH_MIX_SEC0     (0x0438)
 203 #define CDC_RX_RX0_RX_PATH_MIX_SEC1     (0x043C)
 204 #define CDC_RX_RXn_RX_PATH_DSM_CTL(n)   (0x0440 + 0x80 * n)
 205 #define CDC_RX_RXn_DSM_CLK_EN_MASK      BIT(0)
 206 #define CDC_RX_RX0_RX_PATH_DSM_CTL      (0x0440)
 207 #define CDC_RX_RX0_RX_PATH_DSM_DATA1    (0x0444)
 208 #define CDC_RX_RX0_RX_PATH_DSM_DATA2    (0x0448)
 209 #define CDC_RX_RX0_RX_PATH_DSM_DATA3    (0x044C)
 210 #define CDC_RX_RX0_RX_PATH_DSM_DATA4    (0x0450)
 211 #define CDC_RX_RX0_RX_PATH_DSM_DATA5    (0x0454)
 212 #define CDC_RX_RX0_RX_PATH_DSM_DATA6    (0x0458)
 213 #define CDC_RX_RX1_RX_PATH_CTL          (0x0480)
 214 #define CDC_RX_RX1_RX_PATH_CFG0         (0x0484)
 215 #define CDC_RX_RX1_RX_PATH_CFG1         (0x0488)
 216 #define CDC_RX_RX1_RX_PATH_CFG2         (0x048C)
 217 #define CDC_RX_RX1_RX_PATH_CFG3         (0x0490)
 218 #define CDC_RX_RX1_RX_VOL_CTL           (0x0494)
 219 #define CDC_RX_RX1_RX_PATH_MIX_CTL      (0x0498)
 220 #define CDC_RX_RX1_RX_PATH_MIX_CFG      (0x049C)
 221 #define CDC_RX_RX1_RX_VOL_MIX_CTL       (0x04A0)
 222 #define CDC_RX_RX1_RX_PATH_SEC1         (0x04A4)
 223 #define CDC_RX_RX1_RX_PATH_SEC2         (0x04A8)
 224 #define CDC_RX_RX1_RX_PATH_SEC3         (0x04AC)
 225 #define CDC_RX_RXn_HD2_ALPHA_MASK       GENMASK(5, 2)
 226 #define CDC_RX_RX1_RX_PATH_SEC4         (0x04B0)
 227 #define CDC_RX_RX1_RX_PATH_SEC7         (0x04B4)
 228 #define CDC_RX_RX1_RX_PATH_MIX_SEC0     (0x04B8)
 229 #define CDC_RX_RX1_RX_PATH_MIX_SEC1     (0x04BC)
 230 #define CDC_RX_RX1_RX_PATH_DSM_CTL      (0x04C0)
 231 #define CDC_RX_RX1_RX_PATH_DSM_DATA1    (0x04C4)
 232 #define CDC_RX_RX1_RX_PATH_DSM_DATA2    (0x04C8)
 233 #define CDC_RX_RX1_RX_PATH_DSM_DATA3    (0x04CC)
 234 #define CDC_RX_RX1_RX_PATH_DSM_DATA4    (0x04D0)
 235 #define CDC_RX_RX1_RX_PATH_DSM_DATA5    (0x04D4)
 236 #define CDC_RX_RX1_RX_PATH_DSM_DATA6    (0x04D8)
 237 #define CDC_RX_RX2_RX_PATH_CTL          (0x0500)
 238 #define CDC_RX_RX2_RX_PATH_CFG0         (0x0504)
 239 #define CDC_RX_RX2_CLSH_EN_MASK         BIT(4)
 240 #define CDC_RX_RX2_DLY_Z_EN_MASK        BIT(3)
 241 #define CDC_RX_RX2_RX_PATH_CFG1         (0x0508)
 242 #define CDC_RX_RX2_RX_PATH_CFG2         (0x050C)
 243 #define CDC_RX_RX2_RX_PATH_CFG3         (0x0510)
 244 #define CDC_RX_RX2_RX_VOL_CTL           (0x0514)
 245 #define CDC_RX_RX2_RX_PATH_MIX_CTL      (0x0518)
 246 #define CDC_RX_RX2_RX_PATH_MIX_CFG      (0x051C)
 247 #define CDC_RX_RX2_RX_VOL_MIX_CTL       (0x0520)
 248 #define CDC_RX_RX2_RX_PATH_SEC0         (0x0524)
 249 #define CDC_RX_RX2_RX_PATH_SEC1         (0x0528)
 250 #define CDC_RX_RX2_RX_PATH_SEC2         (0x052C)
 251 #define CDC_RX_RX2_RX_PATH_SEC3         (0x0530)
 252 #define CDC_RX_RX2_RX_PATH_SEC4         (0x0534)
 253 #define CDC_RX_RX2_RX_PATH_SEC5         (0x0538)
 254 #define CDC_RX_RX2_RX_PATH_SEC6         (0x053C)
 255 #define CDC_RX_RX2_RX_PATH_SEC7         (0x0540)
 256 #define CDC_RX_RX2_RX_PATH_MIX_SEC0     (0x0544)
 257 #define CDC_RX_RX2_RX_PATH_MIX_SEC1     (0x0548)
 258 #define CDC_RX_RX2_RX_PATH_DSM_CTL      (0x054C)
 259 #define CDC_RX_IDLE_DETECT_PATH_CTL     (0x0780)
 260 #define CDC_RX_IDLE_DETECT_CFG0         (0x0784)
 261 #define CDC_RX_IDLE_DETECT_CFG1         (0x0788)
 262 #define CDC_RX_IDLE_DETECT_CFG2         (0x078C)
 263 #define CDC_RX_IDLE_DETECT_CFG3         (0x0790)
 264 #define CDC_RX_COMPANDERn_CTL0(n)       (0x0800 + 0x40 * n)
 265 #define CDC_RX_COMPANDERn_CLK_EN_MASK   BIT(0)
 266 #define CDC_RX_COMPANDERn_SOFT_RST_MASK BIT(1)
 267 #define CDC_RX_COMPANDERn_HALT_MASK     BIT(2)
 268 #define CDC_RX_COMPANDER0_CTL0          (0x0800)
 269 #define CDC_RX_COMPANDER0_CTL1          (0x0804)
 270 #define CDC_RX_COMPANDER0_CTL2          (0x0808)
 271 #define CDC_RX_COMPANDER0_CTL3          (0x080C)
 272 #define CDC_RX_COMPANDER0_CTL4          (0x0810)
 273 #define CDC_RX_COMPANDER0_CTL5          (0x0814)
 274 #define CDC_RX_COMPANDER0_CTL6          (0x0818)
 275 #define CDC_RX_COMPANDER0_CTL7          (0x081C)
 276 #define CDC_RX_COMPANDER1_CTL0          (0x0840)
 277 #define CDC_RX_COMPANDER1_CTL1          (0x0844)
 278 #define CDC_RX_COMPANDER1_CTL2          (0x0848)
 279 #define CDC_RX_COMPANDER1_CTL3          (0x084C)
 280 #define CDC_RX_COMPANDER1_CTL4          (0x0850)
 281 #define CDC_RX_COMPANDER1_CTL5          (0x0854)
 282 #define CDC_RX_COMPANDER1_CTL6          (0x0858)
 283 #define CDC_RX_COMPANDER1_CTL7          (0x085C)
 284 #define CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK BIT(5)
 285 #define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL       (0x0A00)
 286 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL    (0x0A04)
 287 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL    (0x0A08)
 288 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL    (0x0A0C)
 289 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL    (0x0A10)
 290 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL    (0x0A14)
 291 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL    (0x0A18)
 292 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL    (0x0A1C)
 293 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL    (0x0A20)
 294 #define CDC_RX_SIDETONE_IIR0_IIR_CTL            (0x0A24)
 295 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x0A28)
 296 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL    (0x0A2C)
 297 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL    (0x0A30)
 298 #define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL       (0x0A80)
 299 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL    (0x0A84)
 300 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL    (0x0A88)
 301 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL    (0x0A8C)
 302 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL    (0x0A90)
 303 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL    (0x0A94)
 304 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL    (0x0A98)
 305 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL    (0x0A9C)
 306 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL    (0x0AA0)
 307 #define CDC_RX_SIDETONE_IIR1_IIR_CTL            (0x0AA4)
 308 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL (0x0AA8)
 309 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL    (0x0AAC)
 310 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL    (0x0AB0)
 311 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0        (0x0B00)
 312 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1        (0x0B04)
 313 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2        (0x0B08)
 314 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3        (0x0B0C)
 315 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0        (0x0B10)
 316 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1        (0x0B14)
 317 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2        (0x0B18)
 318 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3        (0x0B1C)
 319 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL    (0x0B40)
 320 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1   (0x0B44)
 321 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL    (0x0B50)
 322 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1   (0x0B54)
 323 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL    (0x0C00)
 324 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0        (0x0C04)
 325 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL    (0x0C40)
 326 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0        (0x0C44)
 327 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL    (0x0C80)
 328 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0        (0x0C84)
 329 #define CDC_RX_EC_ASRC0_CLK_RST_CTL             (0x0D00)
 330 #define CDC_RX_EC_ASRC0_CTL0                    (0x0D04)
 331 #define CDC_RX_EC_ASRC0_CTL1                    (0x0D08)
 332 #define CDC_RX_EC_ASRC0_FIFO_CTL                (0x0D0C)
 333 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB    (0x0D10)
 334 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB    (0x0D14)
 335 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB    (0x0D18)
 336 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB    (0x0D1C)
 337 #define CDC_RX_EC_ASRC0_STATUS_FIFO             (0x0D20)
 338 #define CDC_RX_EC_ASRC1_CLK_RST_CTL             (0x0D40)
 339 #define CDC_RX_EC_ASRC1_CTL0                    (0x0D44)
 340 #define CDC_RX_EC_ASRC1_CTL1                    (0x0D48)
 341 #define CDC_RX_EC_ASRC1_FIFO_CTL                (0x0D4C)
 342 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB    (0x0D50)
 343 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB    (0x0D54)
 344 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB    (0x0D58)
 345 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB    (0x0D5C)
 346 #define CDC_RX_EC_ASRC1_STATUS_FIFO             (0x0D60)
 347 #define CDC_RX_EC_ASRC2_CLK_RST_CTL             (0x0D80)
 348 #define CDC_RX_EC_ASRC2_CTL0                    (0x0D84)
 349 #define CDC_RX_EC_ASRC2_CTL1                    (0x0D88)
 350 #define CDC_RX_EC_ASRC2_FIFO_CTL                (0x0D8C)
 351 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB    (0x0D90)
 352 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB    (0x0D94)
 353 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB    (0x0D98)
 354 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB    (0x0D9C)
 355 #define CDC_RX_EC_ASRC2_STATUS_FIFO             (0x0DA0)
 356 #define CDC_RX_DSD0_PATH_CTL                    (0x0F00)
 357 #define CDC_RX_DSD0_CFG0                        (0x0F04)
 358 #define CDC_RX_DSD0_CFG1                        (0x0F08)
 359 #define CDC_RX_DSD0_CFG2                        (0x0F0C)
 360 #define CDC_RX_DSD1_PATH_CTL                    (0x0F80)
 361 #define CDC_RX_DSD1_CFG0                        (0x0F84)
 362 #define CDC_RX_DSD1_CFG1                        (0x0F88)
 363 #define CDC_RX_DSD1_CFG2                        (0x0F8C)
 364 #define RX_MAX_OFFSET                           (0x0F8C)
 365
 366 #define MCLK_FREQ               9600000
 367
 368 #define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 369                         SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
 370                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
 371                         SNDRV_PCM_RATE_384000)
 372 /* Fractional Rates */
 373 #define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
 374                                 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
 375
 376 #define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 377                 SNDRV_PCM_FMTBIT_S24_LE |\
 378                 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
 379
 380 #define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
 381                         SNDRV_PCM_RATE_48000)
 382 #define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 383                 SNDRV_PCM_FMTBIT_S24_LE |\
 384                 SNDRV_PCM_FMTBIT_S24_3LE)
 385
 386 #define RX_MACRO_MAX_DMA_CH_PER_PORT 2
 387
 388 #define RX_MACRO_EC_MIX_TX0_MASK 0xf0
 389 #define RX_MACRO_EC_MIX_TX1_MASK 0x0f
 390 #define RX_MACRO_EC_MIX_TX2_MASK 0x0f
 391
 392 #define COMP_MAX_COEFF 25
 393 #define RX_NUM_CLKS_MAX 5
 394
 395 struct comp_coeff_val {
 396         u8 lsb;
 397         u8 msb;
 398 };
 399
 400 enum {
 401         HPH_ULP,
 402         HPH_LOHIFI,
 403         HPH_MODE_MAX,
 404 };
 405
 406 static const struct comp_coeff_val comp_coeff_table[HPH_MODE_MAX][COMP_MAX_COEFF] = {
 407         {
 408                 {0x40, 0x00},
 409                 {0x4C, 0x00},
 410                 {0x5A, 0x00},
 411                 {0x6B, 0x00},
 412                 {0x7F, 0x00},
 413                 {0x97, 0x00},
 414                 {0xB3, 0x00},
 415                 {0xD5, 0x00},
 416                 {0xFD, 0x00},
 417                 {0x2D, 0x01},
 418                 {0x66, 0x01},
 419                 {0xA7, 0x01},
 420                 {0xF8, 0x01},
 421                 {0x57, 0x02},
 422                 {0xC7, 0x02},
 423                 {0x4B, 0x03},
 424                 {0xE9, 0x03},
 425                 {0xA3, 0x04},
 426                 {0x7D, 0x05},
 427                 {0x90, 0x06},
 428                 {0xD1, 0x07},
 429                 {0x49, 0x09},
 430                 {0x00, 0x0B},
 431                 {0x01, 0x0D},
 432                 {0x59, 0x0F},
 433         },
 434         {
 435                 {0x40, 0x00},
 436                 {0x4C, 0x00},
 437                 {0x5A, 0x00},
 438                 {0x6B, 0x00},
 439                 {0x80, 0x00},
 440                 {0x98, 0x00},
 441                 {0xB4, 0x00},
 442                 {0xD5, 0x00},
 443                 {0xFE, 0x00},
 444                 {0x2E, 0x01},
 445                 {0x66, 0x01},
 446                 {0xA9, 0x01},
 447                 {0xF8, 0x01},
 448                 {0x56, 0x02},
 449                 {0xC4, 0x02},
 450                 {0x4F, 0x03},
 451                 {0xF0, 0x03},
 452                 {0xAE, 0x04},
 453                 {0x8B, 0x05},
 454                 {0x8E, 0x06},
 455                 {0xBC, 0x07},
 456                 {0x56, 0x09},
 457                 {0x0F, 0x0B},
 458                 {0x13, 0x0D},
 459                 {0x6F, 0x0F},
 460         },
 461 };
 462
 463 struct rx_macro_reg_mask_val {
 464         u16 reg;
 465         u8 mask;
 466         u8 val;
 467 };
 468
 469 enum {
 470         INTERP_HPHL,
 471         INTERP_HPHR,
 472         INTERP_AUX,
 473         INTERP_MAX
 474 };
 475
 476 enum {
 477         RX_MACRO_RX0,
 478         RX_MACRO_RX1,
 479         RX_MACRO_RX2,
 480         RX_MACRO_RX3,
 481         RX_MACRO_RX4,
 482         RX_MACRO_RX5,
 483         RX_MACRO_PORTS_MAX
 484 };
 485
 486 enum {
 487         RX_MACRO_COMP1, /* HPH_L */
 488         RX_MACRO_COMP2, /* HPH_R */
 489         RX_MACRO_COMP_MAX
 490 };
 491
 492 enum {
 493         RX_MACRO_EC0_MUX = 0,
 494         RX_MACRO_EC1_MUX,
 495         RX_MACRO_EC2_MUX,
 496         RX_MACRO_EC_MUX_MAX,
 497 };
 498
 499 enum {
 500         INTn_1_INP_SEL_ZERO = 0,
 501         INTn_1_INP_SEL_DEC0,
 502         INTn_1_INP_SEL_DEC1,
 503         INTn_1_INP_SEL_IIR0,
 504         INTn_1_INP_SEL_IIR1,
 505         INTn_1_INP_SEL_RX0,
 506         INTn_1_INP_SEL_RX1,
 507         INTn_1_INP_SEL_RX2,
 508         INTn_1_INP_SEL_RX3,
 509         INTn_1_INP_SEL_RX4,
 510         INTn_1_INP_SEL_RX5,
 511 };
 512
 513 enum {
 514         INTn_2_INP_SEL_ZERO = 0,
 515         INTn_2_INP_SEL_RX0,
 516         INTn_2_INP_SEL_RX1,
 517         INTn_2_INP_SEL_RX2,
 518         INTn_2_INP_SEL_RX3,
 519         INTn_2_INP_SEL_RX4,
 520         INTn_2_INP_SEL_RX5,
 521 };
 522
 523 enum {
 524         INTERP_MAIN_PATH,
 525         INTERP_MIX_PATH,
 526 };
 527
 528 /* Codec supports 2 IIR filters */
 529 enum {
 530         IIR0 = 0,
 531         IIR1,
 532         IIR_MAX,
 533 };
 534
 535 /* Each IIR has 5 Filter Stages */
 536 enum {
 537         BAND1 = 0,
 538         BAND2,
 539         BAND3,
 540         BAND4,
 541         BAND5,
 542         BAND_MAX,
 543 };
 544
 545 #define RX_MACRO_IIR_FILTER_SIZE        (sizeof(u32) * BAND_MAX)
 546
 547 #define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) \
 548 { \
 549         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 550         .info = rx_macro_iir_filter_info, \
 551         .get = rx_macro_get_iir_band_audio_mixer, \
 552         .put = rx_macro_put_iir_band_audio_mixer, \
 553         .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
 554                 .iir_idx = iidx, \
 555                 .band_idx = bidx, \
 556                 .bytes_ext = {.max = RX_MACRO_IIR_FILTER_SIZE, }, \
 557         } \
 558 }
 559
 560 struct interp_sample_rate {
 561         int sample_rate;
 562         int rate_val;
 563 };
 564
 565 static struct interp_sample_rate sr_val_tbl[] = {
 566         {8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5},
 567         {192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA},
 568         {176400, 0xB}, {352800, 0xC},
 569 };
 570
 571 enum {
 572         RX_MACRO_AIF_INVALID = 0,
 573         RX_MACRO_AIF1_PB,
 574         RX_MACRO_AIF2_PB,
 575         RX_MACRO_AIF3_PB,
 576         RX_MACRO_AIF4_PB,
 577         RX_MACRO_AIF_ECHO,
 578         RX_MACRO_MAX_DAIS,
 579 };
 580
 581 enum {
 582         RX_MACRO_AIF1_CAP = 0,
 583         RX_MACRO_AIF2_CAP,
 584         RX_MACRO_AIF3_CAP,
 585         RX_MACRO_MAX_AIF_CAP_DAIS
 586 };
 587
 588 struct rx_macro {
 589         struct device *dev;
 590         int comp_enabled[RX_MACRO_COMP_MAX];
 591         /* Main path clock users count */
 592         int main_clk_users[INTERP_MAX];
 593         int rx_port_value[RX_MACRO_PORTS_MAX];
 594         u16 prim_int_users[INTERP_MAX];
 595         int rx_mclk_users;
 596         bool reset_swr;
 597         int clsh_users;
 598         int rx_mclk_cnt;
 599         bool is_ear_mode_on;
 600         bool hph_pwr_mode;
 601         bool hph_hd2_mode;
 602         struct snd_soc_component *component;
 603         unsigned long active_ch_mask[RX_MACRO_MAX_DAIS];
 604         unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS];
 605         u16 bit_width[RX_MACRO_MAX_DAIS];
 606         int is_softclip_on;
 607         int is_aux_hpf_on;
 608         int softclip_clk_users;
 609
 610         struct regmap *regmap;
 611         struct clk_bulk_data clks[RX_NUM_CLKS_MAX];
 612         struct clk_hw hw;
 613 };
 614 #define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw)
 615
 616 struct wcd_iir_filter_ctl {
 617         unsigned int iir_idx;
 618         unsigned int band_idx;
 619         struct soc_bytes_ext bytes_ext;
 620 };
 621
 622 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
 623
 624 static const char * const rx_int_mix_mux_text[] = {
 625         "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
 626 };
 627
 628 static const char * const rx_prim_mix_text[] = {
 629         "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
 630         "RX3", "RX4", "RX5"
 631 };
 632
 633 static const char * const rx_sidetone_mix_text[] = {
 634         "ZERO", "SRC0", "SRC1", "SRC_SUM"
 635 };
 636
 637 static const char * const iir_inp_mux_text[] = {
 638         "ZERO", "DEC0", "DEC1", "DEC2", "DEC3",
 639         "RX0", "RX1", "RX2", "RX3", "RX4", "RX5"
 640 };
 641
 642 static const char * const rx_int_dem_inp_mux_text[] = {
 643         "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
 644 };
 645
 646 static const char * const rx_int0_1_interp_mux_text[] = {
 647         "ZERO", "RX INT0_1 MIX1",
 648 };
 649
 650 static const char * const rx_int1_1_interp_mux_text[] = {
 651         "ZERO", "RX INT1_1 MIX1",
 652 };
 653
 654 static const char * const rx_int2_1_interp_mux_text[] = {
 655         "ZERO", "RX INT2_1 MIX1",
 656 };
 657
 658 static const char * const rx_int0_2_interp_mux_text[] = {
 659         "ZERO", "RX INT0_2 MUX",
 660 };
 661
 662 static const char * const rx_int1_2_interp_mux_text[] = {
 663         "ZERO", "RX INT1_2 MUX",
 664 };
 665
 666 static const char * const rx_int2_2_interp_mux_text[] = {
 667         "ZERO", "RX INT2_2 MUX",
 668 };
 669
 670 static const char *const rx_macro_mux_text[] = {
 671         "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB"
 672 };
 673
 674 static const char *const rx_macro_hph_pwr_mode_text[] = {
 675         "ULP", "LOHIFI"
 676 };
 677
 678 static const char * const rx_echo_mux_text[] = {
 679         "ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2"
 680 };
 681
 682 static const struct soc_enum rx_macro_hph_pwr_mode_enum =
 683                 SOC_ENUM_SINGLE_EXT(2, rx_macro_hph_pwr_mode_text);
 684 static const struct soc_enum rx_mix_tx2_mux_enum =
 685                 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG5, 0, 4, rx_echo_mux_text);
 686 static const struct soc_enum rx_mix_tx1_mux_enum =
 687                 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 4, rx_echo_mux_text);
 688 static const struct soc_enum rx_mix_tx0_mux_enum =
 689                 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 4, 4, rx_echo_mux_text);
 690
 691 static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0,
 692                             rx_int_mix_mux_text);
 693 static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0,
 694                             rx_int_mix_mux_text);
 695 static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0,
 696                             rx_int_mix_mux_text);
 697
 698 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0,
 699                             rx_prim_mix_text);
 700 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 4,
 701                             rx_prim_mix_text);
 702 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 4,
 703                             rx_prim_mix_text);
 704 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0,
 705                             rx_prim_mix_text);
 706 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 4,
 707                             rx_prim_mix_text);
 708 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 4,
 709                             rx_prim_mix_text);
 710 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0,
 711                             rx_prim_mix_text);
 712 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 4,
 713                             rx_prim_mix_text);
 714 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 4,
 715                             rx_prim_mix_text);
 716
 717 static SOC_ENUM_SINGLE_DECL(rx_int0_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2,
 718                             rx_sidetone_mix_text);
 719 static SOC_ENUM_SINGLE_DECL(rx_int1_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4,
 720                             rx_sidetone_mix_text);
 721 static SOC_ENUM_SINGLE_DECL(rx_int2_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6,
 722                             rx_sidetone_mix_text);
 723 static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0,
 724                             iir_inp_mux_text);
 725 static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0,
 726                             iir_inp_mux_text);
 727 static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0,
 728                             iir_inp_mux_text);
 729 static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0,
 730                             iir_inp_mux_text);
 731 static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0,
 732                             iir_inp_mux_text);
 733 static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0,
 734                             iir_inp_mux_text);
 735 static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0,
 736                             iir_inp_mux_text);
 737 static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0,
 738                             iir_inp_mux_text);
 739
 740 static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0,
 741                             rx_int0_1_interp_mux_text);
 742 static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0,
 743                             rx_int1_1_interp_mux_text);
 744 static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0,
 745                             rx_int2_1_interp_mux_text);
 746 static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0,
 747                             rx_int0_2_interp_mux_text);
 748 static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0,
 749                             rx_int1_2_interp_mux_text);
 750 static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0,
 751                             rx_int2_2_interp_mux_text);
 752 static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0,
 753                             rx_int_dem_inp_mux_text);
 754 static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0,
 755                             rx_int_dem_inp_mux_text);
 756
 757 static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 758 static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 759 static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 760 static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 761 static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 762 static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 763
 764 static const struct snd_kcontrol_new rx_mix_tx1_mux =
 765                 SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum);
 766 static const struct snd_kcontrol_new rx_mix_tx2_mux =
 767                 SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum);
 768 static const struct snd_kcontrol_new rx_int0_2_mux =
 769                 SOC_DAPM_ENUM("rx_int0_2", rx_int0_2_enum);
 770 static const struct snd_kcontrol_new rx_int1_2_mux =
 771                 SOC_DAPM_ENUM("rx_int1_2", rx_int1_2_enum);
 772 static const struct snd_kcontrol_new rx_int2_2_mux =
 773                 SOC_DAPM_ENUM("rx_int2_2", rx_int2_2_enum);
 774 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
 775                 SOC_DAPM_ENUM("rx_int0_1_mix_inp0", rx_int0_1_mix_inp0_enum);
 776 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
 777                 SOC_DAPM_ENUM("rx_int0_1_mix_inp1", rx_int0_1_mix_inp1_enum);
 778 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
 779                 SOC_DAPM_ENUM("rx_int0_1_mix_inp2", rx_int0_1_mix_inp2_enum);
 780 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
 781                 SOC_DAPM_ENUM("rx_int1_1_mix_inp0", rx_int1_1_mix_inp0_enum);
 782 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
 783                 SOC_DAPM_ENUM("rx_int1_1_mix_inp1", rx_int1_1_mix_inp1_enum);
 784 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
 785                 SOC_DAPM_ENUM("rx_int1_1_mix_inp2", rx_int1_1_mix_inp2_enum);
 786 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
 787                 SOC_DAPM_ENUM("rx_int2_1_mix_inp0", rx_int2_1_mix_inp0_enum);
 788 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
 789                 SOC_DAPM_ENUM("rx_int2_1_mix_inp1", rx_int2_1_mix_inp1_enum);
 790 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
 791                 SOC_DAPM_ENUM("rx_int2_1_mix_inp2", rx_int2_1_mix_inp2_enum);
 792 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
 793                 SOC_DAPM_ENUM("rx_int0_mix2_inp", rx_int0_mix2_inp_enum);
 794 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
 795                 SOC_DAPM_ENUM("rx_int1_mix2_inp", rx_int1_mix2_inp_enum);
 796 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
 797                 SOC_DAPM_ENUM("rx_int2_mix2_inp", rx_int2_mix2_inp_enum);
 798 static const struct snd_kcontrol_new iir0_inp0_mux =
 799                 SOC_DAPM_ENUM("iir0_inp0", iir0_inp0_enum);
 800 static const struct snd_kcontrol_new iir0_inp1_mux =
 801                 SOC_DAPM_ENUM("iir0_inp1", iir0_inp1_enum);
 802 static const struct snd_kcontrol_new iir0_inp2_mux =
 803                 SOC_DAPM_ENUM("iir0_inp2", iir0_inp2_enum);
 804 static const struct snd_kcontrol_new iir0_inp3_mux =
 805                 SOC_DAPM_ENUM("iir0_inp3", iir0_inp3_enum);
 806 static const struct snd_kcontrol_new iir1_inp0_mux =
 807                 SOC_DAPM_ENUM("iir1_inp0", iir1_inp0_enum);
 808 static const struct snd_kcontrol_new iir1_inp1_mux =
 809                 SOC_DAPM_ENUM("iir1_inp1", iir1_inp1_enum);
 810 static const struct snd_kcontrol_new iir1_inp2_mux =
 811                 SOC_DAPM_ENUM("iir1_inp2", iir1_inp2_enum);
 812 static const struct snd_kcontrol_new iir1_inp3_mux =
 813                 SOC_DAPM_ENUM("iir1_inp3", iir1_inp3_enum);
 814 static const struct snd_kcontrol_new rx_int0_1_interp_mux =
 815                 SOC_DAPM_ENUM("rx_int0_1_interp", rx_int0_1_interp_enum);
 816 static const struct snd_kcontrol_new rx_int1_1_interp_mux =
 817                 SOC_DAPM_ENUM("rx_int1_1_interp", rx_int1_1_interp_enum);
 818 static const struct snd_kcontrol_new rx_int2_1_interp_mux =
 819                 SOC_DAPM_ENUM("rx_int2_1_interp", rx_int2_1_interp_enum);
 820 static const struct snd_kcontrol_new rx_int0_2_interp_mux =
 821                 SOC_DAPM_ENUM("rx_int0_2_interp", rx_int0_2_interp_enum);
 822 static const struct snd_kcontrol_new rx_int1_2_interp_mux =
 823                 SOC_DAPM_ENUM("rx_int1_2_interp", rx_int1_2_interp_enum);
 824 static const struct snd_kcontrol_new rx_int2_2_interp_mux =
 825                 SOC_DAPM_ENUM("rx_int2_2_interp", rx_int2_2_interp_enum);
 826 static const struct snd_kcontrol_new rx_mix_tx0_mux =
 827                 SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum);
 828
 829 static const struct reg_default rx_defaults[] = {
 830         /* RX Macro */
 831         { CDC_RX_TOP_TOP_CFG0, 0x00 },
 832         { CDC_RX_TOP_SWR_CTRL, 0x00 },
 833         { CDC_RX_TOP_DEBUG, 0x00 },
 834         { CDC_RX_TOP_DEBUG_BUS, 0x00 },
 835         { CDC_RX_TOP_DEBUG_EN0, 0x00 },
 836         { CDC_RX_TOP_DEBUG_EN1, 0x00 },
 837         { CDC_RX_TOP_DEBUG_EN2, 0x00 },
 838         { CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00 },
 839         { CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00 },
 840         { CDC_RX_TOP_HPHL_COMP_LUT, 0x00 },
 841         { CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00 },
 842         { CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00 },
 843         { CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00 },
 844         { CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00 },
 845         { CDC_RX_TOP_HPHR_COMP_LUT, 0x00 },
 846         { CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00 },
 847         { CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00 },
 848         { CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11 },
 849         { CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20 },
 850         { CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00 },
 851         { CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00 },
 852         { CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11 },
 853         { CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20 },
 854         { CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00 },
 855         { CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00 },
 856         { CDC_RX_TOP_RX_I2S_CTL, 0x0C },
 857         { CDC_RX_TOP_TX_I2S2_CTL, 0x0C },
 858         { CDC_RX_TOP_I2S_CLK, 0x0C },
 859         { CDC_RX_TOP_I2S_RESET, 0x00 },
 860         { CDC_RX_TOP_I2S_MUX, 0x00 },
 861         { CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
 862         { CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
 863         { CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
 864         { CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00 },
 865         { CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08 },
 866         { CDC_RX_SOFTCLIP_CRC, 0x00 },
 867         { CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38 },
 868         { CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 },
 869         { CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 },
 870         { CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 },
 871         { CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 },
 872         { CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 },
 873         { CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 },
 874         { CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 },
 875         { CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00 },
 876         { CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 },
 877         { CDC_RX_CLSH_CRC, 0x00 },
 878         { CDC_RX_CLSH_DLY_CTRL, 0x03 },
 879         { CDC_RX_CLSH_DECAY_CTRL, 0x02 },
 880         { CDC_RX_CLSH_HPH_V_PA, 0x1C },
 881         { CDC_RX_CLSH_EAR_V_PA, 0x39 },
 882         { CDC_RX_CLSH_HPH_V_HD, 0x0C },
 883         { CDC_RX_CLSH_EAR_V_HD, 0x0C },
 884         { CDC_RX_CLSH_K1_MSB, 0x01 },
 885         { CDC_RX_CLSH_K1_LSB, 0x00 },
 886         { CDC_RX_CLSH_K2_MSB, 0x00 },
 887         { CDC_RX_CLSH_K2_LSB, 0x80 },
 888         { CDC_RX_CLSH_IDLE_CTRL, 0x00 },
 889         { CDC_RX_CLSH_IDLE_HPH, 0x00 },
 890         { CDC_RX_CLSH_IDLE_EAR, 0x00 },
 891         { CDC_RX_CLSH_TEST0, 0x07 },
 892         { CDC_RX_CLSH_TEST1, 0x00 },
 893         { CDC_RX_CLSH_OVR_VREF, 0x00 },
 894         { CDC_RX_CLSH_CLSG_CTL, 0x02 },
 895         { CDC_RX_CLSH_CLSG_CFG1, 0x9A },
 896         { CDC_RX_CLSH_CLSG_CFG2, 0x10 },
 897         { CDC_RX_BCL_VBAT_PATH_CTL, 0x00 },
 898         { CDC_RX_BCL_VBAT_CFG, 0x10 },
 899         { CDC_RX_BCL_VBAT_ADC_CAL1, 0x00 },
 900         { CDC_RX_BCL_VBAT_ADC_CAL2, 0x00 },
 901         { CDC_RX_BCL_VBAT_ADC_CAL3, 0x04 },
 902         { CDC_RX_BCL_VBAT_PK_EST1, 0xE0 },
 903         { CDC_RX_BCL_VBAT_PK_EST2, 0x01 },
 904         { CDC_RX_BCL_VBAT_PK_EST3, 0x40 },
 905         { CDC_RX_BCL_VBAT_RF_PROC1, 0x2A },
 906         { CDC_RX_BCL_VBAT_RF_PROC1, 0x00 },
 907         { CDC_RX_BCL_VBAT_TAC1, 0x00 },
 908         { CDC_RX_BCL_VBAT_TAC2, 0x18 },
 909         { CDC_RX_BCL_VBAT_TAC3, 0x18 },
 910         { CDC_RX_BCL_VBAT_TAC4, 0x03 },
 911         { CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01 },
 912         { CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00 },
 913         { CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00 },
 914         { CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64 },
 915         { CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01 },
 916         { CDC_RX_BCL_VBAT_DEBUG1, 0x00 },
 917         { CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00 },
 918         { CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00 },
 919         { CDC_RX_BCL_VBAT_BAN, 0x0C },
 920         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00 },
 921         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77 },
 922         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01 },
 923         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00 },
 924         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B },
 925         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00 },
 926         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01 },
 927         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00 },
 928         { CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00 },
 929         { CDC_RX_BCL_VBAT_ATTN1, 0x04 },
 930         { CDC_RX_BCL_VBAT_ATTN2, 0x08 },
 931         { CDC_RX_BCL_VBAT_ATTN3, 0x0C },
 932         { CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0 },
 933         { CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00 },
 934         { CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00 },
 935         { CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00 },
 936         { CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00 },
 937         { CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00 },
 938         { CDC_RX_BCL_VBAT_DECODE_ST, 0x00 },
 939         { CDC_RX_INTR_CTRL_CFG, 0x00 },
 940         { CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00 },
 941         { CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF },
 942         { CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00 },
 943         { CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00 },
 944         { CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF },
 945         { CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00 },
 946         { CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00 },
 947         { CDC_RX_INTR_CTRL_LEVEL0, 0x00 },
 948         { CDC_RX_INTR_CTRL_BYPASS0, 0x00 },
 949         { CDC_RX_INTR_CTRL_SET0, 0x00 },
 950         { CDC_RX_RX0_RX_PATH_CTL, 0x04 },
 951         { CDC_RX_RX0_RX_PATH_CFG0, 0x00 },
 952         { CDC_RX_RX0_RX_PATH_CFG1, 0x64 },
 953         { CDC_RX_RX0_RX_PATH_CFG2, 0x8F },
 954         { CDC_RX_RX0_RX_PATH_CFG3, 0x00 },
 955         { CDC_RX_RX0_RX_VOL_CTL, 0x00 },
 956         { CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04 },
 957         { CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E },
 958         { CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00 },
 959         { CDC_RX_RX0_RX_PATH_SEC1, 0x08 },
 960         { CDC_RX_RX0_RX_PATH_SEC2, 0x00 },
 961         { CDC_RX_RX0_RX_PATH_SEC3, 0x00 },
 962         { CDC_RX_RX0_RX_PATH_SEC4, 0x00 },
 963         { CDC_RX_RX0_RX_PATH_SEC7, 0x00 },
 964         { CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08 },
 965         { CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00 },
 966         { CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08 },
 967         { CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00 },
 968         { CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00 },
 969         { CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00 },
 970         { CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 },
 971         { CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 },
 972         { CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 },
 973         { CDC_RX_RX1_RX_PATH_CTL, 0x04 },
 974         { CDC_RX_RX1_RX_PATH_CFG0, 0x00 },
 975         { CDC_RX_RX1_RX_PATH_CFG1, 0x64 },
 976         { CDC_RX_RX1_RX_PATH_CFG2, 0x8F },
 977         { CDC_RX_RX1_RX_PATH_CFG3, 0x00 },
 978         { CDC_RX_RX1_RX_VOL_CTL, 0x00 },
 979         { CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
 980         { CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
 981         { CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
 982         { CDC_RX_RX1_RX_PATH_SEC1, 0x08 },
 983         { CDC_RX_RX1_RX_PATH_SEC2, 0x00 },
 984         { CDC_RX_RX1_RX_PATH_SEC3, 0x00 },
 985         { CDC_RX_RX1_RX_PATH_SEC4, 0x00 },
 986         { CDC_RX_RX1_RX_PATH_SEC7, 0x00 },
 987         { CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
 988         { CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
 989         { CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
 990         { CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
 991         { CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
 992         { CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
 993         { CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
 994         { CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
 995         { CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
 996         { CDC_RX_RX2_RX_PATH_CTL, 0x04 },
 997         { CDC_RX_RX2_RX_PATH_CFG0, 0x00 },
 998         { CDC_RX_RX2_RX_PATH_CFG1, 0x64 },
 999         { CDC_RX_RX2_RX_PATH_CFG2, 0x8F },
1000         { CDC_RX_RX2_RX_PATH_CFG3, 0x00 },
1001         { CDC_RX_RX2_RX_VOL_CTL, 0x00 },
1002         { CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
1003         { CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
1004         { CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
1005         { CDC_RX_RX2_RX_PATH_SEC0, 0x04 },
1006         { CDC_RX_RX2_RX_PATH_SEC1, 0x08 },
1007         { CDC_RX_RX2_RX_PATH_SEC2, 0x00 },
1008         { CDC_RX_RX2_RX_PATH_SEC3, 0x00 },
1009         { CDC_RX_RX2_RX_PATH_SEC4, 0x00 },
1010         { CDC_RX_RX2_RX_PATH_SEC5, 0x00 },
1011         { CDC_RX_RX2_RX_PATH_SEC6, 0x00 },
1012         { CDC_RX_RX2_RX_PATH_SEC7, 0x00 },
1013         { CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
1014         { CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
1015         { CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
1016         { CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 },
1017         { CDC_RX_IDLE_DETECT_CFG0, 0x07 },
1018         { CDC_RX_IDLE_DETECT_CFG1, 0x3C },
1019         { CDC_RX_IDLE_DETECT_CFG2, 0x00 },
1020         { CDC_RX_IDLE_DETECT_CFG3, 0x00 },
1021         { CDC_RX_COMPANDER0_CTL0, 0x60 },
1022         { CDC_RX_COMPANDER0_CTL1, 0xDB },
1023         { CDC_RX_COMPANDER0_CTL2, 0xFF },
1024         { CDC_RX_COMPANDER0_CTL3, 0x35 },
1025         { CDC_RX_COMPANDER0_CTL4, 0xFF },
1026         { CDC_RX_COMPANDER0_CTL5, 0x00 },
1027         { CDC_RX_COMPANDER0_CTL6, 0x01 },
1028         { CDC_RX_COMPANDER0_CTL7, 0x28 },
1029         { CDC_RX_COMPANDER1_CTL0, 0x60 },
1030         { CDC_RX_COMPANDER1_CTL1, 0xDB },
1031         { CDC_RX_COMPANDER1_CTL2, 0xFF },
1032         { CDC_RX_COMPANDER1_CTL3, 0x35 },
1033         { CDC_RX_COMPANDER1_CTL4, 0xFF },
1034         { CDC_RX_COMPANDER1_CTL5, 0x00 },
1035         { CDC_RX_COMPANDER1_CTL6, 0x01 },
1036         { CDC_RX_COMPANDER1_CTL7, 0x28 },
1037         { CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 },
1038         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 },
1039         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 },
1040         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 },
1041         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 },
1042         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 },
1043         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 },
1044         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 },
1045         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 },
1046         { CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40 },
1047         { CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 },
1048         { CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 },
1049         { CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 },
1050         { CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 },
1051         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 },
1052         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 },
1053         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 },
1054         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 },
1055         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 },
1056         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 },
1057         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 },
1058         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 },
1059         { CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40 },
1060         { CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 },
1061         { CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 },
1062         { CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 },
1063         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 },
1064         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 },
1065         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 },
1066         { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 },
1067         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 },
1068         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 },
1069         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 },
1070         { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 },
1071         { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 },
1072         { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 },
1073         { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 },
1074         { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 },
1075         { CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00 },
1076         { CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01 },
1077         { CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00 },
1078         { CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01 },
1079         { CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00 },
1080         { CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01 },
1081         { CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00 },
1082         { CDC_RX_EC_ASRC0_CTL0, 0x00 },
1083         { CDC_RX_EC_ASRC0_CTL1, 0x00 },
1084         { CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8 },
1085         { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 },
1086         { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 },
1087         { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 },
1088         { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 },
1089         { CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00 },
1090         { CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00 },
1091         { CDC_RX_EC_ASRC1_CTL0, 0x00 },
1092         { CDC_RX_EC_ASRC1_CTL1, 0x00 },
1093         { CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8 },
1094         { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 },
1095         { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 },
1096         { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 },
1097         { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 },
1098         { CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00 },
1099         { CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00 },
1100         { CDC_RX_EC_ASRC2_CTL0, 0x00 },
1101         { CDC_RX_EC_ASRC2_CTL1, 0x00 },
1102         { CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8 },
1103         { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00 },
1104         { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00 },
1105         { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00 },
1106         { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00 },
1107         { CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00 },
1108         { CDC_RX_DSD0_PATH_CTL, 0x00 },
1109         { CDC_RX_DSD0_CFG0, 0x00 },
1110         { CDC_RX_DSD0_CFG1, 0x62 },
1111         { CDC_RX_DSD0_CFG2, 0x96 },
1112         { CDC_RX_DSD1_PATH_CTL, 0x00 },
1113         { CDC_RX_DSD1_CFG0, 0x00 },
1114         { CDC_RX_DSD1_CFG1, 0x62 },
1115         { CDC_RX_DSD1_CFG2, 0x96 },
1116 };
1117
1118 static bool rx_is_wronly_register(struct device *dev,
1119                                         unsigned int reg)
1120 {
1121         switch (reg) {
1122         case CDC_RX_BCL_VBAT_GAIN_UPD_MON:
1123         case CDC_RX_INTR_CTRL_CLR_COMMIT:
1124         case CDC_RX_INTR_CTRL_PIN1_CLEAR0:
1125         case CDC_RX_INTR_CTRL_PIN2_CLEAR0:
1126                 return true;
1127         }
1128
1129         return false;
1130 }
1131
1132 static bool rx_is_volatile_register(struct device *dev, unsigned int reg)
1133 {
1134         /* Update volatile list for rx/tx macros */
1135         switch (reg) {
1136         case CDC_RX_TOP_HPHL_COMP_RD_LSB:
1137         case CDC_RX_TOP_HPHL_COMP_WR_LSB:
1138         case CDC_RX_TOP_HPHL_COMP_RD_MSB:
1139         case CDC_RX_TOP_HPHL_COMP_WR_MSB:
1140         case CDC_RX_TOP_HPHR_COMP_RD_LSB:
1141         case CDC_RX_TOP_HPHR_COMP_WR_LSB:
1142         case CDC_RX_TOP_HPHR_COMP_RD_MSB:
1143         case CDC_RX_TOP_HPHR_COMP_WR_MSB:
1144         case CDC_RX_TOP_DSD0_DEBUG_CFG2:
1145         case CDC_RX_TOP_DSD1_DEBUG_CFG2:
1146         case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
1147         case CDC_RX_BCL_VBAT_DECODE_ST:
1148         case CDC_RX_INTR_CTRL_PIN1_STATUS0:
1149         case CDC_RX_INTR_CTRL_PIN2_STATUS0:
1150         case CDC_RX_COMPANDER0_CTL6:
1151         case CDC_RX_COMPANDER1_CTL6:
1152         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
1153         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
1154         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
1155         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
1156         case CDC_RX_EC_ASRC0_STATUS_FIFO:
1157         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
1158         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
1159         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
1160         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
1161         case CDC_RX_EC_ASRC1_STATUS_FIFO:
1162         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
1163         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
1164         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
1165         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
1166         case CDC_RX_EC_ASRC2_STATUS_FIFO:
1167                 return true;
1168         }
1169         return false;
1170 }
1171
1172 static bool rx_is_rw_register(struct device *dev, unsigned int reg)
1173 {
1174         switch (reg) {
1175         case CDC_RX_TOP_TOP_CFG0:
1176         case CDC_RX_TOP_SWR_CTRL:
1177         case CDC_RX_TOP_DEBUG:
1178         case CDC_RX_TOP_DEBUG_BUS:
1179         case CDC_RX_TOP_DEBUG_EN0:
1180         case CDC_RX_TOP_DEBUG_EN1:
1181         case CDC_RX_TOP_DEBUG_EN2:
1182         case CDC_RX_TOP_HPHL_COMP_WR_LSB:
1183         case CDC_RX_TOP_HPHL_COMP_WR_MSB:
1184         case CDC_RX_TOP_HPHL_COMP_LUT:
1185         case CDC_RX_TOP_HPHR_COMP_WR_LSB:
1186         case CDC_RX_TOP_HPHR_COMP_WR_MSB:
1187         case CDC_RX_TOP_HPHR_COMP_LUT:
1188         case CDC_RX_TOP_DSD0_DEBUG_CFG0:
1189         case CDC_RX_TOP_DSD0_DEBUG_CFG1:
1190         case CDC_RX_TOP_DSD0_DEBUG_CFG3:
1191         case CDC_RX_TOP_DSD1_DEBUG_CFG0:
1192         case CDC_RX_TOP_DSD1_DEBUG_CFG1:
1193         case CDC_RX_TOP_DSD1_DEBUG_CFG3:
1194         case CDC_RX_TOP_RX_I2S_CTL:
1195         case CDC_RX_TOP_TX_I2S2_CTL:
1196         case CDC_RX_TOP_I2S_CLK:
1197         case CDC_RX_TOP_I2S_RESET:
1198         case CDC_RX_TOP_I2S_MUX:
1199         case CDC_RX_CLK_RST_CTRL_MCLK_CONTROL:
1200         case CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL:
1201         case CDC_RX_CLK_RST_CTRL_SWR_CONTROL:
1202         case CDC_RX_CLK_RST_CTRL_DSD_CONTROL:
1203         case CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL:
1204         case CDC_RX_SOFTCLIP_CRC:
1205         case CDC_RX_SOFTCLIP_SOFTCLIP_CTRL:
1206         case CDC_RX_INP_MUX_RX_INT0_CFG0:
1207         case CDC_RX_INP_MUX_RX_INT0_CFG1:
1208         case CDC_RX_INP_MUX_RX_INT1_CFG0:
1209         case CDC_RX_INP_MUX_RX_INT1_CFG1:
1210         case CDC_RX_INP_MUX_RX_INT2_CFG0:
1211         case CDC_RX_INP_MUX_RX_INT2_CFG1:
1212         case CDC_RX_INP_MUX_RX_MIX_CFG4:
1213         case CDC_RX_INP_MUX_RX_MIX_CFG5:
1214         case CDC_RX_INP_MUX_SIDETONE_SRC_CFG0:
1215         case CDC_RX_CLSH_CRC:
1216         case CDC_RX_CLSH_DLY_CTRL:
1217         case CDC_RX_CLSH_DECAY_CTRL:
1218         case CDC_RX_CLSH_HPH_V_PA:
1219         case CDC_RX_CLSH_EAR_V_PA:
1220         case CDC_RX_CLSH_HPH_V_HD:
1221         case CDC_RX_CLSH_EAR_V_HD:
1222         case CDC_RX_CLSH_K1_MSB:
1223         case CDC_RX_CLSH_K1_LSB:
1224         case CDC_RX_CLSH_K2_MSB:
1225         case CDC_RX_CLSH_K2_LSB:
1226         case CDC_RX_CLSH_IDLE_CTRL:
1227         case CDC_RX_CLSH_IDLE_HPH:
1228         case CDC_RX_CLSH_IDLE_EAR:
1229         case CDC_RX_CLSH_TEST0:
1230         case CDC_RX_CLSH_TEST1:
1231         case CDC_RX_CLSH_OVR_VREF:
1232         case CDC_RX_CLSH_CLSG_CTL:
1233         case CDC_RX_CLSH_CLSG_CFG1:
1234         case CDC_RX_CLSH_CLSG_CFG2:
1235         case CDC_RX_BCL_VBAT_PATH_CTL:
1236         case CDC_RX_BCL_VBAT_CFG:
1237         case CDC_RX_BCL_VBAT_ADC_CAL1:
1238         case CDC_RX_BCL_VBAT_ADC_CAL2:
1239         case CDC_RX_BCL_VBAT_ADC_CAL3:
1240         case CDC_RX_BCL_VBAT_PK_EST1:
1241         case CDC_RX_BCL_VBAT_PK_EST2:
1242         case CDC_RX_BCL_VBAT_PK_EST3:
1243         case CDC_RX_BCL_VBAT_RF_PROC1:
1244         case CDC_RX_BCL_VBAT_RF_PROC2:
1245         case CDC_RX_BCL_VBAT_TAC1:
1246         case CDC_RX_BCL_VBAT_TAC2:
1247         case CDC_RX_BCL_VBAT_TAC3:
1248         case CDC_RX_BCL_VBAT_TAC4:
1249         case CDC_RX_BCL_VBAT_GAIN_UPD1:
1250         case CDC_RX_BCL_VBAT_GAIN_UPD2:
1251         case CDC_RX_BCL_VBAT_GAIN_UPD3:
1252         case CDC_RX_BCL_VBAT_GAIN_UPD4:
1253         case CDC_RX_BCL_VBAT_GAIN_UPD5:
1254         case CDC_RX_BCL_VBAT_DEBUG1:
1255         case CDC_RX_BCL_VBAT_BAN:
1256         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD1:
1257         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD2:
1258         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD3:
1259         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD4:
1260         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD5:
1261         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD6:
1262         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD7:
1263         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD8:
1264         case CDC_RX_BCL_VBAT_BCL_GAIN_UPD9:
1265         case CDC_RX_BCL_VBAT_ATTN1:
1266         case CDC_RX_BCL_VBAT_ATTN2:
1267         case CDC_RX_BCL_VBAT_ATTN3:
1268         case CDC_RX_BCL_VBAT_DECODE_CTL1:
1269         case CDC_RX_BCL_VBAT_DECODE_CTL2:
1270         case CDC_RX_BCL_VBAT_DECODE_CFG1:
1271         case CDC_RX_BCL_VBAT_DECODE_CFG2:
1272         case CDC_RX_BCL_VBAT_DECODE_CFG3:
1273         case CDC_RX_BCL_VBAT_DECODE_CFG4:
1274         case CDC_RX_INTR_CTRL_CFG:
1275         case CDC_RX_INTR_CTRL_PIN1_MASK0:
1276         case CDC_RX_INTR_CTRL_PIN2_MASK0:
1277         case CDC_RX_INTR_CTRL_LEVEL0:
1278         case CDC_RX_INTR_CTRL_BYPASS0:
1279         case CDC_RX_INTR_CTRL_SET0:
1280         case CDC_RX_RX0_RX_PATH_CTL:
1281         case CDC_RX_RX0_RX_PATH_CFG0:
1282         case CDC_RX_RX0_RX_PATH_CFG1:
1283         case CDC_RX_RX0_RX_PATH_CFG2:
1284         case CDC_RX_RX0_RX_PATH_CFG3:
1285         case CDC_RX_RX0_RX_VOL_CTL:
1286         case CDC_RX_RX0_RX_PATH_MIX_CTL:
1287         case CDC_RX_RX0_RX_PATH_MIX_CFG:
1288         case CDC_RX_RX0_RX_VOL_MIX_CTL:
1289         case CDC_RX_RX0_RX_PATH_SEC1:
1290         case CDC_RX_RX0_RX_PATH_SEC2:
1291         case CDC_RX_RX0_RX_PATH_SEC3:
1292         case CDC_RX_RX0_RX_PATH_SEC4:
1293         case CDC_RX_RX0_RX_PATH_SEC7:
1294         case CDC_RX_RX0_RX_PATH_MIX_SEC0:
1295         case CDC_RX_RX0_RX_PATH_MIX_SEC1:
1296         case CDC_RX_RX0_RX_PATH_DSM_CTL:
1297         case CDC_RX_RX0_RX_PATH_DSM_DATA1:
1298         case CDC_RX_RX0_RX_PATH_DSM_DATA2:
1299         case CDC_RX_RX0_RX_PATH_DSM_DATA3:
1300         case CDC_RX_RX0_RX_PATH_DSM_DATA4:
1301         case CDC_RX_RX0_RX_PATH_DSM_DATA5:
1302         case CDC_RX_RX0_RX_PATH_DSM_DATA6:
1303         case CDC_RX_RX1_RX_PATH_CTL:
1304         case CDC_RX_RX1_RX_PATH_CFG0:
1305         case CDC_RX_RX1_RX_PATH_CFG1:
1306         case CDC_RX_RX1_RX_PATH_CFG2:
1307         case CDC_RX_RX1_RX_PATH_CFG3:
1308         case CDC_RX_RX1_RX_VOL_CTL:
1309         case CDC_RX_RX1_RX_PATH_MIX_CTL:
1310         case CDC_RX_RX1_RX_PATH_MIX_CFG:
1311         case CDC_RX_RX1_RX_VOL_MIX_CTL:
1312         case CDC_RX_RX1_RX_PATH_SEC1:
1313         case CDC_RX_RX1_RX_PATH_SEC2:
1314         case CDC_RX_RX1_RX_PATH_SEC3:
1315         case CDC_RX_RX1_RX_PATH_SEC4:
1316         case CDC_RX_RX1_RX_PATH_SEC7:
1317         case CDC_RX_RX1_RX_PATH_MIX_SEC0:
1318         case CDC_RX_RX1_RX_PATH_MIX_SEC1:
1319         case CDC_RX_RX1_RX_PATH_DSM_CTL:
1320         case CDC_RX_RX1_RX_PATH_DSM_DATA1:
1321         case CDC_RX_RX1_RX_PATH_DSM_DATA2:
1322         case CDC_RX_RX1_RX_PATH_DSM_DATA3:
1323         case CDC_RX_RX1_RX_PATH_DSM_DATA4:
1324         case CDC_RX_RX1_RX_PATH_DSM_DATA5:
1325         case CDC_RX_RX1_RX_PATH_DSM_DATA6:
1326         case CDC_RX_RX2_RX_PATH_CTL:
1327         case CDC_RX_RX2_RX_PATH_CFG0:
1328         case CDC_RX_RX2_RX_PATH_CFG1:
1329         case CDC_RX_RX2_RX_PATH_CFG2:
1330         case CDC_RX_RX2_RX_PATH_CFG3:
1331         case CDC_RX_RX2_RX_VOL_CTL:
1332         case CDC_RX_RX2_RX_PATH_MIX_CTL:
1333         case CDC_RX_RX2_RX_PATH_MIX_CFG:
1334         case CDC_RX_RX2_RX_VOL_MIX_CTL:
1335         case CDC_RX_RX2_RX_PATH_SEC0:
1336         case CDC_RX_RX2_RX_PATH_SEC1:
1337         case CDC_RX_RX2_RX_PATH_SEC2:
1338         case CDC_RX_RX2_RX_PATH_SEC3:
1339         case CDC_RX_RX2_RX_PATH_SEC4:
1340         case CDC_RX_RX2_RX_PATH_SEC5:
1341         case CDC_RX_RX2_RX_PATH_SEC6:
1342         case CDC_RX_RX2_RX_PATH_SEC7:
1343         case CDC_RX_RX2_RX_PATH_MIX_SEC0:
1344         case CDC_RX_RX2_RX_PATH_MIX_SEC1:
1345         case CDC_RX_RX2_RX_PATH_DSM_CTL:
1346         case CDC_RX_IDLE_DETECT_PATH_CTL:
1347         case CDC_RX_IDLE_DETECT_CFG0:
1348         case CDC_RX_IDLE_DETECT_CFG1:
1349         case CDC_RX_IDLE_DETECT_CFG2:
1350         case CDC_RX_IDLE_DETECT_CFG3:
1351         case CDC_RX_COMPANDER0_CTL0:
1352         case CDC_RX_COMPANDER0_CTL1:
1353         case CDC_RX_COMPANDER0_CTL2:
1354         case CDC_RX_COMPANDER0_CTL3:
1355         case CDC_RX_COMPANDER0_CTL4:
1356         case CDC_RX_COMPANDER0_CTL5:
1357         case CDC_RX_COMPANDER0_CTL7:
1358         case CDC_RX_COMPANDER1_CTL0:
1359         case CDC_RX_COMPANDER1_CTL1:
1360         case CDC_RX_COMPANDER1_CTL2:
1361         case CDC_RX_COMPANDER1_CTL3:
1362         case CDC_RX_COMPANDER1_CTL4:
1363         case CDC_RX_COMPANDER1_CTL5:
1364         case CDC_RX_COMPANDER1_CTL7:
1365         case CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL:
1366         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL:
1367         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL:
1368         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL:
1369         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL:
1370         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL:
1371         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL:
1372         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL:
1373         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL:
1374         case CDC_RX_SIDETONE_IIR0_IIR_CTL:
1375         case CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL:
1376         case CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL:
1377         case CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL:
1378         case CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL:
1379         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL:
1380         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL:
1381         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL:
1382         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL:
1383         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL:
1384         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL:
1385         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL:
1386         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL:
1387         case CDC_RX_SIDETONE_IIR1_IIR_CTL:
1388         case CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL:
1389         case CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL:
1390         case CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL:
1391         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0:
1392         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1:
1393         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2:
1394         case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3:
1395         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0:
1396         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1:
1397         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2:
1398         case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3:
1399         case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL:
1400         case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1:
1401         case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL:
1402         case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1:
1403         case CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL:
1404         case CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0:
1405         case CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL:
1406         case CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0:
1407         case CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL:
1408         case CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0:
1409         case CDC_RX_EC_ASRC0_CLK_RST_CTL:
1410         case CDC_RX_EC_ASRC0_CTL0:
1411         case CDC_RX_EC_ASRC0_CTL1:
1412         case CDC_RX_EC_ASRC0_FIFO_CTL:
1413         case CDC_RX_EC_ASRC1_CLK_RST_CTL:
1414         case CDC_RX_EC_ASRC1_CTL0:
1415         case CDC_RX_EC_ASRC1_CTL1:
1416         case CDC_RX_EC_ASRC1_FIFO_CTL:
1417         case CDC_RX_EC_ASRC2_CLK_RST_CTL:
1418         case CDC_RX_EC_ASRC2_CTL0:
1419         case CDC_RX_EC_ASRC2_CTL1:
1420         case CDC_RX_EC_ASRC2_FIFO_CTL:
1421         case CDC_RX_DSD0_PATH_CTL:
1422         case CDC_RX_DSD0_CFG0:
1423         case CDC_RX_DSD0_CFG1:
1424         case CDC_RX_DSD0_CFG2:
1425         case CDC_RX_DSD1_PATH_CTL:
1426         case CDC_RX_DSD1_CFG0:
1427         case CDC_RX_DSD1_CFG1:
1428         case CDC_RX_DSD1_CFG2:
1429                 return true;
1430         }
1431
1432         return false;
1433 }
1434
1435 static bool rx_is_writeable_register(struct device *dev, unsigned int reg)
1436 {
1437         bool ret;
1438
1439         ret = rx_is_rw_register(dev, reg);
1440         if (!ret)
1441                 return rx_is_wronly_register(dev, reg);
1442
1443         return ret;
1444 }
1445
1446 static bool rx_is_readable_register(struct device *dev, unsigned int reg)
1447 {
1448         switch (reg) {
1449         case CDC_RX_TOP_HPHL_COMP_RD_LSB:
1450         case CDC_RX_TOP_HPHL_COMP_RD_MSB:
1451         case CDC_RX_TOP_HPHR_COMP_RD_LSB:
1452         case CDC_RX_TOP_HPHR_COMP_RD_MSB:
1453         case CDC_RX_TOP_DSD0_DEBUG_CFG2:
1454         case CDC_RX_TOP_DSD1_DEBUG_CFG2:
1455         case CDC_RX_BCL_VBAT_GAIN_MON_VAL:
1456         case CDC_RX_BCL_VBAT_DECODE_ST:
1457         case CDC_RX_INTR_CTRL_PIN1_STATUS0:
1458         case CDC_RX_INTR_CTRL_PIN2_STATUS0:
1459         case CDC_RX_COMPANDER0_CTL6:
1460         case CDC_RX_COMPANDER1_CTL6:
1461         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
1462         case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
1463         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
1464         case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
1465         case CDC_RX_EC_ASRC0_STATUS_FIFO:
1466         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
1467         case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
1468         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
1469         case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
1470         case CDC_RX_EC_ASRC1_STATUS_FIFO:
1471         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
1472         case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
1473         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
1474         case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
1475         case CDC_RX_EC_ASRC2_STATUS_FIFO:
1476                 return true;
1477         }
1478
1479         return rx_is_rw_register(dev, reg);
1480 }
1481
1482 static const struct regmap_config rx_regmap_config = {
1483         .name = "rx_macro",
1484         .reg_bits = 16,
1485         .val_bits = 32, /* 8 but with 32 bit read/write */
1486         .reg_stride = 4,
1487         .cache_type = REGCACHE_FLAT,
1488         .reg_defaults = rx_defaults,
1489         .num_reg_defaults = ARRAY_SIZE(rx_defaults),
1490         .max_register = RX_MAX_OFFSET,
1491         .writeable_reg = rx_is_writeable_register,
1492         .volatile_reg = rx_is_volatile_register,
1493         .readable_reg = rx_is_readable_register,
1494 };
1495
1496 static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol,
1497                                         struct snd_ctl_elem_value *ucontrol)
1498 {
1499         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
1500         struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
1501         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1502         unsigned short look_ahead_dly_reg;
1503         unsigned int val;
1504
1505         val = ucontrol->value.enumerated.item[0];
1506
1507         if (e->reg == CDC_RX_RX0_RX_PATH_CFG1)
1508                 look_ahead_dly_reg = CDC_RX_RX0_RX_PATH_CFG0;
1509         else if (e->reg == CDC_RX_RX1_RX_PATH_CFG1)
1510                 look_ahead_dly_reg = CDC_RX_RX1_RX_PATH_CFG0;
1511
1512         /* Set Look Ahead Delay */
1513         if (val)
1514                 snd_soc_component_update_bits(component, look_ahead_dly_reg,
1515                                               CDC_RX_DLY_ZN_EN_MASK,
1516                                               CDC_RX_DLY_ZN_ENABLE);
1517         else
1518                 snd_soc_component_update_bits(component, look_ahead_dly_reg,
1519                                               CDC_RX_DLY_ZN_EN_MASK, 0);
1520         /* Set DEM INP Select */
1521         return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1522 }
1523
1524 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1525                 SOC_DAPM_ENUM_EXT("rx_int0_dem_inp", rx_int0_dem_inp_enum,
1526                   snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
1527 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1528                 SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_int1_dem_inp_enum,
1529                   snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
1530
1531 static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1532                                                int rate_reg_val, u32 sample_rate)
1533 {
1534
1535         u8 int_1_mix1_inp;
1536         u32 j, port;
1537         u16 int_mux_cfg0, int_mux_cfg1;
1538         u16 int_fs_reg;
1539         u8 inp0_sel, inp1_sel, inp2_sel;
1540         struct snd_soc_component *component = dai->component;
1541         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1542
1543         for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
1544                 int_1_mix1_inp = port;
1545                 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0;
1546                 /*
1547                  * Loop through all interpolator MUX inputs and find out
1548                  * to which interpolator input, the rx port
1549                  * is connected
1550                  */
1551                 for (j = 0; j < INTERP_MAX; j++) {
1552                         int_mux_cfg1 = int_mux_cfg0 + 4;
1553
1554                         inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1555                                                                 CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
1556                         inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0,
1557                                                                 CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
1558                         inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,
1559                                                                 CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
1560
1561                         if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1562                             (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
1563                             (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
1564                                 int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(j);
1565                                 /* sample_rate is in Hz */
1566                                 snd_soc_component_update_bits(component, int_fs_reg,
1567                                                               CDC_RX_PATH_PCM_RATE_MASK,
1568                                                               rate_reg_val);
1569                         }
1570                         int_mux_cfg0 += 8;
1571                 }
1572         }
1573
1574         return 0;
1575 }
1576
1577 static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1578                                               int rate_reg_val, u32 sample_rate)
1579 {
1580
1581         u8 int_2_inp;
1582         u32 j, port;
1583         u16 int_mux_cfg1, int_fs_reg;
1584         u8 int_mux_cfg1_val;
1585         struct snd_soc_component *component = dai->component;
1586         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1587
1588         for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) {
1589                 int_2_inp = port;
1590
1591                 int_mux_cfg1 = CDC_RX_INP_MUX_RX_INT0_CFG1;
1592                 for (j = 0; j < INTERP_MAX; j++) {
1593                         int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,
1594                                                                         CDC_RX_INTX_2_SEL_MASK);
1595
1596                         if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
1597                                 int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
1598                                 snd_soc_component_update_bits(component, int_fs_reg,
1599                                                               CDC_RX_RXn_MIX_PCM_RATE_MASK,
1600                                                               rate_reg_val);
1601                         }
1602                         int_mux_cfg1 += 8;
1603                 }
1604         }
1605         return 0;
1606 }
1607
1608 static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai,
1609                                           u32 sample_rate)
1610 {
1611         int rate_val = 0;
1612         int i, ret;
1613
1614         for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++)
1615                 if (sample_rate == sr_val_tbl[i].sample_rate)
1616                         rate_val = sr_val_tbl[i].rate_val;
1617
1618         ret = rx_macro_set_prim_interpolator_rate(dai, rate_val, sample_rate);
1619         if (ret)
1620                 return ret;
1621
1622         ret = rx_macro_set_mix_interpolator_rate(dai, rate_val, sample_rate);
1623         if (ret)
1624                 return ret;
1625
1626         return ret;
1627 }
1628
1629 static int rx_macro_hw_params(struct snd_pcm_substream *substream,
1630                               struct snd_pcm_hw_params *params,
1631                               struct snd_soc_dai *dai)
1632 {
1633         struct snd_soc_component *component = dai->component;
1634         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1635         int ret;
1636
1637         switch (substream->stream) {
1638         case SNDRV_PCM_STREAM_PLAYBACK:
1639                 ret = rx_macro_set_interpolator_rate(dai, params_rate(params));
1640                 if (ret) {
1641                         dev_err(component->dev, "%s: cannot set sample rate: %u\n",
1642                                 __func__, params_rate(params));
1643                         return ret;
1644                 }
1645                 rx->bit_width[dai->id] = params_width(params);
1646                 break;
1647         default:
1648                 break;
1649         }
1650         return 0;
1651 }
1652
1653 static int rx_macro_get_channel_map(struct snd_soc_dai *dai,
1654                                     unsigned int *tx_num, unsigned int *tx_slot,
1655                                     unsigned int *rx_num, unsigned int *rx_slot)
1656 {
1657         struct snd_soc_component *component = dai->component;
1658         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1659         u16 val, mask = 0, cnt = 0, temp;
1660
1661         switch (dai->id) {
1662         case RX_MACRO_AIF1_PB:
1663         case RX_MACRO_AIF2_PB:
1664         case RX_MACRO_AIF3_PB:
1665         case RX_MACRO_AIF4_PB:
1666                 for_each_set_bit(temp, &rx->active_ch_mask[dai->id],
1667                          RX_MACRO_PORTS_MAX) {
1668                         mask |= (1 << temp);
1669                         if (++cnt == RX_MACRO_MAX_DMA_CH_PER_PORT)
1670                                 break;
1671                 }
1672                 /*
1673                  * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3
1674                  * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3
1675                  * CDC_DMA_RX_2 port drives RX4     -- ch_mask 0x1
1676                  * CDC_DMA_RX_3 port drives RX5     -- ch_mask 0x1
1677                  * AIFn can pair to any CDC_DMA_RX_n port.
1678                  * In general, below convention is used::
1679                  * CDC_DMA_RX_0(AIF1)/CDC_DMA_RX_1(AIF2)/
1680                  * CDC_DMA_RX_2(AIF3)/CDC_DMA_RX_3(AIF4)
1681                  */
1682                 if (mask & 0x0C)
1683                         mask = mask >> 2;
1684                 if ((mask & 0x10) || (mask & 0x20))
1685                         mask = 0x1;
1686                 *rx_slot = mask;
1687                 *rx_num = rx->active_ch_cnt[dai->id];
1688                 break;
1689         case RX_MACRO_AIF_ECHO:
1690                 val = snd_soc_component_read(component, CDC_RX_INP_MUX_RX_MIX_CFG4);
1691                 if (val & RX_MACRO_EC_MIX_TX0_MASK) {
1692                         mask |= 0x1;
1693                         cnt++;
1694                 }
1695                 if (val & RX_MACRO_EC_MIX_TX1_MASK) {
1696                         mask |= 0x2;
1697                         cnt++;
1698                 }
1699                 val = snd_soc_component_read(component,
1700                         CDC_RX_INP_MUX_RX_MIX_CFG5);
1701                 if (val & RX_MACRO_EC_MIX_TX2_MASK) {
1702                         mask |= 0x4;
1703                         cnt++;
1704                 }
1705                 *tx_slot = mask;
1706                 *tx_num = cnt;
1707                 break;
1708         default:
1709                 dev_err(component->dev, "%s: Invalid AIF\n", __func__);
1710                 break;
1711         }
1712         return 0;
1713 }
1714
1715 static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1716 {
1717         struct snd_soc_component *component = dai->component;
1718         uint16_t j, reg, mix_reg, dsm_reg;
1719         u16 int_mux_cfg0, int_mux_cfg1;
1720         u8 int_mux_cfg0_val, int_mux_cfg1_val;
1721
1722         switch (dai->id) {
1723         case RX_MACRO_AIF1_PB:
1724         case RX_MACRO_AIF2_PB:
1725         case RX_MACRO_AIF3_PB:
1726         case RX_MACRO_AIF4_PB:
1727         for (j = 0; j < INTERP_MAX; j++) {
1728                 reg = CDC_RX_RXn_RX_PATH_CTL(j);
1729                 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
1730                 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(j);
1731
1732                 if (mute) {
1733                         snd_soc_component_update_bits(component, reg,
1734                                                       CDC_RX_PATH_PGA_MUTE_MASK,
1735                                                       CDC_RX_PATH_PGA_MUTE_ENABLE);
1736                         snd_soc_component_update_bits(component, mix_reg,
1737                                                       CDC_RX_PATH_PGA_MUTE_MASK,
1738                                                       CDC_RX_PATH_PGA_MUTE_ENABLE);
1739                 } else {
1740                         snd_soc_component_update_bits(component, reg,
1741                                                       CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
1742                         snd_soc_component_update_bits(component, mix_reg,
1743                                                       CDC_RX_PATH_PGA_MUTE_MASK, 0x0);
1744                 }
1745
1746                 if (j == INTERP_AUX)
1747                         dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
1748
1749                 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8;
1750                 int_mux_cfg1 = int_mux_cfg0 + 4;
1751                 int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0);
1752                 int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1);
1753
1754                 if (snd_soc_component_read(component, dsm_reg) & 0x01) {
1755                         if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0))
1756                                 snd_soc_component_update_bits(component, reg, 0x20, 0x20);
1757                         if (int_mux_cfg1_val & 0x0F) {
1758                                 snd_soc_component_update_bits(component, reg, 0x20, 0x20);
1759                                 snd_soc_component_update_bits(component, mix_reg, 0x20, 0x20);
1760                         }
1761                 }
1762         }
1763                 break;
1764         default:
1765                 break;
1766         }
1767         return 0;
1768 }
1769
1770 static struct snd_soc_dai_ops rx_macro_dai_ops = {
1771         .hw_params = rx_macro_hw_params,
1772         .get_channel_map = rx_macro_get_channel_map,
1773         .mute_stream = rx_macro_digital_mute,
1774 };
1775
1776 static struct snd_soc_dai_driver rx_macro_dai[] = {
1777         {
1778                 .name = "rx_macro_rx1",
1779                 .id = RX_MACRO_AIF1_PB,
1780                 .playback = {
1781                         .stream_name = "RX_MACRO_AIF1 Playback",
1782                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1783                         .formats = RX_MACRO_FORMATS,
1784                         .rate_max = 384000,
1785                         .rate_min = 8000,
1786                         .channels_min = 1,
1787                         .channels_max = 2,
1788                 },
1789                 .ops = &rx_macro_dai_ops,
1790         },
1791         {
1792                 .name = "rx_macro_rx2",
1793                 .id = RX_MACRO_AIF2_PB,
1794                 .playback = {
1795                         .stream_name = "RX_MACRO_AIF2 Playback",
1796                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1797                         .formats = RX_MACRO_FORMATS,
1798                         .rate_max = 384000,
1799                         .rate_min = 8000,
1800                         .channels_min = 1,
1801                         .channels_max = 2,
1802                 },
1803                 .ops = &rx_macro_dai_ops,
1804         },
1805         {
1806                 .name = "rx_macro_rx3",
1807                 .id = RX_MACRO_AIF3_PB,
1808                 .playback = {
1809                         .stream_name = "RX_MACRO_AIF3 Playback",
1810                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1811                         .formats = RX_MACRO_FORMATS,
1812                         .rate_max = 384000,
1813                         .rate_min = 8000,
1814                         .channels_min = 1,
1815                         .channels_max = 2,
1816                 },
1817                 .ops = &rx_macro_dai_ops,
1818         },
1819         {
1820                 .name = "rx_macro_rx4",
1821                 .id = RX_MACRO_AIF4_PB,
1822                 .playback = {
1823                         .stream_name = "RX_MACRO_AIF4 Playback",
1824                         .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES,
1825                         .formats = RX_MACRO_FORMATS,
1826                         .rate_max = 384000,
1827                         .rate_min = 8000,
1828                         .channels_min = 1,
1829                         .channels_max = 2,
1830                 },
1831                 .ops = &rx_macro_dai_ops,
1832         },
1833         {
1834                 .name = "rx_macro_echo",
1835                 .id = RX_MACRO_AIF_ECHO,
1836                 .capture = {
1837                         .stream_name = "RX_AIF_ECHO Capture",
1838                         .rates = RX_MACRO_ECHO_RATES,
1839                         .formats = RX_MACRO_ECHO_FORMATS,
1840                         .rate_max = 48000,
1841                         .rate_min = 8000,
1842                         .channels_min = 1,
1843                         .channels_max = 3,
1844                 },
1845                 .ops = &rx_macro_dai_ops,
1846         },
1847 };
1848
1849 static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable)
1850 {
1851         struct regmap *regmap = rx->regmap;
1852
1853         if (mclk_enable) {
1854                 if (rx->rx_mclk_users == 0) {
1855                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
1856                                            CDC_RX_CLK_MCLK_EN_MASK |
1857                                            CDC_RX_CLK_MCLK2_EN_MASK,
1858                                            CDC_RX_CLK_MCLK_ENABLE |
1859                                            CDC_RX_CLK_MCLK2_ENABLE);
1860                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1861                                            CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00);
1862                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1863                                            CDC_RX_FS_MCLK_CNT_EN_MASK,
1864                                            CDC_RX_FS_MCLK_CNT_ENABLE);
1865                         regcache_mark_dirty(regmap);
1866                         regcache_sync(regmap);
1867                 }
1868                 rx->rx_mclk_users++;
1869         } else {
1870                 if (rx->rx_mclk_users <= 0) {
1871                         dev_err(rx->dev, "%s: clock already disabled\n", __func__);
1872                         rx->rx_mclk_users = 0;
1873                         return;
1874                 }
1875                 rx->rx_mclk_users--;
1876                 if (rx->rx_mclk_users == 0) {
1877                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1878                                            CDC_RX_FS_MCLK_CNT_EN_MASK, 0x0);
1879                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL,
1880                                            CDC_RX_FS_MCLK_CNT_CLR_MASK,
1881                                            CDC_RX_FS_MCLK_CNT_CLR);
1882                         regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL,
1883                                            CDC_RX_CLK_MCLK_EN_MASK |
1884                                            CDC_RX_CLK_MCLK2_EN_MASK, 0x0);
1885                 }
1886         }
1887 }
1888
1889 static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w,
1890                                struct snd_kcontrol *kcontrol, int event)
1891 {
1892         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1893         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
1894         int ret = 0;
1895
1896         switch (event) {
1897         case SND_SOC_DAPM_PRE_PMU:
1898                 rx_macro_mclk_enable(rx, true);
1899                 break;
1900         case SND_SOC_DAPM_POST_PMD:
1901                 rx_macro_mclk_enable(rx, false);
1902                 break;
1903         default:
1904                 dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event);
1905                 ret = -EINVAL;
1906         }
1907         return ret;
1908 }
1909
1910 static bool rx_macro_adie_lb(struct snd_soc_component *component,
1911                              int interp_idx)
1912 {
1913         u16 int_mux_cfg0, int_mux_cfg1;
1914         u8 int_n_inp0, int_n_inp1, int_n_inp2;
1915
1916         int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
1917         int_mux_cfg1 = int_mux_cfg0 + 4;
1918
1919         int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0,
1920                                                   CDC_RX_INTX_1_MIX_INP0_SEL_MASK);
1921         int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0,
1922                                                   CDC_RX_INTX_1_MIX_INP1_SEL_MASK);
1923         int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1,
1924                                                   CDC_RX_INTX_1_MIX_INP2_SEL_MASK);
1925
1926         if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
1927                 int_n_inp0 == INTn_1_INP_SEL_DEC1 ||
1928                 int_n_inp0 == INTn_1_INP_SEL_IIR0 ||
1929                 int_n_inp0 == INTn_1_INP_SEL_IIR1)
1930                 return true;
1931
1932         if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
1933                 int_n_inp1 == INTn_1_INP_SEL_DEC1 ||
1934                 int_n_inp1 == INTn_1_INP_SEL_IIR0 ||
1935                 int_n_inp1 == INTn_1_INP_SEL_IIR1)
1936                 return true;
1937
1938         if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
1939                 int_n_inp2 == INTn_1_INP_SEL_DEC1 ||
1940                 int_n_inp2 == INTn_1_INP_SEL_IIR0 ||
1941                 int_n_inp2 == INTn_1_INP_SEL_IIR1)
1942                 return true;
1943
1944         return false;
1945 }
1946
1947 static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
1948                                       int event, int interp_idx);
1949 static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w,
1950                                         struct snd_kcontrol *kcontrol,
1951                                         int event)
1952 {
1953         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1954         u16 gain_reg, reg;
1955
1956         reg = CDC_RX_RXn_RX_PATH_CTL(w->shift);
1957         gain_reg = CDC_RX_RXn_RX_VOL_CTL(w->shift);
1958
1959         switch (event) {
1960         case SND_SOC_DAPM_PRE_PMU:
1961                 rx_macro_enable_interp_clk(component, event, w->shift);
1962                 if (rx_macro_adie_lb(component, w->shift))
1963                         snd_soc_component_update_bits(component, reg,
1964                                                       CDC_RX_PATH_CLK_EN_MASK,
1965                                                       CDC_RX_PATH_CLK_ENABLE);
1966                 break;
1967         case SND_SOC_DAPM_POST_PMU:
1968                 snd_soc_component_write(component, gain_reg,
1969                         snd_soc_component_read(component, gain_reg));
1970                 break;
1971         case SND_SOC_DAPM_POST_PMD:
1972                 rx_macro_enable_interp_clk(component, event, w->shift);
1973                 break;
1974         }
1975
1976         return 0;
1977 }
1978
1979 static int rx_macro_config_compander(struct snd_soc_component *component,
1980                                 struct rx_macro *rx,
1981                                 int comp, int event)
1982 {
1983         u8 pcm_rate, val;
1984
1985         /* AUX does not have compander */
1986         if (comp == INTERP_AUX)
1987                 return 0;
1988
1989         pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(comp)) & 0x0F;
1990         if (pcm_rate < 0x06)
1991                 val = 0x03;
1992         else if (pcm_rate < 0x08)
1993                 val = 0x01;
1994         else if (pcm_rate < 0x0B)
1995                 val = 0x02;
1996         else
1997                 val = 0x00;
1998
1999         if (SND_SOC_DAPM_EVENT_ON(event))
2000                 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
2001                                               CDC_RX_DC_COEFF_SEL_MASK, val);
2002
2003         if (SND_SOC_DAPM_EVENT_OFF(event))
2004                 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
2005                                               CDC_RX_DC_COEFF_SEL_MASK, 0x3);
2006         if (!rx->comp_enabled[comp])
2007                 return 0;
2008
2009         if (SND_SOC_DAPM_EVENT_ON(event)) {
2010                 /* Enable Compander Clock */
2011                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2012                                               CDC_RX_COMPANDERn_CLK_EN_MASK, 0x1);
2013                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2014                                               CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x1);
2015                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2016                                               CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x0);
2017                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
2018                                               CDC_RX_RXn_COMP_EN_MASK, 0x1);
2019         }
2020
2021         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2022                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2023                                               CDC_RX_COMPANDERn_HALT_MASK, 0x1);
2024                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
2025                                               CDC_RX_RXn_COMP_EN_MASK, 0x0);
2026                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2027                                               CDC_RX_COMPANDERn_CLK_EN_MASK, 0x0);
2028                 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
2029                                               CDC_RX_COMPANDERn_HALT_MASK, 0x0);
2030         }
2031
2032         return 0;
2033 }
2034
2035 static int rx_macro_load_compander_coeff(struct snd_soc_component *component,
2036                                          struct rx_macro *rx,
2037                                          int comp, int event)
2038 {
2039         u16 comp_coeff_lsb_reg, comp_coeff_msb_reg;
2040         int i;
2041         int hph_pwr_mode = HPH_LOHIFI;
2042
2043         if (!rx->comp_enabled[comp])
2044                 return 0;
2045
2046         if (comp == INTERP_HPHL) {
2047                 comp_coeff_lsb_reg = CDC_RX_TOP_HPHL_COMP_WR_LSB;
2048                 comp_coeff_msb_reg = CDC_RX_TOP_HPHL_COMP_WR_MSB;
2049         } else if (comp == INTERP_HPHR) {
2050                 comp_coeff_lsb_reg = CDC_RX_TOP_HPHR_COMP_WR_LSB;
2051                 comp_coeff_msb_reg = CDC_RX_TOP_HPHR_COMP_WR_MSB;
2052         } else {
2053                 /* compander coefficients are loaded only for hph path */
2054                 return 0;
2055         }
2056
2057         hph_pwr_mode = rx->hph_pwr_mode;
2058
2059         if (SND_SOC_DAPM_EVENT_ON(event)) {
2060                 /* Load Compander Coeff */
2061                 for (i = 0; i < COMP_MAX_COEFF; i++) {
2062                         snd_soc_component_write(component, comp_coeff_lsb_reg,
2063                                         comp_coeff_table[hph_pwr_mode][i].lsb);
2064                         snd_soc_component_write(component, comp_coeff_msb_reg,
2065                                         comp_coeff_table[hph_pwr_mode][i].msb);
2066                 }
2067         }
2068
2069         return 0;
2070 }
2071
2072 static void rx_macro_enable_softclip_clk(struct snd_soc_component *component,
2073                                          struct rx_macro *rx, bool enable)
2074 {
2075         if (enable) {
2076                 if (rx->softclip_clk_users == 0)
2077                         snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
2078                                                       CDC_RX_SOFTCLIP_CLK_EN_MASK, 1);
2079                 rx->softclip_clk_users++;
2080         } else {
2081                 rx->softclip_clk_users--;
2082                 if (rx->softclip_clk_users == 0)
2083                         snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC,
2084                                                       CDC_RX_SOFTCLIP_CLK_EN_MASK, 0);
2085         }
2086 }
2087
2088 static int rx_macro_config_softclip(struct snd_soc_component *component,
2089                                     struct rx_macro *rx, int event)
2090 {
2091
2092         if (!rx->is_softclip_on)
2093                 return 0;
2094
2095         if (SND_SOC_DAPM_EVENT_ON(event)) {
2096                 /* Enable Softclip clock */
2097                 rx_macro_enable_softclip_clk(component, rx, true);
2098                 /* Enable Softclip control */
2099                 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
2100                                              CDC_RX_SOFTCLIP_EN_MASK, 0x01);
2101         }
2102
2103         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2104                 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL,
2105                                              CDC_RX_SOFTCLIP_EN_MASK, 0x0);
2106                 rx_macro_enable_softclip_clk(component, rx, false);
2107         }
2108
2109         return 0;
2110 }
2111
2112 static int rx_macro_config_aux_hpf(struct snd_soc_component *component,
2113                                    struct rx_macro *rx, int event)
2114 {
2115         if (SND_SOC_DAPM_EVENT_ON(event)) {
2116                 /* Update Aux HPF control */
2117                 if (!rx->is_aux_hpf_on)
2118                         snd_soc_component_update_bits(component,
2119                                 CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x00);
2120         }
2121
2122         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2123                 /* Reset to default (HPF=ON) */
2124                 snd_soc_component_update_bits(component,
2125                         CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x04);
2126         }
2127
2128         return 0;
2129 }
2130
2131 static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable)
2132 {
2133         if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0))
2134                 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC,
2135                                              CDC_RX_CLSH_CLK_EN_MASK, enable);
2136         if (rx->clsh_users < 0)
2137                 rx->clsh_users = 0;
2138 }
2139
2140 static int rx_macro_config_classh(struct snd_soc_component *component,
2141                                 struct rx_macro *rx,
2142                                 int interp_n, int event)
2143 {
2144         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2145                 rx_macro_enable_clsh_block(rx, false);
2146                 return 0;
2147         }
2148
2149         if (!SND_SOC_DAPM_EVENT_ON(event))
2150                 return 0;
2151
2152         rx_macro_enable_clsh_block(rx, true);
2153         if (interp_n == INTERP_HPHL ||
2154                 interp_n == INTERP_HPHR) {
2155                 /*
2156                  * These K1 values depend on the Headphone Impedance
2157                  * For now it is assumed to be 16 ohm
2158                  */
2159                 snd_soc_component_write(component, CDC_RX_CLSH_K1_LSB, 0xc0);
2160                 snd_soc_component_write_field(component, CDC_RX_CLSH_K1_MSB,
2161                                               CDC_RX_CLSH_K1_MSB_COEFF_MASK, 0);
2162         }
2163         switch (interp_n) {
2164         case INTERP_HPHL:
2165                 if (rx->is_ear_mode_on)
2166                         snd_soc_component_update_bits(component,
2167                                 CDC_RX_CLSH_HPH_V_PA,
2168                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39);
2169                 else
2170                         snd_soc_component_update_bits(component,
2171                                 CDC_RX_CLSH_HPH_V_PA,
2172                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c);
2173                 snd_soc_component_update_bits(component,
2174                                 CDC_RX_CLSH_DECAY_CTRL,
2175                                 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
2176                 snd_soc_component_write_field(component,
2177                                 CDC_RX_RX0_RX_PATH_CFG0,
2178                                 CDC_RX_RXn_CLSH_EN_MASK, 0x1);
2179                 break;
2180         case INTERP_HPHR:
2181                 if (rx->is_ear_mode_on)
2182                         snd_soc_component_update_bits(component,
2183                                 CDC_RX_CLSH_HPH_V_PA,
2184                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39);
2185                 else
2186                         snd_soc_component_update_bits(component,
2187                                 CDC_RX_CLSH_HPH_V_PA,
2188                                 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c);
2189                 snd_soc_component_update_bits(component,
2190                                 CDC_RX_CLSH_DECAY_CTRL,
2191                                 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
2192                 snd_soc_component_update_bits(component,
2193                                 CDC_RX_RX1_RX_PATH_CFG0,
2194                                 CDC_RX_RXn_CLSH_EN_MASK, 0x1);
2195                 break;
2196         case INTERP_AUX:
2197                 snd_soc_component_update_bits(component,
2198                                 CDC_RX_RX2_RX_PATH_CFG0,
2199                                 CDC_RX_RX2_DLY_Z_EN_MASK, 1);
2200                 snd_soc_component_write_field(component,
2201                                 CDC_RX_RX2_RX_PATH_CFG0,
2202                                 CDC_RX_RX2_CLSH_EN_MASK, 1);
2203                 break;
2204         }
2205
2206         return 0;
2207 }
2208
2209 static void rx_macro_hd2_control(struct snd_soc_component *component,
2210                                  u16 interp_idx, int event)
2211 {
2212         u16 hd2_scale_reg, hd2_enable_reg;
2213
2214         switch (interp_idx) {
2215         case INTERP_HPHL:
2216                 hd2_scale_reg = CDC_RX_RX0_RX_PATH_SEC3;
2217                 hd2_enable_reg = CDC_RX_RX0_RX_PATH_CFG0;
2218                 break;
2219         case INTERP_HPHR:
2220                 hd2_scale_reg = CDC_RX_RX1_RX_PATH_SEC3;
2221                 hd2_enable_reg = CDC_RX_RX1_RX_PATH_CFG0;
2222                 break;
2223         }
2224
2225         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
2226                 snd_soc_component_update_bits(component, hd2_scale_reg,
2227                                 CDC_RX_RXn_HD2_ALPHA_MASK, 0x14);
2228                 snd_soc_component_write_field(component, hd2_enable_reg,
2229                                               CDC_RX_RXn_HD2_EN_MASK, 1);
2230         }
2231
2232         if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
2233                 snd_soc_component_write_field(component, hd2_enable_reg,
2234                                               CDC_RX_RXn_HD2_EN_MASK, 0);
2235                 snd_soc_component_update_bits(component, hd2_scale_reg,
2236                                 CDC_RX_RXn_HD2_ALPHA_MASK, 0x0);
2237         }
2238 }
2239
2240 static int rx_macro_get_compander(struct snd_kcontrol *kcontrol,
2241                                struct snd_ctl_elem_value *ucontrol)
2242 {
2243         struct snd_soc_component *component =
2244                                 snd_soc_kcontrol_component(kcontrol);
2245         int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
2246         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2247
2248         ucontrol->value.integer.value[0] = rx->comp_enabled[comp];
2249         return 0;
2250 }
2251
2252 static int rx_macro_set_compander(struct snd_kcontrol *kcontrol,
2253                                struct snd_ctl_elem_value *ucontrol)
2254 {
2255         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2256         int comp = ((struct soc_mixer_control *)  kcontrol->private_value)->shift;
2257         int value = ucontrol->value.integer.value[0];
2258         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2259
2260         rx->comp_enabled[comp] = value;
2261
2262         return 0;
2263 }
2264
2265 static int rx_macro_mux_get(struct snd_kcontrol *kcontrol,
2266                           struct snd_ctl_elem_value *ucontrol)
2267 {
2268         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2269         struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2270         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2271
2272         ucontrol->value.integer.value[0] =
2273                         rx->rx_port_value[widget->shift];
2274         return 0;
2275 }
2276
2277 static int rx_macro_mux_put(struct snd_kcontrol *kcontrol,
2278                             struct snd_ctl_elem_value *ucontrol)
2279 {
2280         struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
2281         struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
2282         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2283         struct snd_soc_dapm_update *update = NULL;
2284         u32 rx_port_value = ucontrol->value.integer.value[0];
2285         u32 aif_rst;
2286         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2287
2288         aif_rst = rx->rx_port_value[widget->shift];
2289         if (!rx_port_value) {
2290                 if (aif_rst == 0) {
2291                         dev_err(component->dev, "%s:AIF reset already\n", __func__);
2292                         return 0;
2293                 }
2294                 if (aif_rst > RX_MACRO_AIF4_PB) {
2295                         dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
2296                         return 0;
2297                 }
2298         }
2299         rx->rx_port_value[widget->shift] = rx_port_value;
2300
2301         switch (rx_port_value) {
2302         case 0:
2303                 if (rx->active_ch_cnt[aif_rst]) {
2304                         clear_bit(widget->shift,
2305                                 &rx->active_ch_mask[aif_rst]);
2306                         rx->active_ch_cnt[aif_rst]--;
2307                 }
2308                 break;
2309         case 1:
2310         case 2:
2311         case 3:
2312         case 4:
2313                 set_bit(widget->shift,
2314                         &rx->active_ch_mask[rx_port_value]);
2315                 rx->active_ch_cnt[rx_port_value]++;
2316                 break;
2317         default:
2318                 dev_err(component->dev,
2319                         "%s:Invalid AIF_ID for RX_MACRO MUX %d\n",
2320                         __func__, rx_port_value);
2321                 goto err;
2322         }
2323
2324         snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
2325                                         rx_port_value, e, update);
2326         return 0;
2327 err:
2328         return -EINVAL;
2329 }
2330
2331 static const struct snd_kcontrol_new rx_macro_rx0_mux =
2332                 SOC_DAPM_ENUM_EXT("rx_macro_rx0", rx_macro_rx0_enum,
2333                   rx_macro_mux_get, rx_macro_mux_put);
2334 static const struct snd_kcontrol_new rx_macro_rx1_mux =
2335                 SOC_DAPM_ENUM_EXT("rx_macro_rx1", rx_macro_rx1_enum,
2336                   rx_macro_mux_get, rx_macro_mux_put);
2337 static const struct snd_kcontrol_new rx_macro_rx2_mux =
2338                 SOC_DAPM_ENUM_EXT("rx_macro_rx2", rx_macro_rx2_enum,
2339                   rx_macro_mux_get, rx_macro_mux_put);
2340 static const struct snd_kcontrol_new rx_macro_rx3_mux =
2341                 SOC_DAPM_ENUM_EXT("rx_macro_rx3", rx_macro_rx3_enum,
2342                   rx_macro_mux_get, rx_macro_mux_put);
2343 static const struct snd_kcontrol_new rx_macro_rx4_mux =
2344                 SOC_DAPM_ENUM_EXT("rx_macro_rx4", rx_macro_rx4_enum,
2345                   rx_macro_mux_get, rx_macro_mux_put);
2346 static const struct snd_kcontrol_new rx_macro_rx5_mux =
2347                 SOC_DAPM_ENUM_EXT("rx_macro_rx5", rx_macro_rx5_enum,
2348                   rx_macro_mux_get, rx_macro_mux_put);
2349
2350 static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol,
2351                                struct snd_ctl_elem_value *ucontrol)
2352 {
2353         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2354         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2355
2356         ucontrol->value.integer.value[0] = rx->is_ear_mode_on;
2357         return 0;
2358 }
2359
2360 static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol,
2361                                struct snd_ctl_elem_value *ucontrol)
2362 {
2363         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2364         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2365
2366         rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true);
2367         return 0;
2368 }
2369
2370 static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol,
2371                                struct snd_ctl_elem_value *ucontrol)
2372 {
2373         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2374         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2375
2376         ucontrol->value.integer.value[0] = rx->hph_hd2_mode;
2377         return 0;
2378 }
2379
2380 static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol,
2381                                struct snd_ctl_elem_value *ucontrol)
2382 {
2383         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2384         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2385
2386         rx->hph_hd2_mode = ucontrol->value.integer.value[0];
2387         return 0;
2388 }
2389
2390 static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol,
2391                                struct snd_ctl_elem_value *ucontrol)
2392 {
2393         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2394         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2395
2396         ucontrol->value.integer.value[0] = rx->hph_pwr_mode;
2397         return 0;
2398 }
2399
2400 static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol,
2401                                struct snd_ctl_elem_value *ucontrol)
2402 {
2403         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2404         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2405
2406         rx->hph_pwr_mode = ucontrol->value.integer.value[0];
2407         return 0;
2408 }
2409
2410 static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
2411                                           struct snd_ctl_elem_value *ucontrol)
2412 {
2413         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2414         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2415
2416         ucontrol->value.integer.value[0] = rx->is_softclip_on;
2417
2418         return 0;
2419 }
2420
2421 static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
2422                                           struct snd_ctl_elem_value *ucontrol)
2423 {
2424         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2425         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2426
2427         rx->is_softclip_on = ucontrol->value.integer.value[0];
2428
2429         return 0;
2430 }
2431
2432 static int rx_macro_aux_hpf_mode_get(struct snd_kcontrol *kcontrol,
2433                                           struct snd_ctl_elem_value *ucontrol)
2434 {
2435         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2436         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2437
2438         ucontrol->value.integer.value[0] = rx->is_aux_hpf_on;
2439
2440         return 0;
2441 }
2442
2443 static int rx_macro_aux_hpf_mode_put(struct snd_kcontrol *kcontrol,
2444                                           struct snd_ctl_elem_value *ucontrol)
2445 {
2446         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2447         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2448
2449         rx->is_aux_hpf_on = ucontrol->value.integer.value[0];
2450
2451         return 0;
2452 }
2453
2454 static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component,
2455                                         struct rx_macro *rx,
2456                                         u16 interp_idx, int event)
2457 {
2458         u16 hph_lut_bypass_reg;
2459         u16 hph_comp_ctrl7;
2460
2461         switch (interp_idx) {
2462         case INTERP_HPHL:
2463                 hph_lut_bypass_reg = CDC_RX_TOP_HPHL_COMP_LUT;
2464                 hph_comp_ctrl7 = CDC_RX_COMPANDER0_CTL7;
2465                 break;
2466         case INTERP_HPHR:
2467                 hph_lut_bypass_reg = CDC_RX_TOP_HPHR_COMP_LUT;
2468                 hph_comp_ctrl7 = CDC_RX_COMPANDER1_CTL7;
2469                 break;
2470         default:
2471                 return -EINVAL;
2472         }
2473
2474         if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) {
2475                 if (interp_idx == INTERP_HPHL) {
2476                         if (rx->is_ear_mode_on)
2477                                 snd_soc_component_write_field(component,
2478                                         CDC_RX_RX0_RX_PATH_CFG1,
2479                                         CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x1);
2480                         else
2481                                 snd_soc_component_write_field(component,
2482                                         hph_lut_bypass_reg,
2483                                         CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1);
2484                 } else {
2485                         snd_soc_component_write_field(component, hph_lut_bypass_reg,
2486                                         CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1);
2487                 }
2488                 if (rx->hph_pwr_mode)
2489                         snd_soc_component_write_field(component, hph_comp_ctrl7,
2490                                         CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x0);
2491         }
2492
2493         if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
2494                 snd_soc_component_write_field(component,
2495                                         CDC_RX_RX0_RX_PATH_CFG1,
2496                                         CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x0);
2497                 snd_soc_component_update_bits(component, hph_lut_bypass_reg,
2498                                         CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 0);
2499                 snd_soc_component_write_field(component, hph_comp_ctrl7,
2500                                         CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x1);
2501         }
2502
2503         return 0;
2504 }
2505
2506 static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
2507                                       int event, int interp_idx)
2508 {
2509         u16 main_reg, dsm_reg, rx_cfg2_reg;
2510         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
2511
2512         main_reg = CDC_RX_RXn_RX_PATH_CTL(interp_idx);
2513         dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(interp_idx);
2514         if (interp_idx == INTERP_AUX)
2515                 dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
2516         rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(interp_idx);
2517
2518         if (SND_SOC_DAPM_EVENT_ON(event)) {
2519                 if (rx->main_clk_users[interp_idx] == 0) {
2520                         /* Main path PGA mute enable */
2521                         snd_soc_component_write_field(component, main_reg,
2522                                                       CDC_RX_PATH_PGA_MUTE_MASK, 0x1);
2523                         snd_soc_component_write_field(component, dsm_reg,
2524                                                       CDC_RX_RXn_DSM_CLK_EN_MASK, 0x1);
2525                         snd_soc_component_update_bits(component, rx_cfg2_reg,
2526                                         CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x03);
2527                         rx_macro_load_compander_coeff(component, rx, interp_idx, event);
2528                         if (rx->hph_hd2_mode)
2529                                 rx_macro_hd2_control(component, interp_idx, event);
2530                         rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
2531                         rx_macro_config_compander(component, rx, interp_idx, event);
2532                         if (interp_idx == INTERP_AUX) {
2533                                 rx_macro_config_softclip(component, rx, event);
2534                                 rx_macro_config_aux_hpf(component, rx, event);
2535                         }
2536                         rx_macro_config_classh(component, rx, interp_idx, event);
2537                 }
2538                 rx->main_clk_users[interp_idx]++;
2539         }
2540
2541         if (SND_SOC_DAPM_EVENT_OFF(event)) {
2542                 rx->main_clk_users[interp_idx]--;
2543                 if (rx->main_clk_users[interp_idx] <= 0) {
2544                         rx->main_clk_users[interp_idx] = 0;
2545                         /* Main path PGA mute enable */
2546                         snd_soc_component_write_field(component, main_reg,
2547                                                       CDC_RX_PATH_PGA_MUTE_MASK, 0x1);
2548                         /* Clk Disable */
2549                         snd_soc_component_write_field(component, dsm_reg,
2550                                                       CDC_RX_RXn_DSM_CLK_EN_MASK, 0);
2551                         snd_soc_component_write_field(component, main_reg,
2552                                                       CDC_RX_PATH_CLK_EN_MASK, 0);
2553                         /* Reset enable and disable */
2554                         snd_soc_component_write_field(component, main_reg,
2555                                                       CDC_RX_PATH_RESET_EN_MASK, 1);
2556                         snd_soc_component_write_field(component, main_reg,
2557                                                       CDC_RX_PATH_RESET_EN_MASK, 0);
2558                         /* Reset rate to 48K*/
2559                         snd_soc_component_update_bits(component, main_reg,
2560                                                       CDC_RX_PATH_PCM_RATE_MASK,
2561                                                       0x04);
2562                         snd_soc_component_update_bits(component, rx_cfg2_reg,
2563                                                       CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x00);
2564                         rx_macro_config_classh(component, rx, interp_idx, event);
2565                         rx_macro_config_compander(component, rx, interp_idx, event);
2566                         if (interp_idx ==  INTERP_AUX) {
2567                                 rx_macro_config_softclip(component, rx, event);
2568                                 rx_macro_config_aux_hpf(component, rx, event);
2569                         }
2570                         rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event);
2571                         if (rx->hph_hd2_mode)
2572                                 rx_macro_hd2_control(component, interp_idx, event);
2573                 }
2574         }
2575
2576         return rx->main_clk_users[interp_idx];
2577 }
2578
2579 static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
2580                                     struct snd_kcontrol *kcontrol, int event)
2581 {
2582         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2583         u16 gain_reg, mix_reg;
2584
2585         gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(w->shift);
2586         mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(w->shift);
2587
2588         switch (event) {
2589         case SND_SOC_DAPM_PRE_PMU:
2590                 rx_macro_enable_interp_clk(component, event, w->shift);
2591                 break;
2592         case SND_SOC_DAPM_POST_PMU:
2593                 snd_soc_component_write(component, gain_reg,
2594                                         snd_soc_component_read(component, gain_reg));
2595                 break;
2596         case SND_SOC_DAPM_POST_PMD:
2597                 /* Clk Disable */
2598                 snd_soc_component_update_bits(component, mix_reg,
2599                                               CDC_RX_RXn_MIX_CLK_EN_MASK, 0x00);
2600                 rx_macro_enable_interp_clk(component, event, w->shift);
2601                 /* Reset enable and disable */
2602                 snd_soc_component_update_bits(component, mix_reg,
2603                                               CDC_RX_RXn_MIX_RESET_MASK,
2604                                               CDC_RX_RXn_MIX_RESET);
2605                 snd_soc_component_update_bits(component, mix_reg,
2606                                               CDC_RX_RXn_MIX_RESET_MASK, 0x00);
2607                 break;
2608         }
2609
2610         return 0;
2611 }
2612
2613 static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w,
2614                                        struct snd_kcontrol *kcontrol, int event)
2615 {
2616         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2617
2618         switch (event) {
2619         case SND_SOC_DAPM_PRE_PMU:
2620                 rx_macro_enable_interp_clk(component, event, w->shift);
2621                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
2622                                               CDC_RX_RXn_SIDETONE_EN_MASK, 1);
2623                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(w->shift),
2624                                               CDC_RX_PATH_CLK_EN_MASK, 1);
2625                 break;
2626         case SND_SOC_DAPM_POST_PMD:
2627                 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
2628                                               CDC_RX_RXn_SIDETONE_EN_MASK, 0);
2629                 rx_macro_enable_interp_clk(component, event, w->shift);
2630                 break;
2631         default:
2632                 break;
2633         };
2634         return 0;
2635 }
2636
2637 static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w,
2638                                  struct snd_kcontrol *kcontrol, int event)
2639 {
2640         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2641
2642         switch (event) {
2643         case SND_SOC_DAPM_POST_PMU: /* fall through */
2644         case SND_SOC_DAPM_PRE_PMD:
2645                 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) {
2646                         snd_soc_component_write(component,
2647                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
2648                         snd_soc_component_read(component,
2649                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL));
2650                         snd_soc_component_write(component,
2651                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL,
2652                         snd_soc_component_read(component,
2653                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL));
2654                         snd_soc_component_write(component,
2655                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL,
2656                         snd_soc_component_read(component,
2657                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL));
2658                         snd_soc_component_write(component,
2659                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL,
2660                         snd_soc_component_read(component,
2661                                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL));
2662                 } else {
2663                         snd_soc_component_write(component,
2664                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
2665                         snd_soc_component_read(component,
2666                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL));
2667                         snd_soc_component_write(component,
2668                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL,
2669                         snd_soc_component_read(component,
2670                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL));
2671                         snd_soc_component_write(component,
2672                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL,
2673                         snd_soc_component_read(component,
2674                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL));
2675                         snd_soc_component_write(component,
2676                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL,
2677                         snd_soc_component_read(component,
2678                                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL));
2679                 }
2680                 break;
2681         }
2682         return 0;
2683 }
2684
2685 static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
2686                                    int iir_idx, int band_idx, int coeff_idx)
2687 {
2688         u32 value;
2689         int reg, b2_reg;
2690
2691         /* Address does not automatically update if reading */
2692         reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2693         b2_reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2694
2695         snd_soc_component_write(component, reg,
2696                                 ((band_idx * BAND_MAX + coeff_idx) *
2697                                  sizeof(uint32_t)) & 0x7F);
2698
2699         value = snd_soc_component_read(component, b2_reg);
2700         snd_soc_component_write(component, reg,
2701                                 ((band_idx * BAND_MAX + coeff_idx)
2702                                  * sizeof(uint32_t) + 1) & 0x7F);
2703
2704         value |= (snd_soc_component_read(component, b2_reg) << 8);
2705         snd_soc_component_write(component, reg,
2706                                 ((band_idx * BAND_MAX + coeff_idx)
2707                                  * sizeof(uint32_t) + 2) & 0x7F);
2708
2709         value |= (snd_soc_component_read(component, b2_reg) << 16);
2710         snd_soc_component_write(component, reg,
2711                 ((band_idx * BAND_MAX + coeff_idx)
2712                 * sizeof(uint32_t) + 3) & 0x7F);
2713
2714         /* Mask bits top 2 bits since they are reserved */
2715         value |= (snd_soc_component_read(component, b2_reg) << 24);
2716         return value;
2717 }
2718
2719 static void set_iir_band_coeff(struct snd_soc_component *component,
2720                                int iir_idx, int band_idx, uint32_t value)
2721 {
2722         int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
2723
2724         snd_soc_component_write(component, reg, (value & 0xFF));
2725         snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
2726         snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
2727         /* Mask top 2 bits, 7-8 are reserved */
2728         snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
2729 }
2730
2731 static int rx_macro_put_iir_band_audio_mixer(
2732                                         struct snd_kcontrol *kcontrol,
2733                                         struct snd_ctl_elem_value *ucontrol)
2734 {
2735         struct snd_soc_component *component =
2736                         snd_soc_kcontrol_component(kcontrol);
2737         struct wcd_iir_filter_ctl *ctl =
2738                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2739         struct soc_bytes_ext *params = &ctl->bytes_ext;
2740         int iir_idx = ctl->iir_idx;
2741         int band_idx = ctl->band_idx;
2742         u32 coeff[BAND_MAX];
2743         int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
2744
2745         memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
2746
2747         /* Mask top bit it is reserved */
2748         /* Updates addr automatically for each B2 write */
2749         snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
2750                                                  sizeof(uint32_t)) & 0x7F);
2751
2752         set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
2753         set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
2754         set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
2755         set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
2756         set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
2757
2758         return 0;
2759 }
2760
2761 static int rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
2762                                     struct snd_ctl_elem_value *ucontrol)
2763 {
2764         struct snd_soc_component *component =
2765                         snd_soc_kcontrol_component(kcontrol);
2766         struct wcd_iir_filter_ctl *ctl =
2767                         (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2768         struct soc_bytes_ext *params = &ctl->bytes_ext;
2769         int iir_idx = ctl->iir_idx;
2770         int band_idx = ctl->band_idx;
2771         u32 coeff[BAND_MAX];
2772
2773         coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
2774         coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
2775         coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
2776         coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
2777         coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
2778
2779         memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
2780
2781         return 0;
2782 }
2783
2784 static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol,
2785                                    struct snd_ctl_elem_info *ucontrol)
2786 {
2787         struct wcd_iir_filter_ctl *ctl =
2788                 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
2789         struct soc_bytes_ext *params = &ctl->bytes_ext;
2790
2791         ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
2792         ucontrol->count = params->max;
2793
2794         return 0;
2795 }
2796
2797 static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
2798         SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
2799                           -84, 40, digital_gain),
2800         SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL,
2801                           -84, 40, digital_gain),
2802         SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL,
2803                           -84, 40, digital_gain),
2804         SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL,
2805                           -84, 40, digital_gain),
2806         SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL,
2807                           -84, 40, digital_gain),
2808         SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL,
2809                           -84, 40, digital_gain),
2810
2811         SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0,
2812                 rx_macro_get_compander, rx_macro_set_compander),
2813         SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0,
2814                 rx_macro_get_compander, rx_macro_set_compander),
2815
2816         SOC_SINGLE_EXT("RX_EAR Mode Switch", SND_SOC_NOPM, 0, 1, 0,
2817                 rx_macro_get_ear_mode, rx_macro_put_ear_mode),
2818
2819         SOC_SINGLE_EXT("RX_HPH HD2 Mode Switch", SND_SOC_NOPM, 0, 1, 0,
2820                 rx_macro_get_hph_hd2_mode, rx_macro_put_hph_hd2_mode),
2821
2822         SOC_ENUM_EXT("RX_HPH PWR Mode", rx_macro_hph_pwr_mode_enum,
2823                 rx_macro_get_hph_pwr_mode, rx_macro_put_hph_pwr_mode),
2824
2825         SOC_SINGLE_EXT("RX_Softclip Switch", SND_SOC_NOPM, 0, 1, 0,
2826                      rx_macro_soft_clip_enable_get,
2827                      rx_macro_soft_clip_enable_put),
2828         SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0,
2829                         rx_macro_aux_hpf_mode_get,
2830                         rx_macro_aux_hpf_mode_put),
2831
2832         SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
2833                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
2834                 digital_gain),
2835         SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
2836                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
2837                 digital_gain),
2838         SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
2839                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
2840                 digital_gain),
2841         SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
2842                 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
2843                 digital_gain),
2844         SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
2845                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
2846                 digital_gain),
2847         SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
2848                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
2849                 digital_gain),
2850         SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
2851                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
2852                 digital_gain),
2853         SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
2854                 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
2855                 digital_gain),
2856
2857         SOC_SINGLE("IIR1 Band1 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2858                    0, 1, 0),
2859         SOC_SINGLE("IIR1 Band2 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2860                    1, 1, 0),
2861         SOC_SINGLE("IIR1 Band3 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2862                    2, 1, 0),
2863         SOC_SINGLE("IIR1 Band4 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2864                    3, 1, 0),
2865         SOC_SINGLE("IIR1 Band5 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL,
2866                    4, 1, 0),
2867         SOC_SINGLE("IIR2 Band1 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2868                    0, 1, 0),
2869         SOC_SINGLE("IIR2 Band2 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2870                    1, 1, 0),
2871         SOC_SINGLE("IIR2 Band3 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2872                    2, 1, 0),
2873         SOC_SINGLE("IIR2 Band4 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2874                    3, 1, 0),
2875         SOC_SINGLE("IIR2 Band5 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL,
2876                    4, 1, 0),
2877
2878         RX_MACRO_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
2879         RX_MACRO_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
2880         RX_MACRO_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
2881         RX_MACRO_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
2882         RX_MACRO_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
2883
2884         RX_MACRO_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
2885         RX_MACRO_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
2886         RX_MACRO_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
2887         RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
2888         RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
2889
2890 };
2891
2892 static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
2893                                 struct snd_kcontrol *kcontrol,
2894                                 int event)
2895 {
2896         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2897         u16 val, ec_hq_reg;
2898         int ec_tx = -1;
2899
2900         val = snd_soc_component_read(component,
2901                         CDC_RX_INP_MUX_RX_MIX_CFG4);
2902         if (!(strcmp(w->name, "RX MIX TX0 MUX")))
2903                 ec_tx = ((val & 0xf0) >> 0x4) - 1;
2904         else if (!(strcmp(w->name, "RX MIX TX1 MUX")))
2905                 ec_tx = (val & 0x0f) - 1;
2906
2907         val = snd_soc_component_read(component,
2908                         CDC_RX_INP_MUX_RX_MIX_CFG5);
2909         if (!(strcmp(w->name, "RX MIX TX2 MUX")))
2910                 ec_tx = (val & 0x0f) - 1;
2911
2912         if (ec_tx < 0 || (ec_tx >= RX_MACRO_EC_MUX_MAX)) {
2913                 dev_err(component->dev, "%s: EC mix control not set correctly\n",
2914                         __func__);
2915                 return -EINVAL;
2916         }
2917         ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL +
2918                             0x40 * ec_tx;
2919         snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01);
2920         ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 +
2921                                 0x40 * ec_tx;
2922         /* default set to 48k */
2923         snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08);
2924
2925         return 0;
2926 }
2927
2928 static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
2929         SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
2930                 SND_SOC_NOPM, 0, 0),
2931
2932         SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0,
2933                 SND_SOC_NOPM, 0, 0),
2934
2935         SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
2936                 SND_SOC_NOPM, 0, 0),
2937
2938         SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0,
2939                 SND_SOC_NOPM, 0, 0),
2940
2941         SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
2942                 SND_SOC_NOPM, 0, 0),
2943
2944         SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0,
2945                          &rx_macro_rx0_mux),
2946         SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0,
2947                          &rx_macro_rx1_mux),
2948         SND_SOC_DAPM_MUX("RX_MACRO RX2 MUX", SND_SOC_NOPM, RX_MACRO_RX2, 0,
2949                          &rx_macro_rx2_mux),
2950         SND_SOC_DAPM_MUX("RX_MACRO RX3 MUX", SND_SOC_NOPM, RX_MACRO_RX3, 0,
2951                          &rx_macro_rx3_mux),
2952         SND_SOC_DAPM_MUX("RX_MACRO RX4 MUX", SND_SOC_NOPM, RX_MACRO_RX4, 0,
2953                          &rx_macro_rx4_mux),
2954         SND_SOC_DAPM_MUX("RX_MACRO RX5 MUX", SND_SOC_NOPM, RX_MACRO_RX5, 0,
2955                          &rx_macro_rx5_mux),
2956
2957         SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2958         SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2959         SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
2960         SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
2961         SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
2962         SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
2963
2964         SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
2965         SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
2966         SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
2967         SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
2968         SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
2969         SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
2970         SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
2971         SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
2972
2973         SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM,
2974                            RX_MACRO_EC0_MUX, 0,
2975                            &rx_mix_tx0_mux, rx_macro_enable_echo,
2976                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2977         SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM,
2978                            RX_MACRO_EC1_MUX, 0,
2979                            &rx_mix_tx1_mux, rx_macro_enable_echo,
2980                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2981         SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM,
2982                            RX_MACRO_EC2_MUX, 0,
2983                            &rx_mix_tx2_mux, rx_macro_enable_echo,
2984                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2985
2986         SND_SOC_DAPM_MIXER_E("IIR0", CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL,
2987                 4, 0, NULL, 0, rx_macro_set_iir_gain,
2988                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2989         SND_SOC_DAPM_MIXER_E("IIR1", CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL,
2990                 4, 0, NULL, 0, rx_macro_set_iir_gain,
2991                 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2992         SND_SOC_DAPM_MIXER("SRC0", CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL,
2993                 4, 0, NULL, 0),
2994         SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL,
2995                 4, 0, NULL, 0),
2996
2997         SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
2998                          &rx_int0_dem_inp_mux),
2999         SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3000                          &rx_int1_dem_inp_mux),
3001
3002         SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
3003                 &rx_int0_2_mux, rx_macro_enable_mix_path,
3004                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3005                 SND_SOC_DAPM_POST_PMD),
3006         SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
3007                 &rx_int1_2_mux, rx_macro_enable_mix_path,
3008                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3009                 SND_SOC_DAPM_POST_PMD),
3010         SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0,
3011                 &rx_int2_2_mux, rx_macro_enable_mix_path,
3012                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3013                 SND_SOC_DAPM_POST_PMD),
3014
3015         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux),
3016         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux),
3017         SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux),
3018         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux),
3019         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux),
3020         SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux),
3021         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux),
3022         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux),
3023         SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux),
3024
3025         SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
3026                 &rx_int0_1_interp_mux, rx_macro_enable_main_path,
3027                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3028                 SND_SOC_DAPM_POST_PMD),
3029         SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
3030                 &rx_int1_1_interp_mux, rx_macro_enable_main_path,
3031                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3032                 SND_SOC_DAPM_POST_PMD),
3033         SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0,
3034                 &rx_int2_1_interp_mux, rx_macro_enable_main_path,
3035                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3036                 SND_SOC_DAPM_POST_PMD),
3037
3038         SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
3039                          &rx_int0_2_interp_mux),
3040         SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
3041                          &rx_int1_2_interp_mux),
3042         SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
3043                          &rx_int2_2_interp_mux),
3044
3045         SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3046         SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3047         SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3048         SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3049         SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3050         SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3051
3052         SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL,
3053                 0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3054                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3055         SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR,
3056                 0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3057                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3058         SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX,
3059                 0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3060                 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3061
3062         SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3063         SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3064         SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3065
3066         SND_SOC_DAPM_OUTPUT("HPHL_OUT"),
3067         SND_SOC_DAPM_OUTPUT("HPHR_OUT"),
3068         SND_SOC_DAPM_OUTPUT("AUX_OUT"),
3069
3070         SND_SOC_DAPM_INPUT("RX_TX DEC0_INP"),
3071         SND_SOC_DAPM_INPUT("RX_TX DEC1_INP"),
3072         SND_SOC_DAPM_INPUT("RX_TX DEC2_INP"),
3073         SND_SOC_DAPM_INPUT("RX_TX DEC3_INP"),
3074
3075         SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0,
3076         rx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3077 };
3078
3079 static const struct snd_soc_dapm_route rx_audio_map[] = {
3080         {"RX AIF1 PB", NULL, "RX_MCLK"},
3081         {"RX AIF2 PB", NULL, "RX_MCLK"},
3082         {"RX AIF3 PB", NULL, "RX_MCLK"},
3083         {"RX AIF4 PB", NULL, "RX_MCLK"},
3084
3085         {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"},
3086         {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"},
3087         {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"},
3088         {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"},
3089         {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"},
3090         {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"},
3091
3092         {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"},
3093         {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"},
3094         {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"},
3095         {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"},
3096         {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"},
3097         {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"},
3098
3099         {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"},
3100         {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"},
3101         {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"},
3102         {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"},
3103         {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"},
3104         {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"},
3105
3106         {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"},
3107         {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"},
3108         {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"},
3109         {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"},
3110         {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"},
3111         {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"},
3112
3113         {"RX_RX0", NULL, "RX_MACRO RX0 MUX"},
3114         {"RX_RX1", NULL, "RX_MACRO RX1 MUX"},
3115         {"RX_RX2", NULL, "RX_MACRO RX2 MUX"},
3116         {"RX_RX3", NULL, "RX_MACRO RX3 MUX"},
3117         {"RX_RX4", NULL, "RX_MACRO RX4 MUX"},
3118         {"RX_RX5", NULL, "RX_MACRO RX5 MUX"},
3119
3120         {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"},
3121         {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"},
3122         {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"},
3123         {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"},
3124         {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"},
3125         {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"},
3126         {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
3127         {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
3128         {"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3129         {"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3130         {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"},
3131         {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"},
3132         {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"},
3133         {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"},
3134         {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"},
3135         {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"},
3136         {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
3137         {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
3138         {"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3139         {"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3140         {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"},
3141         {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"},
3142         {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"},
3143         {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"},
3144         {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"},
3145         {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"},
3146         {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
3147         {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
3148         {"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3149         {"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3150
3151         {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"},
3152         {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"},
3153         {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"},
3154         {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"},
3155         {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"},
3156         {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"},
3157         {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
3158         {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
3159         {"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3160         {"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3161         {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"},
3162         {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"},
3163         {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"},
3164         {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"},
3165         {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"},
3166         {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"},
3167         {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
3168         {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
3169         {"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3170         {"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3171         {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"},
3172         {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"},
3173         {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"},
3174         {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"},
3175         {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"},
3176         {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"},
3177         {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
3178         {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
3179         {"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3180         {"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3181
3182         {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"},
3183         {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"},
3184         {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"},
3185         {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"},
3186         {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"},
3187         {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"},
3188         {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
3189         {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
3190         {"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3191         {"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3192         {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"},
3193         {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"},
3194         {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"},
3195         {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"},
3196         {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"},
3197         {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"},
3198         {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
3199         {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
3200         {"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3201         {"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3202         {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"},
3203         {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"},
3204         {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"},
3205         {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"},
3206         {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"},
3207         {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"},
3208         {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
3209         {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
3210         {"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3211         {"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3212
3213         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
3214         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
3215         {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
3216         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
3217         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
3218         {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
3219         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
3220         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
3221         {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
3222
3223         {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3224         {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3225         {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3226         {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3227         {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3228         {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3229         {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3230         {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3231         {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3232         {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"},
3233         {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"},
3234         {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"},
3235         {"RX AIF_ECHO", NULL, "RX_MCLK"},
3236
3237         /* Mixing path INT0 */
3238         {"RX INT0_2 MUX", "RX0", "RX_RX0"},
3239         {"RX INT0_2 MUX", "RX1", "RX_RX1"},
3240         {"RX INT0_2 MUX", "RX2", "RX_RX2"},
3241         {"RX INT0_2 MUX", "RX3", "RX_RX3"},
3242         {"RX INT0_2 MUX", "RX4", "RX_RX4"},
3243         {"RX INT0_2 MUX", "RX5", "RX_RX5"},
3244         {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
3245         {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
3246
3247         /* Mixing path INT1 */
3248         {"RX INT1_2 MUX", "RX0", "RX_RX0"},
3249         {"RX INT1_2 MUX", "RX1", "RX_RX1"},
3250         {"RX INT1_2 MUX", "RX2", "RX_RX2"},
3251         {"RX INT1_2 MUX", "RX3", "RX_RX3"},
3252         {"RX INT1_2 MUX", "RX4", "RX_RX4"},
3253         {"RX INT1_2 MUX", "RX5", "RX_RX5"},
3254         {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"},
3255         {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"},
3256
3257         /* Mixing path INT2 */
3258         {"RX INT2_2 MUX", "RX0", "RX_RX0"},
3259         {"RX INT2_2 MUX", "RX1", "RX_RX1"},
3260         {"RX INT2_2 MUX", "RX2", "RX_RX2"},
3261         {"RX INT2_2 MUX", "RX3", "RX_RX3"},
3262         {"RX INT2_2 MUX", "RX4", "RX_RX4"},
3263         {"RX INT2_2 MUX", "RX5", "RX_RX5"},
3264         {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"},
3265         {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"},
3266
3267         {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
3268         {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
3269         {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
3270         {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
3271         {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
3272         {"HPHL_OUT", NULL, "RX INT0 DEM MUX"},
3273         {"HPHL_OUT", NULL, "RX_MCLK"},
3274
3275         {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"},
3276         {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"},
3277         {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
3278         {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
3279         {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"},
3280         {"HPHR_OUT", NULL, "RX INT1 DEM MUX"},
3281         {"HPHR_OUT", NULL, "RX_MCLK"},
3282
3283         {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"},
3284
3285         {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"},
3286         {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
3287         {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
3288         {"AUX_OUT", NULL, "RX INT2 MIX2"},
3289         {"AUX_OUT", NULL, "RX_MCLK"},
3290
3291         {"IIR0", NULL, "RX_MCLK"},
3292         {"IIR0", NULL, "IIR0 INP0 MUX"},
3293         {"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
3294         {"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
3295         {"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
3296         {"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
3297         {"IIR0 INP0 MUX", "RX0", "RX_RX0"},
3298         {"IIR0 INP0 MUX", "RX1", "RX_RX1"},
3299         {"IIR0 INP0 MUX", "RX2", "RX_RX2"},
3300         {"IIR0 INP0 MUX", "RX3", "RX_RX3"},
3301         {"IIR0 INP0 MUX", "RX4", "RX_RX4"},
3302         {"IIR0 INP0 MUX", "RX5", "RX_RX5"},
3303         {"IIR0", NULL, "IIR0 INP1 MUX"},
3304         {"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
3305         {"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
3306         {"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
3307         {"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
3308         {"IIR0 INP1 MUX", "RX0", "RX_RX0"},
3309         {"IIR0 INP1 MUX", "RX1", "RX_RX1"},
3310         {"IIR0 INP1 MUX", "RX2", "RX_RX2"},
3311         {"IIR0 INP1 MUX", "RX3", "RX_RX3"},
3312         {"IIR0 INP1 MUX", "RX4", "RX_RX4"},
3313         {"IIR0 INP1 MUX", "RX5", "RX_RX5"},
3314         {"IIR0", NULL, "IIR0 INP2 MUX"},
3315         {"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
3316         {"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
3317         {"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
3318         {"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
3319         {"IIR0 INP2 MUX", "RX0", "RX_RX0"},
3320         {"IIR0 INP2 MUX", "RX1", "RX_RX1"},
3321         {"IIR0 INP2 MUX", "RX2", "RX_RX2"},
3322         {"IIR0 INP2 MUX", "RX3", "RX_RX3"},
3323         {"IIR0 INP2 MUX", "RX4", "RX_RX4"},
3324         {"IIR0 INP2 MUX", "RX5", "RX_RX5"},
3325         {"IIR0", NULL, "IIR0 INP3 MUX"},
3326         {"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
3327         {"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
3328         {"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
3329         {"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
3330         {"IIR0 INP3 MUX", "RX0", "RX_RX0"},
3331         {"IIR0 INP3 MUX", "RX1", "RX_RX1"},
3332         {"IIR0 INP3 MUX", "RX2", "RX_RX2"},
3333         {"IIR0 INP3 MUX", "RX3", "RX_RX3"},
3334         {"IIR0 INP3 MUX", "RX4", "RX_RX4"},
3335         {"IIR0 INP3 MUX", "RX5", "RX_RX5"},
3336
3337         {"IIR1", NULL, "RX_MCLK"},
3338         {"IIR1", NULL, "IIR1 INP0 MUX"},
3339         {"IIR1 INP0 MUX", "DEC0", "RX_TX DEC0_INP"},
3340         {"IIR1 INP0 MUX", "DEC1", "RX_TX DEC1_INP"},
3341         {"IIR1 INP0 MUX", "DEC2", "RX_TX DEC2_INP"},
3342         {"IIR1 INP0 MUX", "DEC3", "RX_TX DEC3_INP"},
3343         {"IIR1 INP0 MUX", "RX0", "RX_RX0"},
3344         {"IIR1 INP0 MUX", "RX1", "RX_RX1"},
3345         {"IIR1 INP0 MUX", "RX2", "RX_RX2"},
3346         {"IIR1 INP0 MUX", "RX3", "RX_RX3"},
3347         {"IIR1 INP0 MUX", "RX4", "RX_RX4"},
3348         {"IIR1 INP0 MUX", "RX5", "RX_RX5"},
3349         {"IIR1", NULL, "IIR1 INP1 MUX"},
3350         {"IIR1 INP1 MUX", "DEC0", "RX_TX DEC0_INP"},
3351         {"IIR1 INP1 MUX", "DEC1", "RX_TX DEC1_INP"},
3352         {"IIR1 INP1 MUX", "DEC2", "RX_TX DEC2_INP"},
3353         {"IIR1 INP1 MUX", "DEC3", "RX_TX DEC3_INP"},
3354         {"IIR1 INP1 MUX", "RX0", "RX_RX0"},
3355         {"IIR1 INP1 MUX", "RX1", "RX_RX1"},
3356         {"IIR1 INP1 MUX", "RX2", "RX_RX2"},
3357         {"IIR1 INP1 MUX", "RX3", "RX_RX3"},
3358         {"IIR1 INP1 MUX", "RX4", "RX_RX4"},
3359         {"IIR1 INP1 MUX", "RX5", "RX_RX5"},
3360         {"IIR1", NULL, "IIR1 INP2 MUX"},
3361         {"IIR1 INP2 MUX", "DEC0", "RX_TX DEC0_INP"},
3362         {"IIR1 INP2 MUX", "DEC1", "RX_TX DEC1_INP"},
3363         {"IIR1 INP2 MUX", "DEC2", "RX_TX DEC2_INP"},
3364         {"IIR1 INP2 MUX", "DEC3", "RX_TX DEC3_INP"},
3365         {"IIR1 INP2 MUX", "RX0", "RX_RX0"},
3366         {"IIR1 INP2 MUX", "RX1", "RX_RX1"},
3367         {"IIR1 INP2 MUX", "RX2", "RX_RX2"},
3368         {"IIR1 INP2 MUX", "RX3", "RX_RX3"},
3369         {"IIR1 INP2 MUX", "RX4", "RX_RX4"},
3370         {"IIR1 INP2 MUX", "RX5", "RX_RX5"},
3371         {"IIR1", NULL, "IIR1 INP3 MUX"},
3372         {"IIR1 INP3 MUX", "DEC0", "RX_TX DEC0_INP"},
3373         {"IIR1 INP3 MUX", "DEC1", "RX_TX DEC1_INP"},
3374         {"IIR1 INP3 MUX", "DEC2", "RX_TX DEC2_INP"},
3375         {"IIR1 INP3 MUX", "DEC3", "RX_TX DEC3_INP"},
3376         {"IIR1 INP3 MUX", "RX0", "RX_RX0"},
3377         {"IIR1 INP3 MUX", "RX1", "RX_RX1"},
3378         {"IIR1 INP3 MUX", "RX2", "RX_RX2"},
3379         {"IIR1 INP3 MUX", "RX3", "RX_RX3"},
3380         {"IIR1 INP3 MUX", "RX4", "RX_RX4"},
3381         {"IIR1 INP3 MUX", "RX5", "RX_RX5"},
3382
3383         {"SRC0", NULL, "IIR0"},
3384         {"SRC1", NULL, "IIR1"},
3385         {"RX INT0 MIX2 INP", "SRC0", "SRC0"},
3386         {"RX INT0 MIX2 INP", "SRC1", "SRC1"},
3387         {"RX INT1 MIX2 INP", "SRC0", "SRC0"},
3388         {"RX INT1 MIX2 INP", "SRC1", "SRC1"},
3389         {"RX INT2 MIX2 INP", "SRC0", "SRC0"},
3390         {"RX INT2 MIX2 INP", "SRC1", "SRC1"},
3391 };
3392
3393 static int rx_macro_component_probe(struct snd_soc_component *component)
3394 {
3395         struct rx_macro *rx = snd_soc_component_get_drvdata(component);
3396
3397         snd_soc_component_init_regmap(component, rx->regmap);
3398
3399         snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_SEC7,
3400                                       CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3401                                       CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3402         snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_SEC7,
3403                                       CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3404                                       CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3405         snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_SEC7,
3406                                       CDC_RX_DSM_OUT_DELAY_SEL_MASK,
3407                                       CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
3408         snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_CFG3,
3409                                       CDC_RX_DC_COEFF_SEL_MASK,
3410                                       CDC_RX_DC_COEFF_SEL_TWO);
3411         snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_CFG3,
3412                                       CDC_RX_DC_COEFF_SEL_MASK,
3413                                       CDC_RX_DC_COEFF_SEL_TWO);
3414         snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_CFG3,
3415                                       CDC_RX_DC_COEFF_SEL_MASK,
3416                                       CDC_RX_DC_COEFF_SEL_TWO);
3417
3418         rx->component = component;
3419
3420         return 0;
3421 }
3422
3423 static int swclk_gate_enable(struct clk_hw *hw)
3424 {
3425         struct rx_macro *rx = to_rx_macro(hw);
3426
3427         rx_macro_mclk_enable(rx, true);
3428         if (rx->reset_swr)
3429                 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3430                                    CDC_RX_SWR_RESET_MASK,
3431                                    CDC_RX_SWR_RESET);
3432
3433         regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3434                            CDC_RX_SWR_CLK_EN_MASK, 1);
3435
3436         if (rx->reset_swr)
3437                 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3438                                    CDC_RX_SWR_RESET_MASK, 0);
3439         rx->reset_swr = false;
3440
3441         return 0;
3442 }
3443
3444 static void swclk_gate_disable(struct clk_hw *hw)
3445 {
3446         struct rx_macro *rx = to_rx_macro(hw);
3447
3448         regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
3449                            CDC_RX_SWR_CLK_EN_MASK, 0);
3450
3451         rx_macro_mclk_enable(rx, false);
3452 }
3453
3454 static int swclk_gate_is_enabled(struct clk_hw *hw)
3455 {
3456         struct rx_macro *rx = to_rx_macro(hw);
3457         int ret, val;
3458
3459         regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val);
3460         ret = val & BIT(0);
3461
3462         return ret;
3463 }
3464
3465 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
3466                                        unsigned long parent_rate)
3467 {
3468         return parent_rate / 2;
3469 }
3470
3471 static const struct clk_ops swclk_gate_ops = {
3472         .prepare = swclk_gate_enable,
3473         .unprepare = swclk_gate_disable,
3474         .is_enabled = swclk_gate_is_enabled,
3475         .recalc_rate = swclk_recalc_rate,
3476
3477 };
3478
3479 static struct clk *rx_macro_register_mclk_output(struct rx_macro *rx)
3480 {
3481         struct device *dev = rx->dev;
3482         struct device_node *np = dev->of_node;
3483         const char *parent_clk_name = NULL;
3484         const char *clk_name = "lpass-rx-mclk";
3485         struct clk_hw *hw;
3486         struct clk_init_data init;
3487         int ret;
3488
3489         parent_clk_name = __clk_get_name(rx->clks[2].clk);
3490
3491         init.name = clk_name;
3492         init.ops = &swclk_gate_ops;
3493         init.flags = 0;
3494         init.parent_names = &parent_clk_name;
3495         init.num_parents = 1;
3496         rx->hw.init = &init;
3497         hw = &rx->hw;
3498         ret = clk_hw_register(rx->dev, hw);
3499         if (ret)
3500                 return ERR_PTR(ret);
3501
3502         of_clk_add_provider(np, of_clk_src_simple_get, hw->clk);
3503
3504         return NULL;
3505 }
3506
3507 static const struct snd_soc_component_driver rx_macro_component_drv = {
3508         .name = "RX-MACRO",
3509         .probe = rx_macro_component_probe,
3510         .controls = rx_macro_snd_controls,
3511         .num_controls = ARRAY_SIZE(rx_macro_snd_controls),
3512         .dapm_widgets = rx_macro_dapm_widgets,
3513         .num_dapm_widgets = ARRAY_SIZE(rx_macro_dapm_widgets),
3514         .dapm_routes = rx_audio_map,
3515         .num_dapm_routes = ARRAY_SIZE(rx_audio_map),
3516 };
3517
3518 static int rx_macro_probe(struct platform_device *pdev)
3519 {
3520         struct device *dev = &pdev->dev;
3521         struct rx_macro *rx;
3522         void __iomem *base;
3523         int ret;
3524
3525         rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL);
3526         if (!rx)
3527                 return -ENOMEM;
3528
3529         rx->clks[0].id = "macro";
3530         rx->clks[1].id = "dcodec";
3531         rx->clks[2].id = "mclk";
3532         rx->clks[3].id = "npl";
3533         rx->clks[4].id = "fsgen";
3534
3535         ret = devm_clk_bulk_get(dev, RX_NUM_CLKS_MAX, rx->clks);
3536         if (ret) {
3537                 dev_err(dev, "Error getting RX Clocks (%d)\n", ret);
3538                 return ret;
3539         }
3540
3541         base = devm_platform_ioremap_resource(pdev, 0);
3542         if (IS_ERR(base))
3543                 return PTR_ERR(base);
3544
3545         rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config);
3546
3547         dev_set_drvdata(dev, rx);
3548
3549         rx->reset_swr = true;
3550         rx->dev = dev;
3551
3552         /* set MCLK and NPL rates */
3553         clk_set_rate(rx->clks[2].clk, MCLK_FREQ);
3554         clk_set_rate(rx->clks[3].clk, MCLK_FREQ);
3555
3556         ret = clk_bulk_prepare_enable(RX_NUM_CLKS_MAX, rx->clks);
3557         if (ret)
3558                 return ret;
3559
3560         rx_macro_register_mclk_output(rx);
3561
3562         ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv,
3563                                               rx_macro_dai,
3564                                               ARRAY_SIZE(rx_macro_dai));
3565         if (ret)
3566                 clk_bulk_disable_unprepare(RX_NUM_CLKS_MAX, rx->clks);
3567
3568         return ret;
3569 }
3570
3571 static int rx_macro_remove(struct platform_device *pdev)
3572 {
3573         struct rx_macro *rx = dev_get_drvdata(&pdev->dev);
3574
3575         of_clk_del_provider(pdev->dev.of_node);
3576         clk_bulk_disable_unprepare(RX_NUM_CLKS_MAX, rx->clks);
3577         return 0;
3578 }
3579
3580 static const struct of_device_id rx_macro_dt_match[] = {
3581         { .compatible = "qcom,sm8250-lpass-rx-macro" },
3582         { }
3583 };
3584
3585 static struct platform_driver rx_macro_driver = {
3586         .driver = {
3587                 .name = "rx_macro",
3588                 .owner = THIS_MODULE,
3589                 .of_match_table = rx_macro_dt_match,
3590                 .suppress_bind_attrs = true,
3591         },
3592         .probe = rx_macro_probe,
3593         .remove = rx_macro_remove,
3594 };
3595
3596 module_platform_driver(rx_macro_driver);
3597
3598 MODULE_DESCRIPTION("RX macro driver");
3599 MODULE_LICENSE("GPL");