2 * es8328.c -- ES8328 ALSA SoC Audio driver
4 * Copyright 2014 Sutajio Ko-Usagi PTE LTD
6 * Author: Sean Cross <xobs@kosagi.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/of_device.h>
16 #include <linux/module.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <linux/regulator/consumer.h>
21 #include <sound/core.h>
22 #include <sound/initval.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/tlv.h>
29 static const unsigned int rates_12288[] = {
30 8000, 12000, 16000, 24000, 32000, 48000, 96000,
33 static const int ratios_12288[] = {
37 static const struct snd_pcm_hw_constraint_list constraints_12288 = {
38 .count = ARRAY_SIZE(rates_12288),
42 static const unsigned int rates_11289[] = {
43 8018, 11025, 22050, 44100, 88200,
46 static const int ratios_11289[] = {
50 static const struct snd_pcm_hw_constraint_list constraints_11289 = {
51 .count = ARRAY_SIZE(rates_11289),
55 /* regulator supplies for sgtl5000, VDDD is an optional external supply */
56 enum sgtl5000_regulator_supplies {
64 /* vddd is optional supply */
65 static const char * const supply_names[ES8328_SUPPLY_NUM] = {
72 #define ES8328_RATES (SNDRV_PCM_RATE_192000 | \
73 SNDRV_PCM_RATE_96000 | \
74 SNDRV_PCM_RATE_88200 | \
75 SNDRV_PCM_RATE_8000_48000)
76 #define ES8328_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
77 SNDRV_PCM_FMTBIT_S18_3LE | \
78 SNDRV_PCM_FMTBIT_S20_3LE | \
79 SNDRV_PCM_FMTBIT_S24_LE | \
80 SNDRV_PCM_FMTBIT_S32_LE)
83 struct regmap *regmap;
88 const struct snd_pcm_hw_constraint_list *sysclk_constraints;
89 const int *mclk_ratios;
91 struct regulator_bulk_data supplies[ES8328_SUPPLY_NUM];
98 static const char * const adcpol_txt[] = {"Normal", "L Invert", "R Invert",
100 static SOC_ENUM_SINGLE_DECL(adcpol,
101 ES8328_ADCCONTROL6, 6, adcpol_txt);
103 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
104 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
105 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
106 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
107 static const DECLARE_TLV_DB_SCALE(mic_tlv, 0, 300, 0);
109 static const struct {
112 } deemph_settings[] = {
113 { 0, ES8328_DACCONTROL6_DEEMPH_OFF },
114 { 32000, ES8328_DACCONTROL6_DEEMPH_32k },
115 { 44100, ES8328_DACCONTROL6_DEEMPH_44_1k },
116 { 48000, ES8328_DACCONTROL6_DEEMPH_48k },
119 static int es8328_set_deemph(struct snd_soc_component *component)
121 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
125 * If we're using deemphasis select the nearest available sample
128 if (es8328->deemph) {
130 for (i = 1; i < ARRAY_SIZE(deemph_settings); i++) {
131 if (abs(deemph_settings[i].rate - es8328->playback_fs) <
132 abs(deemph_settings[best].rate - es8328->playback_fs))
136 val = deemph_settings[best].val;
138 val = ES8328_DACCONTROL6_DEEMPH_OFF;
141 dev_dbg(component->dev, "Set deemphasis %d\n", val);
143 return snd_soc_component_update_bits(component, ES8328_DACCONTROL6,
144 ES8328_DACCONTROL6_DEEMPH_MASK, val);
147 static int es8328_get_deemph(struct snd_kcontrol *kcontrol,
148 struct snd_ctl_elem_value *ucontrol)
150 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
151 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
153 ucontrol->value.integer.value[0] = es8328->deemph;
157 static int es8328_put_deemph(struct snd_kcontrol *kcontrol,
158 struct snd_ctl_elem_value *ucontrol)
160 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
161 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
162 unsigned int deemph = ucontrol->value.integer.value[0];
168 ret = es8328_set_deemph(component);
172 es8328->deemph = deemph;
179 static const struct snd_kcontrol_new es8328_snd_controls[] = {
180 SOC_DOUBLE_R_TLV("Capture Digital Volume",
181 ES8328_ADCCONTROL8, ES8328_ADCCONTROL9,
182 0, 0xc0, 1, dac_adc_tlv),
183 SOC_SINGLE("Capture ZC Switch", ES8328_ADCCONTROL7, 6, 1, 0),
185 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
186 es8328_get_deemph, es8328_put_deemph),
188 SOC_ENUM("Capture Polarity", adcpol),
190 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
191 ES8328_DACCONTROL17, 3, 7, 1, bypass_tlv),
192 SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
193 ES8328_DACCONTROL19, 3, 7, 1, bypass_tlv),
194 SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
195 ES8328_DACCONTROL18, 3, 7, 1, bypass_tlv),
196 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume",
197 ES8328_DACCONTROL20, 3, 7, 1, bypass_tlv),
199 SOC_DOUBLE_R_TLV("PCM Volume",
200 ES8328_LDACVOL, ES8328_RDACVOL,
201 0, ES8328_DACVOL_MAX, 1, dac_adc_tlv),
203 SOC_DOUBLE_R_TLV("Output 1 Playback Volume",
204 ES8328_LOUT1VOL, ES8328_ROUT1VOL,
205 0, ES8328_OUT1VOL_MAX, 0, play_tlv),
207 SOC_DOUBLE_R_TLV("Output 2 Playback Volume",
208 ES8328_LOUT2VOL, ES8328_ROUT2VOL,
209 0, ES8328_OUT2VOL_MAX, 0, play_tlv),
211 SOC_DOUBLE_TLV("Mic PGA Volume", ES8328_ADCCONTROL1,
212 4, 0, 8, 0, mic_tlv),
219 static const char * const es8328_line_texts[] = {
220 "Line 1", "Line 2", "PGA", "Differential"};
222 static const struct soc_enum es8328_lline_enum =
223 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 3,
224 ARRAY_SIZE(es8328_line_texts),
226 static const struct snd_kcontrol_new es8328_left_line_controls =
227 SOC_DAPM_ENUM("Route", es8328_lline_enum);
229 static const struct soc_enum es8328_rline_enum =
230 SOC_ENUM_SINGLE(ES8328_DACCONTROL16, 0,
231 ARRAY_SIZE(es8328_line_texts),
233 static const struct snd_kcontrol_new es8328_right_line_controls =
234 SOC_DAPM_ENUM("Route", es8328_lline_enum);
237 static const struct snd_kcontrol_new es8328_left_mixer_controls[] = {
238 SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL17, 7, 1, 0),
239 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
240 SOC_DAPM_SINGLE("Right Playback Switch", ES8328_DACCONTROL18, 7, 1, 0),
241 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL18, 6, 1, 0),
245 static const struct snd_kcontrol_new es8328_right_mixer_controls[] = {
246 SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
247 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
248 SOC_DAPM_SINGLE("Playback Switch", ES8328_DACCONTROL20, 7, 1, 0),
249 SOC_DAPM_SINGLE("Right Bypass Switch", ES8328_DACCONTROL20, 6, 1, 0),
252 static const char * const es8328_pga_sel[] = {
253 "Line 1", "Line 2", "Line 3", "Differential"};
256 static const struct soc_enum es8328_lpga_enum =
257 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 6,
258 ARRAY_SIZE(es8328_pga_sel),
260 static const struct snd_kcontrol_new es8328_left_pga_controls =
261 SOC_DAPM_ENUM("Route", es8328_lpga_enum);
264 static const struct soc_enum es8328_rpga_enum =
265 SOC_ENUM_SINGLE(ES8328_ADCCONTROL2, 4,
266 ARRAY_SIZE(es8328_pga_sel),
268 static const struct snd_kcontrol_new es8328_right_pga_controls =
269 SOC_DAPM_ENUM("Route", es8328_rpga_enum);
271 /* Differential Mux */
272 static const char * const es8328_diff_sel[] = {"Line 1", "Line 2"};
273 static SOC_ENUM_SINGLE_DECL(diffmux,
274 ES8328_ADCCONTROL3, 7, es8328_diff_sel);
275 static const struct snd_kcontrol_new es8328_diffmux_controls =
276 SOC_DAPM_ENUM("Route", diffmux);
279 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
280 "Mono (Right)", "Digital Mono"};
281 static SOC_ENUM_SINGLE_DECL(monomux,
282 ES8328_ADCCONTROL3, 3, es8328_mono_mux);
283 static const struct snd_kcontrol_new es8328_monomux_controls =
284 SOC_DAPM_ENUM("Route", monomux);
286 static const struct snd_soc_dapm_widget es8328_dapm_widgets[] = {
287 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
288 &es8328_diffmux_controls),
289 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
290 &es8328_monomux_controls),
291 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
292 &es8328_monomux_controls),
294 SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
295 ES8328_ADCPOWER_AINL_OFF, 1,
296 &es8328_left_pga_controls),
297 SND_SOC_DAPM_MUX("Right PGA Mux", ES8328_ADCPOWER,
298 ES8328_ADCPOWER_AINR_OFF, 1,
299 &es8328_right_pga_controls),
301 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
302 &es8328_left_line_controls),
303 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
304 &es8328_right_line_controls),
306 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
307 ES8328_ADCPOWER_ADCR_OFF, 1),
308 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
309 ES8328_ADCPOWER_ADCL_OFF, 1),
311 SND_SOC_DAPM_SUPPLY("Mic Bias", ES8328_ADCPOWER,
312 ES8328_ADCPOWER_MIC_BIAS_OFF, 1, NULL, 0),
313 SND_SOC_DAPM_SUPPLY("Mic Bias Gen", ES8328_ADCPOWER,
314 ES8328_ADCPOWER_ADC_BIAS_GEN_OFF, 1, NULL, 0),
316 SND_SOC_DAPM_SUPPLY("DAC STM", ES8328_CHIPPOWER,
317 ES8328_CHIPPOWER_DACSTM_RESET, 1, NULL, 0),
318 SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER,
319 ES8328_CHIPPOWER_ADCSTM_RESET, 1, NULL, 0),
321 SND_SOC_DAPM_SUPPLY("DAC DIG", ES8328_CHIPPOWER,
322 ES8328_CHIPPOWER_DACDIG_OFF, 1, NULL, 0),
323 SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER,
324 ES8328_CHIPPOWER_ADCDIG_OFF, 1, NULL, 0),
326 SND_SOC_DAPM_SUPPLY("DAC DLL", ES8328_CHIPPOWER,
327 ES8328_CHIPPOWER_DACDLL_OFF, 1, NULL, 0),
328 SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER,
329 ES8328_CHIPPOWER_ADCDLL_OFF, 1, NULL, 0),
331 SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER,
332 ES8328_CHIPPOWER_ADCVREF_OFF, 1, NULL, 0),
333 SND_SOC_DAPM_SUPPLY("DAC Vref", ES8328_CHIPPOWER,
334 ES8328_CHIPPOWER_DACVREF_OFF, 1, NULL, 0),
336 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8328_DACPOWER,
337 ES8328_DACPOWER_RDAC_OFF, 1),
338 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
339 ES8328_DACPOWER_LDAC_OFF, 1),
341 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
342 &es8328_left_mixer_controls[0],
343 ARRAY_SIZE(es8328_left_mixer_controls)),
344 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
345 &es8328_right_mixer_controls[0],
346 ARRAY_SIZE(es8328_right_mixer_controls)),
348 SND_SOC_DAPM_PGA("Right Out 2", ES8328_DACPOWER,
349 ES8328_DACPOWER_ROUT2_ON, 0, NULL, 0),
350 SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
351 ES8328_DACPOWER_LOUT2_ON, 0, NULL, 0),
352 SND_SOC_DAPM_PGA("Right Out 1", ES8328_DACPOWER,
353 ES8328_DACPOWER_ROUT1_ON, 0, NULL, 0),
354 SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
355 ES8328_DACPOWER_LOUT1_ON, 0, NULL, 0),
357 SND_SOC_DAPM_OUTPUT("LOUT1"),
358 SND_SOC_DAPM_OUTPUT("ROUT1"),
359 SND_SOC_DAPM_OUTPUT("LOUT2"),
360 SND_SOC_DAPM_OUTPUT("ROUT2"),
362 SND_SOC_DAPM_INPUT("LINPUT1"),
363 SND_SOC_DAPM_INPUT("LINPUT2"),
364 SND_SOC_DAPM_INPUT("RINPUT1"),
365 SND_SOC_DAPM_INPUT("RINPUT2"),
368 static const struct snd_soc_dapm_route es8328_dapm_routes[] = {
370 { "Left Line Mux", "Line 1", "LINPUT1" },
371 { "Left Line Mux", "Line 2", "LINPUT2" },
372 { "Left Line Mux", "PGA", "Left PGA Mux" },
373 { "Left Line Mux", "Differential", "Differential Mux" },
375 { "Right Line Mux", "Line 1", "RINPUT1" },
376 { "Right Line Mux", "Line 2", "RINPUT2" },
377 { "Right Line Mux", "PGA", "Right PGA Mux" },
378 { "Right Line Mux", "Differential", "Differential Mux" },
380 { "Left PGA Mux", "Line 1", "LINPUT1" },
381 { "Left PGA Mux", "Line 2", "LINPUT2" },
382 { "Left PGA Mux", "Differential", "Differential Mux" },
384 { "Right PGA Mux", "Line 1", "RINPUT1" },
385 { "Right PGA Mux", "Line 2", "RINPUT2" },
386 { "Right PGA Mux", "Differential", "Differential Mux" },
388 { "Differential Mux", "Line 1", "LINPUT1" },
389 { "Differential Mux", "Line 1", "RINPUT1" },
390 { "Differential Mux", "Line 2", "LINPUT2" },
391 { "Differential Mux", "Line 2", "RINPUT2" },
393 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
394 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
395 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
397 { "Right ADC Mux", "Stereo", "Right PGA Mux" },
398 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
399 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
401 { "Left ADC", NULL, "Left ADC Mux" },
402 { "Right ADC", NULL, "Right ADC Mux" },
404 { "ADC DIG", NULL, "ADC STM" },
405 { "ADC DIG", NULL, "ADC Vref" },
406 { "ADC DIG", NULL, "ADC DLL" },
408 { "Left ADC", NULL, "ADC DIG" },
409 { "Right ADC", NULL, "ADC DIG" },
411 { "Mic Bias", NULL, "Mic Bias Gen" },
413 { "Left Line Mux", "Line 1", "LINPUT1" },
414 { "Left Line Mux", "Line 2", "LINPUT2" },
415 { "Left Line Mux", "PGA", "Left PGA Mux" },
416 { "Left Line Mux", "Differential", "Differential Mux" },
418 { "Right Line Mux", "Line 1", "RINPUT1" },
419 { "Right Line Mux", "Line 2", "RINPUT2" },
420 { "Right Line Mux", "PGA", "Right PGA Mux" },
421 { "Right Line Mux", "Differential", "Differential Mux" },
423 { "Left Out 1", NULL, "Left DAC" },
424 { "Right Out 1", NULL, "Right DAC" },
425 { "Left Out 2", NULL, "Left DAC" },
426 { "Right Out 2", NULL, "Right DAC" },
428 { "Left Mixer", "Playback Switch", "Left DAC" },
429 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
430 { "Left Mixer", "Right Playback Switch", "Right DAC" },
431 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
433 { "Right Mixer", "Left Playback Switch", "Left DAC" },
434 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
435 { "Right Mixer", "Playback Switch", "Right DAC" },
436 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
438 { "DAC DIG", NULL, "DAC STM" },
439 { "DAC DIG", NULL, "DAC Vref" },
440 { "DAC DIG", NULL, "DAC DLL" },
442 { "Left DAC", NULL, "DAC DIG" },
443 { "Right DAC", NULL, "DAC DIG" },
445 { "Left Out 1", NULL, "Left Mixer" },
446 { "LOUT1", NULL, "Left Out 1" },
447 { "Right Out 1", NULL, "Right Mixer" },
448 { "ROUT1", NULL, "Right Out 1" },
450 { "Left Out 2", NULL, "Left Mixer" },
451 { "LOUT2", NULL, "Left Out 2" },
452 { "Right Out 2", NULL, "Right Mixer" },
453 { "ROUT2", NULL, "Right Out 2" },
456 static int es8328_mute(struct snd_soc_dai *dai, int mute)
458 return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3,
459 ES8328_DACCONTROL3_DACMUTE,
460 mute ? ES8328_DACCONTROL3_DACMUTE : 0);
463 static int es8328_startup(struct snd_pcm_substream *substream,
464 struct snd_soc_dai *dai)
466 struct snd_soc_component *component = dai->component;
467 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
469 if (es8328->master && es8328->sysclk_constraints)
470 snd_pcm_hw_constraint_list(substream->runtime, 0,
471 SNDRV_PCM_HW_PARAM_RATE,
472 es8328->sysclk_constraints);
477 static int es8328_hw_params(struct snd_pcm_substream *substream,
478 struct snd_pcm_hw_params *params,
479 struct snd_soc_dai *dai)
481 struct snd_soc_component *component = dai->component;
482 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
488 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
489 reg = ES8328_DACCONTROL2;
491 reg = ES8328_ADCCONTROL5;
493 if (es8328->master) {
494 if (!es8328->sysclk_constraints) {
495 dev_err(component->dev, "No MCLK configured\n");
499 for (i = 0; i < es8328->sysclk_constraints->count; i++)
500 if (es8328->sysclk_constraints->list[i] ==
504 if (i == es8328->sysclk_constraints->count) {
505 dev_err(component->dev,
506 "LRCLK %d unsupported with current clock\n",
507 params_rate(params));
510 ratio = es8328->mclk_ratios[i];
513 es8328->mclkdiv2 = 0;
516 snd_soc_component_update_bits(component, ES8328_MASTERMODE,
517 ES8328_MASTERMODE_MCLKDIV2,
518 es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0);
520 switch (params_width(params)) {
540 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
541 snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
542 ES8328_DACCONTROL1_DACWL_MASK,
543 wl << ES8328_DACCONTROL1_DACWL_SHIFT);
545 es8328->playback_fs = params_rate(params);
546 es8328_set_deemph(component);
548 snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
549 ES8328_ADCCONTROL4_ADCWL_MASK,
550 wl << ES8328_ADCCONTROL4_ADCWL_SHIFT);
552 return snd_soc_component_update_bits(component, reg, ES8328_RATEMASK, ratio);
555 static int es8328_set_sysclk(struct snd_soc_dai *codec_dai,
556 int clk_id, unsigned int freq, int dir)
558 struct snd_soc_component *component = codec_dai->component;
559 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
564 es8328->sysclk_constraints = NULL;
565 es8328->mclk_ratios = NULL;
571 es8328->sysclk_constraints = &constraints_11289;
572 es8328->mclk_ratios = ratios_11289;
578 es8328->sysclk_constraints = &constraints_12288;
579 es8328->mclk_ratios = ratios_12288;
585 es8328->mclkdiv2 = mclkdiv2;
589 static int es8328_set_dai_fmt(struct snd_soc_dai *codec_dai,
592 struct snd_soc_component *component = codec_dai->component;
593 struct es8328_priv *es8328 = snd_soc_component_get_drvdata(component);
597 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
598 case SND_SOC_DAIFMT_CBM_CFM:
599 /* Master serial port mode, with BCLK generated automatically */
600 snd_soc_component_update_bits(component, ES8328_MASTERMODE,
601 ES8328_MASTERMODE_MSC,
602 ES8328_MASTERMODE_MSC);
603 es8328->master = true;
605 case SND_SOC_DAIFMT_CBS_CFS:
606 /* Slave serial port mode */
607 snd_soc_component_update_bits(component, ES8328_MASTERMODE,
608 ES8328_MASTERMODE_MSC, 0);
609 es8328->master = false;
615 /* interface format */
616 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
617 case SND_SOC_DAIFMT_I2S:
618 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_I2S;
619 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_I2S;
621 case SND_SOC_DAIFMT_RIGHT_J:
622 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_RJUST;
623 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_RJUST;
625 case SND_SOC_DAIFMT_LEFT_J:
626 dac_mode |= ES8328_DACCONTROL1_DACFORMAT_LJUST;
627 adc_mode |= ES8328_ADCCONTROL4_ADCFORMAT_LJUST;
633 /* clock inversion */
634 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)
637 snd_soc_component_update_bits(component, ES8328_DACCONTROL1,
638 ES8328_DACCONTROL1_DACFORMAT_MASK, dac_mode);
639 snd_soc_component_update_bits(component, ES8328_ADCCONTROL4,
640 ES8328_ADCCONTROL4_ADCFORMAT_MASK, adc_mode);
645 static int es8328_set_bias_level(struct snd_soc_component *component,
646 enum snd_soc_bias_level level)
649 case SND_SOC_BIAS_ON:
652 case SND_SOC_BIAS_PREPARE:
653 /* VREF, VMID=2x50k, digital enabled */
654 snd_soc_component_write(component, ES8328_CHIPPOWER, 0);
655 snd_soc_component_update_bits(component, ES8328_CONTROL1,
656 ES8328_CONTROL1_VMIDSEL_MASK |
657 ES8328_CONTROL1_ENREF,
658 ES8328_CONTROL1_VMIDSEL_50k |
659 ES8328_CONTROL1_ENREF);
662 case SND_SOC_BIAS_STANDBY:
663 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
664 snd_soc_component_update_bits(component, ES8328_CONTROL1,
665 ES8328_CONTROL1_VMIDSEL_MASK |
666 ES8328_CONTROL1_ENREF,
667 ES8328_CONTROL1_VMIDSEL_5k |
668 ES8328_CONTROL1_ENREF);
674 snd_soc_component_write(component, ES8328_CONTROL2,
675 ES8328_CONTROL2_OVERCURRENT_ON |
676 ES8328_CONTROL2_THERMAL_SHUTDOWN_ON);
678 /* VREF, VMID=2*500k, digital stopped */
679 snd_soc_component_update_bits(component, ES8328_CONTROL1,
680 ES8328_CONTROL1_VMIDSEL_MASK |
681 ES8328_CONTROL1_ENREF,
682 ES8328_CONTROL1_VMIDSEL_500k |
683 ES8328_CONTROL1_ENREF);
686 case SND_SOC_BIAS_OFF:
687 snd_soc_component_update_bits(component, ES8328_CONTROL1,
688 ES8328_CONTROL1_VMIDSEL_MASK |
689 ES8328_CONTROL1_ENREF,
696 static const struct snd_soc_dai_ops es8328_dai_ops = {
697 .startup = es8328_startup,
698 .hw_params = es8328_hw_params,
699 .digital_mute = es8328_mute,
700 .set_sysclk = es8328_set_sysclk,
701 .set_fmt = es8328_set_dai_fmt,
704 static struct snd_soc_dai_driver es8328_dai = {
705 .name = "es8328-hifi-analog",
707 .stream_name = "Playback",
710 .rates = ES8328_RATES,
711 .formats = ES8328_FORMATS,
714 .stream_name = "Capture",
717 .rates = ES8328_RATES,
718 .formats = ES8328_FORMATS,
720 .ops = &es8328_dai_ops,
721 .symmetric_rates = 1,
724 static int es8328_suspend(struct snd_soc_component *component)
726 struct es8328_priv *es8328;
729 es8328 = snd_soc_component_get_drvdata(component);
731 clk_disable_unprepare(es8328->clk);
733 ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
736 dev_err(component->dev, "unable to disable regulators\n");
742 static int es8328_resume(struct snd_soc_component *component)
744 struct regmap *regmap = dev_get_regmap(component->dev, NULL);
745 struct es8328_priv *es8328;
748 es8328 = snd_soc_component_get_drvdata(component);
750 ret = clk_prepare_enable(es8328->clk);
752 dev_err(component->dev, "unable to enable clock\n");
756 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
759 dev_err(component->dev, "unable to enable regulators\n");
763 regcache_mark_dirty(regmap);
764 ret = regcache_sync(regmap);
766 dev_err(component->dev, "unable to sync regcache\n");
773 static int es8328_component_probe(struct snd_soc_component *component)
775 struct es8328_priv *es8328;
778 es8328 = snd_soc_component_get_drvdata(component);
780 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),
783 dev_err(component->dev, "unable to enable regulators\n");
788 es8328->clk = devm_clk_get(component->dev, NULL);
789 if (IS_ERR(es8328->clk)) {
790 dev_err(component->dev, "codec clock missing or invalid\n");
791 ret = PTR_ERR(es8328->clk);
795 ret = clk_prepare_enable(es8328->clk);
797 dev_err(component->dev, "unable to prepare codec clk\n");
804 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
809 static void es8328_remove(struct snd_soc_component *component)
811 struct es8328_priv *es8328;
813 es8328 = snd_soc_component_get_drvdata(component);
816 clk_disable_unprepare(es8328->clk);
818 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),
822 const struct regmap_config es8328_regmap_config = {
825 .max_register = ES8328_REG_MAX,
826 .cache_type = REGCACHE_RBTREE,
827 .use_single_read = true,
828 .use_single_write = true,
830 EXPORT_SYMBOL_GPL(es8328_regmap_config);
832 static const struct snd_soc_component_driver es8328_component_driver = {
833 .probe = es8328_component_probe,
834 .remove = es8328_remove,
835 .suspend = es8328_suspend,
836 .resume = es8328_resume,
837 .set_bias_level = es8328_set_bias_level,
838 .controls = es8328_snd_controls,
839 .num_controls = ARRAY_SIZE(es8328_snd_controls),
840 .dapm_widgets = es8328_dapm_widgets,
841 .num_dapm_widgets = ARRAY_SIZE(es8328_dapm_widgets),
842 .dapm_routes = es8328_dapm_routes,
843 .num_dapm_routes = ARRAY_SIZE(es8328_dapm_routes),
844 .suspend_bias_off = 1,
846 .use_pmdown_time = 1,
848 .non_legacy_dai_naming = 1,
851 int es8328_probe(struct device *dev, struct regmap *regmap)
853 struct es8328_priv *es8328;
858 return PTR_ERR(regmap);
860 es8328 = devm_kzalloc(dev, sizeof(*es8328), GFP_KERNEL);
864 es8328->regmap = regmap;
866 for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++)
867 es8328->supplies[i].supply = supply_names[i];
869 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies),
872 dev_err(dev, "unable to get regulators\n");
876 dev_set_drvdata(dev, es8328);
878 return devm_snd_soc_register_component(dev,
879 &es8328_component_driver, &es8328_dai, 1);
881 EXPORT_SYMBOL_GPL(es8328_probe);
883 MODULE_DESCRIPTION("ASoC ES8328 driver");
884 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
885 MODULE_LICENSE("GPL");