sound/soc/codecs/cs43130.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs43130.c  --  CS43130 ALSA Soc Audio driver
   4  *
   5  * Copyright 2017 Cirrus Logic, Inc.
   6  *
   7  * Authors: Li Xu <li.xu@cirrus.com>
   8  */
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/delay.h>
  14 #include <linux/gpio.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm.h>
  18 #include <linux/i2c.h>
  19 #include <linux/of_device.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <linux/of_gpio.h>
  30 #include <linux/regulator/consumer.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/completion.h>
  34 #include <linux/mutex.h>
  35 #include <linux/workqueue.h>
  36 #include <sound/jack.h>
  37
  38 #include "cs43130.h"
  39
  40 static const struct reg_default cs43130_reg_defaults[] = {
  41         {CS43130_SYS_CLK_CTL_1, 0x06},
  42         {CS43130_SP_SRATE, 0x01},
  43         {CS43130_SP_BITSIZE, 0x05},
  44         {CS43130_PAD_INT_CFG, 0x03},
  45         {CS43130_PWDN_CTL, 0xFE},
  46         {CS43130_CRYSTAL_SET, 0x04},
  47         {CS43130_PLL_SET_1, 0x00},
  48         {CS43130_PLL_SET_2, 0x00},
  49         {CS43130_PLL_SET_3, 0x00},
  50         {CS43130_PLL_SET_4, 0x00},
  51         {CS43130_PLL_SET_5, 0x40},
  52         {CS43130_PLL_SET_6, 0x10},
  53         {CS43130_PLL_SET_7, 0x80},
  54         {CS43130_PLL_SET_8, 0x03},
  55         {CS43130_PLL_SET_9, 0x02},
  56         {CS43130_PLL_SET_10, 0x02},
  57         {CS43130_CLKOUT_CTL, 0x00},
  58         {CS43130_ASP_NUM_1, 0x01},
  59         {CS43130_ASP_NUM_2, 0x00},
  60         {CS43130_ASP_DEN_1, 0x08},
  61         {CS43130_ASP_DEN_2, 0x00},
  62         {CS43130_ASP_LRCK_HI_TIME_1, 0x1F},
  63         {CS43130_ASP_LRCK_HI_TIME_2, 0x00},
  64         {CS43130_ASP_LRCK_PERIOD_1, 0x3F},
  65         {CS43130_ASP_LRCK_PERIOD_2, 0x00},
  66         {CS43130_ASP_CLOCK_CONF, 0x0C},
  67         {CS43130_ASP_FRAME_CONF, 0x0A},
  68         {CS43130_XSP_NUM_1, 0x01},
  69         {CS43130_XSP_NUM_2, 0x00},
  70         {CS43130_XSP_DEN_1, 0x02},
  71         {CS43130_XSP_DEN_2, 0x00},
  72         {CS43130_XSP_LRCK_HI_TIME_1, 0x1F},
  73         {CS43130_XSP_LRCK_HI_TIME_2, 0x00},
  74         {CS43130_XSP_LRCK_PERIOD_1, 0x3F},
  75         {CS43130_XSP_LRCK_PERIOD_2, 0x00},
  76         {CS43130_XSP_CLOCK_CONF, 0x0C},
  77         {CS43130_XSP_FRAME_CONF, 0x0A},
  78         {CS43130_ASP_CH_1_LOC, 0x00},
  79         {CS43130_ASP_CH_2_LOC, 0x00},
  80         {CS43130_ASP_CH_1_SZ_EN, 0x06},
  81         {CS43130_ASP_CH_2_SZ_EN, 0x0E},
  82         {CS43130_XSP_CH_1_LOC, 0x00},
  83         {CS43130_XSP_CH_2_LOC, 0x00},
  84         {CS43130_XSP_CH_1_SZ_EN, 0x06},
  85         {CS43130_XSP_CH_2_SZ_EN, 0x0E},
  86         {CS43130_DSD_VOL_B, 0x78},
  87         {CS43130_DSD_VOL_A, 0x78},
  88         {CS43130_DSD_PATH_CTL_1, 0xA8},
  89         {CS43130_DSD_INT_CFG, 0x00},
  90         {CS43130_DSD_PATH_CTL_2, 0x02},
  91         {CS43130_DSD_PCM_MIX_CTL, 0x00},
  92         {CS43130_DSD_PATH_CTL_3, 0x40},
  93         {CS43130_HP_OUT_CTL_1, 0x30},
  94         {CS43130_PCM_FILT_OPT, 0x02},
  95         {CS43130_PCM_VOL_B, 0x78},
  96         {CS43130_PCM_VOL_A, 0x78},
  97         {CS43130_PCM_PATH_CTL_1, 0xA8},
  98         {CS43130_PCM_PATH_CTL_2, 0x00},
  99         {CS43130_CLASS_H_CTL, 0x1E},
 100         {CS43130_HP_DETECT, 0x04},
 101         {CS43130_HP_LOAD_1, 0x00},
 102         {CS43130_HP_MEAS_LOAD_1, 0x00},
 103         {CS43130_HP_MEAS_LOAD_2, 0x00},
 104         {CS43130_INT_MASK_1, 0xFF},
 105         {CS43130_INT_MASK_2, 0xFF},
 106         {CS43130_INT_MASK_3, 0xFF},
 107         {CS43130_INT_MASK_4, 0xFF},
 108         {CS43130_INT_MASK_5, 0xFF},
 109 };
 110
 111 static bool cs43130_volatile_register(struct device *dev, unsigned int reg)
 112 {
 113         switch (reg) {
 114         case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
 115         case CS43130_HP_DC_STAT_1 ... CS43130_HP_DC_STAT_2:
 116         case CS43130_HP_AC_STAT_1 ... CS43130_HP_AC_STAT_2:
 117                 return true;
 118         default:
 119                 return false;
 120         }
 121 }
 122
 123 static bool cs43130_readable_register(struct device *dev, unsigned int reg)
 124 {
 125         switch (reg) {
 126         case CS43130_DEVID_AB ... CS43130_SYS_CLK_CTL_1:
 127         case CS43130_SP_SRATE ... CS43130_PAD_INT_CFG:
 128         case CS43130_PWDN_CTL:
 129         case CS43130_CRYSTAL_SET:
 130         case CS43130_PLL_SET_1 ... CS43130_PLL_SET_5:
 131         case CS43130_PLL_SET_6:
 132         case CS43130_PLL_SET_7:
 133         case CS43130_PLL_SET_8:
 134         case CS43130_PLL_SET_9:
 135         case CS43130_PLL_SET_10:
 136         case CS43130_CLKOUT_CTL:
 137         case CS43130_ASP_NUM_1 ... CS43130_ASP_FRAME_CONF:
 138         case CS43130_XSP_NUM_1 ... CS43130_XSP_FRAME_CONF:
 139         case CS43130_ASP_CH_1_LOC:
 140         case CS43130_ASP_CH_2_LOC:
 141         case CS43130_ASP_CH_1_SZ_EN:
 142         case CS43130_ASP_CH_2_SZ_EN:
 143         case CS43130_XSP_CH_1_LOC:
 144         case CS43130_XSP_CH_2_LOC:
 145         case CS43130_XSP_CH_1_SZ_EN:
 146         case CS43130_XSP_CH_2_SZ_EN:
 147         case CS43130_DSD_VOL_B ... CS43130_DSD_PATH_CTL_3:
 148         case CS43130_HP_OUT_CTL_1:
 149         case CS43130_PCM_FILT_OPT ... CS43130_PCM_PATH_CTL_2:
 150         case CS43130_CLASS_H_CTL:
 151         case CS43130_HP_DETECT:
 152         case CS43130_HP_STATUS:
 153         case CS43130_HP_LOAD_1:
 154         case CS43130_HP_MEAS_LOAD_1:
 155         case CS43130_HP_MEAS_LOAD_2:
 156         case CS43130_HP_DC_STAT_1:
 157         case CS43130_HP_DC_STAT_2:
 158         case CS43130_HP_AC_STAT_1:
 159         case CS43130_HP_AC_STAT_2:
 160         case CS43130_HP_LOAD_STAT:
 161         case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
 162         case CS43130_INT_MASK_1 ... CS43130_INT_MASK_5:
 163                 return true;
 164         default:
 165                 return false;
 166         }
 167 }
 168
 169 static bool cs43130_precious_register(struct device *dev, unsigned int reg)
 170 {
 171         switch (reg) {
 172         case CS43130_INT_STATUS_1 ... CS43130_INT_STATUS_5:
 173                 return true;
 174         default:
 175                 return false;
 176         }
 177 }
 178
 179 struct cs43130_pll_params {
 180         unsigned int pll_in;
 181         u8 sclk_prediv;
 182         u8 pll_div_int;
 183         u32 pll_div_frac;
 184         u8 pll_mode;
 185         u8 pll_divout;
 186         unsigned int pll_out;
 187         u8 pll_cal_ratio;
 188 };
 189
 190 static const struct cs43130_pll_params pll_ratio_table[] = {
 191         {9600000, 0x02, 0x49, 0x800000, 0x00, 0x08, 22579200, 151},
 192         {9600000, 0x02, 0x50, 0x000000, 0x00, 0x08, 24576000, 164},
 193
 194         {11289600, 0x02, 0X40, 0, 0x01, 0x08, 22579200, 128},
 195         {11289600, 0x02, 0x44, 0x06F700, 0x0, 0x08, 24576000, 139},
 196
 197         {12000000, 0x02, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120},
 198         {12000000, 0x02, 0x40, 0x000000, 0x00, 0x08, 24576000, 131},
 199
 200         {12288000, 0x02, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118},
 201         {12288000, 0x02, 0x40, 0x000000, 0x01, 0x08, 24576000, 128},
 202
 203         {13000000, 0x02, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111},
 204         {13000000, 0x02, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121},
 205
 206         {19200000, 0x03, 0x49, 0x800000, 0x00, 0x08, 22579200, 151},
 207         {19200000, 0x03, 0x50, 0x000000, 0x00, 0x08, 24576000, 164},
 208
 209         {22579200, 0, 0, 0, 0, 0, 22579200, 0},
 210         {22579200, 0x03, 0x44, 0x06F700, 0x00, 0x08, 24576000, 139},
 211
 212         {24000000, 0x03, 0x49, 0x800000, 0x00, 0x0A, 22579200, 120},
 213         {24000000, 0x03, 0x40, 0x000000, 0x00, 0x08, 24576000, 131},
 214
 215         {24576000, 0x03, 0x49, 0x800000, 0x01, 0x0A, 22579200, 118},
 216         {24576000, 0, 0, 0, 0, 0, 24576000, 0},
 217
 218         {26000000, 0x03, 0x45, 0x797680, 0x01, 0x0A, 22579200, 111},
 219         {26000000, 0x03, 0x3C, 0x7EA940, 0x01, 0x08, 24576000, 121},
 220 };
 221
 222 static const struct cs43130_pll_params *cs43130_get_pll_table(
 223                 unsigned int freq_in, unsigned int freq_out)
 224 {
 225         int i;
 226
 227         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 228                 if (pll_ratio_table[i].pll_in == freq_in &&
 229                     pll_ratio_table[i].pll_out == freq_out)
 230                         return &pll_ratio_table[i];
 231         }
 232
 233         return NULL;
 234 }
 235
 236 static int cs43130_pll_config(struct snd_soc_component *component)
 237 {
 238         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
 239         const struct cs43130_pll_params *pll_entry;
 240
 241         dev_dbg(component->dev, "cs43130->mclk = %u, cs43130->mclk_int = %u\n",
 242                 cs43130->mclk, cs43130->mclk_int);
 243
 244         pll_entry = cs43130_get_pll_table(cs43130->mclk, cs43130->mclk_int);
 245         if (!pll_entry)
 246                 return -EINVAL;
 247
 248         if (pll_entry->pll_cal_ratio == 0) {
 249                 regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
 250                                    CS43130_PLL_START_MASK, 0);
 251
 252                 cs43130->pll_bypass = true;
 253                 return 0;
 254         }
 255
 256         cs43130->pll_bypass = false;
 257
 258         regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_2,
 259                            CS43130_PLL_DIV_DATA_MASK,
 260                            pll_entry->pll_div_frac >>
 261                            CS43130_PLL_DIV_FRAC_0_DATA_SHIFT);
 262         regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_3,
 263                            CS43130_PLL_DIV_DATA_MASK,
 264                            pll_entry->pll_div_frac >>
 265                            CS43130_PLL_DIV_FRAC_1_DATA_SHIFT);
 266         regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_4,
 267                            CS43130_PLL_DIV_DATA_MASK,
 268                            pll_entry->pll_div_frac >>
 269                            CS43130_PLL_DIV_FRAC_2_DATA_SHIFT);
 270         regmap_write(cs43130->regmap, CS43130_PLL_SET_5,
 271                      pll_entry->pll_div_int);
 272         regmap_write(cs43130->regmap, CS43130_PLL_SET_6, pll_entry->pll_divout);
 273         regmap_write(cs43130->regmap, CS43130_PLL_SET_7,
 274                      pll_entry->pll_cal_ratio);
 275         regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_8,
 276                            CS43130_PLL_MODE_MASK,
 277                            pll_entry->pll_mode << CS43130_PLL_MODE_SHIFT);
 278         regmap_write(cs43130->regmap, CS43130_PLL_SET_9,
 279                      pll_entry->sclk_prediv);
 280         regmap_update_bits(cs43130->regmap, CS43130_PLL_SET_1,
 281                            CS43130_PLL_START_MASK, 1);
 282
 283         return 0;
 284 }
 285
 286 static int cs43130_set_pll(struct snd_soc_component *component, int pll_id, int source,
 287                            unsigned int freq_in, unsigned int freq_out)
 288 {
 289         int ret = 0;
 290         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
 291
 292         switch (freq_in) {
 293         case 9600000:
 294         case 11289600:
 295         case 12000000:
 296         case 12288000:
 297         case 13000000:
 298         case 19200000:
 299         case 22579200:
 300         case 24000000:
 301         case 24576000:
 302         case 26000000:
 303                 cs43130->mclk = freq_in;
 304                 break;
 305         default:
 306                 dev_err(component->dev,
 307                         "unsupported pll input reference clock:%d\n", freq_in);
 308                 return -EINVAL;
 309         }
 310
 311         switch (freq_out) {
 312         case 22579200:
 313                 cs43130->mclk_int = freq_out;
 314                 break;
 315         case 24576000:
 316                 cs43130->mclk_int = freq_out;
 317                 break;
 318         default:
 319                 dev_err(component->dev,
 320                         "unsupported pll output ref clock: %u\n", freq_out);
 321                 return -EINVAL;
 322         }
 323
 324         ret = cs43130_pll_config(component);
 325         dev_dbg(component->dev, "cs43130->pll_bypass = %d", cs43130->pll_bypass);
 326         return ret;
 327 }
 328
 329 static int cs43130_change_clksrc(struct snd_soc_component *component,
 330                                  enum cs43130_mclk_src_sel src)
 331 {
 332         int ret;
 333         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
 334         int mclk_int_decoded;
 335
 336         if (src == cs43130->mclk_int_src) {
 337                 /* clk source has not changed */
 338                 return 0;
 339         }
 340
 341         switch (cs43130->mclk_int) {
 342         case CS43130_MCLK_22M:
 343                 mclk_int_decoded = CS43130_MCLK_22P5;
 344                 break;
 345         case CS43130_MCLK_24M:
 346                 mclk_int_decoded = CS43130_MCLK_24P5;
 347                 break;
 348         default:
 349                 dev_err(component->dev, "Invalid MCLK INT freq: %u\n", cs43130->mclk_int);
 350                 return -EINVAL;
 351         }
 352
 353         switch (src) {
 354         case CS43130_MCLK_SRC_EXT:
 355                 cs43130->pll_bypass = true;
 356                 cs43130->mclk_int_src = CS43130_MCLK_SRC_EXT;
 357                 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
 358                         regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
 359                                            CS43130_PDN_XTAL_MASK,
 360                                            1 << CS43130_PDN_XTAL_SHIFT);
 361                 } else {
 362                         reinit_completion(&cs43130->xtal_rdy);
 363                         regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
 364                                            CS43130_XTAL_RDY_INT_MASK, 0);
 365                         regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
 366                                            CS43130_PDN_XTAL_MASK, 0);
 367                         ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
 368                                                           msecs_to_jiffies(100));
 369                         regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
 370                                            CS43130_XTAL_RDY_INT_MASK,
 371                                            1 << CS43130_XTAL_RDY_INT_SHIFT);
 372                         if (ret == 0) {
 373                                 dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n");
 374                                 return -ETIMEDOUT;
 375                         }
 376                 }
 377
 378                 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
 379                                    CS43130_MCLK_SRC_SEL_MASK,
 380                                    src << CS43130_MCLK_SRC_SEL_SHIFT);
 381                 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
 382                                    CS43130_MCLK_INT_MASK,
 383                                    mclk_int_decoded << CS43130_MCLK_INT_SHIFT);
 384                 usleep_range(150, 200);
 385
 386                 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
 387                                    CS43130_PDN_PLL_MASK,
 388                                    1 << CS43130_PDN_PLL_SHIFT);
 389                 break;
 390         case CS43130_MCLK_SRC_PLL:
 391                 cs43130->pll_bypass = false;
 392                 cs43130->mclk_int_src = CS43130_MCLK_SRC_PLL;
 393                 if (cs43130->xtal_ibias == CS43130_XTAL_UNUSED) {
 394                         regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
 395                                            CS43130_PDN_XTAL_MASK,
 396                                            1 << CS43130_PDN_XTAL_SHIFT);
 397                 } else {
 398                         reinit_completion(&cs43130->xtal_rdy);
 399                         regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
 400                                            CS43130_XTAL_RDY_INT_MASK, 0);
 401                         regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
 402                                            CS43130_PDN_XTAL_MASK, 0);
 403                         ret = wait_for_completion_timeout(&cs43130->xtal_rdy,
 404                                                           msecs_to_jiffies(100));
 405                         regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
 406                                            CS43130_XTAL_RDY_INT_MASK,
 407                                            1 << CS43130_XTAL_RDY_INT_SHIFT);
 408                         if (ret == 0) {
 409                                 dev_err(component->dev, "Timeout waiting for XTAL_READY interrupt\n");
 410                                 return -ETIMEDOUT;
 411                         }
 412                 }
 413
 414                 reinit_completion(&cs43130->pll_rdy);
 415                 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
 416                                    CS43130_PLL_RDY_INT_MASK, 0);
 417                 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
 418                                    CS43130_PDN_PLL_MASK, 0);
 419                 ret = wait_for_completion_timeout(&cs43130->pll_rdy,
 420                                                   msecs_to_jiffies(100));
 421                 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
 422                                    CS43130_PLL_RDY_INT_MASK,
 423                                    1 << CS43130_PLL_RDY_INT_SHIFT);
 424                 if (ret == 0) {
 425                         dev_err(component->dev, "Timeout waiting for PLL_READY interrupt\n");
 426                         return -ETIMEDOUT;
 427                 }
 428
 429                 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
 430                                    CS43130_MCLK_SRC_SEL_MASK,
 431                                    src << CS43130_MCLK_SRC_SEL_SHIFT);
 432                 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
 433                                    CS43130_MCLK_INT_MASK,
 434                                    mclk_int_decoded << CS43130_MCLK_INT_SHIFT);
 435                 usleep_range(150, 200);
 436                 break;
 437         case CS43130_MCLK_SRC_RCO:
 438                 cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;
 439
 440                 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
 441                                    CS43130_MCLK_SRC_SEL_MASK,
 442                                    src << CS43130_MCLK_SRC_SEL_SHIFT);
 443                 regmap_update_bits(cs43130->regmap, CS43130_SYS_CLK_CTL_1,
 444                                    CS43130_MCLK_INT_MASK,
 445                                    CS43130_MCLK_22P5 << CS43130_MCLK_INT_SHIFT);
 446                 usleep_range(150, 200);
 447
 448                 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
 449                                    CS43130_PDN_XTAL_MASK,
 450                                    1 << CS43130_PDN_XTAL_SHIFT);
 451                 regmap_update_bits(cs43130->regmap, CS43130_PWDN_CTL,
 452                                    CS43130_PDN_PLL_MASK,
 453                                    1 << CS43130_PDN_PLL_SHIFT);
 454                 break;
 455         default:
 456                 dev_err(component->dev, "Invalid MCLK source value\n");
 457                 return -EINVAL;
 458         }
 459
 460         return 0;
 461 }
 462
 463 static const struct cs43130_bitwidth_map cs43130_bitwidth_table[] = {
 464         {8,     CS43130_SP_BIT_SIZE_8,  CS43130_CH_BIT_SIZE_8},
 465         {16,    CS43130_SP_BIT_SIZE_16, CS43130_CH_BIT_SIZE_16},
 466         {24,    CS43130_SP_BIT_SIZE_24, CS43130_CH_BIT_SIZE_24},
 467         {32,    CS43130_SP_BIT_SIZE_32, CS43130_CH_BIT_SIZE_32},
 468 };
 469
 470 static const struct cs43130_bitwidth_map *cs43130_get_bitwidth_table(
 471                                 unsigned int bitwidth)
 472 {
 473         int i;
 474
 475         for (i = 0; i < ARRAY_SIZE(cs43130_bitwidth_table); i++) {
 476                 if (cs43130_bitwidth_table[i].bitwidth == bitwidth)
 477                         return &cs43130_bitwidth_table[i];
 478         }
 479
 480         return NULL;
 481 }
 482
 483 static int cs43130_set_bitwidth(int dai_id, unsigned int bitwidth_dai,
 484                           struct regmap *regmap)
 485 {
 486         const struct cs43130_bitwidth_map *bw_map;
 487
 488         bw_map = cs43130_get_bitwidth_table(bitwidth_dai);
 489         if (!bw_map)
 490                 return -EINVAL;
 491
 492         switch (dai_id) {
 493         case CS43130_ASP_PCM_DAI:
 494         case CS43130_ASP_DOP_DAI:
 495                 regmap_update_bits(regmap, CS43130_ASP_CH_1_SZ_EN,
 496                                    CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
 497                 regmap_update_bits(regmap, CS43130_ASP_CH_2_SZ_EN,
 498                                    CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
 499                 regmap_update_bits(regmap, CS43130_SP_BITSIZE,
 500                                    CS43130_ASP_BITSIZE_MASK, bw_map->sp_bit);
 501                 break;
 502         case CS43130_XSP_DOP_DAI:
 503                 regmap_update_bits(regmap, CS43130_XSP_CH_1_SZ_EN,
 504                                    CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
 505                 regmap_update_bits(regmap, CS43130_XSP_CH_2_SZ_EN,
 506                                    CS43130_CH_BITSIZE_MASK, bw_map->ch_bit);
 507                 regmap_update_bits(regmap, CS43130_SP_BITSIZE,
 508                                    CS43130_XSP_BITSIZE_MASK, bw_map->sp_bit <<
 509                                    CS43130_XSP_BITSIZE_SHIFT);
 510                 break;
 511         default:
 512                 return -EINVAL;
 513         }
 514
 515         return 0;
 516 }
 517
 518 static const struct cs43130_rate_map cs43130_rate_table[] = {
 519         {32000,         CS43130_ASP_SPRATE_32K},
 520         {44100,         CS43130_ASP_SPRATE_44_1K},
 521         {48000,         CS43130_ASP_SPRATE_48K},
 522         {88200,         CS43130_ASP_SPRATE_88_2K},
 523         {96000,         CS43130_ASP_SPRATE_96K},
 524         {176400,        CS43130_ASP_SPRATE_176_4K},
 525         {192000,        CS43130_ASP_SPRATE_192K},
 526         {352800,        CS43130_ASP_SPRATE_352_8K},
 527         {384000,        CS43130_ASP_SPRATE_384K},
 528 };
 529
 530 static const struct cs43130_rate_map *cs43130_get_rate_table(int fs)
 531 {
 532         int i;
 533
 534         for (i = 0; i < ARRAY_SIZE(cs43130_rate_table); i++) {
 535                 if (cs43130_rate_table[i].fs == fs)
 536                         return &cs43130_rate_table[i];
 537         }
 538
 539         return NULL;
 540 }
 541
 542 static const struct cs43130_clk_gen *cs43130_get_clk_gen(int mclk_int, int fs,
 543                 const struct cs43130_clk_gen *clk_gen_table, int len_clk_gen_table)
 544 {
 545         int i;
 546
 547         for (i = 0; i < len_clk_gen_table; i++) {
 548                 if (clk_gen_table[i].mclk_int == mclk_int &&
 549                     clk_gen_table[i].fs == fs)
 550                         return &clk_gen_table[i];
 551         }
 552
 553         return NULL;
 554 }
 555
 556 static int cs43130_set_sp_fmt(int dai_id, unsigned int bitwidth_sclk,
 557                               struct snd_pcm_hw_params *params,
 558                               struct cs43130_private *cs43130)
 559 {
 560         u16 frm_size;
 561         u16 hi_size;
 562         u8 frm_delay;
 563         u8 frm_phase;
 564         u8 frm_data;
 565         u8 sclk_edge;
 566         u8 lrck_edge;
 567         u8 clk_data;
 568         u8 loc_ch1;
 569         u8 loc_ch2;
 570         u8 dai_mode_val;
 571         const struct cs43130_clk_gen *clk_gen;
 572
 573         switch (cs43130->dais[dai_id].dai_format) {
 574         case SND_SOC_DAIFMT_I2S:
 575                 hi_size = bitwidth_sclk;
 576                 frm_delay = 2;
 577                 frm_phase = 0;
 578                 break;
 579         case SND_SOC_DAIFMT_LEFT_J:
 580                 hi_size = bitwidth_sclk;
 581                 frm_delay = 2;
 582                 frm_phase = 1;
 583                 break;
 584         case SND_SOC_DAIFMT_DSP_A:
 585                 hi_size = 1;
 586                 frm_delay = 2;
 587                 frm_phase = 1;
 588                 break;
 589         case SND_SOC_DAIFMT_DSP_B:
 590                 hi_size = 1;
 591                 frm_delay = 0;
 592                 frm_phase = 1;
 593                 break;
 594         default:
 595                 return -EINVAL;
 596         }
 597
 598         switch (cs43130->dais[dai_id].dai_mode) {
 599         case SND_SOC_DAIFMT_CBS_CFS:
 600                 dai_mode_val = 0;
 601                 break;
 602         case SND_SOC_DAIFMT_CBM_CFM:
 603                 dai_mode_val = 1;
 604                 break;
 605         default:
 606                 return -EINVAL;
 607         }
 608
 609         frm_size = bitwidth_sclk * params_channels(params);
 610         sclk_edge = 1;
 611         lrck_edge = 0;
 612         loc_ch1 = 0;
 613         loc_ch2 = bitwidth_sclk * (params_channels(params) - 1);
 614
 615         frm_data = frm_delay & CS43130_SP_FSD_MASK;
 616         frm_data |= (frm_phase << CS43130_SP_STP_SHIFT) & CS43130_SP_STP_MASK;
 617
 618         clk_data = lrck_edge & CS43130_SP_LCPOL_IN_MASK;
 619         clk_data |= (lrck_edge << CS43130_SP_LCPOL_OUT_SHIFT) &
 620                     CS43130_SP_LCPOL_OUT_MASK;
 621         clk_data |= (sclk_edge << CS43130_SP_SCPOL_IN_SHIFT) &
 622                     CS43130_SP_SCPOL_IN_MASK;
 623         clk_data |= (sclk_edge << CS43130_SP_SCPOL_OUT_SHIFT) &
 624                     CS43130_SP_SCPOL_OUT_MASK;
 625         clk_data |= (dai_mode_val << CS43130_SP_MODE_SHIFT) &
 626                     CS43130_SP_MODE_MASK;
 627
 628         switch (dai_id) {
 629         case CS43130_ASP_PCM_DAI:
 630         case CS43130_ASP_DOP_DAI:
 631                 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_1,
 632                         CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
 633                         CS43130_SP_LCPR_LSB_DATA_SHIFT);
 634                 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_PERIOD_2,
 635                         CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
 636                         CS43130_SP_LCPR_MSB_DATA_SHIFT);
 637                 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_1,
 638                         CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
 639                         CS43130_SP_LCHI_LSB_DATA_SHIFT);
 640                 regmap_update_bits(cs43130->regmap, CS43130_ASP_LRCK_HI_TIME_2,
 641                         CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
 642                         CS43130_SP_LCHI_MSB_DATA_SHIFT);
 643                 regmap_write(cs43130->regmap, CS43130_ASP_FRAME_CONF, frm_data);
 644                 regmap_write(cs43130->regmap, CS43130_ASP_CH_1_LOC, loc_ch1);
 645                 regmap_write(cs43130->regmap, CS43130_ASP_CH_2_LOC, loc_ch2);
 646                 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_1_SZ_EN,
 647                         CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
 648                 regmap_update_bits(cs43130->regmap, CS43130_ASP_CH_2_SZ_EN,
 649                         CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
 650                 regmap_write(cs43130->regmap, CS43130_ASP_CLOCK_CONF, clk_data);
 651                 break;
 652         case CS43130_XSP_DOP_DAI:
 653                 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_1,
 654                         CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
 655                         CS43130_SP_LCPR_LSB_DATA_SHIFT);
 656                 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_PERIOD_2,
 657                         CS43130_SP_LCPR_DATA_MASK, (frm_size - 1) >>
 658                         CS43130_SP_LCPR_MSB_DATA_SHIFT);
 659                 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_1,
 660                         CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
 661                         CS43130_SP_LCHI_LSB_DATA_SHIFT);
 662                 regmap_update_bits(cs43130->regmap, CS43130_XSP_LRCK_HI_TIME_2,
 663                         CS43130_SP_LCHI_DATA_MASK, (hi_size - 1) >>
 664                         CS43130_SP_LCHI_MSB_DATA_SHIFT);
 665                 regmap_write(cs43130->regmap, CS43130_XSP_FRAME_CONF, frm_data);
 666                 regmap_write(cs43130->regmap, CS43130_XSP_CH_1_LOC, loc_ch1);
 667                 regmap_write(cs43130->regmap, CS43130_XSP_CH_2_LOC, loc_ch2);
 668                 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_1_SZ_EN,
 669                         CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
 670                 regmap_update_bits(cs43130->regmap, CS43130_XSP_CH_2_SZ_EN,
 671                         CS43130_CH_EN_MASK, 1 << CS43130_CH_EN_SHIFT);
 672                 regmap_write(cs43130->regmap, CS43130_XSP_CLOCK_CONF, clk_data);
 673                 break;
 674         default:
 675                 return -EINVAL;
 676         }
 677
 678         switch (frm_size) {
 679         case 16:
 680                 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
 681                                               params_rate(params),
 682                                               cs43130_16_clk_gen,
 683                                               ARRAY_SIZE(cs43130_16_clk_gen));
 684                 break;
 685         case 32:
 686                 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
 687                                               params_rate(params),
 688                                               cs43130_32_clk_gen,
 689                                               ARRAY_SIZE(cs43130_32_clk_gen));
 690                 break;
 691         case 48:
 692                 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
 693                                               params_rate(params),
 694                                               cs43130_48_clk_gen,
 695                                               ARRAY_SIZE(cs43130_48_clk_gen));
 696                 break;
 697         case 64:
 698                 clk_gen = cs43130_get_clk_gen(cs43130->mclk_int,
 699                                               params_rate(params),
 700                                               cs43130_64_clk_gen,
 701                                               ARRAY_SIZE(cs43130_64_clk_gen));
 702                 break;
 703         default:
 704                 return -EINVAL;
 705         }
 706
 707         if (!clk_gen)
 708                 return -EINVAL;
 709
 710         switch (dai_id) {
 711         case CS43130_ASP_PCM_DAI:
 712         case CS43130_ASP_DOP_DAI:
 713                 regmap_write(cs43130->regmap, CS43130_ASP_DEN_1,
 714                              (clk_gen->den & CS43130_SP_M_LSB_DATA_MASK) >>
 715                              CS43130_SP_M_LSB_DATA_SHIFT);
 716                 regmap_write(cs43130->regmap, CS43130_ASP_DEN_2,
 717                              (clk_gen->den & CS43130_SP_M_MSB_DATA_MASK) >>
 718                              CS43130_SP_M_MSB_DATA_SHIFT);
 719                 regmap_write(cs43130->regmap, CS43130_ASP_NUM_1,
 720                              (clk_gen->num & CS43130_SP_N_LSB_DATA_MASK) >>
 721                              CS43130_SP_N_LSB_DATA_SHIFT);
 722                 regmap_write(cs43130->regmap, CS43130_ASP_NUM_2,
 723                              (clk_gen->num & CS43130_SP_N_MSB_DATA_MASK) >>
 724                              CS43130_SP_N_MSB_DATA_SHIFT);
 725                 break;
 726         case CS43130_XSP_DOP_DAI:
 727                 regmap_write(cs43130->regmap, CS43130_XSP_DEN_1,
 728                              (clk_gen->den & CS43130_SP_M_LSB_DATA_MASK) >>
 729                              CS43130_SP_M_LSB_DATA_SHIFT);
 730                 regmap_write(cs43130->regmap, CS43130_XSP_DEN_2,
 731                              (clk_gen->den & CS43130_SP_M_MSB_DATA_MASK) >>
 732                              CS43130_SP_M_MSB_DATA_SHIFT);
 733                 regmap_write(cs43130->regmap, CS43130_XSP_NUM_1,
 734                              (clk_gen->num & CS43130_SP_N_LSB_DATA_MASK) >>
 735                              CS43130_SP_N_LSB_DATA_SHIFT);
 736                 regmap_write(cs43130->regmap, CS43130_XSP_NUM_2,
 737                              (clk_gen->num & CS43130_SP_N_MSB_DATA_MASK) >>
 738                              CS43130_SP_N_MSB_DATA_SHIFT);
 739                 break;
 740         default:
 741                 return -EINVAL;
 742         }
 743
 744         return 0;
 745 }
 746
 747 static int cs43130_pcm_dsd_mix(bool en, struct regmap *regmap)
 748 {
 749         if (en) {
 750                 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
 751                                    CS43130_MIX_PCM_PREP_MASK,
 752                                    1 << CS43130_MIX_PCM_PREP_SHIFT);
 753                 usleep_range(6000, 6050);
 754                 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
 755                                    CS43130_MIX_PCM_DSD_MASK,
 756                                    1 << CS43130_MIX_PCM_DSD_SHIFT);
 757         } else {
 758                 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
 759                                    CS43130_MIX_PCM_DSD_MASK,
 760                                    0 << CS43130_MIX_PCM_DSD_SHIFT);
 761                 usleep_range(1600, 1650);
 762                 regmap_update_bits(regmap, CS43130_DSD_PCM_MIX_CTL,
 763                                    CS43130_MIX_PCM_PREP_MASK,
 764                                    0 << CS43130_MIX_PCM_PREP_SHIFT);
 765         }
 766
 767         return 0;
 768 }
 769
 770 static int cs43130_dsd_hw_params(struct snd_pcm_substream *substream,
 771                                  struct snd_pcm_hw_params *params,
 772                                  struct snd_soc_dai *dai)
 773 {
 774         struct snd_soc_component *component = dai->component;
 775         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
 776         unsigned int required_clk;
 777         u8 dsd_speed;
 778
 779         mutex_lock(&cs43130->clk_mutex);
 780         if (!cs43130->clk_req) {
 781                 /* no DAI is currently using clk */
 782                 if (!(CS43130_MCLK_22M % params_rate(params)))
 783                         required_clk = CS43130_MCLK_22M;
 784                 else
 785                         required_clk = CS43130_MCLK_24M;
 786
 787                 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
 788                 if (cs43130->pll_bypass)
 789                         cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);
 790                 else
 791                         cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);
 792         }
 793
 794         cs43130->clk_req++;
 795         if (cs43130->clk_req == 2)
 796                 cs43130_pcm_dsd_mix(true, cs43130->regmap);
 797         mutex_unlock(&cs43130->clk_mutex);
 798
 799         switch (params_rate(params)) {
 800         case 176400:
 801                 dsd_speed = 0;
 802                 break;
 803         case 352800:
 804                 dsd_speed = 1;
 805                 break;
 806         default:
 807                 dev_err(component->dev, "Rate(%u) not supported\n",
 808                         params_rate(params));
 809                 return -EINVAL;
 810         }
 811
 812         if (cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
 813                 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
 814                                    CS43130_DSD_MASTER, CS43130_DSD_MASTER);
 815         else
 816                 regmap_update_bits(cs43130->regmap, CS43130_DSD_INT_CFG,
 817                                    CS43130_DSD_MASTER, 0);
 818
 819         regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
 820                            CS43130_DSD_SPEED_MASK,
 821                            dsd_speed << CS43130_DSD_SPEED_SHIFT);
 822         regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
 823                            CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_DSD <<
 824                            CS43130_DSD_SRC_SHIFT);
 825
 826         return 0;
 827 }
 828
 829 static int cs43130_hw_params(struct snd_pcm_substream *substream,
 830                                  struct snd_pcm_hw_params *params,
 831                                  struct snd_soc_dai *dai)
 832 {
 833         struct snd_soc_component *component = dai->component;
 834         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
 835         const struct cs43130_rate_map *rate_map;
 836         unsigned int sclk = cs43130->dais[dai->id].sclk;
 837         unsigned int bitwidth_sclk;
 838         unsigned int bitwidth_dai = (unsigned int)(params_width(params));
 839         unsigned int required_clk;
 840         u8 dsd_speed;
 841
 842         mutex_lock(&cs43130->clk_mutex);
 843         if (!cs43130->clk_req) {
 844                 /* no DAI is currently using clk */
 845                 if (!(CS43130_MCLK_22M % params_rate(params)))
 846                         required_clk = CS43130_MCLK_22M;
 847                 else
 848                         required_clk = CS43130_MCLK_24M;
 849
 850                 cs43130_set_pll(component, 0, 0, cs43130->mclk, required_clk);
 851                 if (cs43130->pll_bypass)
 852                         cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);
 853                 else
 854                         cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);
 855         }
 856
 857         cs43130->clk_req++;
 858         if (cs43130->clk_req == 2)
 859                 cs43130_pcm_dsd_mix(true, cs43130->regmap);
 860         mutex_unlock(&cs43130->clk_mutex);
 861
 862         switch (dai->id) {
 863         case CS43130_ASP_DOP_DAI:
 864         case CS43130_XSP_DOP_DAI:
 865                 /* DoP bitwidth is always 24-bit */
 866                 bitwidth_dai = 24;
 867                 sclk = params_rate(params) * bitwidth_dai *
 868                        params_channels(params);
 869
 870                 switch (params_rate(params)) {
 871                 case 176400:
 872                         dsd_speed = 0;
 873                         break;
 874                 case 352800:
 875                         dsd_speed = 1;
 876                         break;
 877                 default:
 878                         dev_err(component->dev, "Rate(%u) not supported\n",
 879                                 params_rate(params));
 880                         return -EINVAL;
 881                 }
 882
 883                 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
 884                                    CS43130_DSD_SPEED_MASK,
 885                                    dsd_speed << CS43130_DSD_SPEED_SHIFT);
 886                 break;
 887         case CS43130_ASP_PCM_DAI:
 888                 rate_map = cs43130_get_rate_table(params_rate(params));
 889                 if (!rate_map)
 890                         return -EINVAL;
 891
 892                 regmap_write(cs43130->regmap, CS43130_SP_SRATE, rate_map->val);
 893                 break;
 894         default:
 895                 dev_err(component->dev, "Invalid DAI (%d)\n", dai->id);
 896                 return -EINVAL;
 897         }
 898
 899         switch (dai->id) {
 900         case CS43130_ASP_DOP_DAI:
 901                 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
 902                                    CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_ASP <<
 903                                    CS43130_DSD_SRC_SHIFT);
 904                 break;
 905         case CS43130_XSP_DOP_DAI:
 906                 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_2,
 907                                    CS43130_DSD_SRC_MASK, CS43130_DSD_SRC_XSP <<
 908                                    CS43130_DSD_SRC_SHIFT);
 909                 break;
 910         }
 911
 912         if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM)
 913                 /* Calculate SCLK in master mode if unassigned */
 914                 sclk = params_rate(params) * bitwidth_dai *
 915                        params_channels(params);
 916
 917         if (!sclk) {
 918                 /* at this point, SCLK must be set */
 919                 dev_err(component->dev, "SCLK freq is not set\n");
 920                 return -EINVAL;
 921         }
 922
 923         bitwidth_sclk = (sclk / params_rate(params)) / params_channels(params);
 924         if (bitwidth_sclk < bitwidth_dai) {
 925                 dev_err(component->dev, "Format not supported: SCLK freq is too low\n");
 926                 return -EINVAL;
 927         }
 928
 929         dev_dbg(component->dev,
 930                 "sclk = %u, fs = %d, bitwidth_dai = %u\n",
 931                 sclk, params_rate(params), bitwidth_dai);
 932
 933         dev_dbg(component->dev,
 934                 "bitwidth_sclk = %u, num_ch = %u\n",
 935                 bitwidth_sclk, params_channels(params));
 936
 937         cs43130_set_bitwidth(dai->id, bitwidth_dai, cs43130->regmap);
 938         cs43130_set_sp_fmt(dai->id, bitwidth_sclk, params, cs43130);
 939
 940         return 0;
 941 }
 942
 943 static int cs43130_hw_free(struct snd_pcm_substream *substream,
 944                            struct snd_soc_dai *dai)
 945 {
 946         struct snd_soc_component *component = dai->component;
 947         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
 948
 949         mutex_lock(&cs43130->clk_mutex);
 950         cs43130->clk_req--;
 951         if (!cs43130->clk_req) {
 952                 /* no DAI is currently using clk */
 953                 cs43130_change_clksrc(component, CS43130_MCLK_SRC_RCO);
 954                 cs43130_pcm_dsd_mix(false, cs43130->regmap);
 955         }
 956         mutex_unlock(&cs43130->clk_mutex);
 957
 958         return 0;
 959 }
 960
 961 static const DECLARE_TLV_DB_SCALE(pcm_vol_tlv, -12750, 50, 1);
 962
 963 static const char * const pcm_ch_text[] = {
 964         "Left-Right Ch",
 965         "Left-Left Ch",
 966         "Right-Left Ch",
 967         "Right-Right Ch",
 968 };
 969
 970 static const struct reg_sequence pcm_ch_en_seq[] = {
 971         {CS43130_DXD1, 0x99},
 972         {0x180005, 0x8C},
 973         {0x180007, 0xAB},
 974         {0x180015, 0x31},
 975         {0x180017, 0xB2},
 976         {0x180025, 0x30},
 977         {0x180027, 0x84},
 978         {0x180035, 0x9C},
 979         {0x180037, 0xAE},
 980         {0x18000D, 0x24},
 981         {0x18000F, 0xA3},
 982         {0x18001D, 0x05},
 983         {0x18001F, 0xD4},
 984         {0x18002D, 0x0B},
 985         {0x18002F, 0xC7},
 986         {0x18003D, 0x71},
 987         {0x18003F, 0xE7},
 988         {CS43130_DXD1, 0},
 989 };
 990
 991 static const struct reg_sequence pcm_ch_dis_seq[] = {
 992         {CS43130_DXD1, 0x99},
 993         {0x180005, 0x24},
 994         {0x180007, 0xA3},
 995         {0x180015, 0x05},
 996         {0x180017, 0xD4},
 997         {0x180025, 0x0B},
 998         {0x180027, 0xC7},
 999         {0x180035, 0x71},
1000         {0x180037, 0xE7},
1001         {0x18000D, 0x8C},
1002         {0x18000F, 0xAB},
1003         {0x18001D, 0x31},
1004         {0x18001F, 0xB2},
1005         {0x18002D, 0x30},
1006         {0x18002F, 0x84},
1007         {0x18003D, 0x9C},
1008         {0x18003F, 0xAE},
1009         {CS43130_DXD1, 0},
1010 };
1011
1012 static int cs43130_pcm_ch_get(struct snd_kcontrol *kcontrol,
1013                               struct snd_ctl_elem_value *ucontrol)
1014 {
1015         return snd_soc_get_enum_double(kcontrol, ucontrol);
1016 }
1017
1018 static int cs43130_pcm_ch_put(struct snd_kcontrol *kcontrol,
1019                               struct snd_ctl_elem_value *ucontrol)
1020 {
1021         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1022         unsigned int *item = ucontrol->value.enumerated.item;
1023         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1024         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1025         unsigned int val;
1026
1027         if (item[0] >= e->items)
1028                 return -EINVAL;
1029         val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
1030
1031         switch (cs43130->dev_id) {
1032         case CS43131_CHIP_ID:
1033         case CS43198_CHIP_ID:
1034                 if (val >= 2)
1035                         regmap_multi_reg_write(cs43130->regmap, pcm_ch_en_seq,
1036                                                ARRAY_SIZE(pcm_ch_en_seq));
1037                 else
1038                         regmap_multi_reg_write(cs43130->regmap, pcm_ch_dis_seq,
1039                                                ARRAY_SIZE(pcm_ch_dis_seq));
1040                 break;
1041         }
1042
1043         return snd_soc_put_enum_double(kcontrol, ucontrol);
1044 }
1045
1046 static SOC_ENUM_SINGLE_DECL(pcm_ch_enum, CS43130_PCM_PATH_CTL_2, 0,
1047                             pcm_ch_text);
1048
1049 static const char * const pcm_spd_texts[] = {
1050         "Fast",
1051         "Slow",
1052 };
1053
1054 static SOC_ENUM_SINGLE_DECL(pcm_spd_enum, CS43130_PCM_FILT_OPT, 7,
1055                             pcm_spd_texts);
1056
1057 static const char * const dsd_texts[] = {
1058         "Off",
1059         "BCKA Mode",
1060         "BCKD Mode",
1061 };
1062
1063 static const unsigned int dsd_values[] = {
1064         CS43130_DSD_SRC_DSD,
1065         CS43130_DSD_SRC_ASP,
1066         CS43130_DSD_SRC_XSP,
1067 };
1068
1069 static SOC_VALUE_ENUM_SINGLE_DECL(dsd_enum, CS43130_DSD_INT_CFG, 0, 0x03,
1070                                   dsd_texts, dsd_values);
1071
1072 static const struct snd_kcontrol_new cs43130_snd_controls[] = {
1073         SOC_DOUBLE_R_TLV("Master Playback Volume",
1074                          CS43130_PCM_VOL_A, CS43130_PCM_VOL_B, 0, 0xFF, 1,
1075                          pcm_vol_tlv),
1076         SOC_DOUBLE_R_TLV("Master DSD Playback Volume",
1077                          CS43130_DSD_VOL_A, CS43130_DSD_VOL_B, 0, 0xFF, 1,
1078                          pcm_vol_tlv),
1079         SOC_ENUM_EXT("PCM Ch Select", pcm_ch_enum, cs43130_pcm_ch_get,
1080                      cs43130_pcm_ch_put),
1081         SOC_ENUM("PCM Filter Speed", pcm_spd_enum),
1082         SOC_SINGLE("PCM Phase Compensation", CS43130_PCM_FILT_OPT, 6, 1, 0),
1083         SOC_SINGLE("PCM Nonoversample Emulate", CS43130_PCM_FILT_OPT, 5, 1, 0),
1084         SOC_SINGLE("PCM High-pass Filter", CS43130_PCM_FILT_OPT, 1, 1, 0),
1085         SOC_SINGLE("PCM De-emphasis Filter", CS43130_PCM_FILT_OPT, 0, 1, 0),
1086         SOC_ENUM("DSD Phase Modulation", dsd_enum),
1087 };
1088
1089 static const struct reg_sequence pcm_seq[] = {
1090         {CS43130_DXD1, 0x99},
1091         {CS43130_DXD7, 0x01},
1092         {CS43130_DXD8, 0},
1093         {CS43130_DXD9, 0x01},
1094         {CS43130_DXD3, 0x12},
1095         {CS43130_DXD4, 0},
1096         {CS43130_DXD10, 0x28},
1097         {CS43130_DXD11, 0x28},
1098         {CS43130_DXD1, 0},
1099 };
1100
1101 static const struct reg_sequence dsd_seq[] = {
1102         {CS43130_DXD1, 0x99},
1103         {CS43130_DXD7, 0x01},
1104         {CS43130_DXD8, 0},
1105         {CS43130_DXD9, 0x01},
1106         {CS43130_DXD3, 0x12},
1107         {CS43130_DXD4, 0},
1108         {CS43130_DXD10, 0x1E},
1109         {CS43130_DXD11, 0x20},
1110         {CS43130_DXD1, 0},
1111 };
1112
1113 static const struct reg_sequence pop_free_seq[] = {
1114         {CS43130_DXD1, 0x99},
1115         {CS43130_DXD12, 0x0A},
1116         {CS43130_DXD1, 0},
1117 };
1118
1119 static const struct reg_sequence pop_free_seq2[] = {
1120         {CS43130_DXD1, 0x99},
1121         {CS43130_DXD13, 0x20},
1122         {CS43130_DXD1, 0},
1123 };
1124
1125 static const struct reg_sequence mute_seq[] = {
1126         {CS43130_DXD1, 0x99},
1127         {CS43130_DXD3, 0x12},
1128         {CS43130_DXD5, 0x02},
1129         {CS43130_DXD4, 0x12},
1130         {CS43130_DXD1, 0},
1131 };
1132
1133 static const struct reg_sequence unmute_seq[] = {
1134         {CS43130_DXD1, 0x99},
1135         {CS43130_DXD3, 0x10},
1136         {CS43130_DXD5, 0},
1137         {CS43130_DXD4, 0x16},
1138         {CS43130_DXD1, 0},
1139 };
1140
1141 static int cs43130_dsd_event(struct snd_soc_dapm_widget *w,
1142                               struct snd_kcontrol *kcontrol, int event)
1143 {
1144         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1145         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1146
1147         switch (event) {
1148         case SND_SOC_DAPM_PRE_PMU:
1149                 switch (cs43130->dev_id) {
1150                 case CS43130_CHIP_ID:
1151                 case CS4399_CHIP_ID:
1152                         regmap_multi_reg_write(cs43130->regmap, dsd_seq,
1153                                                ARRAY_SIZE(dsd_seq));
1154                         break;
1155                 }
1156                 break;
1157         case SND_SOC_DAPM_POST_PMU:
1158                 regmap_update_bits(cs43130->regmap, CS43130_DSD_PATH_CTL_1,
1159                                    CS43130_MUTE_MASK, 0);
1160                 switch (cs43130->dev_id) {
1161                 case CS43130_CHIP_ID:
1162                 case CS4399_CHIP_ID:
1163                         regmap_multi_reg_write(cs43130->regmap, unmute_seq,
1164                                                ARRAY_SIZE(unmute_seq));
1165                         break;
1166                 }
1167                 break;
1168         case SND_SOC_DAPM_PRE_PMD:
1169                 switch (cs43130->dev_id) {
1170                 case CS43130_CHIP_ID:
1171                 case CS4399_CHIP_ID:
1172                         regmap_multi_reg_write(cs43130->regmap, mute_seq,
1173                                                ARRAY_SIZE(mute_seq));
1174                         regmap_update_bits(cs43130->regmap,
1175                                            CS43130_DSD_PATH_CTL_1,
1176                                            CS43130_MUTE_MASK, CS43130_MUTE_EN);
1177                         /*
1178                          * DSD Power Down Sequence
1179                          * According to Design, 130ms is preferred.
1180                          */
1181                         msleep(130);
1182                         break;
1183                 case CS43131_CHIP_ID:
1184                 case CS43198_CHIP_ID:
1185                         regmap_update_bits(cs43130->regmap,
1186                                            CS43130_DSD_PATH_CTL_1,
1187                                            CS43130_MUTE_MASK, CS43130_MUTE_EN);
1188                         break;
1189                 }
1190                 break;
1191         default:
1192                 dev_err(component->dev, "Invalid event = 0x%x\n", event);
1193                 return -EINVAL;
1194         }
1195         return 0;
1196 }
1197
1198 static int cs43130_pcm_event(struct snd_soc_dapm_widget *w,
1199                               struct snd_kcontrol *kcontrol, int event)
1200 {
1201         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1202         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1203
1204         switch (event) {
1205         case SND_SOC_DAPM_PRE_PMU:
1206                 switch (cs43130->dev_id) {
1207                 case CS43130_CHIP_ID:
1208                 case CS4399_CHIP_ID:
1209                         regmap_multi_reg_write(cs43130->regmap, pcm_seq,
1210                                                ARRAY_SIZE(pcm_seq));
1211                         break;
1212                 }
1213                 break;
1214         case SND_SOC_DAPM_POST_PMU:
1215                 regmap_update_bits(cs43130->regmap, CS43130_PCM_PATH_CTL_1,
1216                                    CS43130_MUTE_MASK, 0);
1217                 switch (cs43130->dev_id) {
1218                 case CS43130_CHIP_ID:
1219                 case CS4399_CHIP_ID:
1220                         regmap_multi_reg_write(cs43130->regmap, unmute_seq,
1221                                                ARRAY_SIZE(unmute_seq));
1222                         break;
1223                 }
1224                 break;
1225         case SND_SOC_DAPM_PRE_PMD:
1226                 switch (cs43130->dev_id) {
1227                 case CS43130_CHIP_ID:
1228                 case CS4399_CHIP_ID:
1229                         regmap_multi_reg_write(cs43130->regmap, mute_seq,
1230                                                ARRAY_SIZE(mute_seq));
1231                         regmap_update_bits(cs43130->regmap,
1232                                            CS43130_PCM_PATH_CTL_1,
1233                                            CS43130_MUTE_MASK, CS43130_MUTE_EN);
1234                         /*
1235                          * PCM Power Down Sequence
1236                          * According to Design, 130ms is preferred.
1237                          */
1238                         msleep(130);
1239                         break;
1240                 case CS43131_CHIP_ID:
1241                 case CS43198_CHIP_ID:
1242                         regmap_update_bits(cs43130->regmap,
1243                                            CS43130_PCM_PATH_CTL_1,
1244                                            CS43130_MUTE_MASK, CS43130_MUTE_EN);
1245                         break;
1246                 }
1247                 break;
1248         default:
1249                 dev_err(component->dev, "Invalid event = 0x%x\n", event);
1250                 return -EINVAL;
1251         }
1252         return 0;
1253 }
1254
1255 static const struct reg_sequence dac_postpmu_seq[] = {
1256         {CS43130_DXD9, 0x0C},
1257         {CS43130_DXD3, 0x10},
1258         {CS43130_DXD4, 0x20},
1259 };
1260
1261 static const struct reg_sequence dac_postpmd_seq[] = {
1262         {CS43130_DXD1, 0x99},
1263         {CS43130_DXD6, 0x01},
1264         {CS43130_DXD1, 0},
1265 };
1266
1267 static int cs43130_dac_event(struct snd_soc_dapm_widget *w,
1268                              struct snd_kcontrol *kcontrol, int event)
1269 {
1270         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1271         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1272
1273         switch (event) {
1274         case SND_SOC_DAPM_PRE_PMU:
1275                 switch (cs43130->dev_id) {
1276                 case CS43130_CHIP_ID:
1277                 case CS4399_CHIP_ID:
1278                         regmap_multi_reg_write(cs43130->regmap, pop_free_seq,
1279                                                ARRAY_SIZE(pop_free_seq));
1280                         break;
1281                 case CS43131_CHIP_ID:
1282                 case CS43198_CHIP_ID:
1283                         regmap_multi_reg_write(cs43130->regmap, pop_free_seq2,
1284                                                ARRAY_SIZE(pop_free_seq2));
1285                         break;
1286                 }
1287                 break;
1288         case SND_SOC_DAPM_POST_PMU:
1289                 usleep_range(10000, 10050);
1290
1291                 regmap_write(cs43130->regmap, CS43130_DXD1, 0x99);
1292
1293                 switch (cs43130->dev_id) {
1294                 case CS43130_CHIP_ID:
1295                 case CS4399_CHIP_ID:
1296                         regmap_multi_reg_write(cs43130->regmap, dac_postpmu_seq,
1297                                                ARRAY_SIZE(dac_postpmu_seq));
1298                         /*
1299                          * Per datasheet, Sec. PCM Power-Up Sequence.
1300                          * According to Design, CS43130_DXD12 must be 0 to meet
1301                          * THDN and Dynamic Range spec.
1302                          */
1303                         msleep(1000);
1304                         regmap_write(cs43130->regmap, CS43130_DXD12, 0);
1305                         break;
1306                 case CS43131_CHIP_ID:
1307                 case CS43198_CHIP_ID:
1308                         usleep_range(12000, 12010);
1309                         regmap_write(cs43130->regmap, CS43130_DXD13, 0);
1310                         break;
1311                 }
1312
1313                 regmap_write(cs43130->regmap, CS43130_DXD1, 0);
1314                 break;
1315         case SND_SOC_DAPM_POST_PMD:
1316                 switch (cs43130->dev_id) {
1317                 case CS43130_CHIP_ID:
1318                 case CS4399_CHIP_ID:
1319                         regmap_multi_reg_write(cs43130->regmap, dac_postpmd_seq,
1320                                                ARRAY_SIZE(dac_postpmd_seq));
1321                         break;
1322                 }
1323                 break;
1324         default:
1325                 dev_err(component->dev, "Invalid DAC event = 0x%x\n", event);
1326                 return -EINVAL;
1327         }
1328         return 0;
1329 }
1330
1331 static const struct reg_sequence hpin_prepmd_seq[] = {
1332         {CS43130_DXD1, 0x99},
1333         {CS43130_DXD15, 0x64},
1334         {CS43130_DXD14, 0},
1335         {CS43130_DXD2, 0},
1336         {CS43130_DXD1, 0},
1337 };
1338
1339 static const struct reg_sequence hpin_postpmu_seq[] = {
1340         {CS43130_DXD1, 0x99},
1341         {CS43130_DXD2, 1},
1342         {CS43130_DXD14, 0xDC},
1343         {CS43130_DXD15, 0xE4},
1344         {CS43130_DXD1, 0},
1345 };
1346
1347 static int cs43130_hpin_event(struct snd_soc_dapm_widget *w,
1348                               struct snd_kcontrol *kcontrol, int event)
1349 {
1350         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1351         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1352
1353         switch (event) {
1354         case SND_SOC_DAPM_POST_PMD:
1355                 regmap_multi_reg_write(cs43130->regmap, hpin_prepmd_seq,
1356                                        ARRAY_SIZE(hpin_prepmd_seq));
1357                 break;
1358         case SND_SOC_DAPM_PRE_PMU:
1359                 regmap_multi_reg_write(cs43130->regmap, hpin_postpmu_seq,
1360                                        ARRAY_SIZE(hpin_postpmu_seq));
1361                 break;
1362         default:
1363                 dev_err(component->dev, "Invalid HPIN event = 0x%x\n", event);
1364                 return -EINVAL;
1365         }
1366         return 0;
1367 }
1368
1369 static const struct snd_soc_dapm_widget digital_hp_widgets[] = {
1370         SND_SOC_DAPM_OUTPUT("HPOUTA"),
1371         SND_SOC_DAPM_OUTPUT("HPOUTB"),
1372
1373         SND_SOC_DAPM_AIF_IN_E("ASPIN PCM", NULL, 0, CS43130_PWDN_CTL,
1374                               CS43130_PDN_ASP_SHIFT, 1, cs43130_pcm_event,
1375                               (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1376                                SND_SOC_DAPM_PRE_PMD)),
1377
1378         SND_SOC_DAPM_AIF_IN_E("ASPIN DoP", NULL, 0, CS43130_PWDN_CTL,
1379                               CS43130_PDN_ASP_SHIFT, 1, cs43130_dsd_event,
1380                               (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1381                                SND_SOC_DAPM_PRE_PMD)),
1382
1383         SND_SOC_DAPM_AIF_IN_E("XSPIN DoP", NULL, 0, CS43130_PWDN_CTL,
1384                               CS43130_PDN_XSP_SHIFT, 1, cs43130_dsd_event,
1385                               (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1386                                SND_SOC_DAPM_PRE_PMD)),
1387
1388         SND_SOC_DAPM_AIF_IN_E("XSPIN DSD", NULL, 0, CS43130_PWDN_CTL,
1389                               CS43130_PDN_DSDIF_SHIFT, 1, cs43130_dsd_event,
1390                               (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1391                                SND_SOC_DAPM_PRE_PMD)),
1392
1393         SND_SOC_DAPM_DAC("DSD", NULL, CS43130_DSD_PATH_CTL_2,
1394                          CS43130_DSD_EN_SHIFT, 0),
1395
1396         SND_SOC_DAPM_DAC_E("HiFi DAC", NULL, CS43130_PWDN_CTL,
1397                            CS43130_PDN_HP_SHIFT, 1, cs43130_dac_event,
1398                            (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1399                             SND_SOC_DAPM_POST_PMD)),
1400 };
1401
1402 static const struct snd_soc_dapm_widget analog_hp_widgets[] = {
1403         SND_SOC_DAPM_DAC_E("Analog Playback", NULL, CS43130_HP_OUT_CTL_1,
1404                            CS43130_HP_IN_EN_SHIFT, 0, cs43130_hpin_event,
1405                            (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD)),
1406 };
1407
1408 static struct snd_soc_dapm_widget all_hp_widgets[
1409                         ARRAY_SIZE(digital_hp_widgets) +
1410                         ARRAY_SIZE(analog_hp_widgets)];
1411
1412 static const struct snd_soc_dapm_route digital_hp_routes[] = {
1413         {"ASPIN PCM", NULL, "ASP PCM Playback"},
1414         {"ASPIN DoP", NULL, "ASP DoP Playback"},
1415         {"XSPIN DoP", NULL, "XSP DoP Playback"},
1416         {"XSPIN DSD", NULL, "XSP DSD Playback"},
1417         {"DSD", NULL, "ASPIN DoP"},
1418         {"DSD", NULL, "XSPIN DoP"},
1419         {"DSD", NULL, "XSPIN DSD"},
1420         {"HiFi DAC", NULL, "ASPIN PCM"},
1421         {"HiFi DAC", NULL, "DSD"},
1422         {"HPOUTA", NULL, "HiFi DAC"},
1423         {"HPOUTB", NULL, "HiFi DAC"},
1424 };
1425
1426 static const struct snd_soc_dapm_route analog_hp_routes[] = {
1427         {"HPOUTA", NULL, "Analog Playback"},
1428         {"HPOUTB", NULL, "Analog Playback"},
1429 };
1430
1431 static struct snd_soc_dapm_route all_hp_routes[
1432                         ARRAY_SIZE(digital_hp_routes) +
1433                         ARRAY_SIZE(analog_hp_routes)];
1434
1435 static const unsigned int cs43130_asp_src_rates[] = {
1436         32000, 44100, 48000, 88200, 96000, 176400, 192000, 352800, 384000
1437 };
1438
1439 static const struct snd_pcm_hw_constraint_list cs43130_asp_constraints = {
1440         .count  = ARRAY_SIZE(cs43130_asp_src_rates),
1441         .list   = cs43130_asp_src_rates,
1442 };
1443
1444 static int cs43130_pcm_startup(struct snd_pcm_substream *substream,
1445                                struct snd_soc_dai *dai)
1446 {
1447         return snd_pcm_hw_constraint_list(substream->runtime, 0,
1448                                           SNDRV_PCM_HW_PARAM_RATE,
1449                                           &cs43130_asp_constraints);
1450 }
1451
1452 static const unsigned int cs43130_dop_src_rates[] = {
1453         176400, 352800,
1454 };
1455
1456 static const struct snd_pcm_hw_constraint_list cs43130_dop_constraints = {
1457         .count  = ARRAY_SIZE(cs43130_dop_src_rates),
1458         .list   = cs43130_dop_src_rates,
1459 };
1460
1461 static int cs43130_dop_startup(struct snd_pcm_substream *substream,
1462                                struct snd_soc_dai *dai)
1463 {
1464         return snd_pcm_hw_constraint_list(substream->runtime, 0,
1465                                           SNDRV_PCM_HW_PARAM_RATE,
1466                                           &cs43130_dop_constraints);
1467 }
1468
1469 static int cs43130_pcm_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1470 {
1471         struct snd_soc_component *component = codec_dai->component;
1472         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1473
1474         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1475         case SND_SOC_DAIFMT_CBS_CFS:
1476                 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS;
1477                 break;
1478         case SND_SOC_DAIFMT_CBM_CFM:
1479                 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM;
1480                 break;
1481         default:
1482                 dev_err(component->dev, "unsupported mode\n");
1483                 return -EINVAL;
1484         }
1485
1486         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1487         case SND_SOC_DAIFMT_I2S:
1488                 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_I2S;
1489                 break;
1490         case SND_SOC_DAIFMT_LEFT_J:
1491                 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_LEFT_J;
1492                 break;
1493         case SND_SOC_DAIFMT_DSP_A:
1494                 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_A;
1495                 break;
1496         case SND_SOC_DAIFMT_DSP_B:
1497                 cs43130->dais[codec_dai->id].dai_format = SND_SOC_DAIFMT_DSP_B;
1498                 break;
1499         default:
1500                 dev_err(component->dev,
1501                         "unsupported audio format\n");
1502                 return -EINVAL;
1503         }
1504
1505         dev_dbg(component->dev, "dai_id = %d,  dai_mode = %u, dai_format = %u\n",
1506                 codec_dai->id,
1507                 cs43130->dais[codec_dai->id].dai_mode,
1508                 cs43130->dais[codec_dai->id].dai_format);
1509
1510         return 0;
1511 }
1512
1513 static int cs43130_dsd_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1514 {
1515         struct snd_soc_component *component = codec_dai->component;
1516         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1517
1518         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1519         case SND_SOC_DAIFMT_CBS_CFS:
1520                 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBS_CFS;
1521                 break;
1522         case SND_SOC_DAIFMT_CBM_CFM:
1523                 cs43130->dais[codec_dai->id].dai_mode = SND_SOC_DAIFMT_CBM_CFM;
1524                 break;
1525         default:
1526                 dev_err(component->dev, "Unsupported DAI format.\n");
1527                 return -EINVAL;
1528         }
1529
1530         dev_dbg(component->dev, "dai_mode = 0x%x\n",
1531                 cs43130->dais[codec_dai->id].dai_mode);
1532
1533         return 0;
1534 }
1535
1536 static int cs43130_set_sysclk(struct snd_soc_dai *codec_dai,
1537                                   int clk_id, unsigned int freq, int dir)
1538 {
1539         struct snd_soc_component *component = codec_dai->component;
1540         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1541
1542         cs43130->dais[codec_dai->id].sclk = freq;
1543         dev_dbg(component->dev, "dai_id = %d,  sclk = %u\n", codec_dai->id,
1544                 cs43130->dais[codec_dai->id].sclk);
1545
1546         return 0;
1547 }
1548
1549 static const struct snd_soc_dai_ops cs43130_pcm_ops = {
1550         .startup        = cs43130_pcm_startup,
1551         .hw_params      = cs43130_hw_params,
1552         .hw_free        = cs43130_hw_free,
1553         .set_sysclk     = cs43130_set_sysclk,
1554         .set_fmt        = cs43130_pcm_set_fmt,
1555 };
1556
1557 static const struct snd_soc_dai_ops cs43130_dop_ops = {
1558         .startup        = cs43130_dop_startup,
1559         .hw_params      = cs43130_hw_params,
1560         .hw_free        = cs43130_hw_free,
1561         .set_sysclk     = cs43130_set_sysclk,
1562         .set_fmt        = cs43130_pcm_set_fmt,
1563 };
1564
1565 static const struct snd_soc_dai_ops cs43130_dsd_ops = {
1566         .startup        = cs43130_dop_startup,
1567         .hw_params      = cs43130_dsd_hw_params,
1568         .hw_free        = cs43130_hw_free,
1569         .set_fmt        = cs43130_dsd_set_fmt,
1570 };
1571
1572 static struct snd_soc_dai_driver cs43130_dai[] = {
1573         {
1574                 .name = "cs43130-asp-pcm",
1575                 .id = CS43130_ASP_PCM_DAI,
1576                 .playback = {
1577                         .stream_name = "ASP PCM Playback",
1578                         .channels_min = 1,
1579                         .channels_max = 2,
1580                         .rates = SNDRV_PCM_RATE_KNOT,
1581                         .formats = CS43130_PCM_FORMATS,
1582                 },
1583                 .ops = &cs43130_pcm_ops,
1584                 .symmetric_rate = 1,
1585         },
1586         {
1587                 .name = "cs43130-asp-dop",
1588                 .id = CS43130_ASP_DOP_DAI,
1589                 .playback = {
1590                         .stream_name = "ASP DoP Playback",
1591                         .channels_min = 1,
1592                         .channels_max = 2,
1593                         .rates = SNDRV_PCM_RATE_KNOT,
1594                         .formats = CS43130_DOP_FORMATS,
1595                 },
1596                 .ops = &cs43130_dop_ops,
1597                 .symmetric_rate = 1,
1598         },
1599         {
1600                 .name = "cs43130-xsp-dop",
1601                 .id = CS43130_XSP_DOP_DAI,
1602                 .playback = {
1603                         .stream_name = "XSP DoP Playback",
1604                         .channels_min = 1,
1605                         .channels_max = 2,
1606                         .rates = SNDRV_PCM_RATE_KNOT,
1607                         .formats = CS43130_DOP_FORMATS,
1608                 },
1609                 .ops = &cs43130_dop_ops,
1610                 .symmetric_rate = 1,
1611         },
1612         {
1613                 .name = "cs43130-xsp-dsd",
1614                 .id = CS43130_XSP_DSD_DAI,
1615                 .playback = {
1616                         .stream_name = "XSP DSD Playback",
1617                         .channels_min = 1,
1618                         .channels_max = 2,
1619                         .rates = SNDRV_PCM_RATE_KNOT,
1620                         .formats = CS43130_DOP_FORMATS,
1621                 },
1622                 .ops = &cs43130_dsd_ops,
1623         },
1624
1625 };
1626
1627 static int cs43130_component_set_sysclk(struct snd_soc_component *component,
1628                                     int clk_id, int source, unsigned int freq,
1629                                     int dir)
1630 {
1631         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
1632
1633         dev_dbg(component->dev, "clk_id = %d, source = %d, freq = %d, dir = %d\n",
1634                 clk_id, source, freq, dir);
1635
1636         switch (freq) {
1637         case CS43130_MCLK_22M:
1638         case CS43130_MCLK_24M:
1639                 cs43130->mclk = freq;
1640                 break;
1641         default:
1642                 dev_err(component->dev, "Invalid MCLK INT freq: %u\n", freq);
1643                 return -EINVAL;
1644         }
1645
1646         if (source == CS43130_MCLK_SRC_EXT) {
1647                 cs43130->pll_bypass = true;
1648         } else {
1649                 dev_err(component->dev, "Invalid MCLK source\n");
1650                 return -EINVAL;
1651         }
1652
1653         return 0;
1654 }
1655
1656 static inline u16 cs43130_get_ac_reg_val(u16 ac_freq)
1657 {
1658         /* AC freq is counted in 5.94Hz step. */
1659         return ac_freq / 6;
1660 }
1661
1662 static int cs43130_show_dc(struct device *dev, char *buf, u8 ch)
1663 {
1664         struct i2c_client *client = to_i2c_client(dev);
1665         struct cs43130_private *cs43130 = i2c_get_clientdata(client);
1666
1667         if (!cs43130->hpload_done)
1668                 return scnprintf(buf, PAGE_SIZE, "NO_HPLOAD\n");
1669         else
1670                 return scnprintf(buf, PAGE_SIZE, "%u\n",
1671                                  cs43130->hpload_dc[ch]);
1672 }
1673
1674 static ssize_t cs43130_show_dc_l(struct device *dev,
1675                                  struct device_attribute *attr, char *buf)
1676 {
1677         return cs43130_show_dc(dev, buf, HP_LEFT);
1678 }
1679
1680 static ssize_t cs43130_show_dc_r(struct device *dev,
1681                                  struct device_attribute *attr, char *buf)
1682 {
1683         return cs43130_show_dc(dev, buf, HP_RIGHT);
1684 }
1685
1686 static u16 const cs43130_ac_freq[CS43130_AC_FREQ] = {
1687         24,
1688         43,
1689         93,
1690         200,
1691         431,
1692         928,
1693         2000,
1694         4309,
1695         9283,
1696         20000,
1697 };
1698
1699 static int cs43130_show_ac(struct device *dev, char *buf, u8 ch)
1700 {
1701         int i, j = 0, tmp;
1702         struct i2c_client *client = to_i2c_client(dev);
1703         struct cs43130_private *cs43130 = i2c_get_clientdata(client);
1704
1705         if (cs43130->hpload_done && cs43130->ac_meas) {
1706                 for (i = 0; i < ARRAY_SIZE(cs43130_ac_freq); i++) {
1707                         tmp = scnprintf(buf + j, PAGE_SIZE - j, "%u\n",
1708                                         cs43130->hpload_ac[i][ch]);
1709                         if (!tmp)
1710                                 break;
1711
1712                         j += tmp;
1713                 }
1714
1715                 return j;
1716         } else {
1717                 return scnprintf(buf, PAGE_SIZE, "NO_HPLOAD\n");
1718         }
1719 }
1720
1721 static ssize_t cs43130_show_ac_l(struct device *dev,
1722                                  struct device_attribute *attr, char *buf)
1723 {
1724         return cs43130_show_ac(dev, buf, HP_LEFT);
1725 }
1726
1727 static ssize_t cs43130_show_ac_r(struct device *dev,
1728                                  struct device_attribute *attr, char *buf)
1729 {
1730         return cs43130_show_ac(dev, buf, HP_RIGHT);
1731 }
1732
1733 static DEVICE_ATTR(hpload_dc_l, 0444, cs43130_show_dc_l, NULL);
1734 static DEVICE_ATTR(hpload_dc_r, 0444, cs43130_show_dc_r, NULL);
1735 static DEVICE_ATTR(hpload_ac_l, 0444, cs43130_show_ac_l, NULL);
1736 static DEVICE_ATTR(hpload_ac_r, 0444, cs43130_show_ac_r, NULL);
1737
1738 static struct attribute *hpload_attrs[] = {
1739         &dev_attr_hpload_dc_l.attr,
1740         &dev_attr_hpload_dc_r.attr,
1741         &dev_attr_hpload_ac_l.attr,
1742         &dev_attr_hpload_ac_r.attr,
1743 };
1744 ATTRIBUTE_GROUPS(hpload);
1745
1746 static struct reg_sequence hp_en_cal_seq[] = {
1747         {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL},
1748         {CS43130_HP_MEAS_LOAD_1, 0},
1749         {CS43130_HP_MEAS_LOAD_2, 0},
1750         {CS43130_INT_MASK_4, 0},
1751         {CS43130_DXD1, 0x99},
1752         {CS43130_DXD16, 0xBB},
1753         {CS43130_DXD12, 0x01},
1754         {CS43130_DXD19, 0xCB},
1755         {CS43130_DXD17, 0x95},
1756         {CS43130_DXD18, 0x0B},
1757         {CS43130_DXD1, 0},
1758         {CS43130_HP_LOAD_1, 0x80},
1759 };
1760
1761 static struct reg_sequence hp_en_cal_seq2[] = {
1762         {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL},
1763         {CS43130_HP_MEAS_LOAD_1, 0},
1764         {CS43130_HP_MEAS_LOAD_2, 0},
1765         {CS43130_INT_MASK_4, 0},
1766         {CS43130_HP_LOAD_1, 0x80},
1767 };
1768
1769 static struct reg_sequence hp_dis_cal_seq[] = {
1770         {CS43130_HP_LOAD_1, 0x80},
1771         {CS43130_DXD1, 0x99},
1772         {CS43130_DXD12, 0},
1773         {CS43130_DXD1, 0},
1774         {CS43130_HP_LOAD_1, 0},
1775 };
1776
1777 static struct reg_sequence hp_dis_cal_seq2[] = {
1778         {CS43130_HP_LOAD_1, 0x80},
1779         {CS43130_HP_LOAD_1, 0},
1780 };
1781
1782 static struct reg_sequence hp_dc_ch_l_seq[] = {
1783         {CS43130_DXD1, 0x99},
1784         {CS43130_DXD19, 0x0A},
1785         {CS43130_DXD17, 0x93},
1786         {CS43130_DXD18, 0x0A},
1787         {CS43130_DXD1, 0},
1788         {CS43130_HP_LOAD_1, 0x80},
1789         {CS43130_HP_LOAD_1, 0x81},
1790 };
1791
1792 static struct reg_sequence hp_dc_ch_l_seq2[] = {
1793         {CS43130_HP_LOAD_1, 0x80},
1794         {CS43130_HP_LOAD_1, 0x81},
1795 };
1796
1797 static struct reg_sequence hp_dc_ch_r_seq[] = {
1798         {CS43130_DXD1, 0x99},
1799         {CS43130_DXD19, 0x8A},
1800         {CS43130_DXD17, 0x15},
1801         {CS43130_DXD18, 0x06},
1802         {CS43130_DXD1, 0},
1803         {CS43130_HP_LOAD_1, 0x90},
1804         {CS43130_HP_LOAD_1, 0x91},
1805 };
1806
1807 static struct reg_sequence hp_dc_ch_r_seq2[] = {
1808         {CS43130_HP_LOAD_1, 0x90},
1809         {CS43130_HP_LOAD_1, 0x91},
1810 };
1811
1812 static struct reg_sequence hp_ac_ch_l_seq[] = {
1813         {CS43130_DXD1, 0x99},
1814         {CS43130_DXD19, 0x0A},
1815         {CS43130_DXD17, 0x93},
1816         {CS43130_DXD18, 0x0A},
1817         {CS43130_DXD1, 0},
1818         {CS43130_HP_LOAD_1, 0x80},
1819         {CS43130_HP_LOAD_1, 0x82},
1820 };
1821
1822 static struct reg_sequence hp_ac_ch_l_seq2[] = {
1823         {CS43130_HP_LOAD_1, 0x80},
1824         {CS43130_HP_LOAD_1, 0x82},
1825 };
1826
1827 static struct reg_sequence hp_ac_ch_r_seq[] = {
1828         {CS43130_DXD1, 0x99},
1829         {CS43130_DXD19, 0x8A},
1830         {CS43130_DXD17, 0x15},
1831         {CS43130_DXD18, 0x06},
1832         {CS43130_DXD1, 0},
1833         {CS43130_HP_LOAD_1, 0x90},
1834         {CS43130_HP_LOAD_1, 0x92},
1835 };
1836
1837 static struct reg_sequence hp_ac_ch_r_seq2[] = {
1838         {CS43130_HP_LOAD_1, 0x90},
1839         {CS43130_HP_LOAD_1, 0x92},
1840 };
1841
1842 static struct reg_sequence hp_cln_seq[] = {
1843         {CS43130_INT_MASK_4, CS43130_INT_MASK_ALL},
1844         {CS43130_HP_MEAS_LOAD_1, 0},
1845         {CS43130_HP_MEAS_LOAD_2, 0},
1846 };
1847
1848 struct reg_sequences {
1849         struct reg_sequence     *seq;
1850         int                     size;
1851         unsigned int            msk;
1852 };
1853
1854 static struct reg_sequences hpload_seq1[] = {
1855         {
1856                 .seq    = hp_en_cal_seq,
1857                 .size   = ARRAY_SIZE(hp_en_cal_seq),
1858                 .msk    = CS43130_HPLOAD_ON_INT,
1859         },
1860         {
1861                 .seq    = hp_dc_ch_l_seq,
1862                 .size   = ARRAY_SIZE(hp_dc_ch_l_seq),
1863                 .msk    = CS43130_HPLOAD_DC_INT,
1864         },
1865         {
1866                 .seq    = hp_ac_ch_l_seq,
1867                 .size   = ARRAY_SIZE(hp_ac_ch_l_seq),
1868                 .msk    = CS43130_HPLOAD_AC_INT,
1869         },
1870         {
1871                 .seq    = hp_dis_cal_seq,
1872                 .size   = ARRAY_SIZE(hp_dis_cal_seq),
1873                 .msk    = CS43130_HPLOAD_OFF_INT,
1874         },
1875         {
1876                 .seq    = hp_en_cal_seq,
1877                 .size   = ARRAY_SIZE(hp_en_cal_seq),
1878                 .msk    = CS43130_HPLOAD_ON_INT,
1879         },
1880         {
1881                 .seq    = hp_dc_ch_r_seq,
1882                 .size   = ARRAY_SIZE(hp_dc_ch_r_seq),
1883                 .msk    = CS43130_HPLOAD_DC_INT,
1884         },
1885         {
1886                 .seq    = hp_ac_ch_r_seq,
1887                 .size   = ARRAY_SIZE(hp_ac_ch_r_seq),
1888                 .msk    = CS43130_HPLOAD_AC_INT,
1889         },
1890 };
1891
1892 static struct reg_sequences hpload_seq2[] = {
1893         {
1894                 .seq    = hp_en_cal_seq2,
1895                 .size   = ARRAY_SIZE(hp_en_cal_seq2),
1896                 .msk    = CS43130_HPLOAD_ON_INT,
1897         },
1898         {
1899                 .seq    = hp_dc_ch_l_seq2,
1900                 .size   = ARRAY_SIZE(hp_dc_ch_l_seq2),
1901                 .msk    = CS43130_HPLOAD_DC_INT,
1902         },
1903         {
1904                 .seq    = hp_ac_ch_l_seq2,
1905                 .size   = ARRAY_SIZE(hp_ac_ch_l_seq2),
1906                 .msk    = CS43130_HPLOAD_AC_INT,
1907         },
1908         {
1909                 .seq    = hp_dis_cal_seq2,
1910                 .size   = ARRAY_SIZE(hp_dis_cal_seq2),
1911                 .msk    = CS43130_HPLOAD_OFF_INT,
1912         },
1913         {
1914                 .seq    = hp_en_cal_seq2,
1915                 .size   = ARRAY_SIZE(hp_en_cal_seq2),
1916                 .msk    = CS43130_HPLOAD_ON_INT,
1917         },
1918         {
1919                 .seq    = hp_dc_ch_r_seq2,
1920                 .size   = ARRAY_SIZE(hp_dc_ch_r_seq2),
1921                 .msk    = CS43130_HPLOAD_DC_INT,
1922         },
1923         {
1924                 .seq    = hp_ac_ch_r_seq2,
1925                 .size   = ARRAY_SIZE(hp_ac_ch_r_seq2),
1926                 .msk    = CS43130_HPLOAD_AC_INT,
1927         },
1928 };
1929
1930 static int cs43130_update_hpload(unsigned int msk, int ac_idx,
1931                                  struct cs43130_private *cs43130)
1932 {
1933         bool left_ch = true;
1934         unsigned int reg;
1935         u32 addr;
1936         u16 impedance;
1937         struct snd_soc_component *component = cs43130->component;
1938
1939         switch (msk) {
1940         case CS43130_HPLOAD_DC_INT:
1941         case CS43130_HPLOAD_AC_INT:
1942                 break;
1943         default:
1944                 return 0;
1945         }
1946
1947         regmap_read(cs43130->regmap, CS43130_HP_LOAD_1, &reg);
1948         if (reg & CS43130_HPLOAD_CHN_SEL)
1949                 left_ch = false;
1950
1951         if (msk == CS43130_HPLOAD_DC_INT)
1952                 addr = CS43130_HP_DC_STAT_1;
1953         else
1954                 addr = CS43130_HP_AC_STAT_1;
1955
1956         regmap_read(cs43130->regmap, addr, &reg);
1957         impedance = reg >> 3;
1958         regmap_read(cs43130->regmap, addr + 1, &reg);
1959         impedance |= reg << 5;
1960
1961         if (msk == CS43130_HPLOAD_DC_INT) {
1962                 if (left_ch)
1963                         cs43130->hpload_dc[HP_LEFT] = impedance;
1964                 else
1965                         cs43130->hpload_dc[HP_RIGHT] = impedance;
1966
1967                 dev_dbg(component->dev, "HP DC impedance (Ch %u): %u\n", !left_ch,
1968                         impedance);
1969         } else {
1970                 if (left_ch)
1971                         cs43130->hpload_ac[ac_idx][HP_LEFT] = impedance;
1972                 else
1973                         cs43130->hpload_ac[ac_idx][HP_RIGHT] = impedance;
1974
1975                 dev_dbg(component->dev, "HP AC (%u Hz) impedance (Ch %u): %u\n",
1976                         cs43130->ac_freq[ac_idx], !left_ch, impedance);
1977         }
1978
1979         return 0;
1980 }
1981
1982 static int cs43130_hpload_proc(struct cs43130_private *cs43130,
1983                                struct reg_sequence *seq, int seq_size,
1984                                unsigned int rslt_msk, int ac_idx)
1985 {
1986         int ret;
1987         unsigned int msk;
1988         u16 ac_reg_val;
1989         struct snd_soc_component *component = cs43130->component;
1990
1991         reinit_completion(&cs43130->hpload_evt);
1992
1993         if (rslt_msk == CS43130_HPLOAD_AC_INT) {
1994                 ac_reg_val = cs43130_get_ac_reg_val(cs43130->ac_freq[ac_idx]);
1995                 regmap_update_bits(cs43130->regmap, CS43130_HP_LOAD_1,
1996                                    CS43130_HPLOAD_AC_START, 0);
1997                 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_1,
1998                                    CS43130_HP_MEAS_LOAD_MASK,
1999                                    ac_reg_val >> CS43130_HP_MEAS_LOAD_1_SHIFT);
2000                 regmap_update_bits(cs43130->regmap, CS43130_HP_MEAS_LOAD_2,
2001                                    CS43130_HP_MEAS_LOAD_MASK,
2002                                    ac_reg_val >> CS43130_HP_MEAS_LOAD_2_SHIFT);
2003         }
2004
2005         regmap_multi_reg_write(cs43130->regmap, seq,
2006                                seq_size);
2007
2008         ret = wait_for_completion_timeout(&cs43130->hpload_evt,
2009                                           msecs_to_jiffies(1000));
2010         regmap_read(cs43130->regmap, CS43130_INT_MASK_4, &msk);
2011         if (!ret) {
2012                 dev_err(component->dev, "Timeout waiting for HPLOAD interrupt\n");
2013                 return -1;
2014         }
2015
2016         dev_dbg(component->dev, "HP load stat: %x, INT_MASK_4: %x\n",
2017                 cs43130->hpload_stat, msk);
2018         if ((cs43130->hpload_stat & (CS43130_HPLOAD_NO_DC_INT |
2019                                      CS43130_HPLOAD_UNPLUG_INT |
2020                                      CS43130_HPLOAD_OOR_INT)) ||
2021             !(cs43130->hpload_stat & rslt_msk)) {
2022                 dev_dbg(component->dev, "HP load measure failed\n");
2023                 return -1;
2024         }
2025
2026         return 0;
2027 }
2028
2029 static const struct reg_sequence hv_seq[][2] = {
2030         {
2031                 {CS43130_CLASS_H_CTL, 0x1C},
2032                 {CS43130_HP_OUT_CTL_1, 0x10},
2033         },
2034         {
2035                 {CS43130_CLASS_H_CTL, 0x1E},
2036                 {CS43130_HP_OUT_CTL_1, 0x20},
2037         },
2038         {
2039                 {CS43130_CLASS_H_CTL, 0x1E},
2040                 {CS43130_HP_OUT_CTL_1, 0x30},
2041         },
2042 };
2043
2044 static int cs43130_set_hv(struct regmap *regmap, u16 hpload_dc,
2045                           const u16 *dc_threshold)
2046 {
2047         int i;
2048
2049         for (i = 0; i < CS43130_DC_THRESHOLD; i++) {
2050                 if (hpload_dc <= dc_threshold[i])
2051                         break;
2052         }
2053
2054         regmap_multi_reg_write(regmap, hv_seq[i], ARRAY_SIZE(hv_seq[i]));
2055
2056         return 0;
2057 }
2058
2059 static void cs43130_imp_meas(struct work_struct *wk)
2060 {
2061         unsigned int reg, seq_size;
2062         int i, ret, ac_idx;
2063         struct cs43130_private *cs43130;
2064         struct snd_soc_component *component;
2065         struct reg_sequences *hpload_seq;
2066
2067         cs43130 = container_of(wk, struct cs43130_private, work);
2068         component = cs43130->component;
2069
2070         if (!cs43130->mclk)
2071                 return;
2072
2073         cs43130->hpload_done = false;
2074
2075         mutex_lock(&cs43130->clk_mutex);
2076         if (!cs43130->clk_req) {
2077                 /* clk not in use */
2078                 cs43130_set_pll(component, 0, 0, cs43130->mclk, CS43130_MCLK_22M);
2079                 if (cs43130->pll_bypass)
2080                         cs43130_change_clksrc(component, CS43130_MCLK_SRC_EXT);
2081                 else
2082                         cs43130_change_clksrc(component, CS43130_MCLK_SRC_PLL);
2083         }
2084
2085         cs43130->clk_req++;
2086         mutex_unlock(&cs43130->clk_mutex);
2087
2088         regmap_read(cs43130->regmap, CS43130_INT_STATUS_4, &reg);
2089
2090         switch (cs43130->dev_id) {
2091         case CS43130_CHIP_ID:
2092                 hpload_seq = hpload_seq1;
2093                 seq_size = ARRAY_SIZE(hpload_seq1);
2094                 break;
2095         case CS43131_CHIP_ID:
2096                 hpload_seq = hpload_seq2;
2097                 seq_size = ARRAY_SIZE(hpload_seq2);
2098                 break;
2099         default:
2100                 WARN(1, "Invalid dev_id for meas: %d", cs43130->dev_id);
2101                 return;
2102         }
2103
2104         i = 0;
2105         ac_idx = 0;
2106         while (i < seq_size) {
2107                 ret = cs43130_hpload_proc(cs43130, hpload_seq[i].seq,
2108                                           hpload_seq[i].size,
2109                                           hpload_seq[i].msk, ac_idx);
2110                 if (ret < 0)
2111                         goto exit;
2112
2113                 cs43130_update_hpload(hpload_seq[i].msk, ac_idx, cs43130);
2114
2115                 if (cs43130->ac_meas &&
2116                     hpload_seq[i].msk == CS43130_HPLOAD_AC_INT &&
2117                     ac_idx < CS43130_AC_FREQ - 1) {
2118                         ac_idx++;
2119                 } else {
2120                         ac_idx = 0;
2121                         i++;
2122                 }
2123         }
2124         cs43130->hpload_done = true;
2125
2126         if (cs43130->hpload_dc[HP_LEFT] >= CS43130_LINEOUT_LOAD)
2127                 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_LINEOUT,
2128                                     CS43130_JACK_MASK);
2129         else
2130                 snd_soc_jack_report(&cs43130->jack, CS43130_JACK_HEADPHONE,
2131                                     CS43130_JACK_MASK);
2132
2133         dev_dbg(component->dev, "Set HP output control. DC threshold\n");
2134         for (i = 0; i < CS43130_DC_THRESHOLD; i++)
2135                 dev_dbg(component->dev, "DC threshold[%d]: %u.\n", i,
2136                         cs43130->dc_threshold[i]);
2137
2138         cs43130_set_hv(cs43130->regmap, cs43130->hpload_dc[HP_LEFT],
2139                        cs43130->dc_threshold);
2140
2141 exit:
2142         switch (cs43130->dev_id) {
2143         case CS43130_CHIP_ID:
2144                 cs43130_hpload_proc(cs43130, hp_dis_cal_seq,
2145                                     ARRAY_SIZE(hp_dis_cal_seq),
2146                                     CS43130_HPLOAD_OFF_INT, ac_idx);
2147                 break;
2148         case CS43131_CHIP_ID:
2149                 cs43130_hpload_proc(cs43130, hp_dis_cal_seq2,
2150                                     ARRAY_SIZE(hp_dis_cal_seq2),
2151                                     CS43130_HPLOAD_OFF_INT, ac_idx);
2152                 break;
2153         }
2154
2155         regmap_multi_reg_write(cs43130->regmap, hp_cln_seq,
2156                                ARRAY_SIZE(hp_cln_seq));
2157
2158         mutex_lock(&cs43130->clk_mutex);
2159         cs43130->clk_req--;
2160         /* clk not in use */
2161         if (!cs43130->clk_req)
2162                 cs43130_change_clksrc(component, CS43130_MCLK_SRC_RCO);
2163         mutex_unlock(&cs43130->clk_mutex);
2164 }
2165
2166 static irqreturn_t cs43130_irq_thread(int irq, void *data)
2167 {
2168         struct cs43130_private *cs43130 = (struct cs43130_private *)data;
2169         struct snd_soc_component *component = cs43130->component;
2170         unsigned int stickies[CS43130_NUM_INT];
2171         unsigned int irq_occurrence = 0;
2172         unsigned int masks[CS43130_NUM_INT];
2173         int i, j;
2174
2175         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
2176                 regmap_read(cs43130->regmap, CS43130_INT_STATUS_1 + i,
2177                             &stickies[i]);
2178                 regmap_read(cs43130->regmap, CS43130_INT_MASK_1 + i,
2179                             &masks[i]);
2180         }
2181
2182         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
2183                 stickies[i] = stickies[i] & (~masks[i]);
2184                 for (j = 0; j < 8; j++)
2185                         irq_occurrence += (stickies[i] >> j) & 1;
2186         }
2187         dev_dbg(component->dev, "number of interrupts occurred (%u)\n",
2188                 irq_occurrence);
2189
2190         if (!irq_occurrence)
2191                 return IRQ_NONE;
2192
2193         if (stickies[0] & CS43130_XTAL_RDY_INT) {
2194                 complete(&cs43130->xtal_rdy);
2195                 return IRQ_HANDLED;
2196         }
2197
2198         if (stickies[0] & CS43130_PLL_RDY_INT) {
2199                 complete(&cs43130->pll_rdy);
2200                 return IRQ_HANDLED;
2201         }
2202
2203         if (stickies[3] & CS43130_HPLOAD_NO_DC_INT) {
2204                 cs43130->hpload_stat = stickies[3];
2205                 dev_err(component->dev,
2206                         "DC load has not completed before AC load (%x)\n",
2207                         cs43130->hpload_stat);
2208                 complete(&cs43130->hpload_evt);
2209                 return IRQ_HANDLED;
2210         }
2211
2212         if (stickies[3] & CS43130_HPLOAD_UNPLUG_INT) {
2213                 cs43130->hpload_stat = stickies[3];
2214                 dev_err(component->dev, "HP unplugged during measurement (%x)\n",
2215                         cs43130->hpload_stat);
2216                 complete(&cs43130->hpload_evt);
2217                 return IRQ_HANDLED;
2218         }
2219
2220         if (stickies[3] & CS43130_HPLOAD_OOR_INT) {
2221                 cs43130->hpload_stat = stickies[3];
2222                 dev_err(component->dev, "HP load out of range (%x)\n",
2223                         cs43130->hpload_stat);
2224                 complete(&cs43130->hpload_evt);
2225                 return IRQ_HANDLED;
2226         }
2227
2228         if (stickies[3] & CS43130_HPLOAD_AC_INT) {
2229                 cs43130->hpload_stat = stickies[3];
2230                 dev_dbg(component->dev, "HP AC load measurement done (%x)\n",
2231                         cs43130->hpload_stat);
2232                 complete(&cs43130->hpload_evt);
2233                 return IRQ_HANDLED;
2234         }
2235
2236         if (stickies[3] & CS43130_HPLOAD_DC_INT) {
2237                 cs43130->hpload_stat = stickies[3];
2238                 dev_dbg(component->dev, "HP DC load measurement done (%x)\n",
2239                         cs43130->hpload_stat);
2240                 complete(&cs43130->hpload_evt);
2241                 return IRQ_HANDLED;
2242         }
2243
2244         if (stickies[3] & CS43130_HPLOAD_ON_INT) {
2245                 cs43130->hpload_stat = stickies[3];
2246                 dev_dbg(component->dev, "HP load state machine on done (%x)\n",
2247                         cs43130->hpload_stat);
2248                 complete(&cs43130->hpload_evt);
2249                 return IRQ_HANDLED;
2250         }
2251
2252         if (stickies[3] & CS43130_HPLOAD_OFF_INT) {
2253                 cs43130->hpload_stat = stickies[3];
2254                 dev_dbg(component->dev, "HP load state machine off done (%x)\n",
2255                         cs43130->hpload_stat);
2256                 complete(&cs43130->hpload_evt);
2257                 return IRQ_HANDLED;
2258         }
2259
2260         if (stickies[0] & CS43130_XTAL_ERR_INT) {
2261                 dev_err(component->dev, "Crystal err: clock is not running\n");
2262                 return IRQ_HANDLED;
2263         }
2264
2265         if (stickies[0] & CS43130_HP_UNPLUG_INT) {
2266                 dev_dbg(component->dev, "HP unplugged\n");
2267                 cs43130->hpload_done = false;
2268                 snd_soc_jack_report(&cs43130->jack, 0, CS43130_JACK_MASK);
2269                 return IRQ_HANDLED;
2270         }
2271
2272         if (stickies[0] & CS43130_HP_PLUG_INT) {
2273                 if (cs43130->dc_meas && !cs43130->hpload_done &&
2274                     !work_busy(&cs43130->work)) {
2275                         dev_dbg(component->dev, "HP load queue work\n");
2276                         queue_work(cs43130->wq, &cs43130->work);
2277                 }
2278
2279                 snd_soc_jack_report(&cs43130->jack, SND_JACK_MECHANICAL,
2280                                     CS43130_JACK_MASK);
2281                 return IRQ_HANDLED;
2282         }
2283
2284         return IRQ_NONE;
2285 }
2286
2287 static int cs43130_probe(struct snd_soc_component *component)
2288 {
2289         int ret;
2290         struct cs43130_private *cs43130 = snd_soc_component_get_drvdata(component);
2291         struct snd_soc_card *card = component->card;
2292         unsigned int reg;
2293
2294         cs43130->component = component;
2295
2296         if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED) {
2297                 regmap_update_bits(cs43130->regmap, CS43130_CRYSTAL_SET,
2298                                    CS43130_XTAL_IBIAS_MASK,
2299                                    cs43130->xtal_ibias);
2300                 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2301                                    CS43130_XTAL_ERR_INT, 0);
2302         }
2303
2304         ret = snd_soc_card_jack_new(card, "Headphone", CS43130_JACK_MASK,
2305                                     &cs43130->jack, NULL, 0);
2306         if (ret < 0) {
2307                 dev_err(component->dev, "Cannot create jack\n");
2308                 return ret;
2309         }
2310
2311         cs43130->hpload_done = false;
2312         if (cs43130->dc_meas) {
2313                 ret = sysfs_create_groups(&component->dev->kobj, hpload_groups);
2314                 if (ret)
2315                         return ret;
2316
2317                 cs43130->wq = create_singlethread_workqueue("cs43130_hp");
2318                 if (!cs43130->wq) {
2319                         sysfs_remove_groups(&component->dev->kobj, hpload_groups);
2320                         return -ENOMEM;
2321                 }
2322                 INIT_WORK(&cs43130->work, cs43130_imp_meas);
2323         }
2324
2325         regmap_read(cs43130->regmap, CS43130_INT_STATUS_1, &reg);
2326         regmap_read(cs43130->regmap, CS43130_HP_STATUS, &reg);
2327         regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2328                            CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT, 0);
2329         regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
2330                            CS43130_HP_DETECT_CTRL_MASK, 0);
2331         regmap_update_bits(cs43130->regmap, CS43130_HP_DETECT,
2332                            CS43130_HP_DETECT_CTRL_MASK,
2333                            CS43130_HP_DETECT_CTRL_MASK);
2334
2335         return 0;
2336 }
2337
2338 static struct snd_soc_component_driver soc_component_dev_cs43130 = {
2339         .probe                  = cs43130_probe,
2340         .controls               = cs43130_snd_controls,
2341         .num_controls           = ARRAY_SIZE(cs43130_snd_controls),
2342         .set_sysclk             = cs43130_component_set_sysclk,
2343         .set_pll                = cs43130_set_pll,
2344         .idle_bias_on           = 1,
2345         .use_pmdown_time        = 1,
2346         .endianness             = 1,
2347         .non_legacy_dai_naming  = 1,
2348 };
2349
2350 static const struct regmap_config cs43130_regmap = {
2351         .reg_bits               = 24,
2352         .pad_bits               = 8,
2353         .val_bits               = 8,
2354
2355         .max_register           = CS43130_LASTREG,
2356         .reg_defaults           = cs43130_reg_defaults,
2357         .num_reg_defaults       = ARRAY_SIZE(cs43130_reg_defaults),
2358         .readable_reg           = cs43130_readable_register,
2359         .precious_reg           = cs43130_precious_register,
2360         .volatile_reg           = cs43130_volatile_register,
2361         .cache_type             = REGCACHE_RBTREE,
2362         /* needed for regcache_sync */
2363         .use_single_read        = true,
2364         .use_single_write       = true,
2365 };
2366
2367 static u16 const cs43130_dc_threshold[CS43130_DC_THRESHOLD] = {
2368         50,
2369         120,
2370 };
2371
2372 static int cs43130_handle_device_data(struct i2c_client *i2c_client,
2373                                       struct cs43130_private *cs43130)
2374 {
2375         struct device_node *np = i2c_client->dev.of_node;
2376         unsigned int val;
2377         int i;
2378
2379         if (of_property_read_u32(np, "cirrus,xtal-ibias", &val) < 0) {
2380                 /* Crystal is unused. System clock is used for external MCLK */
2381                 cs43130->xtal_ibias = CS43130_XTAL_UNUSED;
2382                 return 0;
2383         }
2384
2385         switch (val) {
2386         case 1:
2387                 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_7_5UA;
2388                 break;
2389         case 2:
2390                 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_12_5UA;
2391                 break;
2392         case 3:
2393                 cs43130->xtal_ibias = CS43130_XTAL_IBIAS_15UA;
2394                 break;
2395         default:
2396                 dev_err(&i2c_client->dev,
2397                         "Invalid cirrus,xtal-ibias value: %d\n", val);
2398                 return -EINVAL;
2399         }
2400
2401         cs43130->dc_meas = of_property_read_bool(np, "cirrus,dc-measure");
2402         cs43130->ac_meas = of_property_read_bool(np, "cirrus,ac-measure");
2403
2404         if (of_property_read_u16_array(np, "cirrus,ac-freq", cs43130->ac_freq,
2405                                         CS43130_AC_FREQ) < 0) {
2406                 for (i = 0; i < CS43130_AC_FREQ; i++)
2407                         cs43130->ac_freq[i] = cs43130_ac_freq[i];
2408         }
2409
2410         if (of_property_read_u16_array(np, "cirrus,dc-threshold",
2411                                        cs43130->dc_threshold,
2412                                        CS43130_DC_THRESHOLD) < 0) {
2413                 for (i = 0; i < CS43130_DC_THRESHOLD; i++)
2414                         cs43130->dc_threshold[i] = cs43130_dc_threshold[i];
2415         }
2416
2417         return 0;
2418 }
2419
2420 static int cs43130_i2c_probe(struct i2c_client *client,
2421                              const struct i2c_device_id *id)
2422 {
2423         struct cs43130_private *cs43130;
2424         int ret;
2425         unsigned int devid = 0;
2426         unsigned int reg;
2427         int i;
2428
2429         cs43130 = devm_kzalloc(&client->dev, sizeof(*cs43130), GFP_KERNEL);
2430         if (!cs43130)
2431                 return -ENOMEM;
2432
2433         i2c_set_clientdata(client, cs43130);
2434
2435         cs43130->regmap = devm_regmap_init_i2c(client, &cs43130_regmap);
2436         if (IS_ERR(cs43130->regmap)) {
2437                 ret = PTR_ERR(cs43130->regmap);
2438                 return ret;
2439         }
2440
2441         if (client->dev.of_node) {
2442                 ret = cs43130_handle_device_data(client, cs43130);
2443                 if (ret != 0)
2444                         return ret;
2445         }
2446         for (i = 0; i < ARRAY_SIZE(cs43130->supplies); i++)
2447                 cs43130->supplies[i].supply = cs43130_supply_names[i];
2448
2449         ret = devm_regulator_bulk_get(&client->dev,
2450                                       ARRAY_SIZE(cs43130->supplies),
2451                                       cs43130->supplies);
2452         if (ret != 0) {
2453                 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
2454                 return ret;
2455         }
2456         ret = regulator_bulk_enable(ARRAY_SIZE(cs43130->supplies),
2457                                     cs43130->supplies);
2458         if (ret != 0) {
2459                 dev_err(&client->dev, "Failed to enable supplies: %d\n", ret);
2460                 return ret;
2461         }
2462
2463         cs43130->reset_gpio = devm_gpiod_get_optional(&client->dev,
2464                                                       "reset", GPIOD_OUT_LOW);
2465         if (IS_ERR(cs43130->reset_gpio))
2466                 return PTR_ERR(cs43130->reset_gpio);
2467
2468         gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
2469
2470         usleep_range(2000, 2050);
2471
2472         ret = regmap_read(cs43130->regmap, CS43130_DEVID_AB, &reg);
2473
2474         devid = (reg & 0xFF) << 12;
2475         ret = regmap_read(cs43130->regmap, CS43130_DEVID_CD, &reg);
2476         devid |= (reg & 0xFF) << 4;
2477         ret = regmap_read(cs43130->regmap, CS43130_DEVID_E, &reg);
2478         devid |= (reg & 0xF0) >> 4;
2479
2480         switch (devid) {
2481         case CS43130_CHIP_ID:
2482         case CS4399_CHIP_ID:
2483         case CS43131_CHIP_ID:
2484         case CS43198_CHIP_ID:
2485                 break;
2486         default:
2487                 dev_err(&client->dev,
2488                         "CS43130 Device ID %X. Expected ID %X, %X, %X or %X\n",
2489                         devid, CS43130_CHIP_ID, CS4399_CHIP_ID,
2490                         CS43131_CHIP_ID, CS43198_CHIP_ID);
2491                 ret = -ENODEV;
2492                 goto err;
2493         }
2494
2495         cs43130->dev_id = devid;
2496         ret = regmap_read(cs43130->regmap, CS43130_REV_ID, &reg);
2497         if (ret < 0) {
2498                 dev_err(&client->dev, "Get Revision ID failed\n");
2499                 goto err;
2500         }
2501
2502         dev_info(&client->dev,
2503                  "Cirrus Logic CS43130 (%x), Revision: %02X\n", devid,
2504                  reg & 0xFF);
2505
2506         mutex_init(&cs43130->clk_mutex);
2507
2508         init_completion(&cs43130->xtal_rdy);
2509         init_completion(&cs43130->pll_rdy);
2510         init_completion(&cs43130->hpload_evt);
2511
2512         ret = devm_request_threaded_irq(&client->dev, client->irq,
2513                                         NULL, cs43130_irq_thread,
2514                                         IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2515                                         "cs43130", cs43130);
2516         if (ret != 0) {
2517                 dev_err(&client->dev, "Failed to request IRQ: %d\n", ret);
2518                 return ret;
2519         }
2520
2521         cs43130->mclk_int_src = CS43130_MCLK_SRC_RCO;
2522
2523         pm_runtime_set_autosuspend_delay(&client->dev, 100);
2524         pm_runtime_use_autosuspend(&client->dev);
2525         pm_runtime_set_active(&client->dev);
2526         pm_runtime_enable(&client->dev);
2527
2528         switch (cs43130->dev_id) {
2529         case CS43130_CHIP_ID:
2530         case CS43131_CHIP_ID:
2531                 memcpy(all_hp_widgets, digital_hp_widgets,
2532                        sizeof(digital_hp_widgets));
2533                 memcpy(all_hp_widgets + ARRAY_SIZE(digital_hp_widgets),
2534                        analog_hp_widgets, sizeof(analog_hp_widgets));
2535                 memcpy(all_hp_routes, digital_hp_routes,
2536                        sizeof(digital_hp_routes));
2537                 memcpy(all_hp_routes + ARRAY_SIZE(digital_hp_routes),
2538                        analog_hp_routes, sizeof(analog_hp_routes));
2539
2540                 soc_component_dev_cs43130.dapm_widgets =
2541                         all_hp_widgets;
2542                 soc_component_dev_cs43130.num_dapm_widgets =
2543                         ARRAY_SIZE(all_hp_widgets);
2544                 soc_component_dev_cs43130.dapm_routes =
2545                         all_hp_routes;
2546                 soc_component_dev_cs43130.num_dapm_routes =
2547                         ARRAY_SIZE(all_hp_routes);
2548                 break;
2549         case CS43198_CHIP_ID:
2550         case CS4399_CHIP_ID:
2551                 soc_component_dev_cs43130.dapm_widgets =
2552                         digital_hp_widgets;
2553                 soc_component_dev_cs43130.num_dapm_widgets =
2554                         ARRAY_SIZE(digital_hp_widgets);
2555                 soc_component_dev_cs43130.dapm_routes =
2556                         digital_hp_routes;
2557                 soc_component_dev_cs43130.num_dapm_routes =
2558                         ARRAY_SIZE(digital_hp_routes);
2559                 break;
2560         }
2561
2562         ret = devm_snd_soc_register_component(&client->dev,
2563                                      &soc_component_dev_cs43130,
2564                                      cs43130_dai, ARRAY_SIZE(cs43130_dai));
2565         if (ret < 0) {
2566                 dev_err(&client->dev,
2567                         "snd_soc_register_component failed with ret = %d\n", ret);
2568                 goto err;
2569         }
2570
2571         regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
2572                            CS43130_ASP_3ST_MASK, 0);
2573         regmap_update_bits(cs43130->regmap, CS43130_PAD_INT_CFG,
2574                            CS43130_XSP_3ST_MASK, 0);
2575
2576         return 0;
2577 err:
2578         return ret;
2579 }
2580
2581 static int cs43130_i2c_remove(struct i2c_client *client)
2582 {
2583         struct cs43130_private *cs43130 = i2c_get_clientdata(client);
2584
2585         if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
2586                 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2587                                    CS43130_XTAL_ERR_INT,
2588                                    1 << CS43130_XTAL_ERR_INT_SHIFT);
2589
2590         regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2591                            CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT,
2592                            CS43130_HP_PLUG_INT | CS43130_HP_UNPLUG_INT);
2593
2594         if (cs43130->dc_meas) {
2595                 cancel_work_sync(&cs43130->work);
2596                 flush_workqueue(cs43130->wq);
2597
2598                 device_remove_file(&client->dev, &dev_attr_hpload_dc_l);
2599                 device_remove_file(&client->dev, &dev_attr_hpload_dc_r);
2600                 device_remove_file(&client->dev, &dev_attr_hpload_ac_l);
2601                 device_remove_file(&client->dev, &dev_attr_hpload_ac_r);
2602         }
2603
2604         gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
2605
2606         pm_runtime_disable(&client->dev);
2607         regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2608
2609         return 0;
2610 }
2611
2612 static int __maybe_unused cs43130_runtime_suspend(struct device *dev)
2613 {
2614         struct cs43130_private *cs43130 = dev_get_drvdata(dev);
2615
2616         if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
2617                 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2618                                    CS43130_XTAL_ERR_INT,
2619                                    1 << CS43130_XTAL_ERR_INT_SHIFT);
2620
2621         regcache_cache_only(cs43130->regmap, true);
2622         regcache_mark_dirty(cs43130->regmap);
2623
2624         gpiod_set_value_cansleep(cs43130->reset_gpio, 0);
2625
2626         regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2627
2628         return 0;
2629 }
2630
2631 static int __maybe_unused cs43130_runtime_resume(struct device *dev)
2632 {
2633         struct cs43130_private *cs43130 = dev_get_drvdata(dev);
2634         int ret;
2635
2636         ret = regulator_bulk_enable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2637         if (ret != 0) {
2638                 dev_err(dev, "Failed to enable supplies: %d\n", ret);
2639                 return ret;
2640         }
2641
2642         regcache_cache_only(cs43130->regmap, false);
2643
2644         gpiod_set_value_cansleep(cs43130->reset_gpio, 1);
2645
2646         usleep_range(2000, 2050);
2647
2648         ret = regcache_sync(cs43130->regmap);
2649         if (ret != 0) {
2650                 dev_err(dev, "Failed to restore register cache\n");
2651                 goto err;
2652         }
2653
2654         if (cs43130->xtal_ibias != CS43130_XTAL_UNUSED)
2655                 regmap_update_bits(cs43130->regmap, CS43130_INT_MASK_1,
2656                                    CS43130_XTAL_ERR_INT, 0);
2657
2658         return 0;
2659 err:
2660         regcache_cache_only(cs43130->regmap, true);
2661         regulator_bulk_disable(CS43130_NUM_SUPPLIES, cs43130->supplies);
2662
2663         return ret;
2664 }
2665
2666 static const struct dev_pm_ops cs43130_runtime_pm = {
2667         SET_RUNTIME_PM_OPS(cs43130_runtime_suspend, cs43130_runtime_resume,
2668                            NULL)
2669 };
2670
2671 static const struct of_device_id cs43130_of_match[] = {
2672         {.compatible = "cirrus,cs43130",},
2673         {.compatible = "cirrus,cs4399",},
2674         {.compatible = "cirrus,cs43131",},
2675         {.compatible = "cirrus,cs43198",},
2676         {},
2677 };
2678
2679 MODULE_DEVICE_TABLE(of, cs43130_of_match);
2680
2681 static const struct i2c_device_id cs43130_i2c_id[] = {
2682         {"cs43130", 0},
2683         {"cs4399", 0},
2684         {"cs43131", 0},
2685         {"cs43198", 0},
2686         {}
2687 };
2688
2689 MODULE_DEVICE_TABLE(i2c, cs43130_i2c_id);
2690
2691 static struct i2c_driver cs43130_i2c_driver = {
2692         .driver = {
2693                 .name           = "cs43130",
2694                 .of_match_table = cs43130_of_match,
2695                 .pm             = &cs43130_runtime_pm,
2696         },
2697         .id_table       = cs43130_i2c_id,
2698         .probe          = cs43130_i2c_probe,
2699         .remove         = cs43130_i2c_remove,
2700 };
2701
2702 module_i2c_driver(cs43130_i2c_driver);
2703
2704 MODULE_AUTHOR("Li Xu <li.xu@cirrus.com>");
2705 MODULE_DESCRIPTION("Cirrus Logic CS43130 ALSA SoC Codec Driver");
2706 MODULE_LICENSE("GPL");