1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * cs42l42.h -- CS42L42 ALSA SoC audio driver header
5 * Copyright 2016 Cirrus Logic, Inc.
7 * Author: James Schulman <james.schulman@cirrus.com>
8 * Author: Brian Austin <brian.austin@cirrus.com>
9 * Author: Michael White <michael.white@cirrus.com>
15 #include <linux/mutex.h>
16 #include <sound/jack.h>
18 #define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */
19 #define CS42L42_WIN_START 0x00
20 #define CS42L42_WIN_LEN 0x100
21 #define CS42L42_RANGE_MIN 0x00
22 #define CS42L42_RANGE_MAX 0x7F
24 #define CS42L42_PAGE_10 0x1000
25 #define CS42L42_PAGE_11 0x1100
26 #define CS42L42_PAGE_12 0x1200
27 #define CS42L42_PAGE_13 0x1300
28 #define CS42L42_PAGE_15 0x1500
29 #define CS42L42_PAGE_19 0x1900
30 #define CS42L42_PAGE_1B 0x1B00
31 #define CS42L42_PAGE_1C 0x1C00
32 #define CS42L42_PAGE_1D 0x1D00
33 #define CS42L42_PAGE_1F 0x1F00
34 #define CS42L42_PAGE_20 0x2000
35 #define CS42L42_PAGE_21 0x2100
36 #define CS42L42_PAGE_23 0x2300
37 #define CS42L42_PAGE_24 0x2400
38 #define CS42L42_PAGE_25 0x2500
39 #define CS42L42_PAGE_26 0x2600
40 #define CS42L42_PAGE_28 0x2800
41 #define CS42L42_PAGE_29 0x2900
42 #define CS42L42_PAGE_2A 0x2A00
43 #define CS42L42_PAGE_30 0x3000
45 #define CS42L42_CHIP_ID 0x42A42
47 /* Page 0x10 Global Registers */
48 #define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01)
49 #define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02)
50 #define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03)
51 #define CS42L42_FABID (CS42L42_PAGE_10 + 0x04)
52 #define CS42L42_REVID (CS42L42_PAGE_10 + 0x05)
53 #define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06)
55 #define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07)
56 #define CS42L42_SRC_BYPASS_DAC_SHIFT 1
57 #define CS42L42_SRC_BYPASS_DAC_MASK (1 << CS42L42_SRC_BYPASS_DAC_SHIFT)
59 #define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08)
61 #define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09)
62 #define CS42L42_INTERNAL_FS_SHIFT 1
63 #define CS42L42_INTERNAL_FS_MASK (1 << CS42L42_INTERNAL_FS_SHIFT)
65 #define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A)
66 #define CS42L42_SLOW_START_ENABLE (CS42L42_PAGE_10 + 0x0B)
67 #define CS42L42_SLOW_START_EN_MASK GENMASK(6, 4)
68 #define CS42L42_SLOW_START_EN_SHIFT 4
69 #define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E)
70 #define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F)
71 #define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10)
73 /* Page 0x11 Power and Headset Detect Registers */
74 #define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01)
75 #define CS42L42_ASP_DAO_PDN_SHIFT 7
76 #define CS42L42_ASP_DAO_PDN_MASK (1 << CS42L42_ASP_DAO_PDN_SHIFT)
77 #define CS42L42_ASP_DAI_PDN_SHIFT 6
78 #define CS42L42_ASP_DAI_PDN_MASK (1 << CS42L42_ASP_DAI_PDN_SHIFT)
79 #define CS42L42_MIXER_PDN_SHIFT 5
80 #define CS42L42_MIXER_PDN_MASK (1 << CS42L42_MIXER_PDN_SHIFT)
81 #define CS42L42_EQ_PDN_SHIFT 4
82 #define CS42L42_EQ_PDN_MASK (1 << CS42L42_EQ_PDN_SHIFT)
83 #define CS42L42_HP_PDN_SHIFT 3
84 #define CS42L42_HP_PDN_MASK (1 << CS42L42_HP_PDN_SHIFT)
85 #define CS42L42_ADC_PDN_SHIFT 2
86 #define CS42L42_ADC_PDN_MASK (1 << CS42L42_ADC_PDN_SHIFT)
87 #define CS42L42_PDN_ALL_SHIFT 0
88 #define CS42L42_PDN_ALL_MASK (1 << CS42L42_PDN_ALL_SHIFT)
90 #define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02)
91 #define CS42L42_ADC_SRC_PDNB_SHIFT 0
92 #define CS42L42_ADC_SRC_PDNB_MASK (1 << CS42L42_ADC_SRC_PDNB_SHIFT)
93 #define CS42L42_DAC_SRC_PDNB_SHIFT 1
94 #define CS42L42_DAC_SRC_PDNB_MASK (1 << CS42L42_DAC_SRC_PDNB_SHIFT)
95 #define CS42L42_ASP_DAI1_PDN_SHIFT 2
96 #define CS42L42_ASP_DAI1_PDN_MASK (1 << CS42L42_ASP_DAI1_PDN_SHIFT)
97 #define CS42L42_SRC_PDN_OVERRIDE_SHIFT 3
98 #define CS42L42_SRC_PDN_OVERRIDE_MASK (1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT)
99 #define CS42L42_DISCHARGE_FILT_SHIFT 4
100 #define CS42L42_DISCHARGE_FILT_MASK (1 << CS42L42_DISCHARGE_FILT_SHIFT)
102 #define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03)
103 #define CS42L42_RING_SENSE_PDNB_SHIFT 1
104 #define CS42L42_RING_SENSE_PDNB_MASK (1 << \
105 CS42L42_RING_SENSE_PDNB_SHIFT)
106 #define CS42L42_VPMON_PDNB_SHIFT 2
107 #define CS42L42_VPMON_PDNB_MASK (1 << \
108 CS42L42_VPMON_PDNB_SHIFT)
109 #define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT 5
110 #define CS42L42_SW_CLK_STP_STAT_SEL_MASK (3 << \
111 CS42L42_SW_CLK_STP_STAT_SEL_SHIFT)
113 #define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04)
114 #define CS42L42_RS_TRIM_R_SHIFT 0
115 #define CS42L42_RS_TRIM_R_MASK (1 << \
116 CS42L42_RS_TRIM_R_SHIFT)
117 #define CS42L42_RS_TRIM_T_SHIFT 1
118 #define CS42L42_RS_TRIM_T_MASK (1 << \
119 CS42L42_RS_TRIM_T_SHIFT)
120 #define CS42L42_HPREF_RS_SHIFT 2
121 #define CS42L42_HPREF_RS_MASK (1 << \
122 CS42L42_HPREF_RS_SHIFT)
123 #define CS42L42_HSBIAS_FILT_REF_RS_SHIFT 3
124 #define CS42L42_HSBIAS_FILT_REF_RS_MASK (1 << \
125 CS42L42_HSBIAS_FILT_REF_RS_SHIFT)
126 #define CS42L42_RING_SENSE_PU_HIZ_SHIFT 6
127 #define CS42L42_RING_SENSE_PU_HIZ_MASK (1 << \
128 CS42L42_RING_SENSE_PU_HIZ_SHIFT)
130 #define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05)
131 #define CS42L42_TS_RS_GATE_SHIFT 7
132 #define CS42L42_TS_RS_GATE_MAS (1 << CS42L42_TS_RS_GATE_SHIFT)
134 #define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07)
135 #define CS42L42_SCLK_PRESENT_SHIFT 0
136 #define CS42L42_SCLK_PRESENT_MASK (1 << CS42L42_SCLK_PRESENT_SHIFT)
138 #define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09)
139 #define CS42L42_OSC_SW_SEL_STAT_SHIFT 0
140 #define CS42L42_OSC_SW_SEL_STAT_MASK (3 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
141 #define CS42L42_OSC_PDNB_STAT_SHIFT 2
142 #define CS42L42_OSC_PDNB_STAT_MASK (1 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
144 #define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12)
145 #define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0
146 #define CS42L42_RS_RISE_DBNCE_TIME_MASK (7 << \
147 CS42L42_RS_RISE_DBNCE_TIME_SHIFT)
148 #define CS42L42_RS_FALL_DBNCE_TIME_SHIFT 3
149 #define CS42L42_RS_FALL_DBNCE_TIME_MASK (7 << \
150 CS42L42_RS_FALL_DBNCE_TIME_SHIFT)
151 #define CS42L42_RS_PU_EN_SHIFT 6
152 #define CS42L42_RS_PU_EN_MASK (1 << \
153 CS42L42_RS_PU_EN_SHIFT)
154 #define CS42L42_RS_INV_SHIFT 7
155 #define CS42L42_RS_INV_MASK (1 << \
156 CS42L42_RS_INV_SHIFT)
158 #define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13)
159 #define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0
160 #define CS42L42_TS_RISE_DBNCE_TIME_MASK (7 << \
161 CS42L42_TS_RISE_DBNCE_TIME_SHIFT)
162 #define CS42L42_TS_FALL_DBNCE_TIME_SHIFT 3
163 #define CS42L42_TS_FALL_DBNCE_TIME_MASK (7 << \
164 CS42L42_TS_FALL_DBNCE_TIME_SHIFT)
165 #define CS42L42_TS_INV_SHIFT 7
166 #define CS42L42_TS_INV_MASK (1 << \
167 CS42L42_TS_INV_SHIFT)
169 #define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14)
170 #define CS42L42_D_RS_PLUG_DBNC_SHIFT 0
171 #define CS42L42_D_RS_PLUG_DBNC_MASK (1 << CS42L42_D_RS_PLUG_DBNC_SHIFT)
172 #define CS42L42_D_RS_UNPLUG_DBNC_SHIFT 1
173 #define CS42L42_D_RS_UNPLUG_DBNC_MASK (1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT)
174 #define CS42L42_D_TS_PLUG_DBNC_SHIFT 2
175 #define CS42L42_D_TS_PLUG_DBNC_MASK (1 << CS42L42_D_TS_PLUG_DBNC_SHIFT)
176 #define CS42L42_D_TS_UNPLUG_DBNC_SHIFT 3
177 #define CS42L42_D_TS_UNPLUG_DBNC_MASK (1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT)
179 #define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15)
180 #define CS42L42_RS_PLUG_DBNC_SHIFT 0
181 #define CS42L42_RS_PLUG_DBNC_MASK (1 << CS42L42_RS_PLUG_DBNC_SHIFT)
182 #define CS42L42_RS_UNPLUG_DBNC_SHIFT 1
183 #define CS42L42_RS_UNPLUG_DBNC_MASK (1 << CS42L42_RS_UNPLUG_DBNC_SHIFT)
184 #define CS42L42_TS_PLUG_DBNC_SHIFT 2
185 #define CS42L42_TS_PLUG_DBNC_MASK (1 << CS42L42_TS_PLUG_DBNC_SHIFT)
186 #define CS42L42_TS_UNPLUG_DBNC_SHIFT 3
187 #define CS42L42_TS_UNPLUG_DBNC_MASK (1 << CS42L42_TS_UNPLUG_DBNC_SHIFT)
189 #define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F)
190 #define CS42L42_HSDET_COMP1_LVL_SHIFT 0
191 #define CS42L42_HSDET_COMP1_LVL_MASK (15 << CS42L42_HSDET_COMP1_LVL_SHIFT)
192 #define CS42L42_HSDET_COMP2_LVL_SHIFT 4
193 #define CS42L42_HSDET_COMP2_LVL_MASK (15 << CS42L42_HSDET_COMP2_LVL_SHIFT)
195 #define CS42L42_HSDET_COMP1_LVL_VAL 12 /* 1.25V Comparator */
196 #define CS42L42_HSDET_COMP2_LVL_VAL 2 /* 1.75V Comparator */
197 #define CS42L42_HSDET_COMP1_LVL_DEFAULT 7 /* 1V Comparator */
198 #define CS42L42_HSDET_COMP2_LVL_DEFAULT 7 /* 2V Comparator */
200 #define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20)
201 #define CS42L42_HSDET_AUTO_TIME_SHIFT 0
202 #define CS42L42_HSDET_AUTO_TIME_MASK (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)
203 #define CS42L42_HSBIAS_REF_SHIFT 3
204 #define CS42L42_HSBIAS_REF_MASK (1 << CS42L42_HSBIAS_REF_SHIFT)
205 #define CS42L42_HSDET_SET_SHIFT 4
206 #define CS42L42_HSDET_SET_MASK (3 << CS42L42_HSDET_SET_SHIFT)
207 #define CS42L42_HSDET_CTRL_SHIFT 6
208 #define CS42L42_HSDET_CTRL_MASK (3 << CS42L42_HSDET_CTRL_SHIFT)
210 #define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21)
211 #define CS42L42_SW_GNDHS_HS4_SHIFT 0
212 #define CS42L42_SW_GNDHS_HS4_MASK (1 << CS42L42_SW_GNDHS_HS4_SHIFT)
213 #define CS42L42_SW_GNDHS_HS3_SHIFT 1
214 #define CS42L42_SW_GNDHS_HS3_MASK (1 << CS42L42_SW_GNDHS_HS3_SHIFT)
215 #define CS42L42_SW_HSB_HS4_SHIFT 2
216 #define CS42L42_SW_HSB_HS4_MASK (1 << CS42L42_SW_HSB_HS4_SHIFT)
217 #define CS42L42_SW_HSB_HS3_SHIFT 3
218 #define CS42L42_SW_HSB_HS3_MASK (1 << CS42L42_SW_HSB_HS3_SHIFT)
219 #define CS42L42_SW_HSB_FILT_HS4_SHIFT 4
220 #define CS42L42_SW_HSB_FILT_HS4_MASK (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT)
221 #define CS42L42_SW_HSB_FILT_HS3_SHIFT 5
222 #define CS42L42_SW_HSB_FILT_HS3_MASK (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT)
223 #define CS42L42_SW_REF_HS4_SHIFT 6
224 #define CS42L42_SW_REF_HS4_MASK (1 << CS42L42_SW_REF_HS4_SHIFT)
225 #define CS42L42_SW_REF_HS3_SHIFT 7
226 #define CS42L42_SW_REF_HS3_MASK (1 << CS42L42_SW_REF_HS3_SHIFT)
228 #define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24)
229 #define CS42L42_HSDET_TYPE_SHIFT 0
230 #define CS42L42_HSDET_TYPE_MASK (3 << CS42L42_HSDET_TYPE_SHIFT)
231 #define CS42L42_HSDET_COMP1_OUT_SHIFT 6
232 #define CS42L42_HSDET_COMP1_OUT_MASK (1 << CS42L42_HSDET_COMP1_OUT_SHIFT)
233 #define CS42L42_HSDET_COMP2_OUT_SHIFT 7
234 #define CS42L42_HSDET_COMP2_OUT_MASK (1 << CS42L42_HSDET_COMP2_OUT_SHIFT)
235 #define CS42L42_PLUG_CTIA 0
236 #define CS42L42_PLUG_OMTP 1
237 #define CS42L42_PLUG_HEADPHONE 2
238 #define CS42L42_PLUG_INVALID 3
240 #define CS42L42_HSDET_SW_COMP1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
241 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
242 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \
243 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
244 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
245 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
246 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
247 (1 << CS42L42_SW_REF_HS3_SHIFT))
248 #define CS42L42_HSDET_SW_COMP2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
249 (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
250 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
251 (1 << CS42L42_SW_HSB_HS3_SHIFT) | \
252 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
253 (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
254 (1 << CS42L42_SW_REF_HS4_SHIFT) | \
255 (0 << CS42L42_SW_REF_HS3_SHIFT))
256 #define CS42L42_HSDET_SW_TYPE1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
257 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
258 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \
259 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
260 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
261 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
262 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
263 (1 << CS42L42_SW_REF_HS3_SHIFT))
264 #define CS42L42_HSDET_SW_TYPE2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
265 (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
266 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
267 (1 << CS42L42_SW_HSB_HS3_SHIFT) | \
268 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
269 (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
270 (1 << CS42L42_SW_REF_HS4_SHIFT) | \
271 (0 << CS42L42_SW_REF_HS3_SHIFT))
272 #define CS42L42_HSDET_SW_TYPE3 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
273 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
274 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
275 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
276 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
277 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
278 (1 << CS42L42_SW_REF_HS4_SHIFT) | \
279 (1 << CS42L42_SW_REF_HS3_SHIFT))
280 #define CS42L42_HSDET_SW_TYPE4 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
281 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
282 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \
283 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
284 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
285 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
286 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
287 (1 << CS42L42_SW_REF_HS3_SHIFT))
289 #define CS42L42_HSDET_COMP_TYPE1 1
290 #define CS42L42_HSDET_COMP_TYPE2 2
291 #define CS42L42_HSDET_COMP_TYPE3 0
292 #define CS42L42_HSDET_COMP_TYPE4 3
294 #define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29)
295 #define CS42L42_HS_CLAMP_DISABLE_SHIFT 0
296 #define CS42L42_HS_CLAMP_DISABLE_MASK (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)
298 /* Page 0x12 Clocking Registers */
299 #define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01)
300 #define CS42L42_MCLKDIV_SHIFT 1
301 #define CS42L42_MCLKDIV_MASK (1 << CS42L42_MCLKDIV_SHIFT)
302 #define CS42L42_MCLK_SRC_SEL_SHIFT 0
303 #define CS42L42_MCLK_SRC_SEL_MASK (1 << CS42L42_MCLK_SRC_SEL_SHIFT)
305 #define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02)
306 #define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03)
308 #define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04)
309 #define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0
310 #define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \
311 CS42L42_FSYNC_PULSE_WIDTH_SHIFT)
313 #define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05)
315 #define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06)
316 #define CS42L42_FSYNC_PERIOD_SHIFT 0
317 #define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT)
319 #define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07)
320 #define CS42L42_ASP_SCLK_EN_SHIFT 5
321 #define CS42L42_ASP_SCLK_EN_MASK (1 << CS42L42_ASP_SCLK_EN_SHIFT)
322 #define CS42L42_ASP_MASTER_MODE 0x01
323 #define CS42L42_ASP_SLAVE_MODE 0x00
324 #define CS42L42_ASP_MODE_SHIFT 4
325 #define CS42L42_ASP_MODE_MASK (1 << CS42L42_ASP_MODE_SHIFT)
326 #define CS42L42_ASP_SCPOL_SHIFT 2
327 #define CS42L42_ASP_SCPOL_MASK (3 << CS42L42_ASP_SCPOL_SHIFT)
328 #define CS42L42_ASP_SCPOL_NOR 3
329 #define CS42L42_ASP_LCPOL_SHIFT 0
330 #define CS42L42_ASP_LCPOL_MASK (3 << CS42L42_ASP_LCPOL_SHIFT)
331 #define CS42L42_ASP_LCPOL_INV 3
333 #define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08)
334 #define CS42L42_ASP_STP_SHIFT 4
335 #define CS42L42_ASP_STP_MASK (1 << CS42L42_ASP_STP_SHIFT)
336 #define CS42L42_ASP_5050_SHIFT 3
337 #define CS42L42_ASP_5050_MASK (1 << CS42L42_ASP_5050_SHIFT)
338 #define CS42L42_ASP_FSD_SHIFT 0
339 #define CS42L42_ASP_FSD_MASK (7 << CS42L42_ASP_FSD_SHIFT)
340 #define CS42L42_ASP_FSD_0_5 1
341 #define CS42L42_ASP_FSD_1_0 2
342 #define CS42L42_ASP_FSD_1_5 3
343 #define CS42L42_ASP_FSD_2_0 4
345 #define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09)
346 #define CS42L42_FS_EN_SHIFT 0
347 #define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT)
348 #define CS42L42_FS_EN_IASRC_96K 0x1
349 #define CS42L42_FS_EN_OASRC_96K 0x2
351 #define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A)
352 #define CS42L42_CLK_IASRC_SEL_SHIFT 0
353 #define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT)
354 #define CS42L42_CLK_IASRC_SEL_6 0
355 #define CS42L42_CLK_IASRC_SEL_12 1
357 #define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B)
358 #define CS42L42_CLK_OASRC_SEL_SHIFT 0
359 #define CS42L42_CLK_OASRC_SEL_MASK (1 << CS42L42_CLK_OASRC_SEL_SHIFT)
360 #define CS42L42_CLK_OASRC_SEL_12 1
362 #define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C)
363 #define CS42L42_SCLK_PREDIV_SHIFT 0
364 #define CS42L42_SCLK_PREDIV_MASK (3 << CS42L42_SCLK_PREDIV_SHIFT)
366 /* Page 0x13 Interrupt Registers */
368 #define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01)
369 #define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02)
370 #define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03)
371 #define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04)
372 #define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05)
373 #define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08)
374 #define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09)
375 #define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A)
376 #define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B)
377 #define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D)
378 #define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E)
379 #define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F)
381 #define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16)
382 #define CS42L42_ADC_OVFL_SHIFT 0
383 #define CS42L42_ADC_OVFL_MASK (1 << CS42L42_ADC_OVFL_SHIFT)
384 #define CS42L42_ADC_OVFL_VAL_MASK CS42L42_ADC_OVFL_MASK
386 #define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17)
387 #define CS42L42_MIX_CHB_OVFL_SHIFT 0
388 #define CS42L42_MIX_CHB_OVFL_MASK (1 << CS42L42_MIX_CHB_OVFL_SHIFT)
389 #define CS42L42_MIX_CHA_OVFL_SHIFT 1
390 #define CS42L42_MIX_CHA_OVFL_MASK (1 << CS42L42_MIX_CHA_OVFL_SHIFT)
391 #define CS42L42_EQ_OVFL_SHIFT 2
392 #define CS42L42_EQ_OVFL_MASK (1 << CS42L42_EQ_OVFL_SHIFT)
393 #define CS42L42_EQ_BIQUAD_OVFL_SHIFT 3
394 #define CS42L42_EQ_BIQUAD_OVFL_MASK (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)
395 #define CS42L42_MIXER_VAL_MASK (CS42L42_MIX_CHB_OVFL_MASK | \
396 CS42L42_MIX_CHA_OVFL_MASK | \
397 CS42L42_EQ_OVFL_MASK | \
398 CS42L42_EQ_BIQUAD_OVFL_MASK)
400 #define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18)
401 #define CS42L42_SRC_ILK_SHIFT 0
402 #define CS42L42_SRC_ILK_MASK (1 << CS42L42_SRC_ILK_SHIFT)
403 #define CS42L42_SRC_OLK_SHIFT 1
404 #define CS42L42_SRC_OLK_MASK (1 << CS42L42_SRC_OLK_SHIFT)
405 #define CS42L42_SRC_IUNLK_SHIFT 2
406 #define CS42L42_SRC_IUNLK_MASK (1 << CS42L42_SRC_IUNLK_SHIFT)
407 #define CS42L42_SRC_OUNLK_SHIFT 3
408 #define CS42L42_SRC_OUNLK_MASK (1 << CS42L42_SRC_OUNLK_SHIFT)
409 #define CS42L42_SRC_VAL_MASK (CS42L42_SRC_ILK_MASK | \
410 CS42L42_SRC_OLK_MASK | \
411 CS42L42_SRC_IUNLK_MASK | \
412 CS42L42_SRC_OUNLK_MASK)
414 #define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19)
415 #define CS42L42_ASPRX_NOLRCK_SHIFT 0
416 #define CS42L42_ASPRX_NOLRCK_MASK (1 << CS42L42_ASPRX_NOLRCK_SHIFT)
417 #define CS42L42_ASPRX_EARLY_SHIFT 1
418 #define CS42L42_ASPRX_EARLY_MASK (1 << CS42L42_ASPRX_EARLY_SHIFT)
419 #define CS42L42_ASPRX_LATE_SHIFT 2
420 #define CS42L42_ASPRX_LATE_MASK (1 << CS42L42_ASPRX_LATE_SHIFT)
421 #define CS42L42_ASPRX_ERROR_SHIFT 3
422 #define CS42L42_ASPRX_ERROR_MASK (1 << CS42L42_ASPRX_ERROR_SHIFT)
423 #define CS42L42_ASPRX_OVLD_SHIFT 4
424 #define CS42L42_ASPRX_OVLD_MASK (1 << CS42L42_ASPRX_OVLD_SHIFT)
425 #define CS42L42_ASP_RX_VAL_MASK (CS42L42_ASPRX_NOLRCK_MASK | \
426 CS42L42_ASPRX_EARLY_MASK | \
427 CS42L42_ASPRX_LATE_MASK | \
428 CS42L42_ASPRX_ERROR_MASK | \
429 CS42L42_ASPRX_OVLD_MASK)
431 #define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A)
432 #define CS42L42_ASPTX_NOLRCK_SHIFT 0
433 #define CS42L42_ASPTX_NOLRCK_MASK (1 << CS42L42_ASPTX_NOLRCK_SHIFT)
434 #define CS42L42_ASPTX_EARLY_SHIFT 1
435 #define CS42L42_ASPTX_EARLY_MASK (1 << CS42L42_ASPTX_EARLY_SHIFT)
436 #define CS42L42_ASPTX_LATE_SHIFT 2
437 #define CS42L42_ASPTX_LATE_MASK (1 << CS42L42_ASPTX_LATE_SHIFT)
438 #define CS42L42_ASPTX_SMERROR_SHIFT 3
439 #define CS42L42_ASPTX_SMERROR_MASK (1 << CS42L42_ASPTX_SMERROR_SHIFT)
440 #define CS42L42_ASP_TX_VAL_MASK (CS42L42_ASPTX_NOLRCK_MASK | \
441 CS42L42_ASPTX_EARLY_MASK | \
442 CS42L42_ASPTX_LATE_MASK | \
443 CS42L42_ASPTX_SMERROR_MASK)
445 #define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B)
446 #define CS42L42_PDN_DONE_SHIFT 0
447 #define CS42L42_PDN_DONE_MASK (1 << CS42L42_PDN_DONE_SHIFT)
448 #define CS42L42_HSDET_AUTO_DONE_SHIFT 1
449 #define CS42L42_HSDET_AUTO_DONE_MASK (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)
450 #define CS42L42_CODEC_VAL_MASK (CS42L42_PDN_DONE_MASK | \
451 CS42L42_HSDET_AUTO_DONE_MASK)
453 #define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C)
454 #define CS42L42_SRCPL_ADC_LK_SHIFT 0
455 #define CS42L42_SRCPL_ADC_LK_MASK (1 << CS42L42_SRCPL_ADC_LK_SHIFT)
456 #define CS42L42_SRCPL_DAC_LK_SHIFT 2
457 #define CS42L42_SRCPL_DAC_LK_MASK (1 << CS42L42_SRCPL_DAC_LK_SHIFT)
458 #define CS42L42_SRCPL_ADC_UNLK_SHIFT 5
459 #define CS42L42_SRCPL_ADC_UNLK_MASK (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT)
460 #define CS42L42_SRCPL_DAC_UNLK_SHIFT 6
461 #define CS42L42_SRCPL_DAC_UNLK_MASK (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)
462 #define CS42L42_SRCPL_VAL_MASK (CS42L42_SRCPL_ADC_LK_MASK | \
463 CS42L42_SRCPL_DAC_LK_MASK | \
464 CS42L42_SRCPL_ADC_UNLK_MASK | \
465 CS42L42_SRCPL_DAC_UNLK_MASK)
467 #define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E)
468 #define CS42L42_VPMON_SHIFT 0
469 #define CS42L42_VPMON_MASK (1 << CS42L42_VPMON_SHIFT)
470 #define CS42L42_VPMON_VAL_MASK CS42L42_VPMON_MASK
472 #define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F)
473 #define CS42L42_PLL_LOCK_SHIFT 0
474 #define CS42L42_PLL_LOCK_MASK (1 << CS42L42_PLL_LOCK_SHIFT)
475 #define CS42L42_PLL_LOCK_VAL_MASK CS42L42_PLL_LOCK_MASK
477 #define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20)
478 #define CS42L42_RS_PLUG_SHIFT 0
479 #define CS42L42_RS_PLUG_MASK (1 << CS42L42_RS_PLUG_SHIFT)
480 #define CS42L42_RS_UNPLUG_SHIFT 1
481 #define CS42L42_RS_UNPLUG_MASK (1 << CS42L42_RS_UNPLUG_SHIFT)
482 #define CS42L42_TS_PLUG_SHIFT 2
483 #define CS42L42_TS_PLUG_MASK (1 << CS42L42_TS_PLUG_SHIFT)
484 #define CS42L42_TS_UNPLUG_SHIFT 3
485 #define CS42L42_TS_UNPLUG_MASK (1 << CS42L42_TS_UNPLUG_SHIFT)
486 #define CS42L42_TSRS_PLUG_VAL_MASK (CS42L42_RS_PLUG_MASK | \
487 CS42L42_RS_UNPLUG_MASK | \
488 CS42L42_TS_PLUG_MASK | \
489 CS42L42_TS_UNPLUG_MASK)
490 #define CS42L42_TS_PLUG 3
491 #define CS42L42_TS_UNPLUG 0
492 #define CS42L42_TS_TRANS 1
495 * NOTE: PLL_START must be 0 while both ADC_PDN=1 and HP_PDN=1.
496 * Otherwise it will prevent FILT+ from charging properly.
498 #define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01)
499 #define CS42L42_PLL_START_SHIFT 0
500 #define CS42L42_PLL_START_MASK (1 << CS42L42_PLL_START_SHIFT)
502 #define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02)
503 #define CS42L42_PLL_DIV_FRAC_SHIFT 0
504 #define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT)
506 #define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03)
507 #define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04)
509 #define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05)
510 #define CS42L42_PLL_DIV_INT_SHIFT 0
511 #define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT)
513 #define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08)
514 #define CS42L42_PLL_DIVOUT_SHIFT 0
515 #define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT)
517 #define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A)
518 #define CS42L42_PLL_CAL_RATIO_SHIFT 0
519 #define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT)
521 #define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B)
522 #define CS42L42_PLL_MODE_SHIFT 0
523 #define CS42L42_PLL_MODE_MASK (3 << CS42L42_PLL_MODE_SHIFT)
525 /* Page 0x19 HP Load Detect Registers */
526 #define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25)
527 #define CS42L42_RLA_STAT_SHIFT 0
528 #define CS42L42_RLA_STAT_MASK (3 << CS42L42_RLA_STAT_SHIFT)
529 #define CS42L42_RLA_STAT_15_OHM 0
531 #define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26)
532 #define CS42L42_HPLOAD_DET_DONE_SHIFT 0
533 #define CS42L42_HPLOAD_DET_DONE_MASK (1 << CS42L42_HPLOAD_DET_DONE_SHIFT)
535 #define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27)
536 #define CS42L42_HP_LD_EN_SHIFT 0
537 #define CS42L42_HP_LD_EN_MASK (1 << CS42L42_HP_LD_EN_SHIFT)
539 /* Page 0x1B Headset Interface Registers */
540 #define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70)
541 #define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0
542 #define CS42L42_HSBIAS_SENSE_TRIP_MASK (7 << \
543 CS42L42_HSBIAS_SENSE_TRIP_SHIFT)
544 #define CS42L42_TIP_SENSE_EN_SHIFT 5
545 #define CS42L42_TIP_SENSE_EN_MASK (1 << \
546 CS42L42_TIP_SENSE_EN_SHIFT)
547 #define CS42L42_AUTO_HSBIAS_HIZ_SHIFT 6
548 #define CS42L42_AUTO_HSBIAS_HIZ_MASK (1 << \
549 CS42L42_AUTO_HSBIAS_HIZ_SHIFT)
550 #define CS42L42_HSBIAS_SENSE_EN_SHIFT 7
551 #define CS42L42_HSBIAS_SENSE_EN_MASK (1 << \
552 CS42L42_HSBIAS_SENSE_EN_SHIFT)
554 #define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71)
555 #define CS42L42_WAKEB_CLEAR_SHIFT 0
556 #define CS42L42_WAKEB_CLEAR_MASK (1 << CS42L42_WAKEB_CLEAR_SHIFT)
557 #define CS42L42_WAKEB_MODE_SHIFT 5
558 #define CS42L42_WAKEB_MODE_MASK (1 << CS42L42_WAKEB_MODE_SHIFT)
559 #define CS42L42_M_HP_WAKE_SHIFT 6
560 #define CS42L42_M_HP_WAKE_MASK (1 << CS42L42_M_HP_WAKE_SHIFT)
561 #define CS42L42_M_MIC_WAKE_SHIFT 7
562 #define CS42L42_M_MIC_WAKE_MASK (1 << CS42L42_M_MIC_WAKE_SHIFT)
564 #define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72)
565 #define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT 7
566 #define CS42L42_ADC_DISABLE_S0_MUTE_MASK (1 << \
567 CS42L42_ADC_DISABLE_S0_MUTE_SHIFT)
569 #define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73)
570 #define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0
571 #define CS42L42_TIP_SENSE_DEBOUNCE_MASK (3 << \
572 CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)
573 #define CS42L42_TIP_SENSE_INV_SHIFT 5
574 #define CS42L42_TIP_SENSE_INV_MASK (1 << \
575 CS42L42_TIP_SENSE_INV_SHIFT)
576 #define CS42L42_TIP_SENSE_CTRL_SHIFT 6
577 #define CS42L42_TIP_SENSE_CTRL_MASK (3 << \
578 CS42L42_TIP_SENSE_CTRL_SHIFT)
581 * NOTE: DETECT_MODE must be 0 while both ADC_PDN=1 and HP_PDN=1.
582 * Otherwise it will prevent FILT+ from charging properly.
584 #define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74)
585 #define CS42L42_PDN_MIC_LVL_DET_SHIFT 0
586 #define CS42L42_PDN_MIC_LVL_DET_MASK (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)
587 #define CS42L42_HSBIAS_CTL_SHIFT 1
588 #define CS42L42_HSBIAS_CTL_MASK (3 << CS42L42_HSBIAS_CTL_SHIFT)
589 #define CS42L42_DETECT_MODE_SHIFT 3
590 #define CS42L42_DETECT_MODE_MASK (3 << CS42L42_DETECT_MODE_SHIFT)
592 #define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75)
593 #define CS42L42_HS_DET_LEVEL_SHIFT 0
594 #define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT)
595 #define CS42L42_EVENT_STAT_SEL_SHIFT 6
596 #define CS42L42_EVENT_STAT_SEL_MASK (1 << CS42L42_EVENT_STAT_SEL_SHIFT)
597 #define CS42L42_LATCH_TO_VP_SHIFT 7
598 #define CS42L42_LATCH_TO_VP_MASK (1 << CS42L42_LATCH_TO_VP_SHIFT)
600 #define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76)
601 #define CS42L42_DEBOUNCE_TIME_SHIFT 5
602 #define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT)
604 #define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77)
605 #define CS42L42_HSBIAS_HIZ_MODE_SHIFT 6
606 #define CS42L42_HSBIAS_HIZ_MODE_MASK (1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT)
607 #define CS42L42_TIP_SENSE_SHIFT 7
608 #define CS42L42_TIP_SENSE_MASK (1 << CS42L42_TIP_SENSE_SHIFT)
610 #define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78)
611 #define CS42L42_SHORT_TRUE_SHIFT 0
612 #define CS42L42_SHORT_TRUE_MASK (1 << CS42L42_SHORT_TRUE_SHIFT)
613 #define CS42L42_HS_TRUE_SHIFT 1
614 #define CS42L42_HS_TRUE_MASK (1 << CS42L42_HS_TRUE_SHIFT)
616 #define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79)
617 #define CS42L42_TIP_SENSE_UNPLUG_SHIFT 5
618 #define CS42L42_TIP_SENSE_UNPLUG_MASK (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT)
619 #define CS42L42_TIP_SENSE_PLUG_SHIFT 6
620 #define CS42L42_TIP_SENSE_PLUG_MASK (1 << CS42L42_TIP_SENSE_PLUG_SHIFT)
621 #define CS42L42_HSBIAS_SENSE_SHIFT 7
622 #define CS42L42_HSBIAS_SENSE_MASK (1 << CS42L42_HSBIAS_SENSE_SHIFT)
623 #define CS42L42_DET_INT_VAL1_MASK (CS42L42_TIP_SENSE_UNPLUG_MASK | \
624 CS42L42_TIP_SENSE_PLUG_MASK | \
625 CS42L42_HSBIAS_SENSE_MASK)
627 #define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A)
628 #define CS42L42_M_SHORT_DET_SHIFT 0
629 #define CS42L42_M_SHORT_DET_MASK (1 << \
630 CS42L42_M_SHORT_DET_SHIFT)
631 #define CS42L42_M_SHORT_RLS_SHIFT 1
632 #define CS42L42_M_SHORT_RLS_MASK (1 << \
633 CS42L42_M_SHORT_RLS_SHIFT)
634 #define CS42L42_M_HSBIAS_HIZ_SHIFT 2
635 #define CS42L42_M_HSBIAS_HIZ_MASK (1 << \
636 CS42L42_M_HSBIAS_HIZ_SHIFT)
637 #define CS42L42_M_DETECT_FT_SHIFT 6
638 #define CS42L42_M_DETECT_FT_MASK (1 << \
639 CS42L42_M_DETECT_FT_SHIFT)
640 #define CS42L42_M_DETECT_TF_SHIFT 7
641 #define CS42L42_M_DETECT_TF_MASK (1 << \
642 CS42L42_M_DETECT_TF_SHIFT)
643 #define CS42L42_DET_INT_VAL2_MASK (CS42L42_M_SHORT_DET_MASK | \
644 CS42L42_M_SHORT_RLS_MASK | \
645 CS42L42_M_HSBIAS_HIZ_MASK | \
646 CS42L42_M_DETECT_FT_MASK | \
647 CS42L42_M_DETECT_TF_MASK)
649 /* Page 0x1C Headset Bias Registers */
650 #define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03)
651 #define CS42L42_HSBIAS_RAMP_SHIFT 0
652 #define CS42L42_HSBIAS_RAMP_MASK (3 << CS42L42_HSBIAS_RAMP_SHIFT)
653 #define CS42L42_HSBIAS_PD_SHIFT 4
654 #define CS42L42_HSBIAS_PD_MASK (1 << CS42L42_HSBIAS_PD_SHIFT)
655 #define CS42L42_HSBIAS_CAPLESS_SHIFT 7
656 #define CS42L42_HSBIAS_CAPLESS_MASK (1 << CS42L42_HSBIAS_CAPLESS_SHIFT)
658 /* Page 0x1D ADC Registers */
659 #define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01)
660 #define CS42L42_ADC_NOTCH_DIS_SHIFT 5
661 #define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT 4
662 #define CS42L42_ADC_INV_SHIFT 2
663 #define CS42L42_ADC_DIG_BOOST_SHIFT 0
665 #define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03)
666 #define CS42L42_ADC_VOL_SHIFT 0
668 #define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04)
669 #define CS42L42_ADC_WNF_CF_SHIFT 4
670 #define CS42L42_ADC_WNF_EN_SHIFT 3
671 #define CS42L42_ADC_HPF_CF_SHIFT 1
672 #define CS42L42_ADC_HPF_EN_SHIFT 0
674 /* Page 0x1F DAC Registers */
675 #define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01)
676 #define CS42L42_DACB_INV_SHIFT 1
677 #define CS42L42_DACA_INV_SHIFT 0
679 #define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06)
680 #define CS42L42_HPOUT_PULLDOWN_SHIFT 4
681 #define CS42L42_HPOUT_PULLDOWN_MASK (15 << CS42L42_HPOUT_PULLDOWN_SHIFT)
682 #define CS42L42_HPOUT_LOAD_SHIFT 3
683 #define CS42L42_HPOUT_LOAD_MASK (1 << CS42L42_HPOUT_LOAD_SHIFT)
684 #define CS42L42_HPOUT_CLAMP_SHIFT 2
685 #define CS42L42_HPOUT_CLAMP_MASK (1 << CS42L42_HPOUT_CLAMP_SHIFT)
686 #define CS42L42_DAC_HPF_EN_SHIFT 1
687 #define CS42L42_DAC_HPF_EN_MASK (1 << CS42L42_DAC_HPF_EN_SHIFT)
688 #define CS42L42_DAC_MON_EN_SHIFT 0
689 #define CS42L42_DAC_MON_EN_MASK (1 << CS42L42_DAC_MON_EN_SHIFT)
691 /* Page 0x20 HP CTL Registers */
692 #define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01)
693 #define CS42L42_HP_ANA_BMUTE_SHIFT 3
694 #define CS42L42_HP_ANA_BMUTE_MASK (1 << CS42L42_HP_ANA_BMUTE_SHIFT)
695 #define CS42L42_HP_ANA_AMUTE_SHIFT 2
696 #define CS42L42_HP_ANA_AMUTE_MASK (1 << CS42L42_HP_ANA_AMUTE_SHIFT)
697 #define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1
698 #define CS42L42_HP_FULL_SCALE_VOL_MASK (1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT)
700 /* Page 0x21 Class H Registers */
701 #define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01)
703 /* Page 0x23 Mixer Volume Registers */
704 #define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01)
705 #define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02)
707 #define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03)
708 #define CS42L42_MIXER_CH_VOL_SHIFT 0
709 #define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT)
711 /* Page 0x24 EQ Registers */
712 #define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01)
713 #define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02)
714 #define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03)
715 #define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04)
716 #define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06)
717 #define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07)
718 #define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08)
719 #define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09)
720 #define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A)
721 #define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B)
722 #define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C)
723 #define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E)
725 /* Page 0x25 Audio Port Registers */
726 #define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01)
727 #define CS42L42_SP_RX_CHB_SEL_SHIFT 2
728 #define CS42L42_SP_RX_CHB_SEL_MASK (3 << CS42L42_SP_RX_CHB_SEL_SHIFT)
730 #define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02)
731 #define CS42L42_SP_RX_RSYNC_SHIFT 6
732 #define CS42L42_SP_RX_RSYNC_MASK (1 << CS42L42_SP_RX_RSYNC_SHIFT)
733 #define CS42L42_SP_RX_NSB_POS_SHIFT 3
734 #define CS42L42_SP_RX_NSB_POS_MASK (7 << CS42L42_SP_RX_NSB_POS_SHIFT)
735 #define CS42L42_SP_RX_NFS_NSBB_SHIFT 2
736 #define CS42L42_SP_RX_NFS_NSBB_MASK (1 << CS42L42_SP_RX_NFS_NSBB_SHIFT)
737 #define CS42L42_SP_RX_ISOC_MODE_SHIFT 0
738 #define CS42L42_SP_RX_ISOC_MODE_MASK (3 << CS42L42_SP_RX_ISOC_MODE_SHIFT)
740 #define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03)
741 #define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04)
742 #define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05)
743 #define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06)
744 #define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07)
746 /* Page 0x26 SRC Registers */
747 #define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01)
748 #define CS42L42_SRC_SDIN_FS_SHIFT 0
749 #define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT)
751 #define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09)
753 /* Page 0x28 S/PDIF Registers */
754 #define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01)
755 #define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02)
756 #define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03)
757 #define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04)
759 /* Page 0x29 Serial Port TX Registers */
760 #define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01)
761 #define CS42L42_ASP_TX_EN_SHIFT 0
762 #define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02)
763 #define CS42L42_ASP_TX0_CH2_SHIFT 1
764 #define CS42L42_ASP_TX0_CH1_SHIFT 0
766 #define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03)
767 #define CS42L42_ASP_TX_CH1_AP_SHIFT 7
768 #define CS42L42_ASP_TX_CH1_AP_MASK (1 << CS42L42_ASP_TX_CH1_AP_SHIFT)
769 #define CS42L42_ASP_TX_CH2_AP_SHIFT 6
770 #define CS42L42_ASP_TX_CH2_AP_MASK (1 << CS42L42_ASP_TX_CH2_AP_SHIFT)
771 #define CS42L42_ASP_TX_CH2_RES_SHIFT 2
772 #define CS42L42_ASP_TX_CH2_RES_MASK (3 << CS42L42_ASP_TX_CH2_RES_SHIFT)
773 #define CS42L42_ASP_TX_CH1_RES_SHIFT 0
774 #define CS42L42_ASP_TX_CH1_RES_MASK (3 << CS42L42_ASP_TX_CH1_RES_SHIFT)
775 #define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04)
776 #define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05)
777 #define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06)
778 #define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A)
779 #define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B)
781 /* Page 0x2A Serial Port RX Registers */
782 #define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01)
783 #define CS42L42_ASP_RX0_CH_EN_SHIFT 2
784 #define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT)
785 #define CS42L42_ASP_RX0_CH1_SHIFT 2
786 #define CS42L42_ASP_RX0_CH2_SHIFT 3
787 #define CS42L42_ASP_RX0_CH3_SHIFT 4
788 #define CS42L42_ASP_RX0_CH4_SHIFT 5
790 #define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02)
791 #define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03)
792 #define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04)
793 #define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05)
794 #define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06)
795 #define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07)
796 #define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08)
797 #define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09)
798 #define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A)
799 #define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B)
800 #define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C)
801 #define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D)
802 #define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E)
803 #define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F)
804 #define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10)
805 #define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11)
806 #define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12)
807 #define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13)
809 #define CS42L42_ASP_RX_CH_AP_SHIFT 6
810 #define CS42L42_ASP_RX_CH_AP_MASK (1 << CS42L42_ASP_RX_CH_AP_SHIFT)
811 #define CS42L42_ASP_RX_CH_AP_LOW 0
812 #define CS42L42_ASP_RX_CH_AP_HI 1
813 #define CS42L42_ASP_RX_CH_RES_SHIFT 0
814 #define CS42L42_ASP_RX_CH_RES_MASK (3 << CS42L42_ASP_RX_CH_RES_SHIFT)
815 #define CS42L42_ASP_RX_CH_RES_32 3
816 #define CS42L42_ASP_RX_CH_RES_16 1
817 #define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0
818 #define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT)
820 /* Page 0x30 ID Registers */
821 #define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14)
822 #define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14)
824 /* Defines for fracturing values spread across multiple registers */
825 #define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff)
826 #define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8)
827 #define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16)
829 #define CS42L42_NUM_SUPPLIES 5
830 #define CS42L42_BOOT_TIME_US 3000
831 #define CS42L42_PLL_DIVOUT_TIME_US 800
832 #define CS42L42_CLOCK_SWITCH_DELAY_US 150
833 #define CS42L42_PLL_LOCK_POLL_US 250
834 #define CS42L42_PLL_LOCK_TIMEOUT_US 1250
835 #define CS42L42_HP_ADC_EN_TIME_US 20000
836 #define CS42L42_PDN_DONE_POLL_US 1000
837 #define CS42L42_PDN_DONE_TIMEOUT_US 200000
838 #define CS42L42_PDN_DONE_TIME_MS 100
839 #define CS42L42_FILT_DISCHARGE_TIME_MS 46
841 static const char *const cs42l42_supply_names[CS42L42_NUM_SUPPLIES] = {
849 struct cs42l42_private {
850 struct regmap *regmap;
852 struct regulator_bulk_data supplies[CS42L42_NUM_SUPPLIES];
853 struct gpio_desc *reset_gpio;
854 struct completion pdn_done;
855 struct snd_soc_jack *jack;
856 struct mutex irq_lock;
866 u8 btn_det_init_dbnce;
867 u8 btn_det_event_dbnce;
868 u8 bias_thresholds[CS42L42_NUM_BIASES];
869 u8 hs_bias_ramp_rate;
870 u8 hs_bias_ramp_time;
873 bool hp_adc_up_pending;
877 #endif /* __CS42L42_H__ */