sound/soc/codecs/cs42l42.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  * Author: Brian Austin <brian.austin@cirrus.com>
   9  * Author: Michael White <michael.white@cirrus.com>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/types.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/regmap.h>
  18 #include <linux/slab.h>
  19 #include <linux/acpi.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/property.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/gpio/consumer.h>
  25 #include <sound/core.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/soc-dapm.h>
  30 #include <sound/initval.h>
  31 #include <sound/tlv.h>
  32 #include <dt-bindings/sound/cs42l42.h>
  33
  34 #include "cs42l42.h"
  35 #include "cirrus_legacy.h"
  36
  37 static const char * const cs42l42_supply_names[] = {
  38         "VA",
  39         "VP",
  40         "VCP",
  41         "VD_FILT",
  42         "VL",
  43 };
  44
  45 static const struct reg_default cs42l42_reg_defaults[] = {
  46         { CS42L42_FRZ_CTL,                      0x00 },
  47         { CS42L42_SRC_CTL,                      0x10 },
  48         { CS42L42_MCLK_CTL,                     0x02 },
  49         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  50         { CS42L42_SLOW_START_ENABLE,            0x70 },
  51         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  52         { CS42L42_I2C_STRETCH,                  0x03 },
  53         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  54         { CS42L42_PWR_CTL1,                     0xFF },
  55         { CS42L42_PWR_CTL2,                     0x84 },
  56         { CS42L42_PWR_CTL3,                     0x20 },
  57         { CS42L42_RSENSE_CTL1,                  0x40 },
  58         { CS42L42_RSENSE_CTL2,                  0x00 },
  59         { CS42L42_OSC_SWITCH,                   0x00 },
  60         { CS42L42_RSENSE_CTL3,                  0x1B },
  61         { CS42L42_TSENSE_CTL,                   0x1B },
  62         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  63         { CS42L42_HSDET_CTL1,                   0x77 },
  64         { CS42L42_HSDET_CTL2,                   0x00 },
  65         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  66         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  67         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  68         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  69         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  70         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  71         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  72         { CS42L42_FSYNC_P_UPPER,                0x00 },
  73         { CS42L42_ASP_CLK_CFG,                  0x00 },
  74         { CS42L42_ASP_FRM_CFG,                  0x10 },
  75         { CS42L42_FS_RATE_EN,                   0x00 },
  76         { CS42L42_IN_ASRC_CLK,                  0x00 },
  77         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  78         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  79         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  80         { CS42L42_MIXER_INT_MASK,               0x0F },
  81         { CS42L42_SRC_INT_MASK,                 0x0F },
  82         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  83         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  84         { CS42L42_CODEC_INT_MASK,               0x03 },
  85         { CS42L42_SRCPL_INT_MASK,               0x7F },
  86         { CS42L42_VPMON_INT_MASK,               0x01 },
  87         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
  88         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
  89         { CS42L42_PLL_CTL1,                     0x00 },
  90         { CS42L42_PLL_DIV_FRAC0,                0x00 },
  91         { CS42L42_PLL_DIV_FRAC1,                0x00 },
  92         { CS42L42_PLL_DIV_FRAC2,                0x00 },
  93         { CS42L42_PLL_DIV_INT,                  0x40 },
  94         { CS42L42_PLL_CTL3,                     0x10 },
  95         { CS42L42_PLL_CAL_RATIO,                0x80 },
  96         { CS42L42_PLL_CTL4,                     0x03 },
  97         { CS42L42_LOAD_DET_EN,                  0x00 },
  98         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
  99         { CS42L42_WAKE_CTL,                     0xC0 },
 100         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
 101         { CS42L42_TIPSENSE_CTL,                 0x02 },
 102         { CS42L42_MISC_DET_CTL,                 0x03 },
 103         { CS42L42_MIC_DET_CTL1,                 0x1F },
 104         { CS42L42_MIC_DET_CTL2,                 0x2F },
 105         { CS42L42_DET_INT1_MASK,                0xE0 },
 106         { CS42L42_DET_INT2_MASK,                0xFF },
 107         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 108         { CS42L42_ADC_CTL,                      0x00 },
 109         { CS42L42_ADC_VOLUME,                   0x00 },
 110         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 111         { CS42L42_DAC_CTL1,                     0x00 },
 112         { CS42L42_DAC_CTL2,                     0x02 },
 113         { CS42L42_HP_CTL,                       0x0D },
 114         { CS42L42_CLASSH_CTL,                   0x07 },
 115         { CS42L42_MIXER_CHA_VOL,                0x3F },
 116         { CS42L42_MIXER_ADC_VOL,                0x3F },
 117         { CS42L42_MIXER_CHB_VOL,                0x3F },
 118         { CS42L42_EQ_COEF_IN0,                  0x00 },
 119         { CS42L42_EQ_COEF_IN1,                  0x00 },
 120         { CS42L42_EQ_COEF_IN2,                  0x00 },
 121         { CS42L42_EQ_COEF_IN3,                  0x00 },
 122         { CS42L42_EQ_COEF_RW,                   0x00 },
 123         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 124         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 125         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 126         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 127         { CS42L42_EQ_INIT_STAT,                 0x00 },
 128         { CS42L42_EQ_START_FILT,                0x00 },
 129         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 130         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 131         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 132         { CS42L42_SP_RX_FS,                     0x8C },
 133         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 134         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 135         { CS42L42_SP_TX_FS,                     0xCC },
 136         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 137         { CS42L42_SRC_SDIN_FS,                  0x40 },
 138         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 139         { CS42L42_SPDIF_CTL1,                   0x01 },
 140         { CS42L42_SPDIF_CTL2,                   0x00 },
 141         { CS42L42_SPDIF_CTL3,                   0x00 },
 142         { CS42L42_SPDIF_CTL4,                   0x42 },
 143         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 144         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 145         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 146         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 147         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 148         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 149         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 150         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 151         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 152         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 153         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 154         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 155         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 156         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 157         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 158         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 159         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 160         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 161         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 162         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 163         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 164         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 165         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 166         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 167         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 168         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 169         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 170 };
 171
 172 bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 173 {
 174         switch (reg) {
 175         case CS42L42_PAGE_REGISTER:
 176         case CS42L42_DEVID_AB:
 177         case CS42L42_DEVID_CD:
 178         case CS42L42_DEVID_E:
 179         case CS42L42_FABID:
 180         case CS42L42_REVID:
 181         case CS42L42_FRZ_CTL:
 182         case CS42L42_SRC_CTL:
 183         case CS42L42_MCLK_STATUS:
 184         case CS42L42_MCLK_CTL:
 185         case CS42L42_SFTRAMP_RATE:
 186         case CS42L42_SLOW_START_ENABLE:
 187         case CS42L42_I2C_DEBOUNCE:
 188         case CS42L42_I2C_STRETCH:
 189         case CS42L42_I2C_TIMEOUT:
 190         case CS42L42_PWR_CTL1:
 191         case CS42L42_PWR_CTL2:
 192         case CS42L42_PWR_CTL3:
 193         case CS42L42_RSENSE_CTL1:
 194         case CS42L42_RSENSE_CTL2:
 195         case CS42L42_OSC_SWITCH:
 196         case CS42L42_OSC_SWITCH_STATUS:
 197         case CS42L42_RSENSE_CTL3:
 198         case CS42L42_TSENSE_CTL:
 199         case CS42L42_TSRS_INT_DISABLE:
 200         case CS42L42_TRSENSE_STATUS:
 201         case CS42L42_HSDET_CTL1:
 202         case CS42L42_HSDET_CTL2:
 203         case CS42L42_HS_SWITCH_CTL:
 204         case CS42L42_HS_DET_STATUS:
 205         case CS42L42_HS_CLAMP_DISABLE:
 206         case CS42L42_MCLK_SRC_SEL:
 207         case CS42L42_SPDIF_CLK_CFG:
 208         case CS42L42_FSYNC_PW_LOWER:
 209         case CS42L42_FSYNC_PW_UPPER:
 210         case CS42L42_FSYNC_P_LOWER:
 211         case CS42L42_FSYNC_P_UPPER:
 212         case CS42L42_ASP_CLK_CFG:
 213         case CS42L42_ASP_FRM_CFG:
 214         case CS42L42_FS_RATE_EN:
 215         case CS42L42_IN_ASRC_CLK:
 216         case CS42L42_OUT_ASRC_CLK:
 217         case CS42L42_PLL_DIV_CFG1:
 218         case CS42L42_ADC_OVFL_STATUS:
 219         case CS42L42_MIXER_STATUS:
 220         case CS42L42_SRC_STATUS:
 221         case CS42L42_ASP_RX_STATUS:
 222         case CS42L42_ASP_TX_STATUS:
 223         case CS42L42_CODEC_STATUS:
 224         case CS42L42_DET_INT_STATUS1:
 225         case CS42L42_DET_INT_STATUS2:
 226         case CS42L42_SRCPL_INT_STATUS:
 227         case CS42L42_VPMON_STATUS:
 228         case CS42L42_PLL_LOCK_STATUS:
 229         case CS42L42_TSRS_PLUG_STATUS:
 230         case CS42L42_ADC_OVFL_INT_MASK:
 231         case CS42L42_MIXER_INT_MASK:
 232         case CS42L42_SRC_INT_MASK:
 233         case CS42L42_ASP_RX_INT_MASK:
 234         case CS42L42_ASP_TX_INT_MASK:
 235         case CS42L42_CODEC_INT_MASK:
 236         case CS42L42_SRCPL_INT_MASK:
 237         case CS42L42_VPMON_INT_MASK:
 238         case CS42L42_PLL_LOCK_INT_MASK:
 239         case CS42L42_TSRS_PLUG_INT_MASK:
 240         case CS42L42_PLL_CTL1:
 241         case CS42L42_PLL_DIV_FRAC0:
 242         case CS42L42_PLL_DIV_FRAC1:
 243         case CS42L42_PLL_DIV_FRAC2:
 244         case CS42L42_PLL_DIV_INT:
 245         case CS42L42_PLL_CTL3:
 246         case CS42L42_PLL_CAL_RATIO:
 247         case CS42L42_PLL_CTL4:
 248         case CS42L42_LOAD_DET_RCSTAT:
 249         case CS42L42_LOAD_DET_DONE:
 250         case CS42L42_LOAD_DET_EN:
 251         case CS42L42_HSBIAS_SC_AUTOCTL:
 252         case CS42L42_WAKE_CTL:
 253         case CS42L42_ADC_DISABLE_MUTE:
 254         case CS42L42_TIPSENSE_CTL:
 255         case CS42L42_MISC_DET_CTL:
 256         case CS42L42_MIC_DET_CTL1:
 257         case CS42L42_MIC_DET_CTL2:
 258         case CS42L42_DET_STATUS1:
 259         case CS42L42_DET_STATUS2:
 260         case CS42L42_DET_INT1_MASK:
 261         case CS42L42_DET_INT2_MASK:
 262         case CS42L42_HS_BIAS_CTL:
 263         case CS42L42_ADC_CTL:
 264         case CS42L42_ADC_VOLUME:
 265         case CS42L42_ADC_WNF_HPF_CTL:
 266         case CS42L42_DAC_CTL1:
 267         case CS42L42_DAC_CTL2:
 268         case CS42L42_HP_CTL:
 269         case CS42L42_CLASSH_CTL:
 270         case CS42L42_MIXER_CHA_VOL:
 271         case CS42L42_MIXER_ADC_VOL:
 272         case CS42L42_MIXER_CHB_VOL:
 273         case CS42L42_EQ_COEF_IN0:
 274         case CS42L42_EQ_COEF_IN1:
 275         case CS42L42_EQ_COEF_IN2:
 276         case CS42L42_EQ_COEF_IN3:
 277         case CS42L42_EQ_COEF_RW:
 278         case CS42L42_EQ_COEF_OUT0:
 279         case CS42L42_EQ_COEF_OUT1:
 280         case CS42L42_EQ_COEF_OUT2:
 281         case CS42L42_EQ_COEF_OUT3:
 282         case CS42L42_EQ_INIT_STAT:
 283         case CS42L42_EQ_START_FILT:
 284         case CS42L42_EQ_MUTE_CTL:
 285         case CS42L42_SP_RX_CH_SEL:
 286         case CS42L42_SP_RX_ISOC_CTL:
 287         case CS42L42_SP_RX_FS:
 288         case CS42l42_SPDIF_CH_SEL:
 289         case CS42L42_SP_TX_ISOC_CTL:
 290         case CS42L42_SP_TX_FS:
 291         case CS42L42_SPDIF_SW_CTL1:
 292         case CS42L42_SRC_SDIN_FS:
 293         case CS42L42_SRC_SDOUT_FS:
 294         case CS42L42_SOFT_RESET_REBOOT:
 295         case CS42L42_SPDIF_CTL1:
 296         case CS42L42_SPDIF_CTL2:
 297         case CS42L42_SPDIF_CTL3:
 298         case CS42L42_SPDIF_CTL4:
 299         case CS42L42_ASP_TX_SZ_EN:
 300         case CS42L42_ASP_TX_CH_EN:
 301         case CS42L42_ASP_TX_CH_AP_RES:
 302         case CS42L42_ASP_TX_CH1_BIT_MSB:
 303         case CS42L42_ASP_TX_CH1_BIT_LSB:
 304         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 305         case CS42L42_ASP_TX_CH2_BIT_MSB:
 306         case CS42L42_ASP_TX_CH2_BIT_LSB:
 307         case CS42L42_ASP_RX_DAI0_EN:
 308         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 309         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 310         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 311         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 312         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 313         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 314         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 315         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 316         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 317         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 318         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 319         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 320         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 321         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 322         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 323         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 324         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 325         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 326         case CS42L42_SUB_REVID:
 327                 return true;
 328         default:
 329                 return false;
 330         }
 331 }
 332 EXPORT_SYMBOL_NS_GPL(cs42l42_readable_register, SND_SOC_CS42L42_CORE);
 333
 334 bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 335 {
 336         switch (reg) {
 337         case CS42L42_DEVID_AB:
 338         case CS42L42_DEVID_CD:
 339         case CS42L42_DEVID_E:
 340         case CS42L42_MCLK_STATUS:
 341         case CS42L42_OSC_SWITCH_STATUS:
 342         case CS42L42_TRSENSE_STATUS:
 343         case CS42L42_HS_DET_STATUS:
 344         case CS42L42_ADC_OVFL_STATUS:
 345         case CS42L42_MIXER_STATUS:
 346         case CS42L42_SRC_STATUS:
 347         case CS42L42_ASP_RX_STATUS:
 348         case CS42L42_ASP_TX_STATUS:
 349         case CS42L42_CODEC_STATUS:
 350         case CS42L42_DET_INT_STATUS1:
 351         case CS42L42_DET_INT_STATUS2:
 352         case CS42L42_SRCPL_INT_STATUS:
 353         case CS42L42_VPMON_STATUS:
 354         case CS42L42_PLL_LOCK_STATUS:
 355         case CS42L42_TSRS_PLUG_STATUS:
 356         case CS42L42_LOAD_DET_RCSTAT:
 357         case CS42L42_LOAD_DET_DONE:
 358         case CS42L42_DET_STATUS1:
 359         case CS42L42_DET_STATUS2:
 360         case CS42L42_SOFT_RESET_REBOOT:
 361                 return true;
 362         default:
 363                 return false;
 364         }
 365 }
 366 EXPORT_SYMBOL_NS_GPL(cs42l42_volatile_register, SND_SOC_CS42L42_CORE);
 367
 368 const struct regmap_range_cfg cs42l42_page_range = {
 369         .name = "Pages",
 370         .range_min = 0,
 371         .range_max = CS42L42_MAX_REGISTER,
 372         .selector_reg = CS42L42_PAGE_REGISTER,
 373         .selector_mask = 0xff,
 374         .selector_shift = 0,
 375         .window_start = 0,
 376         .window_len = 256,
 377 };
 378 EXPORT_SYMBOL_NS_GPL(cs42l42_page_range, SND_SOC_CS42L42_CORE);
 379
 380 const struct regmap_config cs42l42_regmap = {
 381         .reg_bits = 8,
 382         .val_bits = 8,
 383
 384         .readable_reg = cs42l42_readable_register,
 385         .volatile_reg = cs42l42_volatile_register,
 386
 387         .ranges = &cs42l42_page_range,
 388         .num_ranges = 1,
 389
 390         .max_register = CS42L42_MAX_REGISTER,
 391         .reg_defaults = cs42l42_reg_defaults,
 392         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 393         .cache_type = REGCACHE_MAPLE,
 394
 395         .use_single_read = true,
 396         .use_single_write = true,
 397 };
 398 EXPORT_SYMBOL_NS_GPL(cs42l42_regmap, SND_SOC_CS42L42_CORE);
 399
 400 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
 401 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
 402
 403 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol,
 404                                   struct snd_ctl_elem_value *ucontrol)
 405 {
 406         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 407         u8 val;
 408
 409         /* all bits of SLOW_START_EN must change together */
 410         switch (ucontrol->value.integer.value[0]) {
 411         case 0:
 412                 val = 0;
 413                 break;
 414         case 1:
 415                 val = CS42L42_SLOW_START_EN_MASK;
 416                 break;
 417         default:
 418                 return -EINVAL;
 419         }
 420
 421         return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE,
 422                                              CS42L42_SLOW_START_EN_MASK, val);
 423 }
 424
 425 static const char * const cs42l42_hpf_freq_text[] = {
 426         "1.86Hz", "120Hz", "235Hz", "466Hz"
 427 };
 428
 429 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 430                             CS42L42_ADC_HPF_CF_SHIFT,
 431                             cs42l42_hpf_freq_text);
 432
 433 static const char * const cs42l42_wnf3_freq_text[] = {
 434         "160Hz", "180Hz", "200Hz", "220Hz",
 435         "240Hz", "260Hz", "280Hz", "300Hz"
 436 };
 437
 438 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 439                             CS42L42_ADC_WNF_CF_SHIFT,
 440                             cs42l42_wnf3_freq_text);
 441
 442 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 443         /* ADC Volume and Filter Controls */
 444         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 445                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
 446         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 447                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 448         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 449                                 CS42L42_ADC_INV_SHIFT, true, false),
 450         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 451                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 452         SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
 453         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 454                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 455         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 456                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 457         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 458         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 459
 460         /* DAC Volume and Filter Controls */
 461         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 462                                 CS42L42_DACA_INV_SHIFT, true, false),
 463         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 464                                 CS42L42_DACB_INV_SHIFT, true, false),
 465         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 466                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 467         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 468                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 469                                 0x3f, 1, mixer_tlv),
 470
 471         SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE,
 472                         CS42L42_SLOW_START_EN_SHIFT, true, false,
 473                         snd_soc_get_volsw, cs42l42_slow_start_put),
 474 };
 475
 476 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w,
 477                              struct snd_kcontrol *kcontrol, int event)
 478 {
 479         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 480         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 481
 482         switch (event) {
 483         case SND_SOC_DAPM_PRE_PMU:
 484                 cs42l42->hp_adc_up_pending = true;
 485                 break;
 486         case SND_SOC_DAPM_POST_PMU:
 487                 /* Only need one delay if HP and ADC are both powering-up */
 488                 if (cs42l42->hp_adc_up_pending) {
 489                         usleep_range(CS42L42_HP_ADC_EN_TIME_US,
 490                                      CS42L42_HP_ADC_EN_TIME_US + 1000);
 491                         cs42l42->hp_adc_up_pending = false;
 492                 }
 493                 break;
 494         default:
 495                 break;
 496         }
 497
 498         return 0;
 499 }
 500
 501 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 502         /* Playback Path */
 503         SND_SOC_DAPM_OUTPUT("HP"),
 504         SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1,
 505                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 506         SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
 507         SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
 508         SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
 509
 510         /* Playback Requirements */
 511         SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
 512
 513         /* Capture Path */
 514         SND_SOC_DAPM_INPUT("HS"),
 515         SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1,
 516                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 517         SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
 518         SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
 519
 520         /* Capture Requirements */
 521         SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
 522         SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
 523
 524         /* Playback/Capture Requirements */
 525         SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
 526
 527         /* Soundwire SRC power control */
 528         SND_SOC_DAPM_PGA("DACSRC", CS42L42_PWR_CTL2, CS42L42_DAC_SRC_PDNB_SHIFT, 0, NULL, 0),
 529         SND_SOC_DAPM_PGA("ADCSRC", CS42L42_PWR_CTL2, CS42L42_ADC_SRC_PDNB_SHIFT, 0, NULL, 0),
 530 };
 531
 532 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 533         /* Playback Path */
 534         {"HP", NULL, "DAC"},
 535         {"DAC", NULL, "MIXER"},
 536         {"MIXER", NULL, "SDIN1"},
 537         {"MIXER", NULL, "SDIN2"},
 538         {"SDIN1", NULL, "Playback"},
 539         {"SDIN2", NULL, "Playback"},
 540
 541         /* Playback Requirements */
 542         {"SDIN1", NULL, "ASP DAI0"},
 543         {"SDIN2", NULL, "ASP DAI0"},
 544         {"SDIN1", NULL, "SCLK"},
 545         {"SDIN2", NULL, "SCLK"},
 546
 547         /* Capture Path */
 548         {"ADC", NULL, "HS"},
 549         { "SDOUT1", NULL, "ADC" },
 550         { "SDOUT2", NULL, "ADC" },
 551         { "Capture", NULL, "SDOUT1" },
 552         { "Capture", NULL, "SDOUT2" },
 553
 554         /* Capture Requirements */
 555         { "SDOUT1", NULL, "ASP DAO0" },
 556         { "SDOUT2", NULL, "ASP DAO0" },
 557         { "SDOUT1", NULL, "SCLK" },
 558         { "SDOUT2", NULL, "SCLK" },
 559         { "SDOUT1", NULL, "ASP TX EN" },
 560         { "SDOUT2", NULL, "ASP TX EN" },
 561 };
 562
 563 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
 564 {
 565         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 566
 567         /* Prevent race with interrupt handler */
 568         mutex_lock(&cs42l42->irq_lock);
 569         cs42l42->jack = jk;
 570
 571         if (jk) {
 572                 switch (cs42l42->hs_type) {
 573                 case CS42L42_PLUG_CTIA:
 574                 case CS42L42_PLUG_OMTP:
 575                         snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET);
 576                         break;
 577                 case CS42L42_PLUG_HEADPHONE:
 578                         snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE);
 579                         break;
 580                 default:
 581                         break;
 582                 }
 583         }
 584         mutex_unlock(&cs42l42->irq_lock);
 585
 586         return 0;
 587 }
 588
 589 const struct snd_soc_component_driver cs42l42_soc_component = {
 590         .set_jack               = cs42l42_set_jack,
 591         .dapm_widgets           = cs42l42_dapm_widgets,
 592         .num_dapm_widgets       = ARRAY_SIZE(cs42l42_dapm_widgets),
 593         .dapm_routes            = cs42l42_audio_map,
 594         .num_dapm_routes        = ARRAY_SIZE(cs42l42_audio_map),
 595         .controls               = cs42l42_snd_controls,
 596         .num_controls           = ARRAY_SIZE(cs42l42_snd_controls),
 597         .endianness             = 1,
 598 };
 599 EXPORT_SYMBOL_NS_GPL(cs42l42_soc_component, SND_SOC_CS42L42_CORE);
 600
 601 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
 602 static const struct reg_sequence cs42l42_to_sclk_seq[] = {
 603         {
 604                 .reg = CS42L42_OSC_SWITCH,
 605                 .def = CS42L42_SCLK_PRESENT_MASK,
 606                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 607         },
 608 };
 609
 610 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
 611 static const struct reg_sequence cs42l42_to_osc_seq[] = {
 612         {
 613                 .reg = CS42L42_OSC_SWITCH,
 614                 .def = 0,
 615                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 616         },
 617 };
 618
 619 struct cs42l42_pll_params {
 620         u32 sclk;
 621         u8 mclk_src_sel;
 622         u8 sclk_prediv;
 623         u8 pll_div_int;
 624         u32 pll_div_frac;
 625         u8 pll_mode;
 626         u8 pll_divout;
 627         u32 mclk_int;
 628         u8 pll_cal_ratio;
 629         u8 n;
 630 };
 631
 632 /*
 633  * Common PLL Settings for given SCLK
 634  * Table 4-5 from the Datasheet
 635  */
 636 static const struct cs42l42_pll_params pll_ratio_table[] = {
 637         { 1411200,  1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
 638         { 1536000,  1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
 639         { 2304000,  1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},
 640         { 2400000,  1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
 641         { 2822400,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 642         { 3000000,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 643         { 3072000,  1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 644         { 4000000,  1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},
 645         { 4096000,  1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},
 646         { 4800000,  1, 0x01, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
 647         { 4800000,  1, 0x01, 0x50, 0x000000, 0x01, 0x10, 12288000,  82, 2},
 648         { 5644800,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 649         { 6000000,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 650         { 6144000,  1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 651         { 6144000,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1},
 652         { 9600000,  1, 0x02, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
 653         { 9600000,  1, 0x02, 0x50, 0x000000, 0x01, 0x10, 12288000,  82, 2},
 654         { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
 655         { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
 656         { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
 657         { 19200000, 1, 0x03, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
 658         { 19200000, 1, 0x03, 0x50, 0x000000, 0x01, 0x10, 12288000,  82, 2},
 659         { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 660         { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 661         { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}
 662 };
 663
 664 int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk,
 665                        unsigned int sample_rate)
 666 {
 667         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 668         int i;
 669
 670         /* Don't reconfigure if there is an audio stream running */
 671         if (cs42l42->stream_use) {
 672                 if (pll_ratio_table[cs42l42->pll_config].sclk == clk)
 673                         return 0;
 674                 else
 675                         return -EBUSY;
 676         }
 677
 678         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 679                 /* MCLKint must be a multiple of the sample rate */
 680                 if (pll_ratio_table[i].mclk_int % sample_rate)
 681                         continue;
 682
 683                 if (pll_ratio_table[i].sclk == clk) {
 684                         cs42l42->pll_config = i;
 685
 686                         /* Configure the internal sample rate */
 687                         snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
 688                                         CS42L42_INTERNAL_FS_MASK,
 689                                         ((pll_ratio_table[i].mclk_int !=
 690                                         12000000) &&
 691                                         (pll_ratio_table[i].mclk_int !=
 692                                         24000000)) <<
 693                                         CS42L42_INTERNAL_FS_SHIFT);
 694                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 695                                 /* Pass the clock straight through */
 696                                 snd_soc_component_update_bits(component,
 697                                         CS42L42_PLL_CTL1,
 698                                         CS42L42_PLL_START_MASK, 0);
 699                         } else {
 700                                 /* Configure PLL per table 4-5 */
 701                                 snd_soc_component_update_bits(component,
 702                                         CS42L42_PLL_DIV_CFG1,
 703                                         CS42L42_SCLK_PREDIV_MASK,
 704                                         pll_ratio_table[i].sclk_prediv
 705                                         << CS42L42_SCLK_PREDIV_SHIFT);
 706                                 snd_soc_component_update_bits(component,
 707                                         CS42L42_PLL_DIV_INT,
 708                                         CS42L42_PLL_DIV_INT_MASK,
 709                                         pll_ratio_table[i].pll_div_int
 710                                         << CS42L42_PLL_DIV_INT_SHIFT);
 711                                 snd_soc_component_update_bits(component,
 712                                         CS42L42_PLL_DIV_FRAC0,
 713                                         CS42L42_PLL_DIV_FRAC_MASK,
 714                                         CS42L42_FRAC0_VAL(
 715                                         pll_ratio_table[i].pll_div_frac)
 716                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 717                                 snd_soc_component_update_bits(component,
 718                                         CS42L42_PLL_DIV_FRAC1,
 719                                         CS42L42_PLL_DIV_FRAC_MASK,
 720                                         CS42L42_FRAC1_VAL(
 721                                         pll_ratio_table[i].pll_div_frac)
 722                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 723                                 snd_soc_component_update_bits(component,
 724                                         CS42L42_PLL_DIV_FRAC2,
 725                                         CS42L42_PLL_DIV_FRAC_MASK,
 726                                         CS42L42_FRAC2_VAL(
 727                                         pll_ratio_table[i].pll_div_frac)
 728                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 729                                 snd_soc_component_update_bits(component,
 730                                         CS42L42_PLL_CTL4,
 731                                         CS42L42_PLL_MODE_MASK,
 732                                         pll_ratio_table[i].pll_mode
 733                                         << CS42L42_PLL_MODE_SHIFT);
 734                                 snd_soc_component_update_bits(component,
 735                                         CS42L42_PLL_CTL3,
 736                                         CS42L42_PLL_DIVOUT_MASK,
 737                                         (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
 738                                         << CS42L42_PLL_DIVOUT_SHIFT);
 739                                 snd_soc_component_update_bits(component,
 740                                         CS42L42_PLL_CAL_RATIO,
 741                                         CS42L42_PLL_CAL_RATIO_MASK,
 742                                         pll_ratio_table[i].pll_cal_ratio
 743                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 744                         }
 745                         return 0;
 746                 }
 747         }
 748
 749         return -EINVAL;
 750 }
 751 EXPORT_SYMBOL_NS_GPL(cs42l42_pll_config, SND_SOC_CS42L42_CORE);
 752
 753 void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
 754 {
 755         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 756         unsigned int fs;
 757
 758         /* Don't reconfigure if there is an audio stream running */
 759         if (cs42l42->stream_use)
 760                 return;
 761
 762         /* SRC MCLK must be as close as possible to 125 * sample rate */
 763         if (sample_rate <= 48000)
 764                 fs = CS42L42_CLK_IASRC_SEL_6;
 765         else
 766                 fs = CS42L42_CLK_IASRC_SEL_12;
 767
 768         /* Set the sample rates (96k or lower) */
 769         snd_soc_component_update_bits(component,
 770                                       CS42L42_FS_RATE_EN,
 771                                       CS42L42_FS_EN_MASK,
 772                                       (CS42L42_FS_EN_IASRC_96K |
 773                                        CS42L42_FS_EN_OASRC_96K) <<
 774                                       CS42L42_FS_EN_SHIFT);
 775
 776         snd_soc_component_update_bits(component,
 777                                       CS42L42_IN_ASRC_CLK,
 778                                       CS42L42_CLK_IASRC_SEL_MASK,
 779                                       fs << CS42L42_CLK_IASRC_SEL_SHIFT);
 780         snd_soc_component_update_bits(component,
 781                                       CS42L42_OUT_ASRC_CLK,
 782                                       CS42L42_CLK_OASRC_SEL_MASK,
 783                                       fs << CS42L42_CLK_OASRC_SEL_SHIFT);
 784 }
 785 EXPORT_SYMBOL_NS_GPL(cs42l42_src_config, SND_SOC_CS42L42_CORE);
 786
 787 static int cs42l42_asp_config(struct snd_soc_component *component,
 788                               unsigned int sclk, unsigned int sample_rate)
 789 {
 790         u32 fsync = sclk / sample_rate;
 791
 792         /* Set up the LRCLK */
 793         if (((fsync * sample_rate) != sclk) || ((fsync % 2) != 0)) {
 794                 dev_err(component->dev,
 795                         "Unsupported sclk %d/sample rate %d\n",
 796                         sclk,
 797                         sample_rate);
 798                 return -EINVAL;
 799         }
 800         /* Set the LRCLK period */
 801         snd_soc_component_update_bits(component,
 802                                       CS42L42_FSYNC_P_LOWER,
 803                                       CS42L42_FSYNC_PERIOD_MASK,
 804                                       CS42L42_FRAC0_VAL(fsync - 1) <<
 805                                       CS42L42_FSYNC_PERIOD_SHIFT);
 806         snd_soc_component_update_bits(component,
 807                                       CS42L42_FSYNC_P_UPPER,
 808                                       CS42L42_FSYNC_PERIOD_MASK,
 809                                       CS42L42_FRAC1_VAL(fsync - 1) <<
 810                                       CS42L42_FSYNC_PERIOD_SHIFT);
 811         /* Set the LRCLK to 50% duty cycle */
 812         fsync = fsync / 2;
 813         snd_soc_component_update_bits(component,
 814                                       CS42L42_FSYNC_PW_LOWER,
 815                                       CS42L42_FSYNC_PULSE_WIDTH_MASK,
 816                                       CS42L42_FRAC0_VAL(fsync - 1) <<
 817                                       CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 818         snd_soc_component_update_bits(component,
 819                                       CS42L42_FSYNC_PW_UPPER,
 820                                       CS42L42_FSYNC_PULSE_WIDTH_MASK,
 821                                       CS42L42_FRAC1_VAL(fsync - 1) <<
 822                                       CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 823
 824         return 0;
 825 }
 826
 827 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 828 {
 829         struct snd_soc_component *component = codec_dai->component;
 830         u32 asp_cfg_val = 0;
 831
 832         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 833         case SND_SOC_DAIFMT_CBS_CFM:
 834                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 835                                 CS42L42_ASP_MODE_SHIFT;
 836                 break;
 837         case SND_SOC_DAIFMT_CBS_CFS:
 838                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 839                                 CS42L42_ASP_MODE_SHIFT;
 840                 break;
 841         default:
 842                 return -EINVAL;
 843         }
 844
 845         /* interface format */
 846         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 847         case SND_SOC_DAIFMT_I2S:
 848                 /*
 849                  * 5050 mode, frame starts on falling edge of LRCLK,
 850                  * frame delayed by 1.0 SCLKs
 851                  */
 852                 snd_soc_component_update_bits(component,
 853                                               CS42L42_ASP_FRM_CFG,
 854                                               CS42L42_ASP_STP_MASK |
 855                                               CS42L42_ASP_5050_MASK |
 856                                               CS42L42_ASP_FSD_MASK,
 857                                               CS42L42_ASP_5050_MASK |
 858                                               (CS42L42_ASP_FSD_1_0 <<
 859                                                 CS42L42_ASP_FSD_SHIFT));
 860                 break;
 861         default:
 862                 return -EINVAL;
 863         }
 864
 865         /* Bitclock/frame inversion */
 866         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 867         case SND_SOC_DAIFMT_NB_NF:
 868                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 869                 break;
 870         case SND_SOC_DAIFMT_NB_IF:
 871                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 872                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 873                 break;
 874         case SND_SOC_DAIFMT_IB_NF:
 875                 break;
 876         case SND_SOC_DAIFMT_IB_IF:
 877                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 878                 break;
 879         }
 880
 881         snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
 882                                                                       CS42L42_ASP_SCPOL_MASK |
 883                                                                       CS42L42_ASP_LCPOL_MASK,
 884                                                                       asp_cfg_val);
 885
 886         return 0;
 887 }
 888
 889 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
 890 {
 891         struct snd_soc_component *component = dai->component;
 892         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 893
 894         /*
 895          * Sample rates < 44.1 kHz would produce an out-of-range SCLK with
 896          * a standard I2S frame. If the machine driver sets SCLK it must be
 897          * legal.
 898          */
 899         if (cs42l42->sclk)
 900                 return 0;
 901
 902         /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
 903         return snd_pcm_hw_constraint_minmax(substream->runtime,
 904                                             SNDRV_PCM_HW_PARAM_RATE,
 905                                             44100, 96000);
 906 }
 907
 908 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 909                                 struct snd_pcm_hw_params *params,
 910                                 struct snd_soc_dai *dai)
 911 {
 912         struct snd_soc_component *component = dai->component;
 913         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 914         unsigned int channels = params_channels(params);
 915         unsigned int width = (params_width(params) / 8) - 1;
 916         unsigned int sample_rate = params_rate(params);
 917         unsigned int slot_width = 0;
 918         unsigned int val = 0;
 919         unsigned int bclk;
 920         int ret;
 921
 922         if (cs42l42->bclk_ratio) {
 923                 /* machine driver has set the BCLK/samp-rate ratio */
 924                 bclk = cs42l42->bclk_ratio * params_rate(params);
 925         } else if (cs42l42->sclk) {
 926                 /* machine driver has set the SCLK */
 927                 bclk = cs42l42->sclk;
 928         } else {
 929                 /*
 930                  * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
 931                  * more than assumed (which would result in overclocking).
 932                  */
 933                 if (params_width(params) == 24)
 934                         slot_width = 32;
 935
 936                 /* I2S frame always has multiple of 2 channels */
 937                 bclk = snd_soc_tdm_params_to_bclk(params, slot_width, 0, 2);
 938         }
 939
 940         switch (substream->stream) {
 941         case SNDRV_PCM_STREAM_CAPTURE:
 942                 /* channel 2 on high LRCLK */
 943                 val = CS42L42_ASP_TX_CH2_AP_MASK |
 944                       (width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
 945                       (width << CS42L42_ASP_TX_CH1_RES_SHIFT);
 946
 947                 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
 948                                 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
 949                                 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
 950                 break;
 951         case SNDRV_PCM_STREAM_PLAYBACK:
 952                 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
 953                 /* channel 1 on low LRCLK */
 954                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 955                                                          CS42L42_ASP_RX_CH_AP_MASK |
 956                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 957                 /* Channel 2 on high LRCLK */
 958                 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
 959                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 960                                                          CS42L42_ASP_RX_CH_AP_MASK |
 961                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 962
 963                 /* Channel B comes from the last active channel */
 964                 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
 965                                               CS42L42_SP_RX_CHB_SEL_MASK,
 966                                               (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
 967
 968                 /* Both LRCLK slots must be enabled */
 969                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 970                                               CS42L42_ASP_RX0_CH_EN_MASK,
 971                                               BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
 972                                               BIT(CS42L42_ASP_RX0_CH2_SHIFT));
 973                 break;
 974         default:
 975                 break;
 976         }
 977
 978         ret = cs42l42_pll_config(component, bclk, sample_rate);
 979         if (ret)
 980                 return ret;
 981
 982         ret = cs42l42_asp_config(component, bclk, sample_rate);
 983         if (ret)
 984                 return ret;
 985
 986         cs42l42_src_config(component, sample_rate);
 987
 988         return 0;
 989 }
 990
 991 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 992                                 int clk_id, unsigned int freq, int dir)
 993 {
 994         struct snd_soc_component *component = dai->component;
 995         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 996         int i;
 997
 998         if (freq == 0) {
 999                 cs42l42->sclk = 0;
1000                 return 0;
1001         }
1002
1003         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
1004                 if (pll_ratio_table[i].sclk == freq) {
1005                         cs42l42->sclk = freq;
1006                         return 0;
1007                 }
1008         }
1009
1010         dev_err(component->dev, "SCLK %u not supported\n", freq);
1011
1012         return -EINVAL;
1013 }
1014
1015 static int cs42l42_set_bclk_ratio(struct snd_soc_dai *dai,
1016                                 unsigned int bclk_ratio)
1017 {
1018         struct snd_soc_component *component = dai->component;
1019         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
1020
1021         cs42l42->bclk_ratio = bclk_ratio;
1022
1023         return 0;
1024 }
1025
1026 int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
1027 {
1028         struct snd_soc_component *component = dai->component;
1029         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
1030         unsigned int regval;
1031         int ret;
1032
1033         if (mute) {
1034                 /* Mute the headphone */
1035                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
1036                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1037                                                       CS42L42_HP_ANA_AMUTE_MASK |
1038                                                       CS42L42_HP_ANA_BMUTE_MASK,
1039                                                       CS42L42_HP_ANA_AMUTE_MASK |
1040                                                       CS42L42_HP_ANA_BMUTE_MASK);
1041
1042                 cs42l42->stream_use &= ~(1 << stream);
1043                 if (!cs42l42->stream_use) {
1044                         /*
1045                          * Switch to the internal oscillator.
1046                          * SCLK must remain running until after this clock switch.
1047                          * Without a source of clock the I2C bus doesn't work.
1048                          */
1049                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
1050                                                ARRAY_SIZE(cs42l42_to_osc_seq));
1051
1052                         /* Must disconnect PLL before stopping it */
1053                         snd_soc_component_update_bits(component,
1054                                                       CS42L42_MCLK_SRC_SEL,
1055                                                       CS42L42_MCLK_SRC_SEL_MASK,
1056                                                       0);
1057                         usleep_range(100, 200);
1058
1059                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1060                                                       CS42L42_PLL_START_MASK, 0);
1061                 }
1062         } else {
1063                 if (!cs42l42->stream_use) {
1064                         /* SCLK must be running before codec unmute.
1065                          *
1066                          * PLL must not be started with ADC and HP both off
1067                          * otherwise the FILT+ supply will not charge properly.
1068                          * DAPM widgets power-up before stream unmute so at least
1069                          * one of the "DAC" or "ADC" widgets will already have
1070                          * powered-up.
1071                          */
1072                         if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
1073                                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1074                                                               CS42L42_PLL_START_MASK, 1);
1075
1076                                 if (pll_ratio_table[cs42l42->pll_config].n > 1) {
1077                                         usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
1078                                                      CS42L42_PLL_DIVOUT_TIME_US * 2);
1079                                         regval = pll_ratio_table[cs42l42->pll_config].pll_divout;
1080                                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
1081                                                                       CS42L42_PLL_DIVOUT_MASK,
1082                                                                       regval <<
1083                                                                       CS42L42_PLL_DIVOUT_SHIFT);
1084                                 }
1085
1086                                 ret = regmap_read_poll_timeout(cs42l42->regmap,
1087                                                                CS42L42_PLL_LOCK_STATUS,
1088                                                                regval,
1089                                                                (regval & 1),
1090                                                                CS42L42_PLL_LOCK_POLL_US,
1091                                                                CS42L42_PLL_LOCK_TIMEOUT_US);
1092                                 if (ret < 0)
1093                                         dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
1094
1095                                 /* PLL must be running to drive glitchless switch logic */
1096                                 snd_soc_component_update_bits(component,
1097                                                               CS42L42_MCLK_SRC_SEL,
1098                                                               CS42L42_MCLK_SRC_SEL_MASK,
1099                                                               CS42L42_MCLK_SRC_SEL_MASK);
1100                         }
1101
1102                         /* Mark SCLK as present, turn off internal oscillator */
1103                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
1104                                                ARRAY_SIZE(cs42l42_to_sclk_seq));
1105                 }
1106                 cs42l42->stream_use |= 1 << stream;
1107
1108                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1109                         /* Un-mute the headphone */
1110                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1111                                                       CS42L42_HP_ANA_AMUTE_MASK |
1112                                                       CS42L42_HP_ANA_BMUTE_MASK,
1113                                                       0);
1114                 }
1115         }
1116
1117         return 0;
1118 }
1119 EXPORT_SYMBOL_NS_GPL(cs42l42_mute_stream, SND_SOC_CS42L42_CORE);
1120
1121 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1122                          SNDRV_PCM_FMTBIT_S24_LE |\
1123                          SNDRV_PCM_FMTBIT_S32_LE)
1124
1125 static const struct snd_soc_dai_ops cs42l42_ops = {
1126         .startup        = cs42l42_dai_startup,
1127         .hw_params      = cs42l42_pcm_hw_params,
1128         .set_fmt        = cs42l42_set_dai_fmt,
1129         .set_sysclk     = cs42l42_set_sysclk,
1130         .set_bclk_ratio = cs42l42_set_bclk_ratio,
1131         .mute_stream    = cs42l42_mute_stream,
1132 };
1133
1134 struct snd_soc_dai_driver cs42l42_dai = {
1135                 .name = "cs42l42",
1136                 .playback = {
1137                         .stream_name = "Playback",
1138                         .channels_min = 1,
1139                         .channels_max = 2,
1140                         .rates = SNDRV_PCM_RATE_8000_96000,
1141                         .formats = CS42L42_FORMATS,
1142                 },
1143                 .capture = {
1144                         .stream_name = "Capture",
1145                         .channels_min = 1,
1146                         .channels_max = 2,
1147                         .rates = SNDRV_PCM_RATE_8000_96000,
1148                         .formats = CS42L42_FORMATS,
1149                 },
1150                 .symmetric_rate = 1,
1151                 .symmetric_sample_bits = 1,
1152                 .ops = &cs42l42_ops,
1153 };
1154 EXPORT_SYMBOL_NS_GPL(cs42l42_dai, SND_SOC_CS42L42_CORE);
1155
1156 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42)
1157 {
1158         unsigned int hs_det_status;
1159         unsigned int hs_det_comp1;
1160         unsigned int hs_det_comp2;
1161         unsigned int hs_det_sw;
1162
1163         /* Set hs detect to manual, active mode */
1164         regmap_update_bits(cs42l42->regmap,
1165                 CS42L42_HSDET_CTL2,
1166                 CS42L42_HSDET_CTRL_MASK |
1167                 CS42L42_HSDET_SET_MASK |
1168                 CS42L42_HSBIAS_REF_MASK |
1169                 CS42L42_HSDET_AUTO_TIME_MASK,
1170                 (1 << CS42L42_HSDET_CTRL_SHIFT) |
1171                 (0 << CS42L42_HSDET_SET_SHIFT) |
1172                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1173                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1174
1175         /* Configure HS DET comparator reference levels. */
1176         regmap_update_bits(cs42l42->regmap,
1177                                 CS42L42_HSDET_CTL1,
1178                                 CS42L42_HSDET_COMP1_LVL_MASK |
1179                                 CS42L42_HSDET_COMP2_LVL_MASK,
1180                                 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1181                                 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
1182
1183         /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
1184         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
1185
1186         msleep(100);
1187
1188         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1189
1190         hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1191                         CS42L42_HSDET_COMP1_OUT_SHIFT;
1192         hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1193                         CS42L42_HSDET_COMP2_OUT_SHIFT;
1194
1195         /* Close the SW_HSB_HS3 switch for a Type 2 headset. */
1196         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
1197
1198         msleep(100);
1199
1200         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1201
1202         hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1203                         CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
1204         hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1205                         CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
1206
1207         /* Use Comparator 1 with 1.25V Threshold. */
1208         switch (hs_det_comp1) {
1209         case CS42L42_HSDET_COMP_TYPE1:
1210                 cs42l42->hs_type = CS42L42_PLUG_CTIA;
1211                 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1212                 break;
1213         case CS42L42_HSDET_COMP_TYPE2:
1214                 cs42l42->hs_type = CS42L42_PLUG_OMTP;
1215                 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1216                 break;
1217         default:
1218                 /* Fallback to Comparator 2 with 1.75V Threshold. */
1219                 switch (hs_det_comp2) {
1220                 case CS42L42_HSDET_COMP_TYPE1:
1221                         cs42l42->hs_type = CS42L42_PLUG_CTIA;
1222                         hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1223                         break;
1224                 case CS42L42_HSDET_COMP_TYPE2:
1225                         cs42l42->hs_type = CS42L42_PLUG_OMTP;
1226                         hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1227                         break;
1228                 /* Detect Type 3 and Type 4 Headsets as Headphones */
1229                 default:
1230                         cs42l42->hs_type = CS42L42_PLUG_HEADPHONE;
1231                         hs_det_sw = CS42L42_HSDET_SW_TYPE3;
1232                         break;
1233                 }
1234         }
1235
1236         /* Set Switches */
1237         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw);
1238
1239         /* Set HSDET mode to Manual—Disabled */
1240         regmap_update_bits(cs42l42->regmap,
1241                 CS42L42_HSDET_CTL2,
1242                 CS42L42_HSDET_CTRL_MASK |
1243                 CS42L42_HSDET_SET_MASK |
1244                 CS42L42_HSBIAS_REF_MASK |
1245                 CS42L42_HSDET_AUTO_TIME_MASK,
1246                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1247                 (0 << CS42L42_HSDET_SET_SHIFT) |
1248                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1249                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1250
1251         /* Configure HS DET comparator reference levels. */
1252         regmap_update_bits(cs42l42->regmap,
1253                                 CS42L42_HSDET_CTL1,
1254                                 CS42L42_HSDET_COMP1_LVL_MASK |
1255                                 CS42L42_HSDET_COMP2_LVL_MASK,
1256                                 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1257                                 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
1258 }
1259
1260 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
1261 {
1262         unsigned int hs_det_status;
1263         unsigned int int_status;
1264
1265         /* Read and save the hs detection result */
1266         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1267
1268         /* Mask the auto detect interrupt */
1269         regmap_update_bits(cs42l42->regmap,
1270                 CS42L42_CODEC_INT_MASK,
1271                 CS42L42_PDN_DONE_MASK |
1272                 CS42L42_HSDET_AUTO_DONE_MASK,
1273                 (1 << CS42L42_PDN_DONE_SHIFT) |
1274                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1275
1276
1277         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1278                                 CS42L42_HSDET_TYPE_SHIFT;
1279
1280         /* Set hs detect to automatic, disabled mode */
1281         regmap_update_bits(cs42l42->regmap,
1282                 CS42L42_HSDET_CTL2,
1283                 CS42L42_HSDET_CTRL_MASK |
1284                 CS42L42_HSDET_SET_MASK |
1285                 CS42L42_HSBIAS_REF_MASK |
1286                 CS42L42_HSDET_AUTO_TIME_MASK,
1287                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
1288                 (2 << CS42L42_HSDET_SET_SHIFT) |
1289                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1290                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1291
1292         /* Run Manual detection if auto detect has not found a headset.
1293          * We Re-Run with Manual Detection if the original detection was invalid or headphones,
1294          * to ensure that a headset mic is detected in all cases.
1295          */
1296         if (cs42l42->hs_type == CS42L42_PLUG_INVALID ||
1297                 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) {
1298                 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n");
1299                 cs42l42_manual_hs_type_detect(cs42l42);
1300         }
1301
1302         /* Set up button detection */
1303         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1304               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1305                 /* Set auto HS bias settings to default */
1306                 regmap_update_bits(cs42l42->regmap,
1307                         CS42L42_HSBIAS_SC_AUTOCTL,
1308                         CS42L42_HSBIAS_SENSE_EN_MASK |
1309                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1310                         CS42L42_TIP_SENSE_EN_MASK |
1311                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1312                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1313                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1314                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1315                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1316
1317                 /* Set up hs detect level sensitivity */
1318                 regmap_update_bits(cs42l42->regmap,
1319                         CS42L42_MIC_DET_CTL1,
1320                         CS42L42_LATCH_TO_VP_MASK |
1321                         CS42L42_EVENT_STAT_SEL_MASK |
1322                         CS42L42_HS_DET_LEVEL_MASK,
1323                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1324                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1325                         (cs42l42->bias_thresholds[0] <<
1326                         CS42L42_HS_DET_LEVEL_SHIFT));
1327
1328                 /* Set auto HS bias settings to default */
1329                 regmap_update_bits(cs42l42->regmap,
1330                         CS42L42_HSBIAS_SC_AUTOCTL,
1331                         CS42L42_HSBIAS_SENSE_EN_MASK |
1332                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1333                         CS42L42_TIP_SENSE_EN_MASK |
1334                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1335                         (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1336                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1337                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1338                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1339
1340                 /* Turn on level detect circuitry */
1341                 regmap_update_bits(cs42l42->regmap,
1342                         CS42L42_MISC_DET_CTL,
1343                         CS42L42_HSBIAS_CTL_MASK |
1344                         CS42L42_PDN_MIC_LVL_DET_MASK,
1345                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1346                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1347
1348                 msleep(cs42l42->btn_det_init_dbnce);
1349
1350                 /* Clear any button interrupts before unmasking them */
1351                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1352                             &int_status);
1353
1354                 /* Unmask button detect interrupts */
1355                 regmap_update_bits(cs42l42->regmap,
1356                         CS42L42_DET_INT2_MASK,
1357                         CS42L42_M_DETECT_TF_MASK |
1358                         CS42L42_M_DETECT_FT_MASK |
1359                         CS42L42_M_HSBIAS_HIZ_MASK |
1360                         CS42L42_M_SHORT_RLS_MASK |
1361                         CS42L42_M_SHORT_DET_MASK,
1362                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1363                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1364                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1365                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1366                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1367         } else {
1368                 /* Make sure button detect and HS bias circuits are off */
1369                 regmap_update_bits(cs42l42->regmap,
1370                         CS42L42_MISC_DET_CTL,
1371                         CS42L42_HSBIAS_CTL_MASK |
1372                         CS42L42_PDN_MIC_LVL_DET_MASK,
1373                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1374                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1375         }
1376
1377         regmap_update_bits(cs42l42->regmap,
1378                                 CS42L42_DAC_CTL2,
1379                                 CS42L42_HPOUT_PULLDOWN_MASK |
1380                                 CS42L42_HPOUT_LOAD_MASK |
1381                                 CS42L42_HPOUT_CLAMP_MASK |
1382                                 CS42L42_DAC_HPF_EN_MASK |
1383                                 CS42L42_DAC_MON_EN_MASK,
1384                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1385                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1386                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1387                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1388                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1389
1390         /* Unmask tip sense interrupts */
1391         regmap_update_bits(cs42l42->regmap,
1392                 CS42L42_TSRS_PLUG_INT_MASK,
1393                 CS42L42_TS_PLUG_MASK |
1394                 CS42L42_TS_UNPLUG_MASK,
1395                 (0 << CS42L42_TS_PLUG_SHIFT) |
1396                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1397 }
1398
1399 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1400 {
1401         /* Mask tip sense interrupts */
1402         regmap_update_bits(cs42l42->regmap,
1403                                 CS42L42_TSRS_PLUG_INT_MASK,
1404                                 CS42L42_TS_PLUG_MASK |
1405                                 CS42L42_TS_UNPLUG_MASK,
1406                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1407                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1408
1409         /* Make sure button detect and HS bias circuits are off */
1410         regmap_update_bits(cs42l42->regmap,
1411                                 CS42L42_MISC_DET_CTL,
1412                                 CS42L42_HSBIAS_CTL_MASK |
1413                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1414                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1415                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1416
1417         /* Set auto HS bias settings to default */
1418         regmap_update_bits(cs42l42->regmap,
1419                                 CS42L42_HSBIAS_SC_AUTOCTL,
1420                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1421                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1422                                 CS42L42_TIP_SENSE_EN_MASK |
1423                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1424                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1425                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1426                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1427                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1428
1429         /* Set hs detect to manual, disabled mode */
1430         regmap_update_bits(cs42l42->regmap,
1431                                 CS42L42_HSDET_CTL2,
1432                                 CS42L42_HSDET_CTRL_MASK |
1433                                 CS42L42_HSDET_SET_MASK |
1434                                 CS42L42_HSBIAS_REF_MASK |
1435                                 CS42L42_HSDET_AUTO_TIME_MASK,
1436                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1437                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1438                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1439                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1440
1441         regmap_update_bits(cs42l42->regmap,
1442                                 CS42L42_DAC_CTL2,
1443                                 CS42L42_HPOUT_PULLDOWN_MASK |
1444                                 CS42L42_HPOUT_LOAD_MASK |
1445                                 CS42L42_HPOUT_CLAMP_MASK |
1446                                 CS42L42_DAC_HPF_EN_MASK |
1447                                 CS42L42_DAC_MON_EN_MASK,
1448                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1449                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1450                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1451                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1452                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1453
1454         /* Power up HS bias to 2.7V */
1455         regmap_update_bits(cs42l42->regmap,
1456                                 CS42L42_MISC_DET_CTL,
1457                                 CS42L42_HSBIAS_CTL_MASK |
1458                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1459                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1460                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1461
1462         /* Wait for HS bias to ramp up */
1463         msleep(cs42l42->hs_bias_ramp_time);
1464
1465         /* Unmask auto detect interrupt */
1466         regmap_update_bits(cs42l42->regmap,
1467                                 CS42L42_CODEC_INT_MASK,
1468                                 CS42L42_PDN_DONE_MASK |
1469                                 CS42L42_HSDET_AUTO_DONE_MASK,
1470                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1471                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1472
1473         /* Set hs detect to automatic, enabled mode */
1474         regmap_update_bits(cs42l42->regmap,
1475                                 CS42L42_HSDET_CTL2,
1476                                 CS42L42_HSDET_CTRL_MASK |
1477                                 CS42L42_HSDET_SET_MASK |
1478                                 CS42L42_HSBIAS_REF_MASK |
1479                                 CS42L42_HSDET_AUTO_TIME_MASK,
1480                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1481                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1482                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1483                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1484 }
1485
1486 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1487 {
1488         /* Mask button detect interrupts */
1489         regmap_update_bits(cs42l42->regmap,
1490                 CS42L42_DET_INT2_MASK,
1491                 CS42L42_M_DETECT_TF_MASK |
1492                 CS42L42_M_DETECT_FT_MASK |
1493                 CS42L42_M_HSBIAS_HIZ_MASK |
1494                 CS42L42_M_SHORT_RLS_MASK |
1495                 CS42L42_M_SHORT_DET_MASK,
1496                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1497                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1498                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1499                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1500                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1501
1502         /* Ground HS bias */
1503         regmap_update_bits(cs42l42->regmap,
1504                                 CS42L42_MISC_DET_CTL,
1505                                 CS42L42_HSBIAS_CTL_MASK |
1506                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1507                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1508                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1509
1510         /* Set auto HS bias settings to default */
1511         regmap_update_bits(cs42l42->regmap,
1512                                 CS42L42_HSBIAS_SC_AUTOCTL,
1513                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1514                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1515                                 CS42L42_TIP_SENSE_EN_MASK |
1516                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1517                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1518                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1519                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1520                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1521
1522         /* Set hs detect to manual, disabled mode */
1523         regmap_update_bits(cs42l42->regmap,
1524                                 CS42L42_HSDET_CTL2,
1525                                 CS42L42_HSDET_CTRL_MASK |
1526                                 CS42L42_HSDET_SET_MASK |
1527                                 CS42L42_HSBIAS_REF_MASK |
1528                                 CS42L42_HSDET_AUTO_TIME_MASK,
1529                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1530                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1531                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1532                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1533 }
1534
1535 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1536 {
1537         int bias_level;
1538         unsigned int detect_status;
1539
1540         /* Mask button detect interrupts */
1541         regmap_update_bits(cs42l42->regmap,
1542                 CS42L42_DET_INT2_MASK,
1543                 CS42L42_M_DETECT_TF_MASK |
1544                 CS42L42_M_DETECT_FT_MASK |
1545                 CS42L42_M_HSBIAS_HIZ_MASK |
1546                 CS42L42_M_SHORT_RLS_MASK |
1547                 CS42L42_M_SHORT_DET_MASK,
1548                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1549                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1550                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1551                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1552                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1553
1554         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1555                      cs42l42->btn_det_event_dbnce * 2000);
1556
1557         /* Test all 4 level detect biases */
1558         bias_level = 1;
1559         do {
1560                 /* Adjust button detect level sensitivity */
1561                 regmap_update_bits(cs42l42->regmap,
1562                         CS42L42_MIC_DET_CTL1,
1563                         CS42L42_LATCH_TO_VP_MASK |
1564                         CS42L42_EVENT_STAT_SEL_MASK |
1565                         CS42L42_HS_DET_LEVEL_MASK,
1566                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1567                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1568                         (cs42l42->bias_thresholds[bias_level] <<
1569                         CS42L42_HS_DET_LEVEL_SHIFT));
1570
1571                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1572                                 &detect_status);
1573         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1574                 (++bias_level < CS42L42_NUM_BIASES));
1575
1576         switch (bias_level) {
1577         case 1: /* Function C button press */
1578                 bias_level = SND_JACK_BTN_2;
1579                 dev_dbg(cs42l42->dev, "Function C button press\n");
1580                 break;
1581         case 2: /* Function B button press */
1582                 bias_level = SND_JACK_BTN_1;
1583                 dev_dbg(cs42l42->dev, "Function B button press\n");
1584                 break;
1585         case 3: /* Function D button press */
1586                 bias_level = SND_JACK_BTN_3;
1587                 dev_dbg(cs42l42->dev, "Function D button press\n");
1588                 break;
1589         case 4: /* Function A button press */
1590                 bias_level = SND_JACK_BTN_0;
1591                 dev_dbg(cs42l42->dev, "Function A button press\n");
1592                 break;
1593         default:
1594                 bias_level = 0;
1595                 break;
1596         }
1597
1598         /* Set button detect level sensitivity back to default */
1599         regmap_update_bits(cs42l42->regmap,
1600                 CS42L42_MIC_DET_CTL1,
1601                 CS42L42_LATCH_TO_VP_MASK |
1602                 CS42L42_EVENT_STAT_SEL_MASK |
1603                 CS42L42_HS_DET_LEVEL_MASK,
1604                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1605                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1606                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1607
1608         /* Clear any button interrupts before unmasking them */
1609         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1610                     &detect_status);
1611
1612         /* Unmask button detect interrupts */
1613         regmap_update_bits(cs42l42->regmap,
1614                 CS42L42_DET_INT2_MASK,
1615                 CS42L42_M_DETECT_TF_MASK |
1616                 CS42L42_M_DETECT_FT_MASK |
1617                 CS42L42_M_HSBIAS_HIZ_MASK |
1618                 CS42L42_M_SHORT_RLS_MASK |
1619                 CS42L42_M_SHORT_DET_MASK,
1620                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1621                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1622                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1623                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1624                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1625
1626         return bias_level;
1627 }
1628
1629 struct cs42l42_irq_params {
1630         u16 status_addr;
1631         u16 mask_addr;
1632         u8 mask;
1633 };
1634
1635 static const struct cs42l42_irq_params irq_params_table[] = {
1636         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1637                 CS42L42_ADC_OVFL_VAL_MASK},
1638         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1639                 CS42L42_MIXER_VAL_MASK},
1640         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1641                 CS42L42_SRC_VAL_MASK},
1642         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1643                 CS42L42_ASP_RX_VAL_MASK},
1644         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1645                 CS42L42_ASP_TX_VAL_MASK},
1646         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1647                 CS42L42_CODEC_VAL_MASK},
1648         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1649                 CS42L42_DET_INT_VAL1_MASK},
1650         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1651                 CS42L42_DET_INT_VAL2_MASK},
1652         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1653                 CS42L42_SRCPL_VAL_MASK},
1654         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1655                 CS42L42_VPMON_VAL_MASK},
1656         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1657                 CS42L42_PLL_LOCK_VAL_MASK},
1658         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1659                 CS42L42_TSRS_PLUG_VAL_MASK}
1660 };
1661
1662 irqreturn_t cs42l42_irq_thread(int irq, void *data)
1663 {
1664         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1665         unsigned int stickies[12];
1666         unsigned int masks[12];
1667         unsigned int current_plug_status;
1668         unsigned int current_button_status;
1669         unsigned int i;
1670
1671         pm_runtime_get_sync(cs42l42->dev);
1672         mutex_lock(&cs42l42->irq_lock);
1673         if (cs42l42->suspended || !cs42l42->init_done) {
1674                 mutex_unlock(&cs42l42->irq_lock);
1675                 pm_runtime_put_autosuspend(cs42l42->dev);
1676                 return IRQ_NONE;
1677         }
1678
1679         /* Read sticky registers to clear interurpt */
1680         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1681                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1682                                 &(stickies[i]));
1683                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1684                                 &(masks[i]));
1685                 stickies[i] = stickies[i] & (~masks[i]) &
1686                                 irq_params_table[i].mask;
1687         }
1688
1689         /* Read tip sense status before handling type detect */
1690         current_plug_status = (stickies[11] &
1691                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1692                 CS42L42_TS_PLUG_SHIFT;
1693
1694         /* Read button sense status */
1695         current_button_status = stickies[7] &
1696                 (CS42L42_M_DETECT_TF_MASK |
1697                 CS42L42_M_DETECT_FT_MASK |
1698                 CS42L42_M_HSBIAS_HIZ_MASK);
1699
1700         /*
1701          * Check auto-detect status. Don't assume a previous unplug event has
1702          * cleared the flags. If the jack is unplugged and plugged during
1703          * system suspend there won't have been an unplug event.
1704          */
1705         if ((~masks[5]) & irq_params_table[5].mask) {
1706                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1707                         cs42l42_process_hs_type_detect(cs42l42);
1708                         switch (cs42l42->hs_type) {
1709                         case CS42L42_PLUG_CTIA:
1710                         case CS42L42_PLUG_OMTP:
1711                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1712                                                     SND_JACK_HEADSET |
1713                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1714                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1715                                 break;
1716                         case CS42L42_PLUG_HEADPHONE:
1717                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1718                                                     SND_JACK_HEADSET |
1719                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1720                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1721                                 break;
1722                         default:
1723                                 break;
1724                         }
1725                         dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1726                 }
1727         }
1728
1729         /* Check tip sense status */
1730         if ((~masks[11]) & irq_params_table[11].mask) {
1731                 switch (current_plug_status) {
1732                 case CS42L42_TS_PLUG:
1733                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1734                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1735                                 cs42l42_init_hs_type_detect(cs42l42);
1736                         }
1737                         break;
1738
1739                 case CS42L42_TS_UNPLUG:
1740                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1741                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1742                                 cs42l42_cancel_hs_type_detect(cs42l42);
1743
1744                                 snd_soc_jack_report(cs42l42->jack, 0,
1745                                                     SND_JACK_HEADSET |
1746                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1747                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1748
1749                                 dev_dbg(cs42l42->dev, "Unplug event\n");
1750                         }
1751                         break;
1752
1753                 default:
1754                         cs42l42->plug_state = CS42L42_TS_TRANS;
1755                 }
1756         }
1757
1758         /* Check button detect status */
1759         if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
1760                 if (!(current_button_status &
1761                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1762
1763                         if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1764                                 dev_dbg(cs42l42->dev, "Button released\n");
1765                                 snd_soc_jack_report(cs42l42->jack, 0,
1766                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1767                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1768                         } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1769                                 snd_soc_jack_report(cs42l42->jack,
1770                                                     cs42l42_handle_button_press(cs42l42),
1771                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1772                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1773                         }
1774                 }
1775         }
1776
1777         mutex_unlock(&cs42l42->irq_lock);
1778         pm_runtime_mark_last_busy(cs42l42->dev);
1779         pm_runtime_put_autosuspend(cs42l42->dev);
1780
1781         return IRQ_HANDLED;
1782 }
1783 EXPORT_SYMBOL_NS_GPL(cs42l42_irq_thread, SND_SOC_CS42L42_CORE);
1784
1785 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1786 {
1787         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1788                         CS42L42_ADC_OVFL_MASK,
1789                         (1 << CS42L42_ADC_OVFL_SHIFT));
1790
1791         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1792                         CS42L42_MIX_CHB_OVFL_MASK |
1793                         CS42L42_MIX_CHA_OVFL_MASK |
1794                         CS42L42_EQ_OVFL_MASK |
1795                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1796                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1797                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1798                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1799                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1800
1801         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1802                         CS42L42_SRC_ILK_MASK |
1803                         CS42L42_SRC_OLK_MASK |
1804                         CS42L42_SRC_IUNLK_MASK |
1805                         CS42L42_SRC_OUNLK_MASK,
1806                         (1 << CS42L42_SRC_ILK_SHIFT) |
1807                         (1 << CS42L42_SRC_OLK_SHIFT) |
1808                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1809                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1810
1811         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1812                         CS42L42_ASPRX_NOLRCK_MASK |
1813                         CS42L42_ASPRX_EARLY_MASK |
1814                         CS42L42_ASPRX_LATE_MASK |
1815                         CS42L42_ASPRX_ERROR_MASK |
1816                         CS42L42_ASPRX_OVLD_MASK,
1817                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1818                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1819                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1820                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1821                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1822
1823         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1824                         CS42L42_ASPTX_NOLRCK_MASK |
1825                         CS42L42_ASPTX_EARLY_MASK |
1826                         CS42L42_ASPTX_LATE_MASK |
1827                         CS42L42_ASPTX_SMERROR_MASK,
1828                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1829                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1830                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1831                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1832
1833         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1834                         CS42L42_PDN_DONE_MASK |
1835                         CS42L42_HSDET_AUTO_DONE_MASK,
1836                         (1 << CS42L42_PDN_DONE_SHIFT) |
1837                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1838
1839         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1840                         CS42L42_SRCPL_ADC_LK_MASK |
1841                         CS42L42_SRCPL_DAC_LK_MASK |
1842                         CS42L42_SRCPL_ADC_UNLK_MASK |
1843                         CS42L42_SRCPL_DAC_UNLK_MASK,
1844                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1845                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1846                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1847                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1848
1849         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1850                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1851                         CS42L42_TIP_SENSE_PLUG_MASK |
1852                         CS42L42_HSBIAS_SENSE_MASK,
1853                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1854                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1855                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1856
1857         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1858                         CS42L42_M_DETECT_TF_MASK |
1859                         CS42L42_M_DETECT_FT_MASK |
1860                         CS42L42_M_HSBIAS_HIZ_MASK |
1861                         CS42L42_M_SHORT_RLS_MASK |
1862                         CS42L42_M_SHORT_DET_MASK,
1863                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1864                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1865                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1866                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1867                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1868
1869         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1870                         CS42L42_VPMON_MASK,
1871                         (1 << CS42L42_VPMON_SHIFT));
1872
1873         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1874                         CS42L42_PLL_LOCK_MASK,
1875                         (1 << CS42L42_PLL_LOCK_SHIFT));
1876
1877         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1878                         CS42L42_RS_PLUG_MASK |
1879                         CS42L42_RS_UNPLUG_MASK |
1880                         CS42L42_TS_PLUG_MASK |
1881                         CS42L42_TS_UNPLUG_MASK,
1882                         (1 << CS42L42_RS_PLUG_SHIFT) |
1883                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1884                         (0 << CS42L42_TS_PLUG_SHIFT) |
1885                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1886 }
1887
1888 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1889 {
1890         unsigned int reg;
1891
1892         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1893
1894         /*
1895          * DETECT_MODE must always be 0 with ADC and HP both off otherwise the
1896          * FILT+ supply will not charge properly.
1897          */
1898         regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL,
1899                            CS42L42_DETECT_MODE_MASK, 0);
1900
1901         /* Latch analog controls to VP power domain */
1902         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1903                         CS42L42_LATCH_TO_VP_MASK |
1904                         CS42L42_EVENT_STAT_SEL_MASK |
1905                         CS42L42_HS_DET_LEVEL_MASK,
1906                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1907                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1908                         (cs42l42->bias_thresholds[0] <<
1909                         CS42L42_HS_DET_LEVEL_SHIFT));
1910
1911         /* Remove ground noise-suppression clamps */
1912         regmap_update_bits(cs42l42->regmap,
1913                         CS42L42_HS_CLAMP_DISABLE,
1914                         CS42L42_HS_CLAMP_DISABLE_MASK,
1915                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1916
1917         /* Enable the tip sense circuit */
1918         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1919                            CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
1920
1921         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1922                         CS42L42_TIP_SENSE_CTRL_MASK |
1923                         CS42L42_TIP_SENSE_INV_MASK |
1924                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1925                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1926                         (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
1927                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1928
1929         /* Save the initial status of the tip sense */
1930         regmap_read(cs42l42->regmap,
1931                           CS42L42_TSRS_PLUG_STATUS,
1932                           &reg);
1933         cs42l42->plug_state = (((char) reg) &
1934                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1935                       CS42L42_TS_PLUG_SHIFT;
1936 }
1937
1938 static const unsigned int threshold_defaults[] = {
1939         CS42L42_HS_DET_LEVEL_15,
1940         CS42L42_HS_DET_LEVEL_8,
1941         CS42L42_HS_DET_LEVEL_4,
1942         CS42L42_HS_DET_LEVEL_1
1943 };
1944
1945 static int cs42l42_handle_device_data(struct device *dev,
1946                                         struct cs42l42_private *cs42l42)
1947 {
1948         unsigned int val;
1949         u32 thresholds[CS42L42_NUM_BIASES];
1950         int ret;
1951         int i;
1952
1953         ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1954         if (!ret) {
1955                 switch (val) {
1956                 case CS42L42_TS_INV_EN:
1957                 case CS42L42_TS_INV_DIS:
1958                         cs42l42->ts_inv = val;
1959                         break;
1960                 default:
1961                         dev_err(dev,
1962                                 "Wrong cirrus,ts-inv DT value %d\n",
1963                                 val);
1964                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1965                 }
1966         } else {
1967                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1968         }
1969
1970         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1971         if (!ret) {
1972                 switch (val) {
1973                 case CS42L42_TS_DBNCE_0:
1974                 case CS42L42_TS_DBNCE_125:
1975                 case CS42L42_TS_DBNCE_250:
1976                 case CS42L42_TS_DBNCE_500:
1977                 case CS42L42_TS_DBNCE_750:
1978                 case CS42L42_TS_DBNCE_1000:
1979                 case CS42L42_TS_DBNCE_1250:
1980                 case CS42L42_TS_DBNCE_1500:
1981                         cs42l42->ts_dbnc_rise = val;
1982                         break;
1983                 default:
1984                         dev_err(dev,
1985                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1986                                 val);
1987                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1988                 }
1989         } else {
1990                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1991         }
1992
1993         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1994                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1995                         (cs42l42->ts_dbnc_rise <<
1996                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1997
1998         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1999         if (!ret) {
2000                 switch (val) {
2001                 case CS42L42_TS_DBNCE_0:
2002                 case CS42L42_TS_DBNCE_125:
2003                 case CS42L42_TS_DBNCE_250:
2004                 case CS42L42_TS_DBNCE_500:
2005                 case CS42L42_TS_DBNCE_750:
2006                 case CS42L42_TS_DBNCE_1000:
2007                 case CS42L42_TS_DBNCE_1250:
2008                 case CS42L42_TS_DBNCE_1500:
2009                         cs42l42->ts_dbnc_fall = val;
2010                         break;
2011                 default:
2012                         dev_err(dev,
2013                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
2014                                 val);
2015                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
2016                 }
2017         } else {
2018                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
2019         }
2020
2021         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
2022                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
2023                         (cs42l42->ts_dbnc_fall <<
2024                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
2025
2026         ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
2027         if (!ret) {
2028                 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
2029                         cs42l42->btn_det_init_dbnce = val;
2030                 else {
2031                         dev_err(dev,
2032                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
2033                                 val);
2034                         cs42l42->btn_det_init_dbnce =
2035                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
2036                 }
2037         } else {
2038                 cs42l42->btn_det_init_dbnce =
2039                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
2040         }
2041
2042         ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
2043         if (!ret) {
2044                 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
2045                         cs42l42->btn_det_event_dbnce = val;
2046                 else {
2047                         dev_err(dev,
2048                                 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
2049                         cs42l42->btn_det_event_dbnce =
2050                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
2051                 }
2052         } else {
2053                 cs42l42->btn_det_event_dbnce =
2054                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
2055         }
2056
2057         ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
2058                                              thresholds, ARRAY_SIZE(thresholds));
2059         if (!ret) {
2060                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
2061                         if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
2062                                 cs42l42->bias_thresholds[i] = thresholds[i];
2063                         else {
2064                                 dev_err(dev,
2065                                         "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
2066                                         thresholds[i]);
2067                                 cs42l42->bias_thresholds[i] = threshold_defaults[i];
2068                         }
2069                 }
2070         } else {
2071                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
2072                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
2073         }
2074
2075         ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
2076         if (!ret) {
2077                 switch (val) {
2078                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
2079                         cs42l42->hs_bias_ramp_rate = val;
2080                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
2081                         break;
2082                 case CS42L42_HSBIAS_RAMP_FAST:
2083                         cs42l42->hs_bias_ramp_rate = val;
2084                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
2085                         break;
2086                 case CS42L42_HSBIAS_RAMP_SLOW:
2087                         cs42l42->hs_bias_ramp_rate = val;
2088                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2089                         break;
2090                 case CS42L42_HSBIAS_RAMP_SLOWEST:
2091                         cs42l42->hs_bias_ramp_rate = val;
2092                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
2093                         break;
2094                 default:
2095                         dev_err(dev,
2096                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
2097                                 val);
2098                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2099                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2100                 }
2101         } else {
2102                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2103                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2104         }
2105
2106         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
2107                         CS42L42_HSBIAS_RAMP_MASK,
2108                         (cs42l42->hs_bias_ramp_rate <<
2109                         CS42L42_HSBIAS_RAMP_SHIFT));
2110
2111         if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
2112                 cs42l42->hs_bias_sense_en = 0;
2113         else
2114                 cs42l42->hs_bias_sense_en = 1;
2115
2116         return 0;
2117 }
2118
2119 /* Datasheet suspend sequence */
2120 static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = {
2121         REG_SEQ0(CS42L42_MIC_DET_CTL1,          0x9F),
2122         REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK,     0x01),
2123         REG_SEQ0(CS42L42_MIXER_INT_MASK,        0x0F),
2124         REG_SEQ0(CS42L42_SRC_INT_MASK,          0x0F),
2125         REG_SEQ0(CS42L42_ASP_RX_INT_MASK,       0x1F),
2126         REG_SEQ0(CS42L42_ASP_TX_INT_MASK,       0x0F),
2127         REG_SEQ0(CS42L42_CODEC_INT_MASK,        0x03),
2128         REG_SEQ0(CS42L42_SRCPL_INT_MASK,        0x7F),
2129         REG_SEQ0(CS42L42_VPMON_INT_MASK,        0x01),
2130         REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK,     0x01),
2131         REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK,    0x0F),
2132         REG_SEQ0(CS42L42_WAKE_CTL,              0xE1),
2133         REG_SEQ0(CS42L42_DET_INT1_MASK,         0xE0),
2134         REG_SEQ0(CS42L42_DET_INT2_MASK,         0xFF),
2135         REG_SEQ0(CS42L42_MIXER_CHA_VOL,         0x3F),
2136         REG_SEQ0(CS42L42_MIXER_ADC_VOL,         0x3F),
2137         REG_SEQ0(CS42L42_MIXER_CHB_VOL,         0x3F),
2138         REG_SEQ0(CS42L42_HP_CTL,                0x0F),
2139         REG_SEQ0(CS42L42_ASP_RX_DAI0_EN,        0x00),
2140         REG_SEQ0(CS42L42_ASP_CLK_CFG,           0x00),
2141         REG_SEQ0(CS42L42_HSDET_CTL2,            0x00),
2142         REG_SEQ0(CS42L42_PWR_CTL1,              0xFE),
2143         REG_SEQ0(CS42L42_PWR_CTL2,              0x8C),
2144         REG_SEQ0(CS42L42_DAC_CTL2,              0x02),
2145         REG_SEQ0(CS42L42_HS_CLAMP_DISABLE,      0x00),
2146         REG_SEQ0(CS42L42_MISC_DET_CTL,          0x03),
2147         REG_SEQ0(CS42L42_TIPSENSE_CTL,          0x02),
2148         REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL,     0x03),
2149         REG_SEQ0(CS42L42_PWR_CTL1,              0xFF)
2150 };
2151
2152 int cs42l42_suspend(struct device *dev)
2153 {
2154         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2155         unsigned int reg;
2156         u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)];
2157         int i, ret;
2158
2159         if (!cs42l42->init_done)
2160                 return 0;
2161
2162         /*
2163          * Wait for threaded irq handler to be idle and stop it processing
2164          * future interrupts. This ensures a safe disable if the interrupt
2165          * is shared.
2166          */
2167         mutex_lock(&cs42l42->irq_lock);
2168         cs42l42->suspended = true;
2169
2170         /* Save register values that will be overwritten by shutdown sequence */
2171         for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) {
2172                 regmap_read(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, &reg);
2173                 save_regs[i] = (u8)reg;
2174         }
2175
2176         /* Shutdown codec */
2177         regmap_multi_reg_write(cs42l42->regmap,
2178                                cs42l42_shutdown_seq,
2179                                ARRAY_SIZE(cs42l42_shutdown_seq));
2180
2181         /* All interrupt sources are now disabled */
2182         mutex_unlock(&cs42l42->irq_lock);
2183
2184         /* Wait for power-down complete */
2185         msleep(CS42L42_PDN_DONE_TIME_MS);
2186         ret = regmap_read_poll_timeout(cs42l42->regmap,
2187                                        CS42L42_CODEC_STATUS, reg,
2188                                        (reg & CS42L42_PDN_DONE_MASK),
2189                                        CS42L42_PDN_DONE_POLL_US,
2190                                        CS42L42_PDN_DONE_TIMEOUT_US);
2191         if (ret)
2192                 dev_warn(dev, "Failed to get PDN_DONE: %d\n", ret);
2193
2194         /* Discharge FILT+ */
2195         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
2196                            CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK);
2197
2198         regcache_cache_only(cs42l42->regmap, true);
2199         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2200         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2201
2202         /* Restore register values to the regmap cache */
2203         for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i)
2204                 regmap_write(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, save_regs[i]);
2205
2206         /* The cached address page register value is now stale */
2207         regcache_drop_region(cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER);
2208
2209         dev_dbg(dev, "System suspended\n");
2210
2211         return 0;
2212
2213 }
2214 EXPORT_SYMBOL_NS_GPL(cs42l42_suspend, SND_SOC_CS42L42_CORE);
2215
2216 int cs42l42_resume(struct device *dev)
2217 {
2218         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2219         int ret;
2220
2221         if (!cs42l42->init_done)
2222                 return 0;
2223
2224         /*
2225          * If jack was unplugged and re-plugged during suspend it could
2226          * have changed type but the tip-sense state hasn't changed.
2227          * Force a plugged state to be re-evaluated.
2228          */
2229         if (cs42l42->plug_state != CS42L42_TS_UNPLUG)
2230                 cs42l42->plug_state = CS42L42_TS_TRANS;
2231
2232         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2233         if (ret != 0) {
2234                 dev_err(dev, "Failed to enable supplies: %d\n", ret);
2235                 return ret;
2236         }
2237
2238         gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2239         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2240
2241         dev_dbg(dev, "System resume powered up\n");
2242
2243         return 0;
2244 }
2245 EXPORT_SYMBOL_NS_GPL(cs42l42_resume, SND_SOC_CS42L42_CORE);
2246
2247 void cs42l42_resume_restore(struct device *dev)
2248 {
2249         struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2250
2251         regcache_cache_only(cs42l42->regmap, false);
2252         regcache_mark_dirty(cs42l42->regmap);
2253
2254         mutex_lock(&cs42l42->irq_lock);
2255         /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */
2256         regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1);
2257         regcache_sync(cs42l42->regmap);
2258
2259         cs42l42->suspended = false;
2260         mutex_unlock(&cs42l42->irq_lock);
2261
2262         dev_dbg(dev, "System resumed\n");
2263 }
2264 EXPORT_SYMBOL_NS_GPL(cs42l42_resume_restore, SND_SOC_CS42L42_CORE);
2265
2266 static int __maybe_unused cs42l42_i2c_resume(struct device *dev)
2267 {
2268         int ret;
2269
2270         ret = cs42l42_resume(dev);
2271         if (ret)
2272                 return ret;
2273
2274         cs42l42_resume_restore(dev);
2275
2276         return 0;
2277 }
2278
2279 int cs42l42_common_probe(struct cs42l42_private *cs42l42,
2280                          const struct snd_soc_component_driver *component_drv,
2281                          struct snd_soc_dai_driver *dai)
2282 {
2283         int ret, i;
2284
2285         dev_set_drvdata(cs42l42->dev, cs42l42);
2286         mutex_init(&cs42l42->irq_lock);
2287
2288         BUILD_BUG_ON(ARRAY_SIZE(cs42l42_supply_names) != ARRAY_SIZE(cs42l42->supplies));
2289         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
2290                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
2291
2292         ret = devm_regulator_bulk_get(cs42l42->dev,
2293                                       ARRAY_SIZE(cs42l42->supplies),
2294                                       cs42l42->supplies);
2295         if (ret != 0) {
2296                 dev_err(cs42l42->dev,
2297                         "Failed to request supplies: %d\n", ret);
2298                 return ret;
2299         }
2300
2301         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
2302                                     cs42l42->supplies);
2303         if (ret != 0) {
2304                 dev_err(cs42l42->dev,
2305                         "Failed to enable supplies: %d\n", ret);
2306                 return ret;
2307         }
2308
2309         /* Reset the Device */
2310         cs42l42->reset_gpio = devm_gpiod_get_optional(cs42l42->dev,
2311                 "reset", GPIOD_OUT_LOW);
2312         if (IS_ERR(cs42l42->reset_gpio)) {
2313                 ret = PTR_ERR(cs42l42->reset_gpio);
2314                 goto err_disable_noreset;
2315         }
2316
2317         if (cs42l42->reset_gpio) {
2318                 dev_dbg(cs42l42->dev, "Found reset GPIO\n");
2319
2320                 /*
2321                  * ACPI can override the default GPIO state we requested
2322                  * so ensure that we start with RESET low.
2323                  */
2324                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2325
2326                 /* Ensure minimum reset pulse width */
2327                 usleep_range(10, 500);
2328
2329                 /*
2330                  * On SoundWire keep the chip in reset until we get an UNATTACH
2331                  * notification from the SoundWire core. This acts as a
2332                  * synchronization point to reject stale ATTACH notifications
2333                  * if the chip was already enumerated before we reset it.
2334                  */
2335                 if (cs42l42->sdw_peripheral)
2336                         cs42l42->sdw_waiting_first_unattach = true;
2337                 else
2338                         gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2339         }
2340         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2341
2342         /* Request IRQ if one was specified */
2343         if (cs42l42->irq) {
2344                 ret = request_threaded_irq(cs42l42->irq,
2345                                            NULL, cs42l42_irq_thread,
2346                                            IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2347                                            "cs42l42", cs42l42);
2348                 if (ret) {
2349                         dev_err_probe(cs42l42->dev, ret,
2350                                 "Failed to request IRQ\n");
2351                         goto err_disable_noirq;
2352                 }
2353         }
2354
2355         /* Register codec now so it can EPROBE_DEFER */
2356         ret = devm_snd_soc_register_component(cs42l42->dev, component_drv, dai, 1);
2357         if (ret < 0)
2358                 goto err;
2359
2360         return 0;
2361
2362 err:
2363         if (cs42l42->irq)
2364                 free_irq(cs42l42->irq, cs42l42);
2365
2366 err_disable_noirq:
2367         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2368 err_disable_noreset:
2369         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2370
2371         return ret;
2372 }
2373 EXPORT_SYMBOL_NS_GPL(cs42l42_common_probe, SND_SOC_CS42L42_CORE);
2374
2375 int cs42l42_init(struct cs42l42_private *cs42l42)
2376 {
2377         unsigned int reg;
2378         int devid, ret;
2379
2380         /* initialize codec */
2381         devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
2382         if (devid < 0) {
2383                 ret = devid;
2384                 dev_err(cs42l42->dev, "Failed to read device ID: %d\n", ret);
2385                 goto err_disable;
2386         }
2387
2388         if (devid != cs42l42->devid) {
2389                 ret = -ENODEV;
2390                 dev_err(cs42l42->dev,
2391                         "CS42L%x Device ID (%X). Expected %X\n",
2392                         cs42l42->devid & 0xff, devid, cs42l42->devid);
2393                 goto err_disable;
2394         }
2395
2396         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
2397         if (ret < 0) {
2398                 dev_err(cs42l42->dev, "Get Revision ID failed\n");
2399                 goto err_shutdown;
2400         }
2401
2402         dev_info(cs42l42->dev,
2403                  "Cirrus Logic CS42L%x, Revision: %02X\n",
2404                  cs42l42->devid & 0xff, reg & 0xFF);
2405
2406         /* Power up the codec */
2407         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
2408                         CS42L42_ASP_DAO_PDN_MASK |
2409                         CS42L42_ASP_DAI_PDN_MASK |
2410                         CS42L42_MIXER_PDN_MASK |
2411                         CS42L42_EQ_PDN_MASK |
2412                         CS42L42_HP_PDN_MASK |
2413                         CS42L42_ADC_PDN_MASK |
2414                         CS42L42_PDN_ALL_MASK,
2415                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
2416                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
2417                         (1 << CS42L42_MIXER_PDN_SHIFT) |
2418                         (1 << CS42L42_EQ_PDN_SHIFT) |
2419                         (1 << CS42L42_HP_PDN_SHIFT) |
2420                         (1 << CS42L42_ADC_PDN_SHIFT) |
2421                         (0 << CS42L42_PDN_ALL_SHIFT));
2422
2423         ret = cs42l42_handle_device_data(cs42l42->dev, cs42l42);
2424         if (ret != 0)
2425                 goto err_shutdown;
2426
2427         /*
2428          * SRC power is linked to ASP power so doesn't work in Soundwire mode.
2429          * Override it and use DAPM to control SRC power for Soundwire.
2430          */
2431         if (cs42l42->sdw_peripheral) {
2432                 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
2433                                    CS42L42_SRC_PDN_OVERRIDE_MASK |
2434                                    CS42L42_DAC_SRC_PDNB_MASK |
2435                                    CS42L42_ADC_SRC_PDNB_MASK,
2436                                    CS42L42_SRC_PDN_OVERRIDE_MASK);
2437         }
2438
2439         /* Setup headset detection */
2440         cs42l42_setup_hs_type_detect(cs42l42);
2441
2442         /*
2443          * Set init_done before unmasking interrupts so any triggered
2444          * immediately will be handled.
2445          */
2446         cs42l42->init_done = true;
2447
2448         /* Mask/Unmask Interrupts */
2449         cs42l42_set_interrupt_masks(cs42l42);
2450
2451         return 0;
2452
2453 err_shutdown:
2454         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2455         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2456         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2457
2458 err_disable:
2459         if (cs42l42->irq)
2460                 free_irq(cs42l42->irq, cs42l42);
2461
2462         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2463         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2464                                 cs42l42->supplies);
2465         return ret;
2466 }
2467 EXPORT_SYMBOL_NS_GPL(cs42l42_init, SND_SOC_CS42L42_CORE);
2468
2469 void cs42l42_common_remove(struct cs42l42_private *cs42l42)
2470 {
2471         if (cs42l42->irq)
2472                 free_irq(cs42l42->irq, cs42l42);
2473
2474         /*
2475          * The driver might not have control of reset and power supplies,
2476          * so ensure that the chip internals are powered down.
2477          */
2478         if (cs42l42->init_done) {
2479                 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2480                 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2481                 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2482         }
2483
2484         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2485         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2486 }
2487 EXPORT_SYMBOL_NS_GPL(cs42l42_common_remove, SND_SOC_CS42L42_CORE);
2488
2489 MODULE_DESCRIPTION("ASoC CS42L42 driver");
2490 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2491 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2492 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2493 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
2494 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
2495 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
2496 MODULE_LICENSE("GPL");