sound/soc/codecs/cs42l42.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  * Author: Brian Austin <brian.austin@cirrus.com>
   9  * Author: Michael White <michael.white@cirrus.com>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/version.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c.h>
  19 #include <linux/gpio.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22 #include <linux/acpi.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/property.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/gpio/consumer.h>
  27 #include <linux/of_device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/soc.h>
  32 #include <sound/soc-dapm.h>
  33 #include <sound/initval.h>
  34 #include <sound/tlv.h>
  35 #include <dt-bindings/sound/cs42l42.h>
  36
  37 #include "cs42l42.h"
  38 #include "cirrus_legacy.h"
  39
  40 static const struct reg_default cs42l42_reg_defaults[] = {
  41         { CS42L42_FRZ_CTL,                      0x00 },
  42         { CS42L42_SRC_CTL,                      0x10 },
  43         { CS42L42_MCLK_CTL,                     0x02 },
  44         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  45         { CS42L42_SLOW_START_ENABLE,            0x70 },
  46         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  47         { CS42L42_I2C_STRETCH,                  0x03 },
  48         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  49         { CS42L42_PWR_CTL1,                     0xFF },
  50         { CS42L42_PWR_CTL2,                     0x84 },
  51         { CS42L42_PWR_CTL3,                     0x20 },
  52         { CS42L42_RSENSE_CTL1,                  0x40 },
  53         { CS42L42_RSENSE_CTL2,                  0x00 },
  54         { CS42L42_OSC_SWITCH,                   0x00 },
  55         { CS42L42_RSENSE_CTL3,                  0x1B },
  56         { CS42L42_TSENSE_CTL,                   0x1B },
  57         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  58         { CS42L42_HSDET_CTL1,                   0x77 },
  59         { CS42L42_HSDET_CTL2,                   0x00 },
  60         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  61         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  62         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  63         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  64         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  65         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  66         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  67         { CS42L42_FSYNC_P_UPPER,                0x00 },
  68         { CS42L42_ASP_CLK_CFG,                  0x00 },
  69         { CS42L42_ASP_FRM_CFG,                  0x10 },
  70         { CS42L42_FS_RATE_EN,                   0x00 },
  71         { CS42L42_IN_ASRC_CLK,                  0x00 },
  72         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  73         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  74         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  75         { CS42L42_MIXER_INT_MASK,               0x0F },
  76         { CS42L42_SRC_INT_MASK,                 0x0F },
  77         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  78         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  79         { CS42L42_CODEC_INT_MASK,               0x03 },
  80         { CS42L42_SRCPL_INT_MASK,               0x7F },
  81         { CS42L42_VPMON_INT_MASK,               0x01 },
  82         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
  83         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
  84         { CS42L42_PLL_CTL1,                     0x00 },
  85         { CS42L42_PLL_DIV_FRAC0,                0x00 },
  86         { CS42L42_PLL_DIV_FRAC1,                0x00 },
  87         { CS42L42_PLL_DIV_FRAC2,                0x00 },
  88         { CS42L42_PLL_DIV_INT,                  0x40 },
  89         { CS42L42_PLL_CTL3,                     0x10 },
  90         { CS42L42_PLL_CAL_RATIO,                0x80 },
  91         { CS42L42_PLL_CTL4,                     0x03 },
  92         { CS42L42_LOAD_DET_EN,                  0x00 },
  93         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
  94         { CS42L42_WAKE_CTL,                     0xC0 },
  95         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
  96         { CS42L42_TIPSENSE_CTL,                 0x02 },
  97         { CS42L42_MISC_DET_CTL,                 0x03 },
  98         { CS42L42_MIC_DET_CTL1,                 0x1F },
  99         { CS42L42_MIC_DET_CTL2,                 0x2F },
 100         { CS42L42_DET_INT1_MASK,                0xE0 },
 101         { CS42L42_DET_INT2_MASK,                0xFF },
 102         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 103         { CS42L42_ADC_CTL,                      0x00 },
 104         { CS42L42_ADC_VOLUME,                   0x00 },
 105         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 106         { CS42L42_DAC_CTL1,                     0x00 },
 107         { CS42L42_DAC_CTL2,                     0x02 },
 108         { CS42L42_HP_CTL,                       0x0D },
 109         { CS42L42_CLASSH_CTL,                   0x07 },
 110         { CS42L42_MIXER_CHA_VOL,                0x3F },
 111         { CS42L42_MIXER_ADC_VOL,                0x3F },
 112         { CS42L42_MIXER_CHB_VOL,                0x3F },
 113         { CS42L42_EQ_COEF_IN0,                  0x00 },
 114         { CS42L42_EQ_COEF_IN1,                  0x00 },
 115         { CS42L42_EQ_COEF_IN2,                  0x00 },
 116         { CS42L42_EQ_COEF_IN3,                  0x00 },
 117         { CS42L42_EQ_COEF_RW,                   0x00 },
 118         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 119         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 120         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 121         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 122         { CS42L42_EQ_INIT_STAT,                 0x00 },
 123         { CS42L42_EQ_START_FILT,                0x00 },
 124         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 125         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 126         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 127         { CS42L42_SP_RX_FS,                     0x8C },
 128         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 129         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 130         { CS42L42_SP_TX_FS,                     0xCC },
 131         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 132         { CS42L42_SRC_SDIN_FS,                  0x40 },
 133         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 134         { CS42L42_SPDIF_CTL1,                   0x01 },
 135         { CS42L42_SPDIF_CTL2,                   0x00 },
 136         { CS42L42_SPDIF_CTL3,                   0x00 },
 137         { CS42L42_SPDIF_CTL4,                   0x42 },
 138         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 139         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 140         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 141         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 142         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 143         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 144         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 145         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 146         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 147         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 148         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 149         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 150         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 151         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 152         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 153         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 154         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 155         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 156         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 157         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 158         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 159         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 160         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 161         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 162         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 163         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 164         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 165 };
 166
 167 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 168 {
 169         switch (reg) {
 170         case CS42L42_PAGE_REGISTER:
 171         case CS42L42_DEVID_AB:
 172         case CS42L42_DEVID_CD:
 173         case CS42L42_DEVID_E:
 174         case CS42L42_FABID:
 175         case CS42L42_REVID:
 176         case CS42L42_FRZ_CTL:
 177         case CS42L42_SRC_CTL:
 178         case CS42L42_MCLK_STATUS:
 179         case CS42L42_MCLK_CTL:
 180         case CS42L42_SFTRAMP_RATE:
 181         case CS42L42_SLOW_START_ENABLE:
 182         case CS42L42_I2C_DEBOUNCE:
 183         case CS42L42_I2C_STRETCH:
 184         case CS42L42_I2C_TIMEOUT:
 185         case CS42L42_PWR_CTL1:
 186         case CS42L42_PWR_CTL2:
 187         case CS42L42_PWR_CTL3:
 188         case CS42L42_RSENSE_CTL1:
 189         case CS42L42_RSENSE_CTL2:
 190         case CS42L42_OSC_SWITCH:
 191         case CS42L42_OSC_SWITCH_STATUS:
 192         case CS42L42_RSENSE_CTL3:
 193         case CS42L42_TSENSE_CTL:
 194         case CS42L42_TSRS_INT_DISABLE:
 195         case CS42L42_TRSENSE_STATUS:
 196         case CS42L42_HSDET_CTL1:
 197         case CS42L42_HSDET_CTL2:
 198         case CS42L42_HS_SWITCH_CTL:
 199         case CS42L42_HS_DET_STATUS:
 200         case CS42L42_HS_CLAMP_DISABLE:
 201         case CS42L42_MCLK_SRC_SEL:
 202         case CS42L42_SPDIF_CLK_CFG:
 203         case CS42L42_FSYNC_PW_LOWER:
 204         case CS42L42_FSYNC_PW_UPPER:
 205         case CS42L42_FSYNC_P_LOWER:
 206         case CS42L42_FSYNC_P_UPPER:
 207         case CS42L42_ASP_CLK_CFG:
 208         case CS42L42_ASP_FRM_CFG:
 209         case CS42L42_FS_RATE_EN:
 210         case CS42L42_IN_ASRC_CLK:
 211         case CS42L42_OUT_ASRC_CLK:
 212         case CS42L42_PLL_DIV_CFG1:
 213         case CS42L42_ADC_OVFL_STATUS:
 214         case CS42L42_MIXER_STATUS:
 215         case CS42L42_SRC_STATUS:
 216         case CS42L42_ASP_RX_STATUS:
 217         case CS42L42_ASP_TX_STATUS:
 218         case CS42L42_CODEC_STATUS:
 219         case CS42L42_DET_INT_STATUS1:
 220         case CS42L42_DET_INT_STATUS2:
 221         case CS42L42_SRCPL_INT_STATUS:
 222         case CS42L42_VPMON_STATUS:
 223         case CS42L42_PLL_LOCK_STATUS:
 224         case CS42L42_TSRS_PLUG_STATUS:
 225         case CS42L42_ADC_OVFL_INT_MASK:
 226         case CS42L42_MIXER_INT_MASK:
 227         case CS42L42_SRC_INT_MASK:
 228         case CS42L42_ASP_RX_INT_MASK:
 229         case CS42L42_ASP_TX_INT_MASK:
 230         case CS42L42_CODEC_INT_MASK:
 231         case CS42L42_SRCPL_INT_MASK:
 232         case CS42L42_VPMON_INT_MASK:
 233         case CS42L42_PLL_LOCK_INT_MASK:
 234         case CS42L42_TSRS_PLUG_INT_MASK:
 235         case CS42L42_PLL_CTL1:
 236         case CS42L42_PLL_DIV_FRAC0:
 237         case CS42L42_PLL_DIV_FRAC1:
 238         case CS42L42_PLL_DIV_FRAC2:
 239         case CS42L42_PLL_DIV_INT:
 240         case CS42L42_PLL_CTL3:
 241         case CS42L42_PLL_CAL_RATIO:
 242         case CS42L42_PLL_CTL4:
 243         case CS42L42_LOAD_DET_RCSTAT:
 244         case CS42L42_LOAD_DET_DONE:
 245         case CS42L42_LOAD_DET_EN:
 246         case CS42L42_HSBIAS_SC_AUTOCTL:
 247         case CS42L42_WAKE_CTL:
 248         case CS42L42_ADC_DISABLE_MUTE:
 249         case CS42L42_TIPSENSE_CTL:
 250         case CS42L42_MISC_DET_CTL:
 251         case CS42L42_MIC_DET_CTL1:
 252         case CS42L42_MIC_DET_CTL2:
 253         case CS42L42_DET_STATUS1:
 254         case CS42L42_DET_STATUS2:
 255         case CS42L42_DET_INT1_MASK:
 256         case CS42L42_DET_INT2_MASK:
 257         case CS42L42_HS_BIAS_CTL:
 258         case CS42L42_ADC_CTL:
 259         case CS42L42_ADC_VOLUME:
 260         case CS42L42_ADC_WNF_HPF_CTL:
 261         case CS42L42_DAC_CTL1:
 262         case CS42L42_DAC_CTL2:
 263         case CS42L42_HP_CTL:
 264         case CS42L42_CLASSH_CTL:
 265         case CS42L42_MIXER_CHA_VOL:
 266         case CS42L42_MIXER_ADC_VOL:
 267         case CS42L42_MIXER_CHB_VOL:
 268         case CS42L42_EQ_COEF_IN0:
 269         case CS42L42_EQ_COEF_IN1:
 270         case CS42L42_EQ_COEF_IN2:
 271         case CS42L42_EQ_COEF_IN3:
 272         case CS42L42_EQ_COEF_RW:
 273         case CS42L42_EQ_COEF_OUT0:
 274         case CS42L42_EQ_COEF_OUT1:
 275         case CS42L42_EQ_COEF_OUT2:
 276         case CS42L42_EQ_COEF_OUT3:
 277         case CS42L42_EQ_INIT_STAT:
 278         case CS42L42_EQ_START_FILT:
 279         case CS42L42_EQ_MUTE_CTL:
 280         case CS42L42_SP_RX_CH_SEL:
 281         case CS42L42_SP_RX_ISOC_CTL:
 282         case CS42L42_SP_RX_FS:
 283         case CS42l42_SPDIF_CH_SEL:
 284         case CS42L42_SP_TX_ISOC_CTL:
 285         case CS42L42_SP_TX_FS:
 286         case CS42L42_SPDIF_SW_CTL1:
 287         case CS42L42_SRC_SDIN_FS:
 288         case CS42L42_SRC_SDOUT_FS:
 289         case CS42L42_SPDIF_CTL1:
 290         case CS42L42_SPDIF_CTL2:
 291         case CS42L42_SPDIF_CTL3:
 292         case CS42L42_SPDIF_CTL4:
 293         case CS42L42_ASP_TX_SZ_EN:
 294         case CS42L42_ASP_TX_CH_EN:
 295         case CS42L42_ASP_TX_CH_AP_RES:
 296         case CS42L42_ASP_TX_CH1_BIT_MSB:
 297         case CS42L42_ASP_TX_CH1_BIT_LSB:
 298         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 299         case CS42L42_ASP_TX_CH2_BIT_MSB:
 300         case CS42L42_ASP_TX_CH2_BIT_LSB:
 301         case CS42L42_ASP_RX_DAI0_EN:
 302         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 303         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 304         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 305         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 306         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 307         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 308         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 309         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 310         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 311         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 312         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 313         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 314         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 315         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 316         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 317         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 318         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 319         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 320         case CS42L42_SUB_REVID:
 321                 return true;
 322         default:
 323                 return false;
 324         }
 325 }
 326
 327 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 328 {
 329         switch (reg) {
 330         case CS42L42_DEVID_AB:
 331         case CS42L42_DEVID_CD:
 332         case CS42L42_DEVID_E:
 333         case CS42L42_MCLK_STATUS:
 334         case CS42L42_OSC_SWITCH_STATUS:
 335         case CS42L42_TRSENSE_STATUS:
 336         case CS42L42_HS_DET_STATUS:
 337         case CS42L42_ADC_OVFL_STATUS:
 338         case CS42L42_MIXER_STATUS:
 339         case CS42L42_SRC_STATUS:
 340         case CS42L42_ASP_RX_STATUS:
 341         case CS42L42_ASP_TX_STATUS:
 342         case CS42L42_CODEC_STATUS:
 343         case CS42L42_DET_INT_STATUS1:
 344         case CS42L42_DET_INT_STATUS2:
 345         case CS42L42_SRCPL_INT_STATUS:
 346         case CS42L42_VPMON_STATUS:
 347         case CS42L42_PLL_LOCK_STATUS:
 348         case CS42L42_TSRS_PLUG_STATUS:
 349         case CS42L42_LOAD_DET_RCSTAT:
 350         case CS42L42_LOAD_DET_DONE:
 351         case CS42L42_DET_STATUS1:
 352         case CS42L42_DET_STATUS2:
 353                 return true;
 354         default:
 355                 return false;
 356         }
 357 }
 358
 359 static const struct regmap_range_cfg cs42l42_page_range = {
 360         .name = "Pages",
 361         .range_min = 0,
 362         .range_max = CS42L42_MAX_REGISTER,
 363         .selector_reg = CS42L42_PAGE_REGISTER,
 364         .selector_mask = 0xff,
 365         .selector_shift = 0,
 366         .window_start = 0,
 367         .window_len = 256,
 368 };
 369
 370 static const struct regmap_config cs42l42_regmap = {
 371         .reg_bits = 8,
 372         .val_bits = 8,
 373
 374         .readable_reg = cs42l42_readable_register,
 375         .volatile_reg = cs42l42_volatile_register,
 376
 377         .ranges = &cs42l42_page_range,
 378         .num_ranges = 1,
 379
 380         .max_register = CS42L42_MAX_REGISTER,
 381         .reg_defaults = cs42l42_reg_defaults,
 382         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 383         .cache_type = REGCACHE_RBTREE,
 384
 385         .use_single_read = true,
 386         .use_single_write = true,
 387 };
 388
 389 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
 390 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
 391
 392 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol,
 393                                   struct snd_ctl_elem_value *ucontrol)
 394 {
 395         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 396         u8 val;
 397
 398         /* all bits of SLOW_START_EN much change together */
 399         switch (ucontrol->value.integer.value[0]) {
 400         case 0:
 401                 val = 0;
 402                 break;
 403         case 1:
 404                 val = CS42L42_SLOW_START_EN_MASK;
 405                 break;
 406         default:
 407                 return -EINVAL;
 408         }
 409
 410         return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE,
 411                                              CS42L42_SLOW_START_EN_MASK, val);
 412 }
 413
 414 static const char * const cs42l42_hpf_freq_text[] = {
 415         "1.86Hz", "120Hz", "235Hz", "466Hz"
 416 };
 417
 418 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 419                             CS42L42_ADC_HPF_CF_SHIFT,
 420                             cs42l42_hpf_freq_text);
 421
 422 static const char * const cs42l42_wnf3_freq_text[] = {
 423         "160Hz", "180Hz", "200Hz", "220Hz",
 424         "240Hz", "260Hz", "280Hz", "300Hz"
 425 };
 426
 427 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 428                             CS42L42_ADC_WNF_CF_SHIFT,
 429                             cs42l42_wnf3_freq_text);
 430
 431 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 432         /* ADC Volume and Filter Controls */
 433         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 434                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
 435         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 436                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 437         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 438                                 CS42L42_ADC_INV_SHIFT, true, false),
 439         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 440                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 441         SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
 442         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 443                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 444         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 445                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 446         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 447         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 448
 449         /* DAC Volume and Filter Controls */
 450         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 451                                 CS42L42_DACA_INV_SHIFT, true, false),
 452         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 453                                 CS42L42_DACB_INV_SHIFT, true, false),
 454         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 455                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 456         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 457                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 458                                 0x3f, 1, mixer_tlv),
 459
 460         SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE,
 461                         CS42L42_SLOW_START_EN_SHIFT, true, false,
 462                         snd_soc_get_volsw, cs42l42_slow_start_put),
 463 };
 464
 465 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w,
 466                              struct snd_kcontrol *kcontrol, int event)
 467 {
 468         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 469         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 470
 471         switch (event) {
 472         case SND_SOC_DAPM_PRE_PMU:
 473                 cs42l42->hp_adc_up_pending = true;
 474                 break;
 475         case SND_SOC_DAPM_POST_PMU:
 476                 /* Only need one delay if HP and ADC are both powering-up */
 477                 if (cs42l42->hp_adc_up_pending) {
 478                         usleep_range(CS42L42_HP_ADC_EN_TIME_US,
 479                                      CS42L42_HP_ADC_EN_TIME_US + 1000);
 480                         cs42l42->hp_adc_up_pending = false;
 481                 }
 482                 break;
 483         default:
 484                 break;
 485         }
 486
 487         return 0;
 488 }
 489
 490 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 491         /* Playback Path */
 492         SND_SOC_DAPM_OUTPUT("HP"),
 493         SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1,
 494                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 495         SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
 496         SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
 497         SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
 498
 499         /* Playback Requirements */
 500         SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
 501
 502         /* Capture Path */
 503         SND_SOC_DAPM_INPUT("HS"),
 504         SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1,
 505                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 506         SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
 507         SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
 508
 509         /* Capture Requirements */
 510         SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
 511         SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
 512
 513         /* Playback/Capture Requirements */
 514         SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
 515 };
 516
 517 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 518         /* Playback Path */
 519         {"HP", NULL, "DAC"},
 520         {"DAC", NULL, "MIXER"},
 521         {"MIXER", NULL, "SDIN1"},
 522         {"MIXER", NULL, "SDIN2"},
 523         {"SDIN1", NULL, "Playback"},
 524         {"SDIN2", NULL, "Playback"},
 525
 526         /* Playback Requirements */
 527         {"SDIN1", NULL, "ASP DAI0"},
 528         {"SDIN2", NULL, "ASP DAI0"},
 529         {"SDIN1", NULL, "SCLK"},
 530         {"SDIN2", NULL, "SCLK"},
 531
 532         /* Capture Path */
 533         {"ADC", NULL, "HS"},
 534         { "SDOUT1", NULL, "ADC" },
 535         { "SDOUT2", NULL, "ADC" },
 536         { "Capture", NULL, "SDOUT1" },
 537         { "Capture", NULL, "SDOUT2" },
 538
 539         /* Capture Requirements */
 540         { "SDOUT1", NULL, "ASP DAO0" },
 541         { "SDOUT2", NULL, "ASP DAO0" },
 542         { "SDOUT1", NULL, "SCLK" },
 543         { "SDOUT2", NULL, "SCLK" },
 544         { "SDOUT1", NULL, "ASP TX EN" },
 545         { "SDOUT2", NULL, "ASP TX EN" },
 546 };
 547
 548 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
 549 {
 550         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 551
 552         cs42l42->jack = jk;
 553
 554         return 0;
 555 }
 556
 557 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
 558         .set_jack               = cs42l42_set_jack,
 559         .dapm_widgets           = cs42l42_dapm_widgets,
 560         .num_dapm_widgets       = ARRAY_SIZE(cs42l42_dapm_widgets),
 561         .dapm_routes            = cs42l42_audio_map,
 562         .num_dapm_routes        = ARRAY_SIZE(cs42l42_audio_map),
 563         .controls               = cs42l42_snd_controls,
 564         .num_controls           = ARRAY_SIZE(cs42l42_snd_controls),
 565         .idle_bias_on           = 1,
 566         .endianness             = 1,
 567         .non_legacy_dai_naming  = 1,
 568 };
 569
 570 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
 571 static const struct reg_sequence cs42l42_to_sclk_seq[] = {
 572         {
 573                 .reg = CS42L42_OSC_SWITCH,
 574                 .def = CS42L42_SCLK_PRESENT_MASK,
 575                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 576         },
 577 };
 578
 579 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
 580 static const struct reg_sequence cs42l42_to_osc_seq[] = {
 581         {
 582                 .reg = CS42L42_OSC_SWITCH,
 583                 .def = 0,
 584                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 585         },
 586 };
 587
 588 struct cs42l42_pll_params {
 589         u32 sclk;
 590         u8 mclk_src_sel;
 591         u8 sclk_prediv;
 592         u8 pll_div_int;
 593         u32 pll_div_frac;
 594         u8 pll_mode;
 595         u8 pll_divout;
 596         u32 mclk_int;
 597         u8 pll_cal_ratio;
 598         u8 n;
 599 };
 600
 601 /*
 602  * Common PLL Settings for given SCLK
 603  * Table 4-5 from the Datasheet
 604  */
 605 static const struct cs42l42_pll_params pll_ratio_table[] = {
 606         { 1411200,  1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
 607         { 1536000,  1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
 608         { 2304000,  1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},
 609         { 2400000,  1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
 610         { 2822400,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 611         { 3000000,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 612         { 3072000,  1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 613         { 4000000,  1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},
 614         { 4096000,  1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},
 615         { 5644800,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 616         { 6000000,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 617         { 6144000,  1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 618         { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
 619         { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
 620         { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
 621         { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 622         { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 623         { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}
 624 };
 625
 626 static int cs42l42_pll_config(struct snd_soc_component *component)
 627 {
 628         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 629         int i;
 630         u32 clk;
 631         u32 fsync;
 632
 633         if (!cs42l42->sclk)
 634                 clk = cs42l42->bclk;
 635         else
 636                 clk = cs42l42->sclk;
 637
 638         /* Don't reconfigure if there is an audio stream running */
 639         if (cs42l42->stream_use) {
 640                 if (pll_ratio_table[cs42l42->pll_config].sclk == clk)
 641                         return 0;
 642                 else
 643                         return -EBUSY;
 644         }
 645
 646         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 647                 if (pll_ratio_table[i].sclk == clk) {
 648                         cs42l42->pll_config = i;
 649
 650                         /* Configure the internal sample rate */
 651                         snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
 652                                         CS42L42_INTERNAL_FS_MASK,
 653                                         ((pll_ratio_table[i].mclk_int !=
 654                                         12000000) &&
 655                                         (pll_ratio_table[i].mclk_int !=
 656                                         24000000)) <<
 657                                         CS42L42_INTERNAL_FS_SHIFT);
 658
 659                         /* Set up the LRCLK */
 660                         fsync = clk / cs42l42->srate;
 661                         if (((fsync * cs42l42->srate) != clk)
 662                                 || ((fsync % 2) != 0)) {
 663                                 dev_err(component->dev,
 664                                         "Unsupported sclk %d/sample rate %d\n",
 665                                         clk,
 666                                         cs42l42->srate);
 667                                 return -EINVAL;
 668                         }
 669                         /* Set the LRCLK period */
 670                         snd_soc_component_update_bits(component,
 671                                         CS42L42_FSYNC_P_LOWER,
 672                                         CS42L42_FSYNC_PERIOD_MASK,
 673                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 674                                         CS42L42_FSYNC_PERIOD_SHIFT);
 675                         snd_soc_component_update_bits(component,
 676                                         CS42L42_FSYNC_P_UPPER,
 677                                         CS42L42_FSYNC_PERIOD_MASK,
 678                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 679                                         CS42L42_FSYNC_PERIOD_SHIFT);
 680                         /* Set the LRCLK to 50% duty cycle */
 681                         fsync = fsync / 2;
 682                         snd_soc_component_update_bits(component,
 683                                         CS42L42_FSYNC_PW_LOWER,
 684                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 685                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 686                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 687                         snd_soc_component_update_bits(component,
 688                                         CS42L42_FSYNC_PW_UPPER,
 689                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 690                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 691                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 692                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 693                                 /* Pass the clock straight through */
 694                                 snd_soc_component_update_bits(component,
 695                                         CS42L42_PLL_CTL1,
 696                                         CS42L42_PLL_START_MASK, 0);
 697                         } else {
 698                                 /* Configure PLL per table 4-5 */
 699                                 snd_soc_component_update_bits(component,
 700                                         CS42L42_PLL_DIV_CFG1,
 701                                         CS42L42_SCLK_PREDIV_MASK,
 702                                         pll_ratio_table[i].sclk_prediv
 703                                         << CS42L42_SCLK_PREDIV_SHIFT);
 704                                 snd_soc_component_update_bits(component,
 705                                         CS42L42_PLL_DIV_INT,
 706                                         CS42L42_PLL_DIV_INT_MASK,
 707                                         pll_ratio_table[i].pll_div_int
 708                                         << CS42L42_PLL_DIV_INT_SHIFT);
 709                                 snd_soc_component_update_bits(component,
 710                                         CS42L42_PLL_DIV_FRAC0,
 711                                         CS42L42_PLL_DIV_FRAC_MASK,
 712                                         CS42L42_FRAC0_VAL(
 713                                         pll_ratio_table[i].pll_div_frac)
 714                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 715                                 snd_soc_component_update_bits(component,
 716                                         CS42L42_PLL_DIV_FRAC1,
 717                                         CS42L42_PLL_DIV_FRAC_MASK,
 718                                         CS42L42_FRAC1_VAL(
 719                                         pll_ratio_table[i].pll_div_frac)
 720                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 721                                 snd_soc_component_update_bits(component,
 722                                         CS42L42_PLL_DIV_FRAC2,
 723                                         CS42L42_PLL_DIV_FRAC_MASK,
 724                                         CS42L42_FRAC2_VAL(
 725                                         pll_ratio_table[i].pll_div_frac)
 726                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 727                                 snd_soc_component_update_bits(component,
 728                                         CS42L42_PLL_CTL4,
 729                                         CS42L42_PLL_MODE_MASK,
 730                                         pll_ratio_table[i].pll_mode
 731                                         << CS42L42_PLL_MODE_SHIFT);
 732                                 snd_soc_component_update_bits(component,
 733                                         CS42L42_PLL_CTL3,
 734                                         CS42L42_PLL_DIVOUT_MASK,
 735                                         (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
 736                                         << CS42L42_PLL_DIVOUT_SHIFT);
 737                                 if (pll_ratio_table[i].n != 1)
 738                                         cs42l42->pll_divout = pll_ratio_table[i].pll_divout;
 739                                 else
 740                                         cs42l42->pll_divout = 0;
 741                                 snd_soc_component_update_bits(component,
 742                                         CS42L42_PLL_CAL_RATIO,
 743                                         CS42L42_PLL_CAL_RATIO_MASK,
 744                                         pll_ratio_table[i].pll_cal_ratio
 745                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 746                         }
 747                         return 0;
 748                 }
 749         }
 750
 751         return -EINVAL;
 752 }
 753
 754 static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
 755 {
 756         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 757         unsigned int fs;
 758
 759         /* Don't reconfigure if there is an audio stream running */
 760         if (cs42l42->stream_use)
 761                 return;
 762
 763         /* SRC MCLK must be as close as possible to 125 * sample rate */
 764         if (sample_rate <= 48000)
 765                 fs = CS42L42_CLK_IASRC_SEL_6;
 766         else
 767                 fs = CS42L42_CLK_IASRC_SEL_12;
 768
 769         /* Set the sample rates (96k or lower) */
 770         snd_soc_component_update_bits(component,
 771                                       CS42L42_FS_RATE_EN,
 772                                       CS42L42_FS_EN_MASK,
 773                                       (CS42L42_FS_EN_IASRC_96K |
 774                                        CS42L42_FS_EN_OASRC_96K) <<
 775                                       CS42L42_FS_EN_SHIFT);
 776
 777         snd_soc_component_update_bits(component,
 778                                       CS42L42_IN_ASRC_CLK,
 779                                       CS42L42_CLK_IASRC_SEL_MASK,
 780                                       fs << CS42L42_CLK_IASRC_SEL_SHIFT);
 781         snd_soc_component_update_bits(component,
 782                                       CS42L42_OUT_ASRC_CLK,
 783                                       CS42L42_CLK_OASRC_SEL_MASK,
 784                                       fs << CS42L42_CLK_OASRC_SEL_SHIFT);
 785 }
 786
 787 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 788 {
 789         struct snd_soc_component *component = codec_dai->component;
 790         u32 asp_cfg_val = 0;
 791
 792         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 793         case SND_SOC_DAIFMT_CBS_CFM:
 794                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 795                                 CS42L42_ASP_MODE_SHIFT;
 796                 break;
 797         case SND_SOC_DAIFMT_CBS_CFS:
 798                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 799                                 CS42L42_ASP_MODE_SHIFT;
 800                 break;
 801         default:
 802                 return -EINVAL;
 803         }
 804
 805         /* interface format */
 806         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 807         case SND_SOC_DAIFMT_I2S:
 808                 /*
 809                  * 5050 mode, frame starts on falling edge of LRCLK,
 810                  * frame delayed by 1.0 SCLKs
 811                  */
 812                 snd_soc_component_update_bits(component,
 813                                               CS42L42_ASP_FRM_CFG,
 814                                               CS42L42_ASP_STP_MASK |
 815                                               CS42L42_ASP_5050_MASK |
 816                                               CS42L42_ASP_FSD_MASK,
 817                                               CS42L42_ASP_5050_MASK |
 818                                               (CS42L42_ASP_FSD_1_0 <<
 819                                                 CS42L42_ASP_FSD_SHIFT));
 820                 break;
 821         default:
 822                 return -EINVAL;
 823         }
 824
 825         /* Bitclock/frame inversion */
 826         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 827         case SND_SOC_DAIFMT_NB_NF:
 828                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 829                 break;
 830         case SND_SOC_DAIFMT_NB_IF:
 831                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 832                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 833                 break;
 834         case SND_SOC_DAIFMT_IB_NF:
 835                 break;
 836         case SND_SOC_DAIFMT_IB_IF:
 837                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 838                 break;
 839         }
 840
 841         snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
 842                                                                       CS42L42_ASP_SCPOL_MASK |
 843                                                                       CS42L42_ASP_LCPOL_MASK,
 844                                                                       asp_cfg_val);
 845
 846         return 0;
 847 }
 848
 849 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
 850 {
 851         struct snd_soc_component *component = dai->component;
 852         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 853
 854         /*
 855          * Sample rates < 44.1 kHz would produce an out-of-range SCLK with
 856          * a standard I2S frame. If the machine driver sets SCLK it must be
 857          * legal.
 858          */
 859         if (cs42l42->sclk)
 860                 return 0;
 861
 862         /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
 863         return snd_pcm_hw_constraint_minmax(substream->runtime,
 864                                             SNDRV_PCM_HW_PARAM_RATE,
 865                                             44100, 96000);
 866 }
 867
 868 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 869                                 struct snd_pcm_hw_params *params,
 870                                 struct snd_soc_dai *dai)
 871 {
 872         struct snd_soc_component *component = dai->component;
 873         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 874         unsigned int channels = params_channels(params);
 875         unsigned int width = (params_width(params) / 8) - 1;
 876         unsigned int val = 0;
 877         int ret;
 878
 879         cs42l42->srate = params_rate(params);
 880         cs42l42->bclk = snd_soc_params_to_bclk(params);
 881
 882         /* I2S frame always has 2 channels even for mono audio */
 883         if (channels == 1)
 884                 cs42l42->bclk *= 2;
 885
 886         /*
 887          * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
 888          * more than assumed (which would result in overclocking).
 889          */
 890         if (params_width(params) == 24)
 891                 cs42l42->bclk = (cs42l42->bclk / 3) * 4;
 892
 893         switch (substream->stream) {
 894         case SNDRV_PCM_STREAM_CAPTURE:
 895                 /* channel 2 on high LRCLK */
 896                 val = CS42L42_ASP_TX_CH2_AP_MASK |
 897                       (width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
 898                       (width << CS42L42_ASP_TX_CH1_RES_SHIFT);
 899
 900                 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
 901                                 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
 902                                 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
 903                 break;
 904         case SNDRV_PCM_STREAM_PLAYBACK:
 905                 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
 906                 /* channel 1 on low LRCLK */
 907                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 908                                                          CS42L42_ASP_RX_CH_AP_MASK |
 909                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 910                 /* Channel 2 on high LRCLK */
 911                 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
 912                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 913                                                          CS42L42_ASP_RX_CH_AP_MASK |
 914                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 915
 916                 /* Channel B comes from the last active channel */
 917                 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
 918                                               CS42L42_SP_RX_CHB_SEL_MASK,
 919                                               (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
 920
 921                 /* Both LRCLK slots must be enabled */
 922                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 923                                               CS42L42_ASP_RX0_CH_EN_MASK,
 924                                               BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
 925                                               BIT(CS42L42_ASP_RX0_CH2_SHIFT));
 926                 break;
 927         default:
 928                 break;
 929         }
 930
 931         ret = cs42l42_pll_config(component);
 932         if (ret)
 933                 return ret;
 934
 935         cs42l42_src_config(component, params_rate(params));
 936
 937         return 0;
 938 }
 939
 940 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 941                                 int clk_id, unsigned int freq, int dir)
 942 {
 943         struct snd_soc_component *component = dai->component;
 944         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 945         int i;
 946
 947         if (freq == 0) {
 948                 cs42l42->sclk = 0;
 949                 return 0;
 950         }
 951
 952         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 953                 if (pll_ratio_table[i].sclk == freq) {
 954                         cs42l42->sclk = freq;
 955                         return 0;
 956                 }
 957         }
 958
 959         dev_err(component->dev, "SCLK %u not supported\n", freq);
 960
 961         return -EINVAL;
 962 }
 963
 964 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
 965 {
 966         struct snd_soc_component *component = dai->component;
 967         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 968         unsigned int regval;
 969         int ret;
 970
 971         if (mute) {
 972                 /* Mute the headphone */
 973                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 974                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
 975                                                       CS42L42_HP_ANA_AMUTE_MASK |
 976                                                       CS42L42_HP_ANA_BMUTE_MASK,
 977                                                       CS42L42_HP_ANA_AMUTE_MASK |
 978                                                       CS42L42_HP_ANA_BMUTE_MASK);
 979
 980                 cs42l42->stream_use &= ~(1 << stream);
 981                 if (!cs42l42->stream_use) {
 982                         /*
 983                          * Switch to the internal oscillator.
 984                          * SCLK must remain running until after this clock switch.
 985                          * Without a source of clock the I2C bus doesn't work.
 986                          */
 987                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
 988                                                ARRAY_SIZE(cs42l42_to_osc_seq));
 989
 990                         /* Must disconnect PLL before stopping it */
 991                         snd_soc_component_update_bits(component,
 992                                                       CS42L42_MCLK_SRC_SEL,
 993                                                       CS42L42_MCLK_SRC_SEL_MASK,
 994                                                       0);
 995                         usleep_range(100, 200);
 996
 997                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
 998                                                       CS42L42_PLL_START_MASK, 0);
 999                 }
1000         } else {
1001                 if (!cs42l42->stream_use) {
1002                         /* SCLK must be running before codec unmute */
1003                         if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
1004                                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1005                                                               CS42L42_PLL_START_MASK, 1);
1006
1007                                 if (cs42l42->pll_divout) {
1008                                         usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
1009                                                      CS42L42_PLL_DIVOUT_TIME_US * 2);
1010                                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
1011                                                                       CS42L42_PLL_DIVOUT_MASK,
1012                                                                       cs42l42->pll_divout <<
1013                                                                       CS42L42_PLL_DIVOUT_SHIFT);
1014                                 }
1015
1016                                 ret = regmap_read_poll_timeout(cs42l42->regmap,
1017                                                                CS42L42_PLL_LOCK_STATUS,
1018                                                                regval,
1019                                                                (regval & 1),
1020                                                                CS42L42_PLL_LOCK_POLL_US,
1021                                                                CS42L42_PLL_LOCK_TIMEOUT_US);
1022                                 if (ret < 0)
1023                                         dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
1024
1025                                 /* PLL must be running to drive glitchless switch logic */
1026                                 snd_soc_component_update_bits(component,
1027                                                               CS42L42_MCLK_SRC_SEL,
1028                                                               CS42L42_MCLK_SRC_SEL_MASK,
1029                                                               CS42L42_MCLK_SRC_SEL_MASK);
1030                         }
1031
1032                         /* Mark SCLK as present, turn off internal oscillator */
1033                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
1034                                                ARRAY_SIZE(cs42l42_to_sclk_seq));
1035                 }
1036                 cs42l42->stream_use |= 1 << stream;
1037
1038                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1039                         /* Un-mute the headphone */
1040                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1041                                                       CS42L42_HP_ANA_AMUTE_MASK |
1042                                                       CS42L42_HP_ANA_BMUTE_MASK,
1043                                                       0);
1044                 }
1045         }
1046
1047         return 0;
1048 }
1049
1050 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1051                          SNDRV_PCM_FMTBIT_S24_LE |\
1052                          SNDRV_PCM_FMTBIT_S32_LE)
1053
1054 static const struct snd_soc_dai_ops cs42l42_ops = {
1055         .startup        = cs42l42_dai_startup,
1056         .hw_params      = cs42l42_pcm_hw_params,
1057         .set_fmt        = cs42l42_set_dai_fmt,
1058         .set_sysclk     = cs42l42_set_sysclk,
1059         .mute_stream    = cs42l42_mute_stream,
1060 };
1061
1062 static struct snd_soc_dai_driver cs42l42_dai = {
1063                 .name = "cs42l42",
1064                 .playback = {
1065                         .stream_name = "Playback",
1066                         .channels_min = 1,
1067                         .channels_max = 2,
1068                         .rates = SNDRV_PCM_RATE_8000_96000,
1069                         .formats = CS42L42_FORMATS,
1070                 },
1071                 .capture = {
1072                         .stream_name = "Capture",
1073                         .channels_min = 1,
1074                         .channels_max = 2,
1075                         .rates = SNDRV_PCM_RATE_8000_96000,
1076                         .formats = CS42L42_FORMATS,
1077                 },
1078                 .symmetric_rate = 1,
1079                 .symmetric_sample_bits = 1,
1080                 .ops = &cs42l42_ops,
1081 };
1082
1083 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42)
1084 {
1085         unsigned int hs_det_status;
1086         unsigned int hs_det_comp1;
1087         unsigned int hs_det_comp2;
1088         unsigned int hs_det_sw;
1089
1090         /* Set hs detect to manual, active mode */
1091         regmap_update_bits(cs42l42->regmap,
1092                 CS42L42_HSDET_CTL2,
1093                 CS42L42_HSDET_CTRL_MASK |
1094                 CS42L42_HSDET_SET_MASK |
1095                 CS42L42_HSBIAS_REF_MASK |
1096                 CS42L42_HSDET_AUTO_TIME_MASK,
1097                 (1 << CS42L42_HSDET_CTRL_SHIFT) |
1098                 (0 << CS42L42_HSDET_SET_SHIFT) |
1099                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1100                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1101
1102         /* Configure HS DET comparator reference levels. */
1103         regmap_update_bits(cs42l42->regmap,
1104                                 CS42L42_HSDET_CTL1,
1105                                 CS42L42_HSDET_COMP1_LVL_MASK |
1106                                 CS42L42_HSDET_COMP2_LVL_MASK,
1107                                 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1108                                 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
1109
1110         /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
1111         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
1112
1113         msleep(100);
1114
1115         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1116
1117         hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1118                         CS42L42_HSDET_COMP1_OUT_SHIFT;
1119         hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1120                         CS42L42_HSDET_COMP2_OUT_SHIFT;
1121
1122         /* Close the SW_HSB_HS3 switch for a Type 2 headset. */
1123         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
1124
1125         msleep(100);
1126
1127         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1128
1129         hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1130                         CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
1131         hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1132                         CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
1133
1134         /* Use Comparator 1 with 1.25V Threshold. */
1135         switch (hs_det_comp1) {
1136         case CS42L42_HSDET_COMP_TYPE1:
1137                 cs42l42->hs_type = CS42L42_PLUG_CTIA;
1138                 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1139                 break;
1140         case CS42L42_HSDET_COMP_TYPE2:
1141                 cs42l42->hs_type = CS42L42_PLUG_OMTP;
1142                 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1143                 break;
1144         default:
1145                 /* Fallback to Comparator 2 with 1.75V Threshold. */
1146                 switch (hs_det_comp2) {
1147                 case CS42L42_HSDET_COMP_TYPE1:
1148                         cs42l42->hs_type = CS42L42_PLUG_CTIA;
1149                         hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1150                         break;
1151                 case CS42L42_HSDET_COMP_TYPE2:
1152                         cs42l42->hs_type = CS42L42_PLUG_OMTP;
1153                         hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1154                         break;
1155                 case CS42L42_HSDET_COMP_TYPE3:
1156                         cs42l42->hs_type = CS42L42_PLUG_HEADPHONE;
1157                         hs_det_sw = CS42L42_HSDET_SW_TYPE3;
1158                         break;
1159                 default:
1160                         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1161                         hs_det_sw = CS42L42_HSDET_SW_TYPE4;
1162                         break;
1163                 }
1164         }
1165
1166         /* Set Switches */
1167         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw);
1168
1169         /* Set HSDET mode to Manual—Disabled */
1170         regmap_update_bits(cs42l42->regmap,
1171                 CS42L42_HSDET_CTL2,
1172                 CS42L42_HSDET_CTRL_MASK |
1173                 CS42L42_HSDET_SET_MASK |
1174                 CS42L42_HSBIAS_REF_MASK |
1175                 CS42L42_HSDET_AUTO_TIME_MASK,
1176                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1177                 (0 << CS42L42_HSDET_SET_SHIFT) |
1178                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1179                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1180
1181         /* Configure HS DET comparator reference levels. */
1182         regmap_update_bits(cs42l42->regmap,
1183                                 CS42L42_HSDET_CTL1,
1184                                 CS42L42_HSDET_COMP1_LVL_MASK |
1185                                 CS42L42_HSDET_COMP2_LVL_MASK,
1186                                 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1187                                 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
1188 }
1189
1190 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
1191 {
1192         unsigned int hs_det_status;
1193         unsigned int int_status;
1194
1195         /* Read and save the hs detection result */
1196         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1197
1198         /* Mask the auto detect interrupt */
1199         regmap_update_bits(cs42l42->regmap,
1200                 CS42L42_CODEC_INT_MASK,
1201                 CS42L42_PDN_DONE_MASK |
1202                 CS42L42_HSDET_AUTO_DONE_MASK,
1203                 (1 << CS42L42_PDN_DONE_SHIFT) |
1204                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1205
1206
1207         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1208                                 CS42L42_HSDET_TYPE_SHIFT;
1209
1210         /* Set hs detect to automatic, disabled mode */
1211         regmap_update_bits(cs42l42->regmap,
1212                 CS42L42_HSDET_CTL2,
1213                 CS42L42_HSDET_CTRL_MASK |
1214                 CS42L42_HSDET_SET_MASK |
1215                 CS42L42_HSBIAS_REF_MASK |
1216                 CS42L42_HSDET_AUTO_TIME_MASK,
1217                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
1218                 (2 << CS42L42_HSDET_SET_SHIFT) |
1219                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1220                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1221
1222         /* Run Manual detection if auto detect has not found a headset.
1223          * We Re-Run with Manual Detection if the original detection was invalid or headphones,
1224          * to ensure that a headset mic is detected in all cases.
1225          */
1226         if (cs42l42->hs_type == CS42L42_PLUG_INVALID ||
1227                 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) {
1228                 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n");
1229                 cs42l42_manual_hs_type_detect(cs42l42);
1230         }
1231
1232         /* Set up button detection */
1233         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1234               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1235                 /* Set auto HS bias settings to default */
1236                 regmap_update_bits(cs42l42->regmap,
1237                         CS42L42_HSBIAS_SC_AUTOCTL,
1238                         CS42L42_HSBIAS_SENSE_EN_MASK |
1239                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1240                         CS42L42_TIP_SENSE_EN_MASK |
1241                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1242                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1243                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1244                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1245                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1246
1247                 /* Set up hs detect level sensitivity */
1248                 regmap_update_bits(cs42l42->regmap,
1249                         CS42L42_MIC_DET_CTL1,
1250                         CS42L42_LATCH_TO_VP_MASK |
1251                         CS42L42_EVENT_STAT_SEL_MASK |
1252                         CS42L42_HS_DET_LEVEL_MASK,
1253                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1254                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1255                         (cs42l42->bias_thresholds[0] <<
1256                         CS42L42_HS_DET_LEVEL_SHIFT));
1257
1258                 /* Set auto HS bias settings to default */
1259                 regmap_update_bits(cs42l42->regmap,
1260                         CS42L42_HSBIAS_SC_AUTOCTL,
1261                         CS42L42_HSBIAS_SENSE_EN_MASK |
1262                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1263                         CS42L42_TIP_SENSE_EN_MASK |
1264                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1265                         (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1266                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1267                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1268                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1269
1270                 /* Turn on level detect circuitry */
1271                 regmap_update_bits(cs42l42->regmap,
1272                         CS42L42_MISC_DET_CTL,
1273                         CS42L42_DETECT_MODE_MASK |
1274                         CS42L42_HSBIAS_CTL_MASK |
1275                         CS42L42_PDN_MIC_LVL_DET_MASK,
1276                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1277                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1278                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1279
1280                 msleep(cs42l42->btn_det_init_dbnce);
1281
1282                 /* Clear any button interrupts before unmasking them */
1283                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1284                             &int_status);
1285
1286                 /* Unmask button detect interrupts */
1287                 regmap_update_bits(cs42l42->regmap,
1288                         CS42L42_DET_INT2_MASK,
1289                         CS42L42_M_DETECT_TF_MASK |
1290                         CS42L42_M_DETECT_FT_MASK |
1291                         CS42L42_M_HSBIAS_HIZ_MASK |
1292                         CS42L42_M_SHORT_RLS_MASK |
1293                         CS42L42_M_SHORT_DET_MASK,
1294                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1295                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1296                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1297                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1298                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1299         } else {
1300                 /* Make sure button detect and HS bias circuits are off */
1301                 regmap_update_bits(cs42l42->regmap,
1302                         CS42L42_MISC_DET_CTL,
1303                         CS42L42_DETECT_MODE_MASK |
1304                         CS42L42_HSBIAS_CTL_MASK |
1305                         CS42L42_PDN_MIC_LVL_DET_MASK,
1306                         (0 << CS42L42_DETECT_MODE_SHIFT) |
1307                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1308                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1309         }
1310
1311         regmap_update_bits(cs42l42->regmap,
1312                                 CS42L42_DAC_CTL2,
1313                                 CS42L42_HPOUT_PULLDOWN_MASK |
1314                                 CS42L42_HPOUT_LOAD_MASK |
1315                                 CS42L42_HPOUT_CLAMP_MASK |
1316                                 CS42L42_DAC_HPF_EN_MASK |
1317                                 CS42L42_DAC_MON_EN_MASK,
1318                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1319                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1320                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1321                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1322                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1323
1324         /* Unmask tip sense interrupts */
1325         regmap_update_bits(cs42l42->regmap,
1326                 CS42L42_TSRS_PLUG_INT_MASK,
1327                 CS42L42_RS_PLUG_MASK |
1328                 CS42L42_RS_UNPLUG_MASK |
1329                 CS42L42_TS_PLUG_MASK |
1330                 CS42L42_TS_UNPLUG_MASK,
1331                 (1 << CS42L42_RS_PLUG_SHIFT) |
1332                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1333                 (0 << CS42L42_TS_PLUG_SHIFT) |
1334                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1335 }
1336
1337 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1338 {
1339         /* Mask tip sense interrupts */
1340         regmap_update_bits(cs42l42->regmap,
1341                                 CS42L42_TSRS_PLUG_INT_MASK,
1342                                 CS42L42_RS_PLUG_MASK |
1343                                 CS42L42_RS_UNPLUG_MASK |
1344                                 CS42L42_TS_PLUG_MASK |
1345                                 CS42L42_TS_UNPLUG_MASK,
1346                                 (1 << CS42L42_RS_PLUG_SHIFT) |
1347                                 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1348                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1349                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1350
1351         /* Make sure button detect and HS bias circuits are off */
1352         regmap_update_bits(cs42l42->regmap,
1353                                 CS42L42_MISC_DET_CTL,
1354                                 CS42L42_DETECT_MODE_MASK |
1355                                 CS42L42_HSBIAS_CTL_MASK |
1356                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1357                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1358                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1359                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1360
1361         /* Set auto HS bias settings to default */
1362         regmap_update_bits(cs42l42->regmap,
1363                                 CS42L42_HSBIAS_SC_AUTOCTL,
1364                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1365                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1366                                 CS42L42_TIP_SENSE_EN_MASK |
1367                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1368                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1369                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1370                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1371                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1372
1373         /* Set hs detect to manual, disabled mode */
1374         regmap_update_bits(cs42l42->regmap,
1375                                 CS42L42_HSDET_CTL2,
1376                                 CS42L42_HSDET_CTRL_MASK |
1377                                 CS42L42_HSDET_SET_MASK |
1378                                 CS42L42_HSBIAS_REF_MASK |
1379                                 CS42L42_HSDET_AUTO_TIME_MASK,
1380                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1381                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1382                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1383                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1384
1385         regmap_update_bits(cs42l42->regmap,
1386                                 CS42L42_DAC_CTL2,
1387                                 CS42L42_HPOUT_PULLDOWN_MASK |
1388                                 CS42L42_HPOUT_LOAD_MASK |
1389                                 CS42L42_HPOUT_CLAMP_MASK |
1390                                 CS42L42_DAC_HPF_EN_MASK |
1391                                 CS42L42_DAC_MON_EN_MASK,
1392                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1393                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1394                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1395                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1396                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1397
1398         /* Power up HS bias to 2.7V */
1399         regmap_update_bits(cs42l42->regmap,
1400                                 CS42L42_MISC_DET_CTL,
1401                                 CS42L42_DETECT_MODE_MASK |
1402                                 CS42L42_HSBIAS_CTL_MASK |
1403                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1404                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1405                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1406                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1407
1408         /* Wait for HS bias to ramp up */
1409         msleep(cs42l42->hs_bias_ramp_time);
1410
1411         /* Unmask auto detect interrupt */
1412         regmap_update_bits(cs42l42->regmap,
1413                                 CS42L42_CODEC_INT_MASK,
1414                                 CS42L42_PDN_DONE_MASK |
1415                                 CS42L42_HSDET_AUTO_DONE_MASK,
1416                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1417                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1418
1419         /* Set hs detect to automatic, enabled mode */
1420         regmap_update_bits(cs42l42->regmap,
1421                                 CS42L42_HSDET_CTL2,
1422                                 CS42L42_HSDET_CTRL_MASK |
1423                                 CS42L42_HSDET_SET_MASK |
1424                                 CS42L42_HSBIAS_REF_MASK |
1425                                 CS42L42_HSDET_AUTO_TIME_MASK,
1426                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1427                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1428                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1429                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1430 }
1431
1432 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1433 {
1434         /* Mask button detect interrupts */
1435         regmap_update_bits(cs42l42->regmap,
1436                 CS42L42_DET_INT2_MASK,
1437                 CS42L42_M_DETECT_TF_MASK |
1438                 CS42L42_M_DETECT_FT_MASK |
1439                 CS42L42_M_HSBIAS_HIZ_MASK |
1440                 CS42L42_M_SHORT_RLS_MASK |
1441                 CS42L42_M_SHORT_DET_MASK,
1442                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1443                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1444                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1445                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1446                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1447
1448         /* Ground HS bias */
1449         regmap_update_bits(cs42l42->regmap,
1450                                 CS42L42_MISC_DET_CTL,
1451                                 CS42L42_DETECT_MODE_MASK |
1452                                 CS42L42_HSBIAS_CTL_MASK |
1453                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1454                                 (0 << CS42L42_DETECT_MODE_SHIFT) |
1455                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1456                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1457
1458         /* Set auto HS bias settings to default */
1459         regmap_update_bits(cs42l42->regmap,
1460                                 CS42L42_HSBIAS_SC_AUTOCTL,
1461                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1462                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1463                                 CS42L42_TIP_SENSE_EN_MASK |
1464                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1465                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1466                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1467                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1468                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1469
1470         /* Set hs detect to manual, disabled mode */
1471         regmap_update_bits(cs42l42->regmap,
1472                                 CS42L42_HSDET_CTL2,
1473                                 CS42L42_HSDET_CTRL_MASK |
1474                                 CS42L42_HSDET_SET_MASK |
1475                                 CS42L42_HSBIAS_REF_MASK |
1476                                 CS42L42_HSDET_AUTO_TIME_MASK,
1477                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1478                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1479                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1480                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1481 }
1482
1483 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1484 {
1485         int bias_level;
1486         unsigned int detect_status;
1487
1488         /* Mask button detect interrupts */
1489         regmap_update_bits(cs42l42->regmap,
1490                 CS42L42_DET_INT2_MASK,
1491                 CS42L42_M_DETECT_TF_MASK |
1492                 CS42L42_M_DETECT_FT_MASK |
1493                 CS42L42_M_HSBIAS_HIZ_MASK |
1494                 CS42L42_M_SHORT_RLS_MASK |
1495                 CS42L42_M_SHORT_DET_MASK,
1496                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1497                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1498                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1499                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1500                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1501
1502         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1503                      cs42l42->btn_det_event_dbnce * 2000);
1504
1505         /* Test all 4 level detect biases */
1506         bias_level = 1;
1507         do {
1508                 /* Adjust button detect level sensitivity */
1509                 regmap_update_bits(cs42l42->regmap,
1510                         CS42L42_MIC_DET_CTL1,
1511                         CS42L42_LATCH_TO_VP_MASK |
1512                         CS42L42_EVENT_STAT_SEL_MASK |
1513                         CS42L42_HS_DET_LEVEL_MASK,
1514                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1515                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1516                         (cs42l42->bias_thresholds[bias_level] <<
1517                         CS42L42_HS_DET_LEVEL_SHIFT));
1518
1519                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1520                                 &detect_status);
1521         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1522                 (++bias_level < CS42L42_NUM_BIASES));
1523
1524         switch (bias_level) {
1525         case 1: /* Function C button press */
1526                 bias_level = SND_JACK_BTN_2;
1527                 dev_dbg(cs42l42->dev, "Function C button press\n");
1528                 break;
1529         case 2: /* Function B button press */
1530                 bias_level = SND_JACK_BTN_1;
1531                 dev_dbg(cs42l42->dev, "Function B button press\n");
1532                 break;
1533         case 3: /* Function D button press */
1534                 bias_level = SND_JACK_BTN_3;
1535                 dev_dbg(cs42l42->dev, "Function D button press\n");
1536                 break;
1537         case 4: /* Function A button press */
1538                 bias_level = SND_JACK_BTN_0;
1539                 dev_dbg(cs42l42->dev, "Function A button press\n");
1540                 break;
1541         default:
1542                 bias_level = 0;
1543                 break;
1544         }
1545
1546         /* Set button detect level sensitivity back to default */
1547         regmap_update_bits(cs42l42->regmap,
1548                 CS42L42_MIC_DET_CTL1,
1549                 CS42L42_LATCH_TO_VP_MASK |
1550                 CS42L42_EVENT_STAT_SEL_MASK |
1551                 CS42L42_HS_DET_LEVEL_MASK,
1552                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1553                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1554                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1555
1556         /* Clear any button interrupts before unmasking them */
1557         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1558                     &detect_status);
1559
1560         /* Unmask button detect interrupts */
1561         regmap_update_bits(cs42l42->regmap,
1562                 CS42L42_DET_INT2_MASK,
1563                 CS42L42_M_DETECT_TF_MASK |
1564                 CS42L42_M_DETECT_FT_MASK |
1565                 CS42L42_M_HSBIAS_HIZ_MASK |
1566                 CS42L42_M_SHORT_RLS_MASK |
1567                 CS42L42_M_SHORT_DET_MASK,
1568                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1569                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1570                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1571                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1572                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1573
1574         return bias_level;
1575 }
1576
1577 struct cs42l42_irq_params {
1578         u16 status_addr;
1579         u16 mask_addr;
1580         u8 mask;
1581 };
1582
1583 static const struct cs42l42_irq_params irq_params_table[] = {
1584         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1585                 CS42L42_ADC_OVFL_VAL_MASK},
1586         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1587                 CS42L42_MIXER_VAL_MASK},
1588         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1589                 CS42L42_SRC_VAL_MASK},
1590         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1591                 CS42L42_ASP_RX_VAL_MASK},
1592         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1593                 CS42L42_ASP_TX_VAL_MASK},
1594         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1595                 CS42L42_CODEC_VAL_MASK},
1596         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1597                 CS42L42_DET_INT_VAL1_MASK},
1598         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1599                 CS42L42_DET_INT_VAL2_MASK},
1600         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1601                 CS42L42_SRCPL_VAL_MASK},
1602         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1603                 CS42L42_VPMON_VAL_MASK},
1604         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1605                 CS42L42_PLL_LOCK_VAL_MASK},
1606         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1607                 CS42L42_TSRS_PLUG_VAL_MASK}
1608 };
1609
1610 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1611 {
1612         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1613         unsigned int stickies[12];
1614         unsigned int masks[12];
1615         unsigned int current_plug_status;
1616         unsigned int current_button_status;
1617         unsigned int i;
1618         int report = 0;
1619
1620
1621         /* Read sticky registers to clear interurpt */
1622         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1623                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1624                                 &(stickies[i]));
1625                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1626                                 &(masks[i]));
1627                 stickies[i] = stickies[i] & (~masks[i]) &
1628                                 irq_params_table[i].mask;
1629         }
1630
1631         /* Read tip sense status before handling type detect */
1632         current_plug_status = (stickies[11] &
1633                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1634                 CS42L42_TS_PLUG_SHIFT;
1635
1636         /* Read button sense status */
1637         current_button_status = stickies[7] &
1638                 (CS42L42_M_DETECT_TF_MASK |
1639                 CS42L42_M_DETECT_FT_MASK |
1640                 CS42L42_M_HSBIAS_HIZ_MASK);
1641
1642         /* Check auto-detect status */
1643         if ((~masks[5]) & irq_params_table[5].mask) {
1644                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1645                         cs42l42_process_hs_type_detect(cs42l42);
1646                         switch (cs42l42->hs_type) {
1647                         case CS42L42_PLUG_CTIA:
1648                         case CS42L42_PLUG_OMTP:
1649                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1650                                                     SND_JACK_HEADSET);
1651                                 break;
1652                         case CS42L42_PLUG_HEADPHONE:
1653                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1654                                                     SND_JACK_HEADPHONE);
1655                                 break;
1656                         default:
1657                                 break;
1658                         }
1659                         dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1660                 }
1661         }
1662
1663         /* Check tip sense status */
1664         if ((~masks[11]) & irq_params_table[11].mask) {
1665                 switch (current_plug_status) {
1666                 case CS42L42_TS_PLUG:
1667                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1668                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1669                                 cs42l42_init_hs_type_detect(cs42l42);
1670                         }
1671                         break;
1672
1673                 case CS42L42_TS_UNPLUG:
1674                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1675                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1676                                 cs42l42_cancel_hs_type_detect(cs42l42);
1677
1678                                 switch (cs42l42->hs_type) {
1679                                 case CS42L42_PLUG_CTIA:
1680                                 case CS42L42_PLUG_OMTP:
1681                                         snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADSET);
1682                                         break;
1683                                 case CS42L42_PLUG_HEADPHONE:
1684                                         snd_soc_jack_report(cs42l42->jack, 0, SND_JACK_HEADPHONE);
1685                                         break;
1686                                 default:
1687                                         break;
1688                                 }
1689                                 snd_soc_jack_report(cs42l42->jack, 0,
1690                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1691                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1692
1693                                 dev_dbg(cs42l42->dev, "Unplug event\n");
1694                         }
1695                         break;
1696
1697                 default:
1698                         if (cs42l42->plug_state != CS42L42_TS_TRANS)
1699                                 cs42l42->plug_state = CS42L42_TS_TRANS;
1700                 }
1701         }
1702
1703         /* Check button detect status */
1704         if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
1705                 if (!(current_button_status &
1706                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1707
1708                         if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1709                                 dev_dbg(cs42l42->dev, "Button released\n");
1710                                 report = 0;
1711                         } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1712                                 report = cs42l42_handle_button_press(cs42l42);
1713
1714                         }
1715                         snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1716                                                                    SND_JACK_BTN_2 | SND_JACK_BTN_3);
1717                 }
1718         }
1719
1720         return IRQ_HANDLED;
1721 }
1722
1723 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1724 {
1725         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1726                         CS42L42_ADC_OVFL_MASK,
1727                         (1 << CS42L42_ADC_OVFL_SHIFT));
1728
1729         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1730                         CS42L42_MIX_CHB_OVFL_MASK |
1731                         CS42L42_MIX_CHA_OVFL_MASK |
1732                         CS42L42_EQ_OVFL_MASK |
1733                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1734                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1735                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1736                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1737                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1738
1739         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1740                         CS42L42_SRC_ILK_MASK |
1741                         CS42L42_SRC_OLK_MASK |
1742                         CS42L42_SRC_IUNLK_MASK |
1743                         CS42L42_SRC_OUNLK_MASK,
1744                         (1 << CS42L42_SRC_ILK_SHIFT) |
1745                         (1 << CS42L42_SRC_OLK_SHIFT) |
1746                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1747                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1748
1749         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1750                         CS42L42_ASPRX_NOLRCK_MASK |
1751                         CS42L42_ASPRX_EARLY_MASK |
1752                         CS42L42_ASPRX_LATE_MASK |
1753                         CS42L42_ASPRX_ERROR_MASK |
1754                         CS42L42_ASPRX_OVLD_MASK,
1755                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1756                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1757                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1758                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1759                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1760
1761         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1762                         CS42L42_ASPTX_NOLRCK_MASK |
1763                         CS42L42_ASPTX_EARLY_MASK |
1764                         CS42L42_ASPTX_LATE_MASK |
1765                         CS42L42_ASPTX_SMERROR_MASK,
1766                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1767                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1768                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1769                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1770
1771         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1772                         CS42L42_PDN_DONE_MASK |
1773                         CS42L42_HSDET_AUTO_DONE_MASK,
1774                         (1 << CS42L42_PDN_DONE_SHIFT) |
1775                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1776
1777         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1778                         CS42L42_SRCPL_ADC_LK_MASK |
1779                         CS42L42_SRCPL_DAC_LK_MASK |
1780                         CS42L42_SRCPL_ADC_UNLK_MASK |
1781                         CS42L42_SRCPL_DAC_UNLK_MASK,
1782                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1783                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1784                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1785                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1786
1787         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1788                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1789                         CS42L42_TIP_SENSE_PLUG_MASK |
1790                         CS42L42_HSBIAS_SENSE_MASK,
1791                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1792                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1793                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1794
1795         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1796                         CS42L42_M_DETECT_TF_MASK |
1797                         CS42L42_M_DETECT_FT_MASK |
1798                         CS42L42_M_HSBIAS_HIZ_MASK |
1799                         CS42L42_M_SHORT_RLS_MASK |
1800                         CS42L42_M_SHORT_DET_MASK,
1801                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1802                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1803                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1804                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1805                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1806
1807         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1808                         CS42L42_VPMON_MASK,
1809                         (1 << CS42L42_VPMON_SHIFT));
1810
1811         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1812                         CS42L42_PLL_LOCK_MASK,
1813                         (1 << CS42L42_PLL_LOCK_SHIFT));
1814
1815         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1816                         CS42L42_RS_PLUG_MASK |
1817                         CS42L42_RS_UNPLUG_MASK |
1818                         CS42L42_TS_PLUG_MASK |
1819                         CS42L42_TS_UNPLUG_MASK,
1820                         (1 << CS42L42_RS_PLUG_SHIFT) |
1821                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1822                         (0 << CS42L42_TS_PLUG_SHIFT) |
1823                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1824 }
1825
1826 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1827 {
1828         unsigned int reg;
1829
1830         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1831
1832         /* Latch analog controls to VP power domain */
1833         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1834                         CS42L42_LATCH_TO_VP_MASK |
1835                         CS42L42_EVENT_STAT_SEL_MASK |
1836                         CS42L42_HS_DET_LEVEL_MASK,
1837                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1838                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1839                         (cs42l42->bias_thresholds[0] <<
1840                         CS42L42_HS_DET_LEVEL_SHIFT));
1841
1842         /* Remove ground noise-suppression clamps */
1843         regmap_update_bits(cs42l42->regmap,
1844                         CS42L42_HS_CLAMP_DISABLE,
1845                         CS42L42_HS_CLAMP_DISABLE_MASK,
1846                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1847
1848         /* Enable the tip sense circuit */
1849         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1850                            CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
1851
1852         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1853                         CS42L42_TIP_SENSE_CTRL_MASK |
1854                         CS42L42_TIP_SENSE_INV_MASK |
1855                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1856                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1857                         (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
1858                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1859
1860         /* Save the initial status of the tip sense */
1861         regmap_read(cs42l42->regmap,
1862                           CS42L42_TSRS_PLUG_STATUS,
1863                           &reg);
1864         cs42l42->plug_state = (((char) reg) &
1865                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1866                       CS42L42_TS_PLUG_SHIFT;
1867 }
1868
1869 static const unsigned int threshold_defaults[] = {
1870         CS42L42_HS_DET_LEVEL_15,
1871         CS42L42_HS_DET_LEVEL_8,
1872         CS42L42_HS_DET_LEVEL_4,
1873         CS42L42_HS_DET_LEVEL_1
1874 };
1875
1876 static int cs42l42_handle_device_data(struct device *dev,
1877                                         struct cs42l42_private *cs42l42)
1878 {
1879         unsigned int val;
1880         u32 thresholds[CS42L42_NUM_BIASES];
1881         int ret;
1882         int i;
1883
1884         ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1885         if (!ret) {
1886                 switch (val) {
1887                 case CS42L42_TS_INV_EN:
1888                 case CS42L42_TS_INV_DIS:
1889                         cs42l42->ts_inv = val;
1890                         break;
1891                 default:
1892                         dev_err(dev,
1893                                 "Wrong cirrus,ts-inv DT value %d\n",
1894                                 val);
1895                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1896                 }
1897         } else {
1898                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1899         }
1900
1901         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1902         if (!ret) {
1903                 switch (val) {
1904                 case CS42L42_TS_DBNCE_0:
1905                 case CS42L42_TS_DBNCE_125:
1906                 case CS42L42_TS_DBNCE_250:
1907                 case CS42L42_TS_DBNCE_500:
1908                 case CS42L42_TS_DBNCE_750:
1909                 case CS42L42_TS_DBNCE_1000:
1910                 case CS42L42_TS_DBNCE_1250:
1911                 case CS42L42_TS_DBNCE_1500:
1912                         cs42l42->ts_dbnc_rise = val;
1913                         break;
1914                 default:
1915                         dev_err(dev,
1916                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1917                                 val);
1918                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1919                 }
1920         } else {
1921                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1922         }
1923
1924         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1925                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1926                         (cs42l42->ts_dbnc_rise <<
1927                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1928
1929         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1930         if (!ret) {
1931                 switch (val) {
1932                 case CS42L42_TS_DBNCE_0:
1933                 case CS42L42_TS_DBNCE_125:
1934                 case CS42L42_TS_DBNCE_250:
1935                 case CS42L42_TS_DBNCE_500:
1936                 case CS42L42_TS_DBNCE_750:
1937                 case CS42L42_TS_DBNCE_1000:
1938                 case CS42L42_TS_DBNCE_1250:
1939                 case CS42L42_TS_DBNCE_1500:
1940                         cs42l42->ts_dbnc_fall = val;
1941                         break;
1942                 default:
1943                         dev_err(dev,
1944                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1945                                 val);
1946                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1947                 }
1948         } else {
1949                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1950         }
1951
1952         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1953                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1954                         (cs42l42->ts_dbnc_fall <<
1955                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1956
1957         ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
1958         if (!ret) {
1959                 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1960                         cs42l42->btn_det_init_dbnce = val;
1961                 else {
1962                         dev_err(dev,
1963                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1964                                 val);
1965                         cs42l42->btn_det_init_dbnce =
1966                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1967                 }
1968         } else {
1969                 cs42l42->btn_det_init_dbnce =
1970                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1971         }
1972
1973         ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
1974         if (!ret) {
1975                 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1976                         cs42l42->btn_det_event_dbnce = val;
1977                 else {
1978                         dev_err(dev,
1979                                 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1980                         cs42l42->btn_det_event_dbnce =
1981                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1982                 }
1983         } else {
1984                 cs42l42->btn_det_event_dbnce =
1985                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1986         }
1987
1988         ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
1989                                              thresholds, ARRAY_SIZE(thresholds));
1990         if (!ret) {
1991                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1992                         if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
1993                                 cs42l42->bias_thresholds[i] = thresholds[i];
1994                         else {
1995                                 dev_err(dev,
1996                                         "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1997                                         thresholds[i]);
1998                                 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1999                         }
2000                 }
2001         } else {
2002                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
2003                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
2004         }
2005
2006         ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
2007         if (!ret) {
2008                 switch (val) {
2009                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
2010                         cs42l42->hs_bias_ramp_rate = val;
2011                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
2012                         break;
2013                 case CS42L42_HSBIAS_RAMP_FAST:
2014                         cs42l42->hs_bias_ramp_rate = val;
2015                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
2016                         break;
2017                 case CS42L42_HSBIAS_RAMP_SLOW:
2018                         cs42l42->hs_bias_ramp_rate = val;
2019                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2020                         break;
2021                 case CS42L42_HSBIAS_RAMP_SLOWEST:
2022                         cs42l42->hs_bias_ramp_rate = val;
2023                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
2024                         break;
2025                 default:
2026                         dev_err(dev,
2027                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
2028                                 val);
2029                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2030                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2031                 }
2032         } else {
2033                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2034                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2035         }
2036
2037         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
2038                         CS42L42_HSBIAS_RAMP_MASK,
2039                         (cs42l42->hs_bias_ramp_rate <<
2040                         CS42L42_HSBIAS_RAMP_SHIFT));
2041
2042         if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
2043                 cs42l42->hs_bias_sense_en = 0;
2044         else
2045                 cs42l42->hs_bias_sense_en = 1;
2046
2047         return 0;
2048 }
2049
2050 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
2051                                        const struct i2c_device_id *id)
2052 {
2053         struct cs42l42_private *cs42l42;
2054         int ret, i, devid;
2055         unsigned int reg;
2056
2057         cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
2058                                GFP_KERNEL);
2059         if (!cs42l42)
2060                 return -ENOMEM;
2061
2062         cs42l42->dev = &i2c_client->dev;
2063         i2c_set_clientdata(i2c_client, cs42l42);
2064
2065         cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
2066         if (IS_ERR(cs42l42->regmap)) {
2067                 ret = PTR_ERR(cs42l42->regmap);
2068                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
2069                 return ret;
2070         }
2071
2072         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
2073                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
2074
2075         ret = devm_regulator_bulk_get(&i2c_client->dev,
2076                                       ARRAY_SIZE(cs42l42->supplies),
2077                                       cs42l42->supplies);
2078         if (ret != 0) {
2079                 dev_err(&i2c_client->dev,
2080                         "Failed to request supplies: %d\n", ret);
2081                 return ret;
2082         }
2083
2084         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
2085                                     cs42l42->supplies);
2086         if (ret != 0) {
2087                 dev_err(&i2c_client->dev,
2088                         "Failed to enable supplies: %d\n", ret);
2089                 return ret;
2090         }
2091
2092         /* Reset the Device */
2093         cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
2094                 "reset", GPIOD_OUT_LOW);
2095         if (IS_ERR(cs42l42->reset_gpio)) {
2096                 ret = PTR_ERR(cs42l42->reset_gpio);
2097                 goto err_disable_noreset;
2098         }
2099
2100         if (cs42l42->reset_gpio) {
2101                 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
2102                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2103         }
2104         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2105
2106         /* Request IRQ if one was specified */
2107         if (i2c_client->irq) {
2108                 ret = request_threaded_irq(i2c_client->irq,
2109                                            NULL, cs42l42_irq_thread,
2110                                            IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2111                                            "cs42l42", cs42l42);
2112                 if (ret == -EPROBE_DEFER) {
2113                         goto err_disable_noirq;
2114                 } else if (ret != 0) {
2115                         dev_err(&i2c_client->dev,
2116                                 "Failed to request IRQ: %d\n", ret);
2117                         goto err_disable_noirq;
2118                 }
2119         }
2120
2121         /* initialize codec */
2122         devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
2123         if (devid < 0) {
2124                 ret = devid;
2125                 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
2126                 goto err_disable;
2127         }
2128
2129         if (devid != CS42L42_CHIP_ID) {
2130                 ret = -ENODEV;
2131                 dev_err(&i2c_client->dev,
2132                         "CS42L42 Device ID (%X). Expected %X\n",
2133                         devid, CS42L42_CHIP_ID);
2134                 goto err_disable;
2135         }
2136
2137         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
2138         if (ret < 0) {
2139                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
2140                 goto err_shutdown;
2141         }
2142
2143         dev_info(&i2c_client->dev,
2144                  "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
2145
2146         /* Power up the codec */
2147         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
2148                         CS42L42_ASP_DAO_PDN_MASK |
2149                         CS42L42_ASP_DAI_PDN_MASK |
2150                         CS42L42_MIXER_PDN_MASK |
2151                         CS42L42_EQ_PDN_MASK |
2152                         CS42L42_HP_PDN_MASK |
2153                         CS42L42_ADC_PDN_MASK |
2154                         CS42L42_PDN_ALL_MASK,
2155                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
2156                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
2157                         (1 << CS42L42_MIXER_PDN_SHIFT) |
2158                         (1 << CS42L42_EQ_PDN_SHIFT) |
2159                         (1 << CS42L42_HP_PDN_SHIFT) |
2160                         (1 << CS42L42_ADC_PDN_SHIFT) |
2161                         (0 << CS42L42_PDN_ALL_SHIFT));
2162
2163         ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42);
2164         if (ret != 0)
2165                 goto err_shutdown;
2166
2167         /* Setup headset detection */
2168         cs42l42_setup_hs_type_detect(cs42l42);
2169
2170         /* Mask/Unmask Interrupts */
2171         cs42l42_set_interrupt_masks(cs42l42);
2172
2173         /* Register codec for machine driver */
2174         ret = devm_snd_soc_register_component(&i2c_client->dev,
2175                         &soc_component_dev_cs42l42, &cs42l42_dai, 1);
2176         if (ret < 0)
2177                 goto err_shutdown;
2178
2179         return 0;
2180
2181 err_shutdown:
2182         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2183         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2184         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2185
2186 err_disable:
2187         if (i2c_client->irq)
2188                 free_irq(i2c_client->irq, cs42l42);
2189
2190 err_disable_noirq:
2191         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2192 err_disable_noreset:
2193         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2194                                 cs42l42->supplies);
2195         return ret;
2196 }
2197
2198 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
2199 {
2200         struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
2201
2202         if (i2c_client->irq)
2203                 free_irq(i2c_client->irq, cs42l42);
2204
2205         /*
2206          * The driver might not have control of reset and power supplies,
2207          * so ensure that the chip internals are powered down.
2208          */
2209         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2210         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2211         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2212
2213         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2214         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2215
2216         return 0;
2217 }
2218
2219 #ifdef CONFIG_OF
2220 static const struct of_device_id cs42l42_of_match[] = {
2221         { .compatible = "cirrus,cs42l42", },
2222         {}
2223 };
2224 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
2225 #endif
2226
2227 #ifdef CONFIG_ACPI
2228 static const struct acpi_device_id cs42l42_acpi_match[] = {
2229         {"10134242", 0,},
2230         {}
2231 };
2232 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match);
2233 #endif
2234
2235 static const struct i2c_device_id cs42l42_id[] = {
2236         {"cs42l42", 0},
2237         {}
2238 };
2239
2240 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
2241
2242 static struct i2c_driver cs42l42_i2c_driver = {
2243         .driver = {
2244                 .name = "cs42l42",
2245                 .of_match_table = of_match_ptr(cs42l42_of_match),
2246                 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match),
2247                 },
2248         .id_table = cs42l42_id,
2249         .probe = cs42l42_i2c_probe,
2250         .remove = cs42l42_i2c_remove,
2251 };
2252
2253 module_i2c_driver(cs42l42_i2c_driver);
2254
2255 MODULE_DESCRIPTION("ASoC CS42L42 driver");
2256 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2257 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2258 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2259 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
2260 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
2261 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
2262 MODULE_LICENSE("GPL");