sound/soc/codecs/cs42l42.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * cs42l42.c -- CS42L42 ALSA SoC audio driver
   4  *
   5  * Copyright 2016 Cirrus Logic, Inc.
   6  *
   7  * Author: James Schulman <james.schulman@cirrus.com>
   8  * Author: Brian Austin <brian.austin@cirrus.com>
   9  * Author: Michael White <michael.white@cirrus.com>
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/version.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/i2c.h>
  19 #include <linux/gpio.h>
  20 #include <linux/regmap.h>
  21 #include <linux/slab.h>
  22 #include <linux/acpi.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/property.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/gpio/consumer.h>
  27 #include <linux/of_device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/soc.h>
  32 #include <sound/soc-dapm.h>
  33 #include <sound/initval.h>
  34 #include <sound/tlv.h>
  35 #include <dt-bindings/sound/cs42l42.h>
  36
  37 #include "cs42l42.h"
  38 #include "cirrus_legacy.h"
  39
  40 static const struct reg_default cs42l42_reg_defaults[] = {
  41         { CS42L42_FRZ_CTL,                      0x00 },
  42         { CS42L42_SRC_CTL,                      0x10 },
  43         { CS42L42_MCLK_CTL,                     0x02 },
  44         { CS42L42_SFTRAMP_RATE,                 0xA4 },
  45         { CS42L42_SLOW_START_ENABLE,            0x70 },
  46         { CS42L42_I2C_DEBOUNCE,                 0x88 },
  47         { CS42L42_I2C_STRETCH,                  0x03 },
  48         { CS42L42_I2C_TIMEOUT,                  0xB7 },
  49         { CS42L42_PWR_CTL1,                     0xFF },
  50         { CS42L42_PWR_CTL2,                     0x84 },
  51         { CS42L42_PWR_CTL3,                     0x20 },
  52         { CS42L42_RSENSE_CTL1,                  0x40 },
  53         { CS42L42_RSENSE_CTL2,                  0x00 },
  54         { CS42L42_OSC_SWITCH,                   0x00 },
  55         { CS42L42_RSENSE_CTL3,                  0x1B },
  56         { CS42L42_TSENSE_CTL,                   0x1B },
  57         { CS42L42_TSRS_INT_DISABLE,             0x00 },
  58         { CS42L42_HSDET_CTL1,                   0x77 },
  59         { CS42L42_HSDET_CTL2,                   0x00 },
  60         { CS42L42_HS_SWITCH_CTL,                0xF3 },
  61         { CS42L42_HS_CLAMP_DISABLE,             0x00 },
  62         { CS42L42_MCLK_SRC_SEL,                 0x00 },
  63         { CS42L42_SPDIF_CLK_CFG,                0x00 },
  64         { CS42L42_FSYNC_PW_LOWER,               0x00 },
  65         { CS42L42_FSYNC_PW_UPPER,               0x00 },
  66         { CS42L42_FSYNC_P_LOWER,                0xF9 },
  67         { CS42L42_FSYNC_P_UPPER,                0x00 },
  68         { CS42L42_ASP_CLK_CFG,                  0x00 },
  69         { CS42L42_ASP_FRM_CFG,                  0x10 },
  70         { CS42L42_FS_RATE_EN,                   0x00 },
  71         { CS42L42_IN_ASRC_CLK,                  0x00 },
  72         { CS42L42_OUT_ASRC_CLK,                 0x00 },
  73         { CS42L42_PLL_DIV_CFG1,                 0x00 },
  74         { CS42L42_ADC_OVFL_INT_MASK,            0x01 },
  75         { CS42L42_MIXER_INT_MASK,               0x0F },
  76         { CS42L42_SRC_INT_MASK,                 0x0F },
  77         { CS42L42_ASP_RX_INT_MASK,              0x1F },
  78         { CS42L42_ASP_TX_INT_MASK,              0x0F },
  79         { CS42L42_CODEC_INT_MASK,               0x03 },
  80         { CS42L42_SRCPL_INT_MASK,               0x7F },
  81         { CS42L42_VPMON_INT_MASK,               0x01 },
  82         { CS42L42_PLL_LOCK_INT_MASK,            0x01 },
  83         { CS42L42_TSRS_PLUG_INT_MASK,           0x0F },
  84         { CS42L42_PLL_CTL1,                     0x00 },
  85         { CS42L42_PLL_DIV_FRAC0,                0x00 },
  86         { CS42L42_PLL_DIV_FRAC1,                0x00 },
  87         { CS42L42_PLL_DIV_FRAC2,                0x00 },
  88         { CS42L42_PLL_DIV_INT,                  0x40 },
  89         { CS42L42_PLL_CTL3,                     0x10 },
  90         { CS42L42_PLL_CAL_RATIO,                0x80 },
  91         { CS42L42_PLL_CTL4,                     0x03 },
  92         { CS42L42_LOAD_DET_EN,                  0x00 },
  93         { CS42L42_HSBIAS_SC_AUTOCTL,            0x03 },
  94         { CS42L42_WAKE_CTL,                     0xC0 },
  95         { CS42L42_ADC_DISABLE_MUTE,             0x00 },
  96         { CS42L42_TIPSENSE_CTL,                 0x02 },
  97         { CS42L42_MISC_DET_CTL,                 0x03 },
  98         { CS42L42_MIC_DET_CTL1,                 0x1F },
  99         { CS42L42_MIC_DET_CTL2,                 0x2F },
 100         { CS42L42_DET_INT1_MASK,                0xE0 },
 101         { CS42L42_DET_INT2_MASK,                0xFF },
 102         { CS42L42_HS_BIAS_CTL,                  0xC2 },
 103         { CS42L42_ADC_CTL,                      0x00 },
 104         { CS42L42_ADC_VOLUME,                   0x00 },
 105         { CS42L42_ADC_WNF_HPF_CTL,              0x71 },
 106         { CS42L42_DAC_CTL1,                     0x00 },
 107         { CS42L42_DAC_CTL2,                     0x02 },
 108         { CS42L42_HP_CTL,                       0x0D },
 109         { CS42L42_CLASSH_CTL,                   0x07 },
 110         { CS42L42_MIXER_CHA_VOL,                0x3F },
 111         { CS42L42_MIXER_ADC_VOL,                0x3F },
 112         { CS42L42_MIXER_CHB_VOL,                0x3F },
 113         { CS42L42_EQ_COEF_IN0,                  0x00 },
 114         { CS42L42_EQ_COEF_IN1,                  0x00 },
 115         { CS42L42_EQ_COEF_IN2,                  0x00 },
 116         { CS42L42_EQ_COEF_IN3,                  0x00 },
 117         { CS42L42_EQ_COEF_RW,                   0x00 },
 118         { CS42L42_EQ_COEF_OUT0,                 0x00 },
 119         { CS42L42_EQ_COEF_OUT1,                 0x00 },
 120         { CS42L42_EQ_COEF_OUT2,                 0x00 },
 121         { CS42L42_EQ_COEF_OUT3,                 0x00 },
 122         { CS42L42_EQ_INIT_STAT,                 0x00 },
 123         { CS42L42_EQ_START_FILT,                0x00 },
 124         { CS42L42_EQ_MUTE_CTL,                  0x00 },
 125         { CS42L42_SP_RX_CH_SEL,                 0x04 },
 126         { CS42L42_SP_RX_ISOC_CTL,               0x04 },
 127         { CS42L42_SP_RX_FS,                     0x8C },
 128         { CS42l42_SPDIF_CH_SEL,                 0x0E },
 129         { CS42L42_SP_TX_ISOC_CTL,               0x04 },
 130         { CS42L42_SP_TX_FS,                     0xCC },
 131         { CS42L42_SPDIF_SW_CTL1,                0x3F },
 132         { CS42L42_SRC_SDIN_FS,                  0x40 },
 133         { CS42L42_SRC_SDOUT_FS,                 0x40 },
 134         { CS42L42_SPDIF_CTL1,                   0x01 },
 135         { CS42L42_SPDIF_CTL2,                   0x00 },
 136         { CS42L42_SPDIF_CTL3,                   0x00 },
 137         { CS42L42_SPDIF_CTL4,                   0x42 },
 138         { CS42L42_ASP_TX_SZ_EN,                 0x00 },
 139         { CS42L42_ASP_TX_CH_EN,                 0x00 },
 140         { CS42L42_ASP_TX_CH_AP_RES,             0x0F },
 141         { CS42L42_ASP_TX_CH1_BIT_MSB,           0x00 },
 142         { CS42L42_ASP_TX_CH1_BIT_LSB,           0x00 },
 143         { CS42L42_ASP_TX_HIZ_DLY_CFG,           0x00 },
 144         { CS42L42_ASP_TX_CH2_BIT_MSB,           0x00 },
 145         { CS42L42_ASP_TX_CH2_BIT_LSB,           0x00 },
 146         { CS42L42_ASP_RX_DAI0_EN,               0x00 },
 147         { CS42L42_ASP_RX_DAI0_CH1_AP_RES,       0x03 },
 148         { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB,      0x00 },
 149         { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB,      0x00 },
 150         { CS42L42_ASP_RX_DAI0_CH2_AP_RES,       0x03 },
 151         { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB,      0x00 },
 152         { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB,      0x00 },
 153         { CS42L42_ASP_RX_DAI0_CH3_AP_RES,       0x03 },
 154         { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB,      0x00 },
 155         { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB,      0x00 },
 156         { CS42L42_ASP_RX_DAI0_CH4_AP_RES,       0x03 },
 157         { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB,      0x00 },
 158         { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB,      0x00 },
 159         { CS42L42_ASP_RX_DAI1_CH1_AP_RES,       0x03 },
 160         { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB,      0x00 },
 161         { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB,      0x00 },
 162         { CS42L42_ASP_RX_DAI1_CH2_AP_RES,       0x03 },
 163         { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB,      0x00 },
 164         { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB,      0x00 },
 165 };
 166
 167 static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
 168 {
 169         switch (reg) {
 170         case CS42L42_PAGE_REGISTER:
 171         case CS42L42_DEVID_AB:
 172         case CS42L42_DEVID_CD:
 173         case CS42L42_DEVID_E:
 174         case CS42L42_FABID:
 175         case CS42L42_REVID:
 176         case CS42L42_FRZ_CTL:
 177         case CS42L42_SRC_CTL:
 178         case CS42L42_MCLK_STATUS:
 179         case CS42L42_MCLK_CTL:
 180         case CS42L42_SFTRAMP_RATE:
 181         case CS42L42_SLOW_START_ENABLE:
 182         case CS42L42_I2C_DEBOUNCE:
 183         case CS42L42_I2C_STRETCH:
 184         case CS42L42_I2C_TIMEOUT:
 185         case CS42L42_PWR_CTL1:
 186         case CS42L42_PWR_CTL2:
 187         case CS42L42_PWR_CTL3:
 188         case CS42L42_RSENSE_CTL1:
 189         case CS42L42_RSENSE_CTL2:
 190         case CS42L42_OSC_SWITCH:
 191         case CS42L42_OSC_SWITCH_STATUS:
 192         case CS42L42_RSENSE_CTL3:
 193         case CS42L42_TSENSE_CTL:
 194         case CS42L42_TSRS_INT_DISABLE:
 195         case CS42L42_TRSENSE_STATUS:
 196         case CS42L42_HSDET_CTL1:
 197         case CS42L42_HSDET_CTL2:
 198         case CS42L42_HS_SWITCH_CTL:
 199         case CS42L42_HS_DET_STATUS:
 200         case CS42L42_HS_CLAMP_DISABLE:
 201         case CS42L42_MCLK_SRC_SEL:
 202         case CS42L42_SPDIF_CLK_CFG:
 203         case CS42L42_FSYNC_PW_LOWER:
 204         case CS42L42_FSYNC_PW_UPPER:
 205         case CS42L42_FSYNC_P_LOWER:
 206         case CS42L42_FSYNC_P_UPPER:
 207         case CS42L42_ASP_CLK_CFG:
 208         case CS42L42_ASP_FRM_CFG:
 209         case CS42L42_FS_RATE_EN:
 210         case CS42L42_IN_ASRC_CLK:
 211         case CS42L42_OUT_ASRC_CLK:
 212         case CS42L42_PLL_DIV_CFG1:
 213         case CS42L42_ADC_OVFL_STATUS:
 214         case CS42L42_MIXER_STATUS:
 215         case CS42L42_SRC_STATUS:
 216         case CS42L42_ASP_RX_STATUS:
 217         case CS42L42_ASP_TX_STATUS:
 218         case CS42L42_CODEC_STATUS:
 219         case CS42L42_DET_INT_STATUS1:
 220         case CS42L42_DET_INT_STATUS2:
 221         case CS42L42_SRCPL_INT_STATUS:
 222         case CS42L42_VPMON_STATUS:
 223         case CS42L42_PLL_LOCK_STATUS:
 224         case CS42L42_TSRS_PLUG_STATUS:
 225         case CS42L42_ADC_OVFL_INT_MASK:
 226         case CS42L42_MIXER_INT_MASK:
 227         case CS42L42_SRC_INT_MASK:
 228         case CS42L42_ASP_RX_INT_MASK:
 229         case CS42L42_ASP_TX_INT_MASK:
 230         case CS42L42_CODEC_INT_MASK:
 231         case CS42L42_SRCPL_INT_MASK:
 232         case CS42L42_VPMON_INT_MASK:
 233         case CS42L42_PLL_LOCK_INT_MASK:
 234         case CS42L42_TSRS_PLUG_INT_MASK:
 235         case CS42L42_PLL_CTL1:
 236         case CS42L42_PLL_DIV_FRAC0:
 237         case CS42L42_PLL_DIV_FRAC1:
 238         case CS42L42_PLL_DIV_FRAC2:
 239         case CS42L42_PLL_DIV_INT:
 240         case CS42L42_PLL_CTL3:
 241         case CS42L42_PLL_CAL_RATIO:
 242         case CS42L42_PLL_CTL4:
 243         case CS42L42_LOAD_DET_RCSTAT:
 244         case CS42L42_LOAD_DET_DONE:
 245         case CS42L42_LOAD_DET_EN:
 246         case CS42L42_HSBIAS_SC_AUTOCTL:
 247         case CS42L42_WAKE_CTL:
 248         case CS42L42_ADC_DISABLE_MUTE:
 249         case CS42L42_TIPSENSE_CTL:
 250         case CS42L42_MISC_DET_CTL:
 251         case CS42L42_MIC_DET_CTL1:
 252         case CS42L42_MIC_DET_CTL2:
 253         case CS42L42_DET_STATUS1:
 254         case CS42L42_DET_STATUS2:
 255         case CS42L42_DET_INT1_MASK:
 256         case CS42L42_DET_INT2_MASK:
 257         case CS42L42_HS_BIAS_CTL:
 258         case CS42L42_ADC_CTL:
 259         case CS42L42_ADC_VOLUME:
 260         case CS42L42_ADC_WNF_HPF_CTL:
 261         case CS42L42_DAC_CTL1:
 262         case CS42L42_DAC_CTL2:
 263         case CS42L42_HP_CTL:
 264         case CS42L42_CLASSH_CTL:
 265         case CS42L42_MIXER_CHA_VOL:
 266         case CS42L42_MIXER_ADC_VOL:
 267         case CS42L42_MIXER_CHB_VOL:
 268         case CS42L42_EQ_COEF_IN0:
 269         case CS42L42_EQ_COEF_IN1:
 270         case CS42L42_EQ_COEF_IN2:
 271         case CS42L42_EQ_COEF_IN3:
 272         case CS42L42_EQ_COEF_RW:
 273         case CS42L42_EQ_COEF_OUT0:
 274         case CS42L42_EQ_COEF_OUT1:
 275         case CS42L42_EQ_COEF_OUT2:
 276         case CS42L42_EQ_COEF_OUT3:
 277         case CS42L42_EQ_INIT_STAT:
 278         case CS42L42_EQ_START_FILT:
 279         case CS42L42_EQ_MUTE_CTL:
 280         case CS42L42_SP_RX_CH_SEL:
 281         case CS42L42_SP_RX_ISOC_CTL:
 282         case CS42L42_SP_RX_FS:
 283         case CS42l42_SPDIF_CH_SEL:
 284         case CS42L42_SP_TX_ISOC_CTL:
 285         case CS42L42_SP_TX_FS:
 286         case CS42L42_SPDIF_SW_CTL1:
 287         case CS42L42_SRC_SDIN_FS:
 288         case CS42L42_SRC_SDOUT_FS:
 289         case CS42L42_SPDIF_CTL1:
 290         case CS42L42_SPDIF_CTL2:
 291         case CS42L42_SPDIF_CTL3:
 292         case CS42L42_SPDIF_CTL4:
 293         case CS42L42_ASP_TX_SZ_EN:
 294         case CS42L42_ASP_TX_CH_EN:
 295         case CS42L42_ASP_TX_CH_AP_RES:
 296         case CS42L42_ASP_TX_CH1_BIT_MSB:
 297         case CS42L42_ASP_TX_CH1_BIT_LSB:
 298         case CS42L42_ASP_TX_HIZ_DLY_CFG:
 299         case CS42L42_ASP_TX_CH2_BIT_MSB:
 300         case CS42L42_ASP_TX_CH2_BIT_LSB:
 301         case CS42L42_ASP_RX_DAI0_EN:
 302         case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
 303         case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
 304         case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
 305         case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
 306         case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
 307         case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
 308         case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
 309         case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
 310         case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
 311         case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
 312         case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
 313         case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
 314         case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
 315         case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
 316         case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
 317         case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
 318         case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
 319         case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
 320         case CS42L42_SUB_REVID:
 321                 return true;
 322         default:
 323                 return false;
 324         }
 325 }
 326
 327 static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
 328 {
 329         switch (reg) {
 330         case CS42L42_DEVID_AB:
 331         case CS42L42_DEVID_CD:
 332         case CS42L42_DEVID_E:
 333         case CS42L42_MCLK_STATUS:
 334         case CS42L42_OSC_SWITCH_STATUS:
 335         case CS42L42_TRSENSE_STATUS:
 336         case CS42L42_HS_DET_STATUS:
 337         case CS42L42_ADC_OVFL_STATUS:
 338         case CS42L42_MIXER_STATUS:
 339         case CS42L42_SRC_STATUS:
 340         case CS42L42_ASP_RX_STATUS:
 341         case CS42L42_ASP_TX_STATUS:
 342         case CS42L42_CODEC_STATUS:
 343         case CS42L42_DET_INT_STATUS1:
 344         case CS42L42_DET_INT_STATUS2:
 345         case CS42L42_SRCPL_INT_STATUS:
 346         case CS42L42_VPMON_STATUS:
 347         case CS42L42_PLL_LOCK_STATUS:
 348         case CS42L42_TSRS_PLUG_STATUS:
 349         case CS42L42_LOAD_DET_RCSTAT:
 350         case CS42L42_LOAD_DET_DONE:
 351         case CS42L42_DET_STATUS1:
 352         case CS42L42_DET_STATUS2:
 353                 return true;
 354         default:
 355                 return false;
 356         }
 357 }
 358
 359 static const struct regmap_range_cfg cs42l42_page_range = {
 360         .name = "Pages",
 361         .range_min = 0,
 362         .range_max = CS42L42_MAX_REGISTER,
 363         .selector_reg = CS42L42_PAGE_REGISTER,
 364         .selector_mask = 0xff,
 365         .selector_shift = 0,
 366         .window_start = 0,
 367         .window_len = 256,
 368 };
 369
 370 static const struct regmap_config cs42l42_regmap = {
 371         .reg_bits = 8,
 372         .val_bits = 8,
 373
 374         .readable_reg = cs42l42_readable_register,
 375         .volatile_reg = cs42l42_volatile_register,
 376
 377         .ranges = &cs42l42_page_range,
 378         .num_ranges = 1,
 379
 380         .max_register = CS42L42_MAX_REGISTER,
 381         .reg_defaults = cs42l42_reg_defaults,
 382         .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
 383         .cache_type = REGCACHE_RBTREE,
 384
 385         .use_single_read = true,
 386         .use_single_write = true,
 387 };
 388
 389 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
 390 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
 391
 392 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol,
 393                                   struct snd_ctl_elem_value *ucontrol)
 394 {
 395         struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 396         u8 val;
 397
 398         /* all bits of SLOW_START_EN much change together */
 399         switch (ucontrol->value.integer.value[0]) {
 400         case 0:
 401                 val = 0;
 402                 break;
 403         case 1:
 404                 val = CS42L42_SLOW_START_EN_MASK;
 405                 break;
 406         default:
 407                 return -EINVAL;
 408         }
 409
 410         return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE,
 411                                              CS42L42_SLOW_START_EN_MASK, val);
 412 }
 413
 414 static const char * const cs42l42_hpf_freq_text[] = {
 415         "1.86Hz", "120Hz", "235Hz", "466Hz"
 416 };
 417
 418 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 419                             CS42L42_ADC_HPF_CF_SHIFT,
 420                             cs42l42_hpf_freq_text);
 421
 422 static const char * const cs42l42_wnf3_freq_text[] = {
 423         "160Hz", "180Hz", "200Hz", "220Hz",
 424         "240Hz", "260Hz", "280Hz", "300Hz"
 425 };
 426
 427 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
 428                             CS42L42_ADC_WNF_CF_SHIFT,
 429                             cs42l42_wnf3_freq_text);
 430
 431 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
 432         /* ADC Volume and Filter Controls */
 433         SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
 434                                 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
 435         SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
 436                                 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
 437         SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
 438                                 CS42L42_ADC_INV_SHIFT, true, false),
 439         SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
 440                                 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
 441         SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
 442         SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
 443                                 CS42L42_ADC_WNF_EN_SHIFT, true, false),
 444         SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
 445                                 CS42L42_ADC_HPF_EN_SHIFT, true, false),
 446         SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
 447         SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
 448
 449         /* DAC Volume and Filter Controls */
 450         SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
 451                                 CS42L42_DACA_INV_SHIFT, true, false),
 452         SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
 453                                 CS42L42_DACB_INV_SHIFT, true, false),
 454         SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
 455                                 CS42L42_DAC_HPF_EN_SHIFT, true, false),
 456         SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
 457                          CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
 458                                 0x3f, 1, mixer_tlv),
 459
 460         SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE,
 461                         CS42L42_SLOW_START_EN_SHIFT, true, false,
 462                         snd_soc_get_volsw, cs42l42_slow_start_put),
 463 };
 464
 465 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w,
 466                              struct snd_kcontrol *kcontrol, int event)
 467 {
 468         struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 469         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 470
 471         switch (event) {
 472         case SND_SOC_DAPM_PRE_PMU:
 473                 cs42l42->hp_adc_up_pending = true;
 474                 break;
 475         case SND_SOC_DAPM_POST_PMU:
 476                 /* Only need one delay if HP and ADC are both powering-up */
 477                 if (cs42l42->hp_adc_up_pending) {
 478                         usleep_range(CS42L42_HP_ADC_EN_TIME_US,
 479                                      CS42L42_HP_ADC_EN_TIME_US + 1000);
 480                         cs42l42->hp_adc_up_pending = false;
 481                 }
 482                 break;
 483         default:
 484                 break;
 485         }
 486
 487         return 0;
 488 }
 489
 490 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
 491         /* Playback Path */
 492         SND_SOC_DAPM_OUTPUT("HP"),
 493         SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1,
 494                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 495         SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
 496         SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
 497         SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
 498
 499         /* Playback Requirements */
 500         SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
 501
 502         /* Capture Path */
 503         SND_SOC_DAPM_INPUT("HS"),
 504         SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1,
 505                            cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
 506         SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
 507         SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
 508
 509         /* Capture Requirements */
 510         SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
 511         SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
 512
 513         /* Playback/Capture Requirements */
 514         SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
 515 };
 516
 517 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
 518         /* Playback Path */
 519         {"HP", NULL, "DAC"},
 520         {"DAC", NULL, "MIXER"},
 521         {"MIXER", NULL, "SDIN1"},
 522         {"MIXER", NULL, "SDIN2"},
 523         {"SDIN1", NULL, "Playback"},
 524         {"SDIN2", NULL, "Playback"},
 525
 526         /* Playback Requirements */
 527         {"SDIN1", NULL, "ASP DAI0"},
 528         {"SDIN2", NULL, "ASP DAI0"},
 529         {"SDIN1", NULL, "SCLK"},
 530         {"SDIN2", NULL, "SCLK"},
 531
 532         /* Capture Path */
 533         {"ADC", NULL, "HS"},
 534         { "SDOUT1", NULL, "ADC" },
 535         { "SDOUT2", NULL, "ADC" },
 536         { "Capture", NULL, "SDOUT1" },
 537         { "Capture", NULL, "SDOUT2" },
 538
 539         /* Capture Requirements */
 540         { "SDOUT1", NULL, "ASP DAO0" },
 541         { "SDOUT2", NULL, "ASP DAO0" },
 542         { "SDOUT1", NULL, "SCLK" },
 543         { "SDOUT2", NULL, "SCLK" },
 544         { "SDOUT1", NULL, "ASP TX EN" },
 545         { "SDOUT2", NULL, "ASP TX EN" },
 546 };
 547
 548 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
 549 {
 550         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 551
 552         /* Prevent race with interrupt handler */
 553         mutex_lock(&cs42l42->jack_detect_mutex);
 554         cs42l42->jack = jk;
 555
 556         if (jk) {
 557                 switch (cs42l42->hs_type) {
 558                 case CS42L42_PLUG_CTIA:
 559                 case CS42L42_PLUG_OMTP:
 560                         snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET);
 561                         break;
 562                 case CS42L42_PLUG_HEADPHONE:
 563                         snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE);
 564                         break;
 565                 default:
 566                         break;
 567                 }
 568         }
 569         mutex_unlock(&cs42l42->jack_detect_mutex);
 570
 571         return 0;
 572 }
 573
 574 static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
 575         .set_jack               = cs42l42_set_jack,
 576         .dapm_widgets           = cs42l42_dapm_widgets,
 577         .num_dapm_widgets       = ARRAY_SIZE(cs42l42_dapm_widgets),
 578         .dapm_routes            = cs42l42_audio_map,
 579         .num_dapm_routes        = ARRAY_SIZE(cs42l42_audio_map),
 580         .controls               = cs42l42_snd_controls,
 581         .num_controls           = ARRAY_SIZE(cs42l42_snd_controls),
 582         .idle_bias_on           = 1,
 583         .endianness             = 1,
 584         .non_legacy_dai_naming  = 1,
 585 };
 586
 587 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
 588 static const struct reg_sequence cs42l42_to_sclk_seq[] = {
 589         {
 590                 .reg = CS42L42_OSC_SWITCH,
 591                 .def = CS42L42_SCLK_PRESENT_MASK,
 592                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 593         },
 594 };
 595
 596 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
 597 static const struct reg_sequence cs42l42_to_osc_seq[] = {
 598         {
 599                 .reg = CS42L42_OSC_SWITCH,
 600                 .def = 0,
 601                 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
 602         },
 603 };
 604
 605 struct cs42l42_pll_params {
 606         u32 sclk;
 607         u8 mclk_src_sel;
 608         u8 sclk_prediv;
 609         u8 pll_div_int;
 610         u32 pll_div_frac;
 611         u8 pll_mode;
 612         u8 pll_divout;
 613         u32 mclk_int;
 614         u8 pll_cal_ratio;
 615         u8 n;
 616 };
 617
 618 /*
 619  * Common PLL Settings for given SCLK
 620  * Table 4-5 from the Datasheet
 621  */
 622 static const struct cs42l42_pll_params pll_ratio_table[] = {
 623         { 1411200,  1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
 624         { 1536000,  1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
 625         { 2304000,  1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000,  85, 2},
 626         { 2400000,  1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000,  80, 2},
 627         { 2822400,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 628         { 3000000,  1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 629         { 3072000,  1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 630         { 4000000,  1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000,  96, 1},
 631         { 4096000,  1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000,  94, 1},
 632         { 5644800,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 633         { 6000000,  1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 634         { 6144000,  1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
 635         { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
 636         { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
 637         { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
 638         { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
 639         { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
 640         { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}
 641 };
 642
 643 static int cs42l42_pll_config(struct snd_soc_component *component)
 644 {
 645         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 646         int i;
 647         u32 clk;
 648         u32 fsync;
 649
 650         if (!cs42l42->sclk)
 651                 clk = cs42l42->bclk;
 652         else
 653                 clk = cs42l42->sclk;
 654
 655         /* Don't reconfigure if there is an audio stream running */
 656         if (cs42l42->stream_use) {
 657                 if (pll_ratio_table[cs42l42->pll_config].sclk == clk)
 658                         return 0;
 659                 else
 660                         return -EBUSY;
 661         }
 662
 663         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 664                 if (pll_ratio_table[i].sclk == clk) {
 665                         cs42l42->pll_config = i;
 666
 667                         /* Configure the internal sample rate */
 668                         snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
 669                                         CS42L42_INTERNAL_FS_MASK,
 670                                         ((pll_ratio_table[i].mclk_int !=
 671                                         12000000) &&
 672                                         (pll_ratio_table[i].mclk_int !=
 673                                         24000000)) <<
 674                                         CS42L42_INTERNAL_FS_SHIFT);
 675
 676                         /* Set up the LRCLK */
 677                         fsync = clk / cs42l42->srate;
 678                         if (((fsync * cs42l42->srate) != clk)
 679                                 || ((fsync % 2) != 0)) {
 680                                 dev_err(component->dev,
 681                                         "Unsupported sclk %d/sample rate %d\n",
 682                                         clk,
 683                                         cs42l42->srate);
 684                                 return -EINVAL;
 685                         }
 686                         /* Set the LRCLK period */
 687                         snd_soc_component_update_bits(component,
 688                                         CS42L42_FSYNC_P_LOWER,
 689                                         CS42L42_FSYNC_PERIOD_MASK,
 690                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 691                                         CS42L42_FSYNC_PERIOD_SHIFT);
 692                         snd_soc_component_update_bits(component,
 693                                         CS42L42_FSYNC_P_UPPER,
 694                                         CS42L42_FSYNC_PERIOD_MASK,
 695                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 696                                         CS42L42_FSYNC_PERIOD_SHIFT);
 697                         /* Set the LRCLK to 50% duty cycle */
 698                         fsync = fsync / 2;
 699                         snd_soc_component_update_bits(component,
 700                                         CS42L42_FSYNC_PW_LOWER,
 701                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 702                                         CS42L42_FRAC0_VAL(fsync - 1) <<
 703                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 704                         snd_soc_component_update_bits(component,
 705                                         CS42L42_FSYNC_PW_UPPER,
 706                                         CS42L42_FSYNC_PULSE_WIDTH_MASK,
 707                                         CS42L42_FRAC1_VAL(fsync - 1) <<
 708                                         CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
 709                         if (pll_ratio_table[i].mclk_src_sel == 0) {
 710                                 /* Pass the clock straight through */
 711                                 snd_soc_component_update_bits(component,
 712                                         CS42L42_PLL_CTL1,
 713                                         CS42L42_PLL_START_MASK, 0);
 714                         } else {
 715                                 /* Configure PLL per table 4-5 */
 716                                 snd_soc_component_update_bits(component,
 717                                         CS42L42_PLL_DIV_CFG1,
 718                                         CS42L42_SCLK_PREDIV_MASK,
 719                                         pll_ratio_table[i].sclk_prediv
 720                                         << CS42L42_SCLK_PREDIV_SHIFT);
 721                                 snd_soc_component_update_bits(component,
 722                                         CS42L42_PLL_DIV_INT,
 723                                         CS42L42_PLL_DIV_INT_MASK,
 724                                         pll_ratio_table[i].pll_div_int
 725                                         << CS42L42_PLL_DIV_INT_SHIFT);
 726                                 snd_soc_component_update_bits(component,
 727                                         CS42L42_PLL_DIV_FRAC0,
 728                                         CS42L42_PLL_DIV_FRAC_MASK,
 729                                         CS42L42_FRAC0_VAL(
 730                                         pll_ratio_table[i].pll_div_frac)
 731                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 732                                 snd_soc_component_update_bits(component,
 733                                         CS42L42_PLL_DIV_FRAC1,
 734                                         CS42L42_PLL_DIV_FRAC_MASK,
 735                                         CS42L42_FRAC1_VAL(
 736                                         pll_ratio_table[i].pll_div_frac)
 737                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 738                                 snd_soc_component_update_bits(component,
 739                                         CS42L42_PLL_DIV_FRAC2,
 740                                         CS42L42_PLL_DIV_FRAC_MASK,
 741                                         CS42L42_FRAC2_VAL(
 742                                         pll_ratio_table[i].pll_div_frac)
 743                                         << CS42L42_PLL_DIV_FRAC_SHIFT);
 744                                 snd_soc_component_update_bits(component,
 745                                         CS42L42_PLL_CTL4,
 746                                         CS42L42_PLL_MODE_MASK,
 747                                         pll_ratio_table[i].pll_mode
 748                                         << CS42L42_PLL_MODE_SHIFT);
 749                                 snd_soc_component_update_bits(component,
 750                                         CS42L42_PLL_CTL3,
 751                                         CS42L42_PLL_DIVOUT_MASK,
 752                                         (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
 753                                         << CS42L42_PLL_DIVOUT_SHIFT);
 754                                 snd_soc_component_update_bits(component,
 755                                         CS42L42_PLL_CAL_RATIO,
 756                                         CS42L42_PLL_CAL_RATIO_MASK,
 757                                         pll_ratio_table[i].pll_cal_ratio
 758                                         << CS42L42_PLL_CAL_RATIO_SHIFT);
 759                         }
 760                         return 0;
 761                 }
 762         }
 763
 764         return -EINVAL;
 765 }
 766
 767 static void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
 768 {
 769         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 770         unsigned int fs;
 771
 772         /* Don't reconfigure if there is an audio stream running */
 773         if (cs42l42->stream_use)
 774                 return;
 775
 776         /* SRC MCLK must be as close as possible to 125 * sample rate */
 777         if (sample_rate <= 48000)
 778                 fs = CS42L42_CLK_IASRC_SEL_6;
 779         else
 780                 fs = CS42L42_CLK_IASRC_SEL_12;
 781
 782         /* Set the sample rates (96k or lower) */
 783         snd_soc_component_update_bits(component,
 784                                       CS42L42_FS_RATE_EN,
 785                                       CS42L42_FS_EN_MASK,
 786                                       (CS42L42_FS_EN_IASRC_96K |
 787                                        CS42L42_FS_EN_OASRC_96K) <<
 788                                       CS42L42_FS_EN_SHIFT);
 789
 790         snd_soc_component_update_bits(component,
 791                                       CS42L42_IN_ASRC_CLK,
 792                                       CS42L42_CLK_IASRC_SEL_MASK,
 793                                       fs << CS42L42_CLK_IASRC_SEL_SHIFT);
 794         snd_soc_component_update_bits(component,
 795                                       CS42L42_OUT_ASRC_CLK,
 796                                       CS42L42_CLK_OASRC_SEL_MASK,
 797                                       fs << CS42L42_CLK_OASRC_SEL_SHIFT);
 798 }
 799
 800 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 801 {
 802         struct snd_soc_component *component = codec_dai->component;
 803         u32 asp_cfg_val = 0;
 804
 805         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 806         case SND_SOC_DAIFMT_CBS_CFM:
 807                 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
 808                                 CS42L42_ASP_MODE_SHIFT;
 809                 break;
 810         case SND_SOC_DAIFMT_CBS_CFS:
 811                 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
 812                                 CS42L42_ASP_MODE_SHIFT;
 813                 break;
 814         default:
 815                 return -EINVAL;
 816         }
 817
 818         /* interface format */
 819         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 820         case SND_SOC_DAIFMT_I2S:
 821                 /*
 822                  * 5050 mode, frame starts on falling edge of LRCLK,
 823                  * frame delayed by 1.0 SCLKs
 824                  */
 825                 snd_soc_component_update_bits(component,
 826                                               CS42L42_ASP_FRM_CFG,
 827                                               CS42L42_ASP_STP_MASK |
 828                                               CS42L42_ASP_5050_MASK |
 829                                               CS42L42_ASP_FSD_MASK,
 830                                               CS42L42_ASP_5050_MASK |
 831                                               (CS42L42_ASP_FSD_1_0 <<
 832                                                 CS42L42_ASP_FSD_SHIFT));
 833                 break;
 834         default:
 835                 return -EINVAL;
 836         }
 837
 838         /* Bitclock/frame inversion */
 839         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 840         case SND_SOC_DAIFMT_NB_NF:
 841                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 842                 break;
 843         case SND_SOC_DAIFMT_NB_IF:
 844                 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
 845                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 846                 break;
 847         case SND_SOC_DAIFMT_IB_NF:
 848                 break;
 849         case SND_SOC_DAIFMT_IB_IF:
 850                 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
 851                 break;
 852         }
 853
 854         snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
 855                                                                       CS42L42_ASP_SCPOL_MASK |
 856                                                                       CS42L42_ASP_LCPOL_MASK,
 857                                                                       asp_cfg_val);
 858
 859         return 0;
 860 }
 861
 862 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
 863 {
 864         struct snd_soc_component *component = dai->component;
 865         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 866
 867         /*
 868          * Sample rates < 44.1 kHz would produce an out-of-range SCLK with
 869          * a standard I2S frame. If the machine driver sets SCLK it must be
 870          * legal.
 871          */
 872         if (cs42l42->sclk)
 873                 return 0;
 874
 875         /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
 876         return snd_pcm_hw_constraint_minmax(substream->runtime,
 877                                             SNDRV_PCM_HW_PARAM_RATE,
 878                                             44100, 96000);
 879 }
 880
 881 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
 882                                 struct snd_pcm_hw_params *params,
 883                                 struct snd_soc_dai *dai)
 884 {
 885         struct snd_soc_component *component = dai->component;
 886         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 887         unsigned int channels = params_channels(params);
 888         unsigned int width = (params_width(params) / 8) - 1;
 889         unsigned int val = 0;
 890         int ret;
 891
 892         cs42l42->srate = params_rate(params);
 893         cs42l42->bclk = snd_soc_params_to_bclk(params);
 894
 895         /* I2S frame always has 2 channels even for mono audio */
 896         if (channels == 1)
 897                 cs42l42->bclk *= 2;
 898
 899         /*
 900          * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
 901          * more than assumed (which would result in overclocking).
 902          */
 903         if (params_width(params) == 24)
 904                 cs42l42->bclk = (cs42l42->bclk / 3) * 4;
 905
 906         switch (substream->stream) {
 907         case SNDRV_PCM_STREAM_CAPTURE:
 908                 /* channel 2 on high LRCLK */
 909                 val = CS42L42_ASP_TX_CH2_AP_MASK |
 910                       (width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
 911                       (width << CS42L42_ASP_TX_CH1_RES_SHIFT);
 912
 913                 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
 914                                 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
 915                                 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
 916                 break;
 917         case SNDRV_PCM_STREAM_PLAYBACK:
 918                 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
 919                 /* channel 1 on low LRCLK */
 920                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
 921                                                          CS42L42_ASP_RX_CH_AP_MASK |
 922                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 923                 /* Channel 2 on high LRCLK */
 924                 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
 925                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
 926                                                          CS42L42_ASP_RX_CH_AP_MASK |
 927                                                          CS42L42_ASP_RX_CH_RES_MASK, val);
 928
 929                 /* Channel B comes from the last active channel */
 930                 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
 931                                               CS42L42_SP_RX_CHB_SEL_MASK,
 932                                               (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
 933
 934                 /* Both LRCLK slots must be enabled */
 935                 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
 936                                               CS42L42_ASP_RX0_CH_EN_MASK,
 937                                               BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
 938                                               BIT(CS42L42_ASP_RX0_CH2_SHIFT));
 939                 break;
 940         default:
 941                 break;
 942         }
 943
 944         ret = cs42l42_pll_config(component);
 945         if (ret)
 946                 return ret;
 947
 948         cs42l42_src_config(component, params_rate(params));
 949
 950         return 0;
 951 }
 952
 953 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
 954                                 int clk_id, unsigned int freq, int dir)
 955 {
 956         struct snd_soc_component *component = dai->component;
 957         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 958         int i;
 959
 960         if (freq == 0) {
 961                 cs42l42->sclk = 0;
 962                 return 0;
 963         }
 964
 965         for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
 966                 if (pll_ratio_table[i].sclk == freq) {
 967                         cs42l42->sclk = freq;
 968                         return 0;
 969                 }
 970         }
 971
 972         dev_err(component->dev, "SCLK %u not supported\n", freq);
 973
 974         return -EINVAL;
 975 }
 976
 977 static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
 978 {
 979         struct snd_soc_component *component = dai->component;
 980         struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
 981         unsigned int regval;
 982         int ret;
 983
 984         if (mute) {
 985                 /* Mute the headphone */
 986                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
 987                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
 988                                                       CS42L42_HP_ANA_AMUTE_MASK |
 989                                                       CS42L42_HP_ANA_BMUTE_MASK,
 990                                                       CS42L42_HP_ANA_AMUTE_MASK |
 991                                                       CS42L42_HP_ANA_BMUTE_MASK);
 992
 993                 cs42l42->stream_use &= ~(1 << stream);
 994                 if (!cs42l42->stream_use) {
 995                         /*
 996                          * Switch to the internal oscillator.
 997                          * SCLK must remain running until after this clock switch.
 998                          * Without a source of clock the I2C bus doesn't work.
 999                          */
1000                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
1001                                                ARRAY_SIZE(cs42l42_to_osc_seq));
1002
1003                         /* Must disconnect PLL before stopping it */
1004                         snd_soc_component_update_bits(component,
1005                                                       CS42L42_MCLK_SRC_SEL,
1006                                                       CS42L42_MCLK_SRC_SEL_MASK,
1007                                                       0);
1008                         usleep_range(100, 200);
1009
1010                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1011                                                       CS42L42_PLL_START_MASK, 0);
1012                 }
1013         } else {
1014                 if (!cs42l42->stream_use) {
1015                         /* SCLK must be running before codec unmute */
1016                         if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
1017                                 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1018                                                               CS42L42_PLL_START_MASK, 1);
1019
1020                                 if (pll_ratio_table[cs42l42->pll_config].n > 1) {
1021                                         usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
1022                                                      CS42L42_PLL_DIVOUT_TIME_US * 2);
1023                                         regval = pll_ratio_table[cs42l42->pll_config].pll_divout;
1024                                         snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
1025                                                                       CS42L42_PLL_DIVOUT_MASK,
1026                                                                       regval <<
1027                                                                       CS42L42_PLL_DIVOUT_SHIFT);
1028                                 }
1029
1030                                 ret = regmap_read_poll_timeout(cs42l42->regmap,
1031                                                                CS42L42_PLL_LOCK_STATUS,
1032                                                                regval,
1033                                                                (regval & 1),
1034                                                                CS42L42_PLL_LOCK_POLL_US,
1035                                                                CS42L42_PLL_LOCK_TIMEOUT_US);
1036                                 if (ret < 0)
1037                                         dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
1038
1039                                 /* PLL must be running to drive glitchless switch logic */
1040                                 snd_soc_component_update_bits(component,
1041                                                               CS42L42_MCLK_SRC_SEL,
1042                                                               CS42L42_MCLK_SRC_SEL_MASK,
1043                                                               CS42L42_MCLK_SRC_SEL_MASK);
1044                         }
1045
1046                         /* Mark SCLK as present, turn off internal oscillator */
1047                         regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
1048                                                ARRAY_SIZE(cs42l42_to_sclk_seq));
1049                 }
1050                 cs42l42->stream_use |= 1 << stream;
1051
1052                 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1053                         /* Un-mute the headphone */
1054                         snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1055                                                       CS42L42_HP_ANA_AMUTE_MASK |
1056                                                       CS42L42_HP_ANA_BMUTE_MASK,
1057                                                       0);
1058                 }
1059         }
1060
1061         return 0;
1062 }
1063
1064 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1065                          SNDRV_PCM_FMTBIT_S24_LE |\
1066                          SNDRV_PCM_FMTBIT_S32_LE)
1067
1068 static const struct snd_soc_dai_ops cs42l42_ops = {
1069         .startup        = cs42l42_dai_startup,
1070         .hw_params      = cs42l42_pcm_hw_params,
1071         .set_fmt        = cs42l42_set_dai_fmt,
1072         .set_sysclk     = cs42l42_set_sysclk,
1073         .mute_stream    = cs42l42_mute_stream,
1074 };
1075
1076 static struct snd_soc_dai_driver cs42l42_dai = {
1077                 .name = "cs42l42",
1078                 .playback = {
1079                         .stream_name = "Playback",
1080                         .channels_min = 1,
1081                         .channels_max = 2,
1082                         .rates = SNDRV_PCM_RATE_8000_96000,
1083                         .formats = CS42L42_FORMATS,
1084                 },
1085                 .capture = {
1086                         .stream_name = "Capture",
1087                         .channels_min = 1,
1088                         .channels_max = 2,
1089                         .rates = SNDRV_PCM_RATE_8000_96000,
1090                         .formats = CS42L42_FORMATS,
1091                 },
1092                 .symmetric_rate = 1,
1093                 .symmetric_sample_bits = 1,
1094                 .ops = &cs42l42_ops,
1095 };
1096
1097 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42)
1098 {
1099         unsigned int hs_det_status;
1100         unsigned int hs_det_comp1;
1101         unsigned int hs_det_comp2;
1102         unsigned int hs_det_sw;
1103
1104         /* Set hs detect to manual, active mode */
1105         regmap_update_bits(cs42l42->regmap,
1106                 CS42L42_HSDET_CTL2,
1107                 CS42L42_HSDET_CTRL_MASK |
1108                 CS42L42_HSDET_SET_MASK |
1109                 CS42L42_HSBIAS_REF_MASK |
1110                 CS42L42_HSDET_AUTO_TIME_MASK,
1111                 (1 << CS42L42_HSDET_CTRL_SHIFT) |
1112                 (0 << CS42L42_HSDET_SET_SHIFT) |
1113                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1114                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1115
1116         /* Configure HS DET comparator reference levels. */
1117         regmap_update_bits(cs42l42->regmap,
1118                                 CS42L42_HSDET_CTL1,
1119                                 CS42L42_HSDET_COMP1_LVL_MASK |
1120                                 CS42L42_HSDET_COMP2_LVL_MASK,
1121                                 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1122                                 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
1123
1124         /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
1125         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
1126
1127         msleep(100);
1128
1129         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1130
1131         hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1132                         CS42L42_HSDET_COMP1_OUT_SHIFT;
1133         hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1134                         CS42L42_HSDET_COMP2_OUT_SHIFT;
1135
1136         /* Close the SW_HSB_HS3 switch for a Type 2 headset. */
1137         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
1138
1139         msleep(100);
1140
1141         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1142
1143         hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1144                         CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
1145         hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1146                         CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
1147
1148         /* Use Comparator 1 with 1.25V Threshold. */
1149         switch (hs_det_comp1) {
1150         case CS42L42_HSDET_COMP_TYPE1:
1151                 cs42l42->hs_type = CS42L42_PLUG_CTIA;
1152                 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1153                 break;
1154         case CS42L42_HSDET_COMP_TYPE2:
1155                 cs42l42->hs_type = CS42L42_PLUG_OMTP;
1156                 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1157                 break;
1158         default:
1159                 /* Fallback to Comparator 2 with 1.75V Threshold. */
1160                 switch (hs_det_comp2) {
1161                 case CS42L42_HSDET_COMP_TYPE1:
1162                         cs42l42->hs_type = CS42L42_PLUG_CTIA;
1163                         hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1164                         break;
1165                 case CS42L42_HSDET_COMP_TYPE2:
1166                         cs42l42->hs_type = CS42L42_PLUG_OMTP;
1167                         hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1168                         break;
1169                 case CS42L42_HSDET_COMP_TYPE3:
1170                         cs42l42->hs_type = CS42L42_PLUG_HEADPHONE;
1171                         hs_det_sw = CS42L42_HSDET_SW_TYPE3;
1172                         break;
1173                 default:
1174                         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1175                         hs_det_sw = CS42L42_HSDET_SW_TYPE4;
1176                         break;
1177                 }
1178         }
1179
1180         /* Set Switches */
1181         regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw);
1182
1183         /* Set HSDET mode to Manual—Disabled */
1184         regmap_update_bits(cs42l42->regmap,
1185                 CS42L42_HSDET_CTL2,
1186                 CS42L42_HSDET_CTRL_MASK |
1187                 CS42L42_HSDET_SET_MASK |
1188                 CS42L42_HSBIAS_REF_MASK |
1189                 CS42L42_HSDET_AUTO_TIME_MASK,
1190                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1191                 (0 << CS42L42_HSDET_SET_SHIFT) |
1192                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1193                 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1194
1195         /* Configure HS DET comparator reference levels. */
1196         regmap_update_bits(cs42l42->regmap,
1197                                 CS42L42_HSDET_CTL1,
1198                                 CS42L42_HSDET_COMP1_LVL_MASK |
1199                                 CS42L42_HSDET_COMP2_LVL_MASK,
1200                                 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1201                                 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
1202 }
1203
1204 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
1205 {
1206         unsigned int hs_det_status;
1207         unsigned int int_status;
1208
1209         /* Read and save the hs detection result */
1210         regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1211
1212         /* Mask the auto detect interrupt */
1213         regmap_update_bits(cs42l42->regmap,
1214                 CS42L42_CODEC_INT_MASK,
1215                 CS42L42_PDN_DONE_MASK |
1216                 CS42L42_HSDET_AUTO_DONE_MASK,
1217                 (1 << CS42L42_PDN_DONE_SHIFT) |
1218                 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1219
1220
1221         cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1222                                 CS42L42_HSDET_TYPE_SHIFT;
1223
1224         /* Set hs detect to automatic, disabled mode */
1225         regmap_update_bits(cs42l42->regmap,
1226                 CS42L42_HSDET_CTL2,
1227                 CS42L42_HSDET_CTRL_MASK |
1228                 CS42L42_HSDET_SET_MASK |
1229                 CS42L42_HSBIAS_REF_MASK |
1230                 CS42L42_HSDET_AUTO_TIME_MASK,
1231                 (2 << CS42L42_HSDET_CTRL_SHIFT) |
1232                 (2 << CS42L42_HSDET_SET_SHIFT) |
1233                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1234                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1235
1236         /* Run Manual detection if auto detect has not found a headset.
1237          * We Re-Run with Manual Detection if the original detection was invalid or headphones,
1238          * to ensure that a headset mic is detected in all cases.
1239          */
1240         if (cs42l42->hs_type == CS42L42_PLUG_INVALID ||
1241                 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) {
1242                 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n");
1243                 cs42l42_manual_hs_type_detect(cs42l42);
1244         }
1245
1246         /* Set up button detection */
1247         if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1248               (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1249                 /* Set auto HS bias settings to default */
1250                 regmap_update_bits(cs42l42->regmap,
1251                         CS42L42_HSBIAS_SC_AUTOCTL,
1252                         CS42L42_HSBIAS_SENSE_EN_MASK |
1253                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1254                         CS42L42_TIP_SENSE_EN_MASK |
1255                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1256                         (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1257                         (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1258                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1259                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1260
1261                 /* Set up hs detect level sensitivity */
1262                 regmap_update_bits(cs42l42->regmap,
1263                         CS42L42_MIC_DET_CTL1,
1264                         CS42L42_LATCH_TO_VP_MASK |
1265                         CS42L42_EVENT_STAT_SEL_MASK |
1266                         CS42L42_HS_DET_LEVEL_MASK,
1267                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1268                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1269                         (cs42l42->bias_thresholds[0] <<
1270                         CS42L42_HS_DET_LEVEL_SHIFT));
1271
1272                 /* Set auto HS bias settings to default */
1273                 regmap_update_bits(cs42l42->regmap,
1274                         CS42L42_HSBIAS_SC_AUTOCTL,
1275                         CS42L42_HSBIAS_SENSE_EN_MASK |
1276                         CS42L42_AUTO_HSBIAS_HIZ_MASK |
1277                         CS42L42_TIP_SENSE_EN_MASK |
1278                         CS42L42_HSBIAS_SENSE_TRIP_MASK,
1279                         (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1280                         (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1281                         (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1282                         (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1283
1284                 /* Turn on level detect circuitry */
1285                 regmap_update_bits(cs42l42->regmap,
1286                         CS42L42_MISC_DET_CTL,
1287                         CS42L42_HSBIAS_CTL_MASK |
1288                         CS42L42_PDN_MIC_LVL_DET_MASK,
1289                         (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1290                         (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1291
1292                 msleep(cs42l42->btn_det_init_dbnce);
1293
1294                 /* Clear any button interrupts before unmasking them */
1295                 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1296                             &int_status);
1297
1298                 /* Unmask button detect interrupts */
1299                 regmap_update_bits(cs42l42->regmap,
1300                         CS42L42_DET_INT2_MASK,
1301                         CS42L42_M_DETECT_TF_MASK |
1302                         CS42L42_M_DETECT_FT_MASK |
1303                         CS42L42_M_HSBIAS_HIZ_MASK |
1304                         CS42L42_M_SHORT_RLS_MASK |
1305                         CS42L42_M_SHORT_DET_MASK,
1306                         (0 << CS42L42_M_DETECT_TF_SHIFT) |
1307                         (0 << CS42L42_M_DETECT_FT_SHIFT) |
1308                         (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1309                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1310                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1311         } else {
1312                 /* Make sure button detect and HS bias circuits are off */
1313                 regmap_update_bits(cs42l42->regmap,
1314                         CS42L42_MISC_DET_CTL,
1315                         CS42L42_HSBIAS_CTL_MASK |
1316                         CS42L42_PDN_MIC_LVL_DET_MASK,
1317                         (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1318                         (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1319         }
1320
1321         regmap_update_bits(cs42l42->regmap,
1322                                 CS42L42_DAC_CTL2,
1323                                 CS42L42_HPOUT_PULLDOWN_MASK |
1324                                 CS42L42_HPOUT_LOAD_MASK |
1325                                 CS42L42_HPOUT_CLAMP_MASK |
1326                                 CS42L42_DAC_HPF_EN_MASK |
1327                                 CS42L42_DAC_MON_EN_MASK,
1328                                 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1329                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1330                                 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1331                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1332                                 (0 << CS42L42_DAC_MON_EN_SHIFT));
1333
1334         /* Unmask tip sense interrupts */
1335         regmap_update_bits(cs42l42->regmap,
1336                 CS42L42_TSRS_PLUG_INT_MASK,
1337                 CS42L42_TS_PLUG_MASK |
1338                 CS42L42_TS_UNPLUG_MASK,
1339                 (0 << CS42L42_TS_PLUG_SHIFT) |
1340                 (0 << CS42L42_TS_UNPLUG_SHIFT));
1341 }
1342
1343 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1344 {
1345         /* Mask tip sense interrupts */
1346         regmap_update_bits(cs42l42->regmap,
1347                                 CS42L42_TSRS_PLUG_INT_MASK,
1348                                 CS42L42_TS_PLUG_MASK |
1349                                 CS42L42_TS_UNPLUG_MASK,
1350                                 (1 << CS42L42_TS_PLUG_SHIFT) |
1351                                 (1 << CS42L42_TS_UNPLUG_SHIFT));
1352
1353         /* Make sure button detect and HS bias circuits are off */
1354         regmap_update_bits(cs42l42->regmap,
1355                                 CS42L42_MISC_DET_CTL,
1356                                 CS42L42_HSBIAS_CTL_MASK |
1357                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1358                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1359                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1360
1361         /* Set auto HS bias settings to default */
1362         regmap_update_bits(cs42l42->regmap,
1363                                 CS42L42_HSBIAS_SC_AUTOCTL,
1364                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1365                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1366                                 CS42L42_TIP_SENSE_EN_MASK |
1367                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1368                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1369                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1370                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1371                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1372
1373         /* Set hs detect to manual, disabled mode */
1374         regmap_update_bits(cs42l42->regmap,
1375                                 CS42L42_HSDET_CTL2,
1376                                 CS42L42_HSDET_CTRL_MASK |
1377                                 CS42L42_HSDET_SET_MASK |
1378                                 CS42L42_HSBIAS_REF_MASK |
1379                                 CS42L42_HSDET_AUTO_TIME_MASK,
1380                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1381                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1382                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1383                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1384
1385         regmap_update_bits(cs42l42->regmap,
1386                                 CS42L42_DAC_CTL2,
1387                                 CS42L42_HPOUT_PULLDOWN_MASK |
1388                                 CS42L42_HPOUT_LOAD_MASK |
1389                                 CS42L42_HPOUT_CLAMP_MASK |
1390                                 CS42L42_DAC_HPF_EN_MASK |
1391                                 CS42L42_DAC_MON_EN_MASK,
1392                                 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1393                                 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1394                                 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1395                                 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1396                                 (1 << CS42L42_DAC_MON_EN_SHIFT));
1397
1398         /* Power up HS bias to 2.7V */
1399         regmap_update_bits(cs42l42->regmap,
1400                                 CS42L42_MISC_DET_CTL,
1401                                 CS42L42_HSBIAS_CTL_MASK |
1402                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1403                                 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1404                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1405
1406         /* Wait for HS bias to ramp up */
1407         msleep(cs42l42->hs_bias_ramp_time);
1408
1409         /* Unmask auto detect interrupt */
1410         regmap_update_bits(cs42l42->regmap,
1411                                 CS42L42_CODEC_INT_MASK,
1412                                 CS42L42_PDN_DONE_MASK |
1413                                 CS42L42_HSDET_AUTO_DONE_MASK,
1414                                 (1 << CS42L42_PDN_DONE_SHIFT) |
1415                                 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1416
1417         /* Set hs detect to automatic, enabled mode */
1418         regmap_update_bits(cs42l42->regmap,
1419                                 CS42L42_HSDET_CTL2,
1420                                 CS42L42_HSDET_CTRL_MASK |
1421                                 CS42L42_HSDET_SET_MASK |
1422                                 CS42L42_HSBIAS_REF_MASK |
1423                                 CS42L42_HSDET_AUTO_TIME_MASK,
1424                                 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1425                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1426                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1427                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1428 }
1429
1430 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1431 {
1432         /* Mask button detect interrupts */
1433         regmap_update_bits(cs42l42->regmap,
1434                 CS42L42_DET_INT2_MASK,
1435                 CS42L42_M_DETECT_TF_MASK |
1436                 CS42L42_M_DETECT_FT_MASK |
1437                 CS42L42_M_HSBIAS_HIZ_MASK |
1438                 CS42L42_M_SHORT_RLS_MASK |
1439                 CS42L42_M_SHORT_DET_MASK,
1440                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1441                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1442                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1443                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1444                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1445
1446         /* Ground HS bias */
1447         regmap_update_bits(cs42l42->regmap,
1448                                 CS42L42_MISC_DET_CTL,
1449                                 CS42L42_HSBIAS_CTL_MASK |
1450                                 CS42L42_PDN_MIC_LVL_DET_MASK,
1451                                 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1452                                 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1453
1454         /* Set auto HS bias settings to default */
1455         regmap_update_bits(cs42l42->regmap,
1456                                 CS42L42_HSBIAS_SC_AUTOCTL,
1457                                 CS42L42_HSBIAS_SENSE_EN_MASK |
1458                                 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1459                                 CS42L42_TIP_SENSE_EN_MASK |
1460                                 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1461                                 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1462                                 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1463                                 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1464                                 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1465
1466         /* Set hs detect to manual, disabled mode */
1467         regmap_update_bits(cs42l42->regmap,
1468                                 CS42L42_HSDET_CTL2,
1469                                 CS42L42_HSDET_CTRL_MASK |
1470                                 CS42L42_HSDET_SET_MASK |
1471                                 CS42L42_HSBIAS_REF_MASK |
1472                                 CS42L42_HSDET_AUTO_TIME_MASK,
1473                                 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1474                                 (2 << CS42L42_HSDET_SET_SHIFT) |
1475                                 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1476                                 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1477 }
1478
1479 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1480 {
1481         int bias_level;
1482         unsigned int detect_status;
1483
1484         /* Mask button detect interrupts */
1485         regmap_update_bits(cs42l42->regmap,
1486                 CS42L42_DET_INT2_MASK,
1487                 CS42L42_M_DETECT_TF_MASK |
1488                 CS42L42_M_DETECT_FT_MASK |
1489                 CS42L42_M_HSBIAS_HIZ_MASK |
1490                 CS42L42_M_SHORT_RLS_MASK |
1491                 CS42L42_M_SHORT_DET_MASK,
1492                 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1493                 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1494                 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1495                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1496                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1497
1498         usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1499                      cs42l42->btn_det_event_dbnce * 2000);
1500
1501         /* Test all 4 level detect biases */
1502         bias_level = 1;
1503         do {
1504                 /* Adjust button detect level sensitivity */
1505                 regmap_update_bits(cs42l42->regmap,
1506                         CS42L42_MIC_DET_CTL1,
1507                         CS42L42_LATCH_TO_VP_MASK |
1508                         CS42L42_EVENT_STAT_SEL_MASK |
1509                         CS42L42_HS_DET_LEVEL_MASK,
1510                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1511                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1512                         (cs42l42->bias_thresholds[bias_level] <<
1513                         CS42L42_HS_DET_LEVEL_SHIFT));
1514
1515                 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1516                                 &detect_status);
1517         } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1518                 (++bias_level < CS42L42_NUM_BIASES));
1519
1520         switch (bias_level) {
1521         case 1: /* Function C button press */
1522                 bias_level = SND_JACK_BTN_2;
1523                 dev_dbg(cs42l42->dev, "Function C button press\n");
1524                 break;
1525         case 2: /* Function B button press */
1526                 bias_level = SND_JACK_BTN_1;
1527                 dev_dbg(cs42l42->dev, "Function B button press\n");
1528                 break;
1529         case 3: /* Function D button press */
1530                 bias_level = SND_JACK_BTN_3;
1531                 dev_dbg(cs42l42->dev, "Function D button press\n");
1532                 break;
1533         case 4: /* Function A button press */
1534                 bias_level = SND_JACK_BTN_0;
1535                 dev_dbg(cs42l42->dev, "Function A button press\n");
1536                 break;
1537         default:
1538                 bias_level = 0;
1539                 break;
1540         }
1541
1542         /* Set button detect level sensitivity back to default */
1543         regmap_update_bits(cs42l42->regmap,
1544                 CS42L42_MIC_DET_CTL1,
1545                 CS42L42_LATCH_TO_VP_MASK |
1546                 CS42L42_EVENT_STAT_SEL_MASK |
1547                 CS42L42_HS_DET_LEVEL_MASK,
1548                 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1549                 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1550                 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1551
1552         /* Clear any button interrupts before unmasking them */
1553         regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1554                     &detect_status);
1555
1556         /* Unmask button detect interrupts */
1557         regmap_update_bits(cs42l42->regmap,
1558                 CS42L42_DET_INT2_MASK,
1559                 CS42L42_M_DETECT_TF_MASK |
1560                 CS42L42_M_DETECT_FT_MASK |
1561                 CS42L42_M_HSBIAS_HIZ_MASK |
1562                 CS42L42_M_SHORT_RLS_MASK |
1563                 CS42L42_M_SHORT_DET_MASK,
1564                 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1565                 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1566                 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1567                 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1568                 (1 << CS42L42_M_SHORT_DET_SHIFT));
1569
1570         return bias_level;
1571 }
1572
1573 struct cs42l42_irq_params {
1574         u16 status_addr;
1575         u16 mask_addr;
1576         u8 mask;
1577 };
1578
1579 static const struct cs42l42_irq_params irq_params_table[] = {
1580         {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1581                 CS42L42_ADC_OVFL_VAL_MASK},
1582         {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1583                 CS42L42_MIXER_VAL_MASK},
1584         {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1585                 CS42L42_SRC_VAL_MASK},
1586         {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1587                 CS42L42_ASP_RX_VAL_MASK},
1588         {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1589                 CS42L42_ASP_TX_VAL_MASK},
1590         {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1591                 CS42L42_CODEC_VAL_MASK},
1592         {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1593                 CS42L42_DET_INT_VAL1_MASK},
1594         {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1595                 CS42L42_DET_INT_VAL2_MASK},
1596         {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1597                 CS42L42_SRCPL_VAL_MASK},
1598         {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1599                 CS42L42_VPMON_VAL_MASK},
1600         {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1601                 CS42L42_PLL_LOCK_VAL_MASK},
1602         {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1603                 CS42L42_TSRS_PLUG_VAL_MASK}
1604 };
1605
1606 static irqreturn_t cs42l42_irq_thread(int irq, void *data)
1607 {
1608         struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1609         unsigned int stickies[12];
1610         unsigned int masks[12];
1611         unsigned int current_plug_status;
1612         unsigned int current_button_status;
1613         unsigned int i;
1614         int report = 0;
1615
1616
1617         /* Read sticky registers to clear interurpt */
1618         for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1619                 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1620                                 &(stickies[i]));
1621                 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1622                                 &(masks[i]));
1623                 stickies[i] = stickies[i] & (~masks[i]) &
1624                                 irq_params_table[i].mask;
1625         }
1626
1627         /* Read tip sense status before handling type detect */
1628         current_plug_status = (stickies[11] &
1629                 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1630                 CS42L42_TS_PLUG_SHIFT;
1631
1632         /* Read button sense status */
1633         current_button_status = stickies[7] &
1634                 (CS42L42_M_DETECT_TF_MASK |
1635                 CS42L42_M_DETECT_FT_MASK |
1636                 CS42L42_M_HSBIAS_HIZ_MASK);
1637
1638         mutex_lock(&cs42l42->jack_detect_mutex);
1639
1640         /* Check auto-detect status */
1641         if ((~masks[5]) & irq_params_table[5].mask) {
1642                 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1643                         cs42l42_process_hs_type_detect(cs42l42);
1644                         switch (cs42l42->hs_type) {
1645                         case CS42L42_PLUG_CTIA:
1646                         case CS42L42_PLUG_OMTP:
1647                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1648                                                     SND_JACK_HEADSET);
1649                                 break;
1650                         case CS42L42_PLUG_HEADPHONE:
1651                                 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1652                                                     SND_JACK_HEADPHONE);
1653                                 break;
1654                         default:
1655                                 break;
1656                         }
1657                         dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1658                 }
1659         }
1660
1661         /* Check tip sense status */
1662         if ((~masks[11]) & irq_params_table[11].mask) {
1663                 switch (current_plug_status) {
1664                 case CS42L42_TS_PLUG:
1665                         if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1666                                 cs42l42->plug_state = CS42L42_TS_PLUG;
1667                                 cs42l42_init_hs_type_detect(cs42l42);
1668                         }
1669                         break;
1670
1671                 case CS42L42_TS_UNPLUG:
1672                         if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1673                                 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1674                                 cs42l42_cancel_hs_type_detect(cs42l42);
1675
1676                                 snd_soc_jack_report(cs42l42->jack, 0,
1677                                                     SND_JACK_HEADSET |
1678                                                     SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1679                                                     SND_JACK_BTN_2 | SND_JACK_BTN_3);
1680
1681                                 dev_dbg(cs42l42->dev, "Unplug event\n");
1682                         }
1683                         break;
1684
1685                 default:
1686                         if (cs42l42->plug_state != CS42L42_TS_TRANS)
1687                                 cs42l42->plug_state = CS42L42_TS_TRANS;
1688                 }
1689         }
1690
1691         /* Check button detect status */
1692         if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
1693                 if (!(current_button_status &
1694                         CS42L42_M_HSBIAS_HIZ_MASK)) {
1695
1696                         if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1697                                 dev_dbg(cs42l42->dev, "Button released\n");
1698                                 report = 0;
1699                         } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1700                                 report = cs42l42_handle_button_press(cs42l42);
1701
1702                         }
1703                         snd_soc_jack_report(cs42l42->jack, report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1704                                                                    SND_JACK_BTN_2 | SND_JACK_BTN_3);
1705                 }
1706         }
1707
1708         mutex_unlock(&cs42l42->jack_detect_mutex);
1709
1710         return IRQ_HANDLED;
1711 }
1712
1713 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1714 {
1715         regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1716                         CS42L42_ADC_OVFL_MASK,
1717                         (1 << CS42L42_ADC_OVFL_SHIFT));
1718
1719         regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1720                         CS42L42_MIX_CHB_OVFL_MASK |
1721                         CS42L42_MIX_CHA_OVFL_MASK |
1722                         CS42L42_EQ_OVFL_MASK |
1723                         CS42L42_EQ_BIQUAD_OVFL_MASK,
1724                         (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1725                         (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1726                         (1 << CS42L42_EQ_OVFL_SHIFT) |
1727                         (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1728
1729         regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1730                         CS42L42_SRC_ILK_MASK |
1731                         CS42L42_SRC_OLK_MASK |
1732                         CS42L42_SRC_IUNLK_MASK |
1733                         CS42L42_SRC_OUNLK_MASK,
1734                         (1 << CS42L42_SRC_ILK_SHIFT) |
1735                         (1 << CS42L42_SRC_OLK_SHIFT) |
1736                         (1 << CS42L42_SRC_IUNLK_SHIFT) |
1737                         (1 << CS42L42_SRC_OUNLK_SHIFT));
1738
1739         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1740                         CS42L42_ASPRX_NOLRCK_MASK |
1741                         CS42L42_ASPRX_EARLY_MASK |
1742                         CS42L42_ASPRX_LATE_MASK |
1743                         CS42L42_ASPRX_ERROR_MASK |
1744                         CS42L42_ASPRX_OVLD_MASK,
1745                         (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1746                         (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1747                         (1 << CS42L42_ASPRX_LATE_SHIFT) |
1748                         (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1749                         (1 << CS42L42_ASPRX_OVLD_SHIFT));
1750
1751         regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1752                         CS42L42_ASPTX_NOLRCK_MASK |
1753                         CS42L42_ASPTX_EARLY_MASK |
1754                         CS42L42_ASPTX_LATE_MASK |
1755                         CS42L42_ASPTX_SMERROR_MASK,
1756                         (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1757                         (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1758                         (1 << CS42L42_ASPTX_LATE_SHIFT) |
1759                         (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1760
1761         regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1762                         CS42L42_PDN_DONE_MASK |
1763                         CS42L42_HSDET_AUTO_DONE_MASK,
1764                         (1 << CS42L42_PDN_DONE_SHIFT) |
1765                         (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1766
1767         regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1768                         CS42L42_SRCPL_ADC_LK_MASK |
1769                         CS42L42_SRCPL_DAC_LK_MASK |
1770                         CS42L42_SRCPL_ADC_UNLK_MASK |
1771                         CS42L42_SRCPL_DAC_UNLK_MASK,
1772                         (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1773                         (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1774                         (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1775                         (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1776
1777         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1778                         CS42L42_TIP_SENSE_UNPLUG_MASK |
1779                         CS42L42_TIP_SENSE_PLUG_MASK |
1780                         CS42L42_HSBIAS_SENSE_MASK,
1781                         (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1782                         (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1783                         (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1784
1785         regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1786                         CS42L42_M_DETECT_TF_MASK |
1787                         CS42L42_M_DETECT_FT_MASK |
1788                         CS42L42_M_HSBIAS_HIZ_MASK |
1789                         CS42L42_M_SHORT_RLS_MASK |
1790                         CS42L42_M_SHORT_DET_MASK,
1791                         (1 << CS42L42_M_DETECT_TF_SHIFT) |
1792                         (1 << CS42L42_M_DETECT_FT_SHIFT) |
1793                         (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1794                         (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1795                         (1 << CS42L42_M_SHORT_DET_SHIFT));
1796
1797         regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1798                         CS42L42_VPMON_MASK,
1799                         (1 << CS42L42_VPMON_SHIFT));
1800
1801         regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1802                         CS42L42_PLL_LOCK_MASK,
1803                         (1 << CS42L42_PLL_LOCK_SHIFT));
1804
1805         regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1806                         CS42L42_RS_PLUG_MASK |
1807                         CS42L42_RS_UNPLUG_MASK |
1808                         CS42L42_TS_PLUG_MASK |
1809                         CS42L42_TS_UNPLUG_MASK,
1810                         (1 << CS42L42_RS_PLUG_SHIFT) |
1811                         (1 << CS42L42_RS_UNPLUG_SHIFT) |
1812                         (0 << CS42L42_TS_PLUG_SHIFT) |
1813                         (0 << CS42L42_TS_UNPLUG_SHIFT));
1814 }
1815
1816 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1817 {
1818         unsigned int reg;
1819
1820         cs42l42->hs_type = CS42L42_PLUG_INVALID;
1821
1822         regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL,
1823                            CS42L42_DETECT_MODE_MASK, 0);
1824
1825         /* Latch analog controls to VP power domain */
1826         regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1827                         CS42L42_LATCH_TO_VP_MASK |
1828                         CS42L42_EVENT_STAT_SEL_MASK |
1829                         CS42L42_HS_DET_LEVEL_MASK,
1830                         (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1831                         (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1832                         (cs42l42->bias_thresholds[0] <<
1833                         CS42L42_HS_DET_LEVEL_SHIFT));
1834
1835         /* Remove ground noise-suppression clamps */
1836         regmap_update_bits(cs42l42->regmap,
1837                         CS42L42_HS_CLAMP_DISABLE,
1838                         CS42L42_HS_CLAMP_DISABLE_MASK,
1839                         (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1840
1841         /* Enable the tip sense circuit */
1842         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1843                            CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
1844
1845         regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1846                         CS42L42_TIP_SENSE_CTRL_MASK |
1847                         CS42L42_TIP_SENSE_INV_MASK |
1848                         CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1849                         (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1850                         (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
1851                         (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1852
1853         /* Save the initial status of the tip sense */
1854         regmap_read(cs42l42->regmap,
1855                           CS42L42_TSRS_PLUG_STATUS,
1856                           &reg);
1857         cs42l42->plug_state = (((char) reg) &
1858                       (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1859                       CS42L42_TS_PLUG_SHIFT;
1860 }
1861
1862 static const unsigned int threshold_defaults[] = {
1863         CS42L42_HS_DET_LEVEL_15,
1864         CS42L42_HS_DET_LEVEL_8,
1865         CS42L42_HS_DET_LEVEL_4,
1866         CS42L42_HS_DET_LEVEL_1
1867 };
1868
1869 static int cs42l42_handle_device_data(struct device *dev,
1870                                         struct cs42l42_private *cs42l42)
1871 {
1872         unsigned int val;
1873         u32 thresholds[CS42L42_NUM_BIASES];
1874         int ret;
1875         int i;
1876
1877         ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1878         if (!ret) {
1879                 switch (val) {
1880                 case CS42L42_TS_INV_EN:
1881                 case CS42L42_TS_INV_DIS:
1882                         cs42l42->ts_inv = val;
1883                         break;
1884                 default:
1885                         dev_err(dev,
1886                                 "Wrong cirrus,ts-inv DT value %d\n",
1887                                 val);
1888                         cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1889                 }
1890         } else {
1891                 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1892         }
1893
1894         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1895         if (!ret) {
1896                 switch (val) {
1897                 case CS42L42_TS_DBNCE_0:
1898                 case CS42L42_TS_DBNCE_125:
1899                 case CS42L42_TS_DBNCE_250:
1900                 case CS42L42_TS_DBNCE_500:
1901                 case CS42L42_TS_DBNCE_750:
1902                 case CS42L42_TS_DBNCE_1000:
1903                 case CS42L42_TS_DBNCE_1250:
1904                 case CS42L42_TS_DBNCE_1500:
1905                         cs42l42->ts_dbnc_rise = val;
1906                         break;
1907                 default:
1908                         dev_err(dev,
1909                                 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1910                                 val);
1911                         cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1912                 }
1913         } else {
1914                 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1915         }
1916
1917         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1918                         CS42L42_TS_RISE_DBNCE_TIME_MASK,
1919                         (cs42l42->ts_dbnc_rise <<
1920                         CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1921
1922         ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1923         if (!ret) {
1924                 switch (val) {
1925                 case CS42L42_TS_DBNCE_0:
1926                 case CS42L42_TS_DBNCE_125:
1927                 case CS42L42_TS_DBNCE_250:
1928                 case CS42L42_TS_DBNCE_500:
1929                 case CS42L42_TS_DBNCE_750:
1930                 case CS42L42_TS_DBNCE_1000:
1931                 case CS42L42_TS_DBNCE_1250:
1932                 case CS42L42_TS_DBNCE_1500:
1933                         cs42l42->ts_dbnc_fall = val;
1934                         break;
1935                 default:
1936                         dev_err(dev,
1937                                 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
1938                                 val);
1939                         cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1940                 }
1941         } else {
1942                 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
1943         }
1944
1945         regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1946                         CS42L42_TS_FALL_DBNCE_TIME_MASK,
1947                         (cs42l42->ts_dbnc_fall <<
1948                         CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
1949
1950         ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
1951         if (!ret) {
1952                 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
1953                         cs42l42->btn_det_init_dbnce = val;
1954                 else {
1955                         dev_err(dev,
1956                                 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
1957                                 val);
1958                         cs42l42->btn_det_init_dbnce =
1959                                 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1960                 }
1961         } else {
1962                 cs42l42->btn_det_init_dbnce =
1963                         CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
1964         }
1965
1966         ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
1967         if (!ret) {
1968                 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
1969                         cs42l42->btn_det_event_dbnce = val;
1970                 else {
1971                         dev_err(dev,
1972                                 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
1973                         cs42l42->btn_det_event_dbnce =
1974                                 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1975                 }
1976         } else {
1977                 cs42l42->btn_det_event_dbnce =
1978                         CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
1979         }
1980
1981         ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
1982                                              thresholds, ARRAY_SIZE(thresholds));
1983         if (!ret) {
1984                 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
1985                         if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
1986                                 cs42l42->bias_thresholds[i] = thresholds[i];
1987                         else {
1988                                 dev_err(dev,
1989                                         "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
1990                                         thresholds[i]);
1991                                 cs42l42->bias_thresholds[i] = threshold_defaults[i];
1992                         }
1993                 }
1994         } else {
1995                 for (i = 0; i < CS42L42_NUM_BIASES; i++)
1996                         cs42l42->bias_thresholds[i] = threshold_defaults[i];
1997         }
1998
1999         ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
2000         if (!ret) {
2001                 switch (val) {
2002                 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
2003                         cs42l42->hs_bias_ramp_rate = val;
2004                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
2005                         break;
2006                 case CS42L42_HSBIAS_RAMP_FAST:
2007                         cs42l42->hs_bias_ramp_rate = val;
2008                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
2009                         break;
2010                 case CS42L42_HSBIAS_RAMP_SLOW:
2011                         cs42l42->hs_bias_ramp_rate = val;
2012                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2013                         break;
2014                 case CS42L42_HSBIAS_RAMP_SLOWEST:
2015                         cs42l42->hs_bias_ramp_rate = val;
2016                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
2017                         break;
2018                 default:
2019                         dev_err(dev,
2020                                 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
2021                                 val);
2022                         cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2023                         cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2024                 }
2025         } else {
2026                 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2027                 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2028         }
2029
2030         regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
2031                         CS42L42_HSBIAS_RAMP_MASK,
2032                         (cs42l42->hs_bias_ramp_rate <<
2033                         CS42L42_HSBIAS_RAMP_SHIFT));
2034
2035         if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
2036                 cs42l42->hs_bias_sense_en = 0;
2037         else
2038                 cs42l42->hs_bias_sense_en = 1;
2039
2040         return 0;
2041 }
2042
2043 static int cs42l42_i2c_probe(struct i2c_client *i2c_client,
2044                                        const struct i2c_device_id *id)
2045 {
2046         struct cs42l42_private *cs42l42;
2047         int ret, i, devid;
2048         unsigned int reg;
2049
2050         cs42l42 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42l42_private),
2051                                GFP_KERNEL);
2052         if (!cs42l42)
2053                 return -ENOMEM;
2054
2055         cs42l42->dev = &i2c_client->dev;
2056         i2c_set_clientdata(i2c_client, cs42l42);
2057         mutex_init(&cs42l42->jack_detect_mutex);
2058
2059         cs42l42->regmap = devm_regmap_init_i2c(i2c_client, &cs42l42_regmap);
2060         if (IS_ERR(cs42l42->regmap)) {
2061                 ret = PTR_ERR(cs42l42->regmap);
2062                 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
2063                 return ret;
2064         }
2065
2066         for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
2067                 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
2068
2069         ret = devm_regulator_bulk_get(&i2c_client->dev,
2070                                       ARRAY_SIZE(cs42l42->supplies),
2071                                       cs42l42->supplies);
2072         if (ret != 0) {
2073                 dev_err(&i2c_client->dev,
2074                         "Failed to request supplies: %d\n", ret);
2075                 return ret;
2076         }
2077
2078         ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
2079                                     cs42l42->supplies);
2080         if (ret != 0) {
2081                 dev_err(&i2c_client->dev,
2082                         "Failed to enable supplies: %d\n", ret);
2083                 return ret;
2084         }
2085
2086         /* Reset the Device */
2087         cs42l42->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
2088                 "reset", GPIOD_OUT_LOW);
2089         if (IS_ERR(cs42l42->reset_gpio)) {
2090                 ret = PTR_ERR(cs42l42->reset_gpio);
2091                 goto err_disable_noreset;
2092         }
2093
2094         if (cs42l42->reset_gpio) {
2095                 dev_dbg(&i2c_client->dev, "Found reset GPIO\n");
2096                 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2097         }
2098         usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2099
2100         /* Request IRQ if one was specified */
2101         if (i2c_client->irq) {
2102                 ret = request_threaded_irq(i2c_client->irq,
2103                                            NULL, cs42l42_irq_thread,
2104                                            IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2105                                            "cs42l42", cs42l42);
2106                 if (ret == -EPROBE_DEFER) {
2107                         goto err_disable_noirq;
2108                 } else if (ret != 0) {
2109                         dev_err(&i2c_client->dev,
2110                                 "Failed to request IRQ: %d\n", ret);
2111                         goto err_disable_noirq;
2112                 }
2113         }
2114
2115         /* initialize codec */
2116         devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
2117         if (devid < 0) {
2118                 ret = devid;
2119                 dev_err(&i2c_client->dev, "Failed to read device ID: %d\n", ret);
2120                 goto err_disable;
2121         }
2122
2123         if (devid != CS42L42_CHIP_ID) {
2124                 ret = -ENODEV;
2125                 dev_err(&i2c_client->dev,
2126                         "CS42L42 Device ID (%X). Expected %X\n",
2127                         devid, CS42L42_CHIP_ID);
2128                 goto err_disable;
2129         }
2130
2131         ret = regmap_read(cs42l42->regmap, CS42L42_REVID, &reg);
2132         if (ret < 0) {
2133                 dev_err(&i2c_client->dev, "Get Revision ID failed\n");
2134                 goto err_shutdown;
2135         }
2136
2137         dev_info(&i2c_client->dev,
2138                  "Cirrus Logic CS42L42, Revision: %02X\n", reg & 0xFF);
2139
2140         /* Power up the codec */
2141         regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
2142                         CS42L42_ASP_DAO_PDN_MASK |
2143                         CS42L42_ASP_DAI_PDN_MASK |
2144                         CS42L42_MIXER_PDN_MASK |
2145                         CS42L42_EQ_PDN_MASK |
2146                         CS42L42_HP_PDN_MASK |
2147                         CS42L42_ADC_PDN_MASK |
2148                         CS42L42_PDN_ALL_MASK,
2149                         (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
2150                         (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
2151                         (1 << CS42L42_MIXER_PDN_SHIFT) |
2152                         (1 << CS42L42_EQ_PDN_SHIFT) |
2153                         (1 << CS42L42_HP_PDN_SHIFT) |
2154                         (1 << CS42L42_ADC_PDN_SHIFT) |
2155                         (0 << CS42L42_PDN_ALL_SHIFT));
2156
2157         ret = cs42l42_handle_device_data(&i2c_client->dev, cs42l42);
2158         if (ret != 0)
2159                 goto err_shutdown;
2160
2161         /* Setup headset detection */
2162         cs42l42_setup_hs_type_detect(cs42l42);
2163
2164         /* Mask/Unmask Interrupts */
2165         cs42l42_set_interrupt_masks(cs42l42);
2166
2167         /* Register codec for machine driver */
2168         ret = devm_snd_soc_register_component(&i2c_client->dev,
2169                         &soc_component_dev_cs42l42, &cs42l42_dai, 1);
2170         if (ret < 0)
2171                 goto err_shutdown;
2172
2173         return 0;
2174
2175 err_shutdown:
2176         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2177         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2178         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2179
2180 err_disable:
2181         if (i2c_client->irq)
2182                 free_irq(i2c_client->irq, cs42l42);
2183
2184 err_disable_noirq:
2185         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2186 err_disable_noreset:
2187         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2188                                 cs42l42->supplies);
2189         return ret;
2190 }
2191
2192 static int cs42l42_i2c_remove(struct i2c_client *i2c_client)
2193 {
2194         struct cs42l42_private *cs42l42 = i2c_get_clientdata(i2c_client);
2195
2196         if (i2c_client->irq)
2197                 free_irq(i2c_client->irq, cs42l42);
2198
2199         /*
2200          * The driver might not have control of reset and power supplies,
2201          * so ensure that the chip internals are powered down.
2202          */
2203         regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2204         regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2205         regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2206
2207         gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2208         regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2209
2210         return 0;
2211 }
2212
2213 #ifdef CONFIG_OF
2214 static const struct of_device_id cs42l42_of_match[] = {
2215         { .compatible = "cirrus,cs42l42", },
2216         {}
2217 };
2218 MODULE_DEVICE_TABLE(of, cs42l42_of_match);
2219 #endif
2220
2221 #ifdef CONFIG_ACPI
2222 static const struct acpi_device_id cs42l42_acpi_match[] = {
2223         {"10134242", 0,},
2224         {}
2225 };
2226 MODULE_DEVICE_TABLE(acpi, cs42l42_acpi_match);
2227 #endif
2228
2229 static const struct i2c_device_id cs42l42_id[] = {
2230         {"cs42l42", 0},
2231         {}
2232 };
2233
2234 MODULE_DEVICE_TABLE(i2c, cs42l42_id);
2235
2236 static struct i2c_driver cs42l42_i2c_driver = {
2237         .driver = {
2238                 .name = "cs42l42",
2239                 .of_match_table = of_match_ptr(cs42l42_of_match),
2240                 .acpi_match_table = ACPI_PTR(cs42l42_acpi_match),
2241                 },
2242         .id_table = cs42l42_id,
2243         .probe = cs42l42_i2c_probe,
2244         .remove = cs42l42_i2c_remove,
2245 };
2246
2247 module_i2c_driver(cs42l42_i2c_driver);
2248
2249 MODULE_DESCRIPTION("ASoC CS42L42 driver");
2250 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2251 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2252 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2253 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
2254 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
2255 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
2256 MODULE_LICENSE("GPL");