sound/soc/codecs/cs35l36.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // cs35l36.c -- CS35L36 ALSA SoC audio driver
   4 //
   5 // Copyright 2018 Cirrus Logic, Inc.
   6 //
   7 // Author: James Schulman <james.schulman@cirrus.com>
   8
   9 #include <linux/module.h>
  10 #include <linux/moduleparam.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/delay.h>
  14 #include <linux/i2c.h>
  15 #include <linux/slab.h>
  16 #include <linux/workqueue.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/gpio/consumer.h>
  20 #include <linux/of_device.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/regmap.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <linux/gpio.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31 #include <sound/cs35l36.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/completion.h>
  34
  35 #include "cs35l36.h"
  36
  37 /*
  38  * Some fields take zero as a valid value so use a high bit flag that won't
  39  * get written to the device to mark those.
  40  */
  41 #define CS35L36_VALID_PDATA 0x80000000
  42
  43 static const char * const cs35l36_supplies[] = {
  44         "VA",
  45         "VP",
  46 };
  47
  48 struct  cs35l36_private {
  49         struct device *dev;
  50         struct cs35l36_platform_data pdata;
  51         struct regmap *regmap;
  52         struct regulator_bulk_data supplies[2];
  53         int num_supplies;
  54         int clksrc;
  55         int chip_version;
  56         int rev_id;
  57         int ldm_mode_sel;
  58         struct gpio_desc *reset_gpio;
  59 };
  60
  61 struct cs35l36_pll_config {
  62         int freq;
  63         int clk_cfg;
  64         int fll_igain;
  65 };
  66
  67 static const struct cs35l36_pll_config cs35l36_pll_sysclk[] = {
  68         {32768,         0x00, 0x05},
  69         {8000,          0x01, 0x03},
  70         {11025,         0x02, 0x03},
  71         {12000,         0x03, 0x03},
  72         {16000,         0x04, 0x04},
  73         {22050,         0x05, 0x04},
  74         {24000,         0x06, 0x04},
  75         {32000,         0x07, 0x05},
  76         {44100,         0x08, 0x05},
  77         {48000,         0x09, 0x05},
  78         {88200,         0x0A, 0x06},
  79         {96000,         0x0B, 0x06},
  80         {128000,        0x0C, 0x07},
  81         {176400,        0x0D, 0x07},
  82         {192000,        0x0E, 0x07},
  83         {256000,        0x0F, 0x08},
  84         {352800,        0x10, 0x08},
  85         {384000,        0x11, 0x08},
  86         {512000,        0x12, 0x09},
  87         {705600,        0x13, 0x09},
  88         {750000,        0x14, 0x09},
  89         {768000,        0x15, 0x09},
  90         {1000000,       0x16, 0x0A},
  91         {1024000,       0x17, 0x0A},
  92         {1200000,       0x18, 0x0A},
  93         {1411200,       0x19, 0x0A},
  94         {1500000,       0x1A, 0x0A},
  95         {1536000,       0x1B, 0x0A},
  96         {2000000,       0x1C, 0x0A},
  97         {2048000,       0x1D, 0x0A},
  98         {2400000,       0x1E, 0x0A},
  99         {2822400,       0x1F, 0x0A},
 100         {3000000,       0x20, 0x0A},
 101         {3072000,       0x21, 0x0A},
 102         {3200000,       0x22, 0x0A},
 103         {4000000,       0x23, 0x0A},
 104         {4096000,       0x24, 0x0A},
 105         {4800000,       0x25, 0x0A},
 106         {5644800,       0x26, 0x0A},
 107         {6000000,       0x27, 0x0A},
 108         {6144000,       0x28, 0x0A},
 109         {6250000,       0x29, 0x08},
 110         {6400000,       0x2A, 0x0A},
 111         {6500000,       0x2B, 0x08},
 112         {6750000,       0x2C, 0x09},
 113         {7526400,       0x2D, 0x0A},
 114         {8000000,       0x2E, 0x0A},
 115         {8192000,       0x2F, 0x0A},
 116         {9600000,       0x30, 0x0A},
 117         {11289600,      0x31, 0x0A},
 118         {12000000,      0x32, 0x0A},
 119         {12288000,      0x33, 0x0A},
 120         {12500000,      0x34, 0x08},
 121         {12800000,      0x35, 0x0A},
 122         {13000000,      0x36, 0x0A},
 123         {13500000,      0x37, 0x0A},
 124         {19200000,      0x38, 0x0A},
 125         {22579200,      0x39, 0x0A},
 126         {24000000,      0x3A, 0x0A},
 127         {24576000,      0x3B, 0x0A},
 128         {25000000,      0x3C, 0x0A},
 129         {25600000,      0x3D, 0x0A},
 130         {26000000,      0x3E, 0x0A},
 131         {27000000,      0x3F, 0x0A},
 132 };
 133
 134 static struct reg_default cs35l36_reg[] = {
 135         {CS35L36_TESTKEY_CTRL,                  0x00000000},
 136         {CS35L36_USERKEY_CTL,                   0x00000000},
 137         {CS35L36_OTP_CTRL1,                     0x00002460},
 138         {CS35L36_OTP_CTRL2,                     0x00000000},
 139         {CS35L36_OTP_CTRL3,                     0x00000000},
 140         {CS35L36_OTP_CTRL4,                     0x00000000},
 141         {CS35L36_OTP_CTRL5,                     0x00000000},
 142         {CS35L36_PAC_CTL1,                      0x00000004},
 143         {CS35L36_PAC_CTL2,                      0x00000000},
 144         {CS35L36_PAC_CTL3,                      0x00000000},
 145         {CS35L36_PWR_CTRL1,                     0x00000000},
 146         {CS35L36_PWR_CTRL2,                     0x00003321},
 147         {CS35L36_PWR_CTRL3,                     0x01000010},
 148         {CS35L36_CTRL_OVRRIDE,                  0x00000002},
 149         {CS35L36_AMP_OUT_MUTE,                  0x00000000},
 150         {CS35L36_OTP_TRIM_STATUS,               0x00000000},
 151         {CS35L36_DISCH_FILT,                    0x00000000},
 152         {CS35L36_PROTECT_REL_ERR,               0x00000000},
 153         {CS35L36_PAD_INTERFACE,                 0x00000038},
 154         {CS35L36_PLL_CLK_CTRL,                  0x00000010},
 155         {CS35L36_GLOBAL_CLK_CTRL,               0x00000003},
 156         {CS35L36_ADC_CLK_CTRL,                  0x00000000},
 157         {CS35L36_SWIRE_CLK_CTRL,                0x00000000},
 158         {CS35L36_SP_SCLK_CLK_CTRL,              0x00000000},
 159         {CS35L36_MDSYNC_EN,                     0x00000000},
 160         {CS35L36_MDSYNC_TX_ID,                  0x00000000},
 161         {CS35L36_MDSYNC_PWR_CTRL,               0x00000000},
 162         {CS35L36_MDSYNC_DATA_TX,                0x00000000},
 163         {CS35L36_MDSYNC_TX_STATUS,              0x00000002},
 164         {CS35L36_MDSYNC_RX_STATUS,              0x00000000},
 165         {CS35L36_MDSYNC_ERR_STATUS,             0x00000000},
 166         {CS35L36_BSTCVRT_VCTRL1,                0x00000000},
 167         {CS35L36_BSTCVRT_VCTRL2,                0x00000001},
 168         {CS35L36_BSTCVRT_PEAK_CUR,              0x0000004A},
 169         {CS35L36_BSTCVRT_SFT_RAMP,              0x00000003},
 170         {CS35L36_BSTCVRT_COEFF,                 0x00002424},
 171         {CS35L36_BSTCVRT_SLOPE_LBST,            0x00005800},
 172         {CS35L36_BSTCVRT_SW_FREQ,               0x00010000},
 173         {CS35L36_BSTCVRT_DCM_CTRL,              0x00002001},
 174         {CS35L36_BSTCVRT_DCM_MODE_FORCE,        0x00000000},
 175         {CS35L36_BSTCVRT_OVERVOLT_CTRL,         0x00000130},
 176         {CS35L36_VPI_LIMIT_MODE,                0x00000000},
 177         {CS35L36_VPI_LIMIT_MINMAX,              0x00003000},
 178         {CS35L36_VPI_VP_THLD,                   0x00101010},
 179         {CS35L36_VPI_TRACK_CTRL,                0x00000000},
 180         {CS35L36_VPI_TRIG_MODE_CTRL,            0x00000000},
 181         {CS35L36_VPI_TRIG_STEPS,                0x00000000},
 182         {CS35L36_VI_SPKMON_FILT,                0x00000003},
 183         {CS35L36_VI_SPKMON_GAIN,                0x00000909},
 184         {CS35L36_VI_SPKMON_IP_SEL,              0x00000000},
 185         {CS35L36_DTEMP_WARN_THLD,               0x00000002},
 186         {CS35L36_DTEMP_STATUS,                  0x00000000},
 187         {CS35L36_VPVBST_FS_SEL,                 0x00000001},
 188         {CS35L36_VPVBST_VP_CTRL,                0x000001C0},
 189         {CS35L36_VPVBST_VBST_CTRL,              0x000001C0},
 190         {CS35L36_ASP_TX_PIN_CTRL,               0x00000028},
 191         {CS35L36_ASP_RATE_CTRL,                 0x00090000},
 192         {CS35L36_ASP_FORMAT,                    0x00000002},
 193         {CS35L36_ASP_FRAME_CTRL,                0x00180018},
 194         {CS35L36_ASP_TX1_TX2_SLOT,              0x00010000},
 195         {CS35L36_ASP_TX3_TX4_SLOT,              0x00030002},
 196         {CS35L36_ASP_TX5_TX6_SLOT,              0x00050004},
 197         {CS35L36_ASP_TX7_TX8_SLOT,              0x00070006},
 198         {CS35L36_ASP_RX1_SLOT,                  0x00000000},
 199         {CS35L36_ASP_RX_TX_EN,                  0x00000000},
 200         {CS35L36_ASP_RX1_SEL,                   0x00000008},
 201         {CS35L36_ASP_TX1_SEL,                   0x00000018},
 202         {CS35L36_ASP_TX2_SEL,                   0x00000019},
 203         {CS35L36_ASP_TX3_SEL,                   0x00000028},
 204         {CS35L36_ASP_TX4_SEL,                   0x00000029},
 205         {CS35L36_ASP_TX5_SEL,                   0x00000020},
 206         {CS35L36_ASP_TX6_SEL,                   0x00000000},
 207         {CS35L36_SWIRE_P1_TX1_SEL,              0x00000018},
 208         {CS35L36_SWIRE_P1_TX2_SEL,              0x00000019},
 209         {CS35L36_SWIRE_P2_TX1_SEL,              0x00000028},
 210         {CS35L36_SWIRE_P2_TX2_SEL,              0x00000029},
 211         {CS35L36_SWIRE_P2_TX3_SEL,              0x00000020},
 212         {CS35L36_SWIRE_DP1_FIFO_CFG,            0x0000001B},
 213         {CS35L36_SWIRE_DP2_FIFO_CFG,            0x0000001B},
 214         {CS35L36_SWIRE_DP3_FIFO_CFG,            0x0000001B},
 215         {CS35L36_SWIRE_PCM_RX_DATA,             0x00000000},
 216         {CS35L36_SWIRE_FS_SEL,                  0x00000001},
 217         {CS35L36_AMP_DIG_VOL_CTRL,              0x00008000},
 218         {CS35L36_VPBR_CFG,                      0x02AA1905},
 219         {CS35L36_VBBR_CFG,                      0x02AA1905},
 220         {CS35L36_VPBR_STATUS,                   0x00000000},
 221         {CS35L36_VBBR_STATUS,                   0x00000000},
 222         {CS35L36_OVERTEMP_CFG,                  0x00000001},
 223         {CS35L36_AMP_ERR_VOL,                   0x00000000},
 224         {CS35L36_CLASSH_CFG,                    0x000B0405},
 225         {CS35L36_CLASSH_FET_DRV_CFG,            0x00000111},
 226         {CS35L36_NG_CFG,                        0x00000033},
 227         {CS35L36_AMP_GAIN_CTRL,                 0x00000273},
 228         {CS35L36_PWM_MOD_IO_CTRL,               0x00000000},
 229         {CS35L36_PWM_MOD_STATUS,                0x00000000},
 230         {CS35L36_DAC_MSM_CFG,                   0x00000000},
 231         {CS35L36_AMP_SLOPE_CTRL,                0x00000B00},
 232         {CS35L36_AMP_PDM_VOLUME,                0x00000000},
 233         {CS35L36_AMP_PDM_RATE_CTRL,             0x00000000},
 234         {CS35L36_PDM_CH_SEL,                    0x00000000},
 235         {CS35L36_AMP_NG_CTRL,                   0x0000212F},
 236         {CS35L36_PDM_HIGHFILT_CTRL,             0x00000000},
 237         {CS35L36_PAC_INT0_CTRL,                 0x00000001},
 238         {CS35L36_PAC_INT1_CTRL,                 0x00000001},
 239         {CS35L36_PAC_INT2_CTRL,                 0x00000001},
 240         {CS35L36_PAC_INT3_CTRL,                 0x00000001},
 241         {CS35L36_PAC_INT4_CTRL,                 0x00000001},
 242         {CS35L36_PAC_INT5_CTRL,                 0x00000001},
 243         {CS35L36_PAC_INT6_CTRL,                 0x00000001},
 244         {CS35L36_PAC_INT7_CTRL,                 0x00000001},
 245 };
 246
 247 static bool cs35l36_readable_reg(struct device *dev, unsigned int reg)
 248 {
 249         switch (reg) {
 250         case CS35L36_SW_RESET:
 251         case CS35L36_SW_REV:
 252         case CS35L36_HW_REV:
 253         case CS35L36_TESTKEY_CTRL:
 254         case CS35L36_USERKEY_CTL:
 255         case CS35L36_OTP_MEM30:
 256         case CS35L36_OTP_CTRL1:
 257         case CS35L36_OTP_CTRL2:
 258         case CS35L36_OTP_CTRL3:
 259         case CS35L36_OTP_CTRL4:
 260         case CS35L36_OTP_CTRL5:
 261         case CS35L36_PAC_CTL1:
 262         case CS35L36_PAC_CTL2:
 263         case CS35L36_PAC_CTL3:
 264         case CS35L36_DEVICE_ID:
 265         case CS35L36_FAB_ID:
 266         case CS35L36_REV_ID:
 267         case CS35L36_PWR_CTRL1:
 268         case CS35L36_PWR_CTRL2:
 269         case CS35L36_PWR_CTRL3:
 270         case CS35L36_CTRL_OVRRIDE:
 271         case CS35L36_AMP_OUT_MUTE:
 272         case CS35L36_OTP_TRIM_STATUS:
 273         case CS35L36_DISCH_FILT:
 274         case CS35L36_PROTECT_REL_ERR:
 275         case CS35L36_PAD_INTERFACE:
 276         case CS35L36_PLL_CLK_CTRL:
 277         case CS35L36_GLOBAL_CLK_CTRL:
 278         case CS35L36_ADC_CLK_CTRL:
 279         case CS35L36_SWIRE_CLK_CTRL:
 280         case CS35L36_SP_SCLK_CLK_CTRL:
 281         case CS35L36_TST_FS_MON0:
 282         case CS35L36_MDSYNC_EN:
 283         case CS35L36_MDSYNC_TX_ID:
 284         case CS35L36_MDSYNC_PWR_CTRL:
 285         case CS35L36_MDSYNC_DATA_TX:
 286         case CS35L36_MDSYNC_TX_STATUS:
 287         case CS35L36_MDSYNC_RX_STATUS:
 288         case CS35L36_MDSYNC_ERR_STATUS:
 289         case CS35L36_BSTCVRT_VCTRL1:
 290         case CS35L36_BSTCVRT_VCTRL2:
 291         case CS35L36_BSTCVRT_PEAK_CUR:
 292         case CS35L36_BSTCVRT_SFT_RAMP:
 293         case CS35L36_BSTCVRT_COEFF:
 294         case CS35L36_BSTCVRT_SLOPE_LBST:
 295         case CS35L36_BSTCVRT_SW_FREQ:
 296         case CS35L36_BSTCVRT_DCM_CTRL:
 297         case CS35L36_BSTCVRT_DCM_MODE_FORCE:
 298         case CS35L36_BSTCVRT_OVERVOLT_CTRL:
 299         case CS35L36_BST_TST_MANUAL:
 300         case CS35L36_BST_ANA2_TEST:
 301         case CS35L36_VPI_LIMIT_MODE:
 302         case CS35L36_VPI_LIMIT_MINMAX:
 303         case CS35L36_VPI_VP_THLD:
 304         case CS35L36_VPI_TRACK_CTRL:
 305         case CS35L36_VPI_TRIG_MODE_CTRL:
 306         case CS35L36_VPI_TRIG_STEPS:
 307         case CS35L36_VI_SPKMON_FILT:
 308         case CS35L36_VI_SPKMON_GAIN:
 309         case CS35L36_VI_SPKMON_IP_SEL:
 310         case CS35L36_DTEMP_WARN_THLD:
 311         case CS35L36_DTEMP_STATUS:
 312         case CS35L36_VPVBST_FS_SEL:
 313         case CS35L36_VPVBST_VP_CTRL:
 314         case CS35L36_VPVBST_VBST_CTRL:
 315         case CS35L36_ASP_TX_PIN_CTRL:
 316         case CS35L36_ASP_RATE_CTRL:
 317         case CS35L36_ASP_FORMAT:
 318         case CS35L36_ASP_FRAME_CTRL:
 319         case CS35L36_ASP_TX1_TX2_SLOT:
 320         case CS35L36_ASP_TX3_TX4_SLOT:
 321         case CS35L36_ASP_TX5_TX6_SLOT:
 322         case CS35L36_ASP_TX7_TX8_SLOT:
 323         case CS35L36_ASP_RX1_SLOT:
 324         case CS35L36_ASP_RX_TX_EN:
 325         case CS35L36_ASP_RX1_SEL:
 326         case CS35L36_ASP_TX1_SEL:
 327         case CS35L36_ASP_TX2_SEL:
 328         case CS35L36_ASP_TX3_SEL:
 329         case CS35L36_ASP_TX4_SEL:
 330         case CS35L36_ASP_TX5_SEL:
 331         case CS35L36_ASP_TX6_SEL:
 332         case CS35L36_SWIRE_P1_TX1_SEL:
 333         case CS35L36_SWIRE_P1_TX2_SEL:
 334         case CS35L36_SWIRE_P2_TX1_SEL:
 335         case CS35L36_SWIRE_P2_TX2_SEL:
 336         case CS35L36_SWIRE_P2_TX3_SEL:
 337         case CS35L36_SWIRE_DP1_FIFO_CFG:
 338         case CS35L36_SWIRE_DP2_FIFO_CFG:
 339         case CS35L36_SWIRE_DP3_FIFO_CFG:
 340         case CS35L36_SWIRE_PCM_RX_DATA:
 341         case CS35L36_SWIRE_FS_SEL:
 342         case CS35L36_AMP_DIG_VOL_CTRL:
 343         case CS35L36_VPBR_CFG:
 344         case CS35L36_VBBR_CFG:
 345         case CS35L36_VPBR_STATUS:
 346         case CS35L36_VBBR_STATUS:
 347         case CS35L36_OVERTEMP_CFG:
 348         case CS35L36_AMP_ERR_VOL:
 349         case CS35L36_CLASSH_CFG:
 350         case CS35L36_CLASSH_FET_DRV_CFG:
 351         case CS35L36_NG_CFG:
 352         case CS35L36_AMP_GAIN_CTRL:
 353         case CS35L36_PWM_MOD_IO_CTRL:
 354         case CS35L36_PWM_MOD_STATUS:
 355         case CS35L36_DAC_MSM_CFG:
 356         case CS35L36_AMP_SLOPE_CTRL:
 357         case CS35L36_AMP_PDM_VOLUME:
 358         case CS35L36_AMP_PDM_RATE_CTRL:
 359         case CS35L36_PDM_CH_SEL:
 360         case CS35L36_AMP_NG_CTRL:
 361         case CS35L36_PDM_HIGHFILT_CTRL:
 362         case CS35L36_INT1_STATUS:
 363         case CS35L36_INT2_STATUS:
 364         case CS35L36_INT3_STATUS:
 365         case CS35L36_INT4_STATUS:
 366         case CS35L36_INT1_RAW_STATUS:
 367         case CS35L36_INT2_RAW_STATUS:
 368         case CS35L36_INT3_RAW_STATUS:
 369         case CS35L36_INT4_RAW_STATUS:
 370         case CS35L36_INT1_MASK:
 371         case CS35L36_INT2_MASK:
 372         case CS35L36_INT3_MASK:
 373         case CS35L36_INT4_MASK:
 374         case CS35L36_INT1_EDGE_LVL_CTRL:
 375         case CS35L36_INT3_EDGE_LVL_CTRL:
 376         case CS35L36_PAC_INT_STATUS:
 377         case CS35L36_PAC_INT_RAW_STATUS:
 378         case CS35L36_PAC_INT_FLUSH_CTRL:
 379         case CS35L36_PAC_INT0_CTRL:
 380         case CS35L36_PAC_INT1_CTRL:
 381         case CS35L36_PAC_INT2_CTRL:
 382         case CS35L36_PAC_INT3_CTRL:
 383         case CS35L36_PAC_INT4_CTRL:
 384         case CS35L36_PAC_INT5_CTRL:
 385         case CS35L36_PAC_INT6_CTRL:
 386         case CS35L36_PAC_INT7_CTRL:
 387                 return true;
 388         default:
 389                 if (reg >= CS35L36_PAC_PMEM_WORD0 &&
 390                         reg <= CS35L36_PAC_PMEM_WORD1023)
 391                         return true;
 392                 else
 393                         return false;
 394         }
 395 }
 396
 397 static bool cs35l36_precious_reg(struct device *dev, unsigned int reg)
 398 {
 399         switch (reg) {
 400         case CS35L36_TESTKEY_CTRL:
 401         case CS35L36_USERKEY_CTL:
 402         case CS35L36_TST_FS_MON0:
 403                 return true;
 404         default:
 405                 return false;
 406         }
 407 }
 408
 409 static bool cs35l36_volatile_reg(struct device *dev, unsigned int reg)
 410 {
 411         switch (reg) {
 412         case CS35L36_SW_RESET:
 413         case CS35L36_SW_REV:
 414         case CS35L36_HW_REV:
 415         case CS35L36_TESTKEY_CTRL:
 416         case CS35L36_USERKEY_CTL:
 417         case CS35L36_DEVICE_ID:
 418         case CS35L36_FAB_ID:
 419         case CS35L36_REV_ID:
 420         case CS35L36_INT1_STATUS:
 421         case CS35L36_INT2_STATUS:
 422         case CS35L36_INT3_STATUS:
 423         case CS35L36_INT4_STATUS:
 424         case CS35L36_INT1_RAW_STATUS:
 425         case CS35L36_INT2_RAW_STATUS:
 426         case CS35L36_INT3_RAW_STATUS:
 427         case CS35L36_INT4_RAW_STATUS:
 428         case CS35L36_INT1_MASK:
 429         case CS35L36_INT2_MASK:
 430         case CS35L36_INT3_MASK:
 431         case CS35L36_INT4_MASK:
 432         case CS35L36_INT1_EDGE_LVL_CTRL:
 433         case CS35L36_INT3_EDGE_LVL_CTRL:
 434         case CS35L36_PAC_INT_STATUS:
 435         case CS35L36_PAC_INT_RAW_STATUS:
 436         case CS35L36_PAC_INT_FLUSH_CTRL:
 437                 return true;
 438         default:
 439                 if (reg >= CS35L36_PAC_PMEM_WORD0 &&
 440                         reg <= CS35L36_PAC_PMEM_WORD1023)
 441                         return true;
 442                 else
 443                         return false;
 444         }
 445 }
 446
 447 static const DECLARE_TLV_DB_RANGE(dig_vol_tlv, 0, 912,
 448                                   TLV_DB_MINMAX_ITEM(-10200, 1200));
 449 static DECLARE_TLV_DB_SCALE(amp_gain_tlv, 0, 1, 1);
 450
 451 static const char * const cs35l36_pcm_sftramp_text[] =  {
 452         "Off", ".5ms", "1ms", "2ms", "4ms", "8ms", "15ms", "30ms"};
 453
 454 static SOC_ENUM_SINGLE_DECL(pcm_sft_ramp, CS35L36_AMP_DIG_VOL_CTRL, 0,
 455                             cs35l36_pcm_sftramp_text);
 456
 457 static int cs35l36_ldm_sel_get(struct snd_kcontrol *kcontrol,
 458                                struct snd_ctl_elem_value *ucontrol)
 459 {
 460         struct snd_soc_component *component =
 461                         snd_soc_kcontrol_component(kcontrol);
 462         struct cs35l36_private *cs35l36 =
 463                         snd_soc_component_get_drvdata(component);
 464
 465         ucontrol->value.integer.value[0] = cs35l36->ldm_mode_sel;
 466
 467         return 0;
 468 }
 469
 470 static int cs35l36_ldm_sel_put(struct snd_kcontrol *kcontrol,
 471                                struct snd_ctl_elem_value *ucontrol)
 472 {
 473         struct snd_soc_component *component =
 474                         snd_soc_kcontrol_component(kcontrol);
 475         struct cs35l36_private *cs35l36 =
 476                         snd_soc_component_get_drvdata(component);
 477         int val = (ucontrol->value.integer.value[0]) ? CS35L36_NG_AMP_EN_MASK :
 478                                                        0;
 479
 480         cs35l36->ldm_mode_sel = val;
 481
 482         regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
 483                            CS35L36_NG_AMP_EN_MASK, val);
 484
 485         return 0;
 486 }
 487
 488 static const struct snd_kcontrol_new cs35l36_aud_controls[] = {
 489         SOC_SINGLE_SX_TLV("Digital PCM Volume", CS35L36_AMP_DIG_VOL_CTRL,
 490                 3, 0x4D0, 0x390, dig_vol_tlv),
 491         SOC_SINGLE_TLV("Analog PCM Volume", CS35L36_AMP_GAIN_CTRL, 5, 0x13, 0,
 492                 amp_gain_tlv),
 493         SOC_ENUM("PCM Soft Ramp", pcm_sft_ramp),
 494         SOC_SINGLE("Amp Gain Zero-Cross Switch", CS35L36_AMP_GAIN_CTRL,
 495                 CS35L36_AMP_ZC_SHIFT, 1, 0),
 496         SOC_SINGLE("PDM LDM Enter Ramp Switch", CS35L36_DAC_MSM_CFG,
 497                 CS35L36_PDM_LDM_ENTER_SHIFT, 1, 0),
 498         SOC_SINGLE("PDM LDM Exit Ramp Switch", CS35L36_DAC_MSM_CFG,
 499                 CS35L36_PDM_LDM_EXIT_SHIFT, 1, 0),
 500         SOC_SINGLE_BOOL_EXT("LDM Select Switch", 0, cs35l36_ldm_sel_get,
 501                 cs35l36_ldm_sel_put),
 502 };
 503
 504 static int cs35l36_main_amp_event(struct snd_soc_dapm_widget *w,
 505                                   struct snd_kcontrol *kcontrol, int event)
 506 {
 507         struct snd_soc_component *component =
 508                         snd_soc_dapm_to_component(w->dapm);
 509         struct cs35l36_private *cs35l36 =
 510                         snd_soc_component_get_drvdata(component);
 511         u32 reg;
 512
 513         switch (event) {
 514         case SND_SOC_DAPM_POST_PMU:
 515                 regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
 516                                    CS35L36_GLOBAL_EN_MASK,
 517                                    1 << CS35L36_GLOBAL_EN_SHIFT);
 518
 519                 usleep_range(2000, 2100);
 520
 521                 regmap_read(cs35l36->regmap, CS35L36_INT4_RAW_STATUS, &reg);
 522
 523                 if (WARN_ON_ONCE(reg & CS35L36_PLL_UNLOCK_MASK))
 524                         dev_crit(cs35l36->dev, "PLL Unlocked\n");
 525
 526                 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
 527                                    CS35L36_PCM_RX_SEL_MASK,
 528                                    CS35L36_PCM_RX_SEL_PCM);
 529                 regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
 530                                    CS35L36_AMP_MUTE_MASK,
 531                                    0 << CS35L36_AMP_MUTE_SHIFT);
 532                 break;
 533         case SND_SOC_DAPM_PRE_PMD:
 534                 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RX1_SEL,
 535                                    CS35L36_PCM_RX_SEL_MASK,
 536                                    CS35L36_PCM_RX_SEL_ZERO);
 537                 regmap_update_bits(cs35l36->regmap, CS35L36_AMP_OUT_MUTE,
 538                                    CS35L36_AMP_MUTE_MASK,
 539                                    1 << CS35L36_AMP_MUTE_SHIFT);
 540                 break;
 541         case SND_SOC_DAPM_POST_PMD:
 542                 regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL1,
 543                                    CS35L36_GLOBAL_EN_MASK,
 544                                    0 << CS35L36_GLOBAL_EN_SHIFT);
 545
 546                 usleep_range(2000, 2100);
 547                 break;
 548         default:
 549                 dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
 550                 return -EINVAL;
 551         }
 552
 553         return 0;
 554 }
 555
 556 static int cs35l36_boost_event(struct snd_soc_dapm_widget *w,
 557                                struct snd_kcontrol *kcontrol, int event)
 558 {
 559         struct snd_soc_component *component =
 560                         snd_soc_dapm_to_component(w->dapm);
 561         struct cs35l36_private *cs35l36 =
 562                         snd_soc_component_get_drvdata(component);
 563
 564         switch (event) {
 565         case SND_SOC_DAPM_POST_PMU:
 566                 if (!cs35l36->pdata.extern_boost)
 567                         regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
 568                                            CS35L36_BST_EN_MASK,
 569                                            CS35L36_BST_EN <<
 570                                            CS35L36_BST_EN_SHIFT);
 571                 break;
 572         case SND_SOC_DAPM_POST_PMD:
 573                 if (!cs35l36->pdata.extern_boost)
 574                         regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL2,
 575                                            CS35L36_BST_EN_MASK,
 576                                            CS35L36_BST_DIS_VP <<
 577                                            CS35L36_BST_EN_SHIFT);
 578                 break;
 579         default:
 580                 dev_dbg(component->dev, "Invalid event = 0x%x\n", event);
 581                 return -EINVAL;
 582         }
 583
 584         return 0;
 585 }
 586
 587 static const char * const cs35l36_chan_text[] = {
 588         "RX1",
 589         "RX2",
 590 };
 591
 592 static SOC_ENUM_SINGLE_DECL(chansel_enum, CS35L36_ASP_RX1_SLOT, 0,
 593                             cs35l36_chan_text);
 594
 595 static const struct snd_kcontrol_new cs35l36_chan_mux =
 596                 SOC_DAPM_ENUM("Input Mux", chansel_enum);
 597
 598 static const struct snd_kcontrol_new amp_enable_ctrl =
 599                 SOC_DAPM_SINGLE_AUTODISABLE("Switch", CS35L36_AMP_OUT_MUTE,
 600                                             CS35L36_AMP_MUTE_SHIFT, 1, 1);
 601
 602 static const struct snd_kcontrol_new boost_ctrl =
 603                 SOC_DAPM_SINGLE_VIRT("Switch", 1);
 604
 605 static const char * const asp_tx_src_text[] = {
 606         "Zero Fill", "ASPRX1", "VMON", "IMON", "ERRVOL", "VPMON", "VBSTMON"
 607 };
 608
 609 static const unsigned int asp_tx_src_values[] = {
 610         0x00, 0x08, 0x18, 0x19, 0x20, 0x28, 0x29
 611 };
 612
 613 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx1_src_enum, CS35L36_ASP_TX1_SEL, 0,
 614                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
 615                                   asp_tx_src_values);
 616
 617 static const struct snd_kcontrol_new asp_tx1_src =
 618                 SOC_DAPM_ENUM("ASPTX1SRC", asp_tx1_src_enum);
 619
 620 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx2_src_enum, CS35L36_ASP_TX2_SEL, 0,
 621                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
 622                                   asp_tx_src_values);
 623
 624 static const struct snd_kcontrol_new asp_tx2_src =
 625                 SOC_DAPM_ENUM("ASPTX2SRC", asp_tx2_src_enum);
 626
 627 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx3_src_enum, CS35L36_ASP_TX3_SEL, 0,
 628                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
 629                                   asp_tx_src_values);
 630
 631 static const struct snd_kcontrol_new asp_tx3_src =
 632                 SOC_DAPM_ENUM("ASPTX3SRC", asp_tx3_src_enum);
 633
 634 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx4_src_enum, CS35L36_ASP_TX4_SEL, 0,
 635                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
 636                                   asp_tx_src_values);
 637
 638 static const struct snd_kcontrol_new asp_tx4_src =
 639                 SOC_DAPM_ENUM("ASPTX4SRC", asp_tx4_src_enum);
 640
 641 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx5_src_enum, CS35L36_ASP_TX5_SEL, 0,
 642                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
 643                                   asp_tx_src_values);
 644
 645 static const struct snd_kcontrol_new asp_tx5_src =
 646                 SOC_DAPM_ENUM("ASPTX5SRC", asp_tx5_src_enum);
 647
 648 static SOC_VALUE_ENUM_SINGLE_DECL(asp_tx6_src_enum, CS35L36_ASP_TX6_SEL, 0,
 649                                   CS35L36_APS_TX_SEL_MASK, asp_tx_src_text,
 650                                   asp_tx_src_values);
 651
 652 static const struct snd_kcontrol_new asp_tx6_src =
 653                 SOC_DAPM_ENUM("ASPTX6SRC", asp_tx6_src_enum);
 654
 655 static const struct snd_soc_dapm_widget cs35l36_dapm_widgets[] = {
 656         SND_SOC_DAPM_MUX("Channel Mux", SND_SOC_NOPM, 0, 0, &cs35l36_chan_mux),
 657         SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS35L36_ASP_RX_TX_EN, 16, 0),
 658
 659         SND_SOC_DAPM_OUT_DRV_E("Main AMP", CS35L36_PWR_CTRL2, 0, 0, NULL, 0,
 660                                cs35l36_main_amp_event, SND_SOC_DAPM_POST_PMD |
 661                                SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 662
 663         SND_SOC_DAPM_OUTPUT("SPK"),
 664         SND_SOC_DAPM_SWITCH("AMP Enable", SND_SOC_NOPM, 0, 1, &amp_enable_ctrl),
 665         SND_SOC_DAPM_MIXER("CLASS H", CS35L36_PWR_CTRL3, 4, 0, NULL, 0),
 666         SND_SOC_DAPM_SWITCH_E("BOOST Enable", SND_SOC_NOPM, 0, 0, &boost_ctrl,
 667                               cs35l36_boost_event, SND_SOC_DAPM_POST_PMD |
 668                               SND_SOC_DAPM_POST_PMU),
 669
 670         SND_SOC_DAPM_AIF_OUT("ASPTX1", NULL, 0, CS35L36_ASP_RX_TX_EN, 0, 0),
 671         SND_SOC_DAPM_AIF_OUT("ASPTX2", NULL, 1, CS35L36_ASP_RX_TX_EN, 1, 0),
 672         SND_SOC_DAPM_AIF_OUT("ASPTX3", NULL, 2, CS35L36_ASP_RX_TX_EN, 2, 0),
 673         SND_SOC_DAPM_AIF_OUT("ASPTX4", NULL, 3, CS35L36_ASP_RX_TX_EN, 3, 0),
 674         SND_SOC_DAPM_AIF_OUT("ASPTX5", NULL, 4, CS35L36_ASP_RX_TX_EN, 4, 0),
 675         SND_SOC_DAPM_AIF_OUT("ASPTX6", NULL, 5, CS35L36_ASP_RX_TX_EN, 5, 0),
 676
 677         SND_SOC_DAPM_MUX("ASPTX1SRC", SND_SOC_NOPM, 0, 0, &asp_tx1_src),
 678         SND_SOC_DAPM_MUX("ASPTX2SRC", SND_SOC_NOPM, 0, 0, &asp_tx2_src),
 679         SND_SOC_DAPM_MUX("ASPTX3SRC", SND_SOC_NOPM, 0, 0, &asp_tx3_src),
 680         SND_SOC_DAPM_MUX("ASPTX4SRC", SND_SOC_NOPM, 0, 0, &asp_tx4_src),
 681         SND_SOC_DAPM_MUX("ASPTX5SRC", SND_SOC_NOPM, 0, 0, &asp_tx5_src),
 682         SND_SOC_DAPM_MUX("ASPTX6SRC", SND_SOC_NOPM, 0, 0, &asp_tx6_src),
 683
 684         SND_SOC_DAPM_ADC("VMON ADC", NULL, CS35L36_PWR_CTRL2, 12, 0),
 685         SND_SOC_DAPM_ADC("IMON ADC", NULL, CS35L36_PWR_CTRL2, 13, 0),
 686         SND_SOC_DAPM_ADC("VPMON ADC", NULL, CS35L36_PWR_CTRL2, 8, 0),
 687         SND_SOC_DAPM_ADC("VBSTMON ADC", NULL, CS35L36_PWR_CTRL2, 9, 0),
 688
 689         SND_SOC_DAPM_INPUT("VP"),
 690         SND_SOC_DAPM_INPUT("VBST"),
 691         SND_SOC_DAPM_INPUT("VSENSE"),
 692 };
 693
 694 static const struct snd_soc_dapm_route cs35l36_audio_map[] = {
 695         {"VPMON ADC", NULL, "VP"},
 696         {"VBSTMON ADC", NULL, "VBST"},
 697         {"IMON ADC", NULL, "VSENSE"},
 698         {"VMON ADC", NULL, "VSENSE"},
 699
 700         {"ASPTX1SRC", "IMON", "IMON ADC"},
 701         {"ASPTX1SRC", "VMON", "VMON ADC"},
 702         {"ASPTX1SRC", "VBSTMON", "VBSTMON ADC"},
 703         {"ASPTX1SRC", "VPMON", "VPMON ADC"},
 704
 705         {"ASPTX2SRC", "IMON", "IMON ADC"},
 706         {"ASPTX2SRC", "VMON", "VMON ADC"},
 707         {"ASPTX2SRC", "VBSTMON", "VBSTMON ADC"},
 708         {"ASPTX2SRC", "VPMON", "VPMON ADC"},
 709
 710         {"ASPTX3SRC", "IMON", "IMON ADC"},
 711         {"ASPTX3SRC", "VMON", "VMON ADC"},
 712         {"ASPTX3SRC", "VBSTMON", "VBSTMON ADC"},
 713         {"ASPTX3SRC", "VPMON", "VPMON ADC"},
 714
 715         {"ASPTX4SRC", "IMON", "IMON ADC"},
 716         {"ASPTX4SRC", "VMON", "VMON ADC"},
 717         {"ASPTX4SRC", "VBSTMON", "VBSTMON ADC"},
 718         {"ASPTX4SRC", "VPMON", "VPMON ADC"},
 719
 720         {"ASPTX5SRC", "IMON", "IMON ADC"},
 721         {"ASPTX5SRC", "VMON", "VMON ADC"},
 722         {"ASPTX5SRC", "VBSTMON", "VBSTMON ADC"},
 723         {"ASPTX5SRC", "VPMON", "VPMON ADC"},
 724
 725         {"ASPTX6SRC", "IMON", "IMON ADC"},
 726         {"ASPTX6SRC", "VMON", "VMON ADC"},
 727         {"ASPTX6SRC", "VBSTMON", "VBSTMON ADC"},
 728         {"ASPTX6SRC", "VPMON", "VPMON ADC"},
 729
 730         {"ASPTX1", NULL, "ASPTX1SRC"},
 731         {"ASPTX2", NULL, "ASPTX2SRC"},
 732         {"ASPTX3", NULL, "ASPTX3SRC"},
 733         {"ASPTX4", NULL, "ASPTX4SRC"},
 734         {"ASPTX5", NULL, "ASPTX5SRC"},
 735         {"ASPTX6", NULL, "ASPTX6SRC"},
 736
 737         {"AMP Capture", NULL, "ASPTX1"},
 738         {"AMP Capture", NULL, "ASPTX2"},
 739         {"AMP Capture", NULL, "ASPTX3"},
 740         {"AMP Capture", NULL, "ASPTX4"},
 741         {"AMP Capture", NULL, "ASPTX5"},
 742         {"AMP Capture", NULL, "ASPTX6"},
 743
 744         {"AMP Enable", "Switch", "AMP Playback"},
 745         {"SDIN", NULL, "AMP Enable"},
 746         {"Channel Mux", "RX1", "SDIN"},
 747         {"Channel Mux", "RX2", "SDIN"},
 748         {"BOOST Enable", "Switch", "Channel Mux"},
 749         {"CLASS H", NULL, "BOOST Enable"},
 750         {"Main AMP", NULL, "Channel Mux"},
 751         {"Main AMP", NULL, "CLASS H"},
 752         {"SPK", NULL, "Main AMP"},
 753 };
 754
 755 static int cs35l36_set_dai_fmt(struct snd_soc_dai *component_dai,
 756                                unsigned int fmt)
 757 {
 758         struct cs35l36_private *cs35l36 =
 759                         snd_soc_component_get_drvdata(component_dai->component);
 760         unsigned int asp_fmt, lrclk_fmt, sclk_fmt, clock_provider, clk_frc;
 761
 762         switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
 763         case SND_SOC_DAIFMT_CBP_CFP:
 764                 clock_provider = 1;
 765                 break;
 766         case SND_SOC_DAIFMT_CBC_CFC:
 767                 clock_provider = 0;
 768                 break;
 769         default:
 770                 return -EINVAL;
 771         }
 772
 773         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
 774                                 CS35L36_SCLK_MSTR_MASK,
 775                                 clock_provider << CS35L36_SCLK_MSTR_SHIFT);
 776         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
 777                                 CS35L36_LRCLK_MSTR_MASK,
 778                                 clock_provider << CS35L36_LRCLK_MSTR_SHIFT);
 779
 780         switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
 781         case SND_SOC_DAIFMT_CONT:
 782                 clk_frc = 1;
 783                 break;
 784         case SND_SOC_DAIFMT_GATED:
 785                 clk_frc = 0;
 786                 break;
 787         default:
 788                 return -EINVAL;
 789         }
 790
 791         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
 792                            CS35L36_SCLK_FRC_MASK, clk_frc <<
 793                            CS35L36_SCLK_FRC_SHIFT);
 794         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
 795                            CS35L36_LRCLK_FRC_MASK, clk_frc <<
 796                            CS35L36_LRCLK_FRC_SHIFT);
 797
 798         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 799         case SND_SOC_DAIFMT_DSP_A:
 800                 asp_fmt = 0;
 801                 break;
 802         case SND_SOC_DAIFMT_I2S:
 803                 asp_fmt = 2;
 804                 break;
 805         default:
 806                 return -EINVAL;
 807         }
 808
 809         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 810         case SND_SOC_DAIFMT_NB_IF:
 811                 lrclk_fmt = 1;
 812                 sclk_fmt = 0;
 813                 break;
 814         case SND_SOC_DAIFMT_IB_NF:
 815                 lrclk_fmt = 0;
 816                 sclk_fmt = 1;
 817                 break;
 818         case SND_SOC_DAIFMT_IB_IF:
 819                 lrclk_fmt = 1;
 820                 sclk_fmt = 1;
 821                 break;
 822         case SND_SOC_DAIFMT_NB_NF:
 823                 lrclk_fmt = 0;
 824                 sclk_fmt = 0;
 825                 break;
 826         default:
 827                 return -EINVAL;
 828         }
 829
 830         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_RATE_CTRL,
 831                            CS35L36_LRCLK_INV_MASK,
 832                            lrclk_fmt << CS35L36_LRCLK_INV_SHIFT);
 833         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
 834                            CS35L36_SCLK_INV_MASK,
 835                            sclk_fmt << CS35L36_SCLK_INV_SHIFT);
 836         regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FORMAT,
 837                            CS35L36_ASP_FMT_MASK, asp_fmt);
 838
 839         return 0;
 840 }
 841
 842 struct cs35l36_global_fs_config {
 843         int rate;
 844         int fs_cfg;
 845 };
 846
 847 static const struct cs35l36_global_fs_config cs35l36_fs_rates[] = {
 848         {12000, 0x01},
 849         {24000, 0x02},
 850         {48000, 0x03},
 851         {96000, 0x04},
 852         {192000, 0x05},
 853         {384000, 0x06},
 854         {11025, 0x09},
 855         {22050, 0x0A},
 856         {44100, 0x0B},
 857         {88200, 0x0C},
 858         {176400, 0x0D},
 859         {8000, 0x11},
 860         {16000, 0x12},
 861         {32000, 0x13},
 862 };
 863
 864 static int cs35l36_pcm_hw_params(struct snd_pcm_substream *substream,
 865                                  struct snd_pcm_hw_params *params,
 866                                  struct snd_soc_dai *dai)
 867 {
 868         struct cs35l36_private *cs35l36 =
 869                         snd_soc_component_get_drvdata(dai->component);
 870         unsigned int asp_width, global_fs = params_rate(params);
 871         int i;
 872
 873         for (i = 0; i < ARRAY_SIZE(cs35l36_fs_rates); i++) {
 874                 if (global_fs == cs35l36_fs_rates[i].rate)
 875                         regmap_update_bits(cs35l36->regmap,
 876                                            CS35L36_GLOBAL_CLK_CTRL,
 877                                            CS35L36_GLOBAL_FS_MASK,
 878                                            cs35l36_fs_rates[i].fs_cfg <<
 879                                            CS35L36_GLOBAL_FS_SHIFT);
 880         }
 881
 882         switch (params_width(params)) {
 883         case 16:
 884                 asp_width = CS35L36_ASP_WIDTH_16;
 885                 break;
 886         case 24:
 887                 asp_width = CS35L36_ASP_WIDTH_24;
 888                 break;
 889         case 32:
 890                 asp_width = CS35L36_ASP_WIDTH_32;
 891                 break;
 892         default:
 893                 return -EINVAL;
 894         }
 895
 896         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 897                 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
 898                                    CS35L36_ASP_RX_WIDTH_MASK,
 899                                    asp_width << CS35L36_ASP_RX_WIDTH_SHIFT);
 900         } else {
 901                 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_FRAME_CTRL,
 902                                    CS35L36_ASP_TX_WIDTH_MASK,
 903                                    asp_width << CS35L36_ASP_TX_WIDTH_SHIFT);
 904         }
 905
 906         return 0;
 907 }
 908
 909 static int cs35l36_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 910                                   unsigned int freq, int dir)
 911 {
 912         struct snd_soc_component *component = dai->component;
 913         struct cs35l36_private *cs35l36 =
 914                         snd_soc_component_get_drvdata(component);
 915         int fs1, fs2;
 916
 917         if (freq > CS35L36_FS_NOM_6MHZ) {
 918                 fs1 = CS35L36_FS1_DEFAULT_VAL;
 919                 fs2 = CS35L36_FS2_DEFAULT_VAL;
 920         } else {
 921                 fs1 = 3 * ((CS35L36_FS_NOM_6MHZ * 4 + freq - 1) / freq) + 4;
 922                 fs2 = 5 * ((CS35L36_FS_NOM_6MHZ * 4 + freq - 1) / freq) + 4;
 923         }
 924
 925         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
 926                         CS35L36_TEST_UNLOCK1);
 927         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
 928                         CS35L36_TEST_UNLOCK2);
 929
 930         regmap_update_bits(cs35l36->regmap, CS35L36_TST_FS_MON0,
 931                            CS35L36_FS1_WINDOW_MASK | CS35L36_FS2_WINDOW_MASK,
 932                            fs1 | (fs2 << CS35L36_FS2_WINDOW_SHIFT));
 933
 934         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
 935                         CS35L36_TEST_LOCK1);
 936         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
 937                         CS35L36_TEST_LOCK2);
 938         return 0;
 939 }
 940
 941 static const struct cs35l36_pll_config *cs35l36_get_clk_config(
 942                 struct cs35l36_private *cs35l36, int freq)
 943 {
 944         int i;
 945
 946         for (i = 0; i < ARRAY_SIZE(cs35l36_pll_sysclk); i++) {
 947                 if (cs35l36_pll_sysclk[i].freq == freq)
 948                         return &cs35l36_pll_sysclk[i];
 949         }
 950
 951         return NULL;
 952 }
 953
 954 static const unsigned int cs35l36_src_rates[] = {
 955         8000, 12000, 11025, 16000, 22050, 24000, 32000,
 956         44100, 48000, 88200, 96000, 176400, 192000, 384000
 957 };
 958
 959 static const struct snd_pcm_hw_constraint_list cs35l36_constraints = {
 960         .count  = ARRAY_SIZE(cs35l36_src_rates),
 961         .list   = cs35l36_src_rates,
 962 };
 963
 964 static int cs35l36_pcm_startup(struct snd_pcm_substream *substream,
 965                                struct snd_soc_dai *dai)
 966 {
 967         snd_pcm_hw_constraint_list(substream->runtime, 0,
 968                                 SNDRV_PCM_HW_PARAM_RATE, &cs35l36_constraints);
 969
 970         return 0;
 971 }
 972
 973 static const struct snd_soc_dai_ops cs35l36_ops = {
 974         .startup = cs35l36_pcm_startup,
 975         .set_fmt = cs35l36_set_dai_fmt,
 976         .hw_params = cs35l36_pcm_hw_params,
 977         .set_sysclk = cs35l36_dai_set_sysclk,
 978 };
 979
 980 static struct snd_soc_dai_driver cs35l36_dai[] = {
 981         {
 982                 .name = "cs35l36-pcm",
 983                 .id = 0,
 984                 .playback = {
 985                         .stream_name = "AMP Playback",
 986                         .channels_min = 1,
 987                         .channels_max = 8,
 988                         .rates = SNDRV_PCM_RATE_KNOT,
 989                         .formats = CS35L36_RX_FORMATS,
 990                 },
 991                 .capture = {
 992                         .stream_name = "AMP Capture",
 993                         .channels_min = 1,
 994                         .channels_max = 8,
 995                         .rates = SNDRV_PCM_RATE_KNOT,
 996                         .formats = CS35L36_TX_FORMATS,
 997                 },
 998                 .ops = &cs35l36_ops,
 999                 .symmetric_rate = 1,
1000         },
1001 };
1002
1003 static int cs35l36_component_set_sysclk(struct snd_soc_component *component,
1004                                 int clk_id, int source, unsigned int freq,
1005                                 int dir)
1006 {
1007         struct cs35l36_private *cs35l36 =
1008                         snd_soc_component_get_drvdata(component);
1009         const struct cs35l36_pll_config *clk_cfg;
1010         int prev_clksrc;
1011         bool pdm_switch;
1012
1013         prev_clksrc = cs35l36->clksrc;
1014
1015         switch (clk_id) {
1016         case 0:
1017                 cs35l36->clksrc = CS35L36_PLLSRC_SCLK;
1018                 break;
1019         case 1:
1020                 cs35l36->clksrc = CS35L36_PLLSRC_LRCLK;
1021                 break;
1022         case 2:
1023                 cs35l36->clksrc = CS35L36_PLLSRC_PDMCLK;
1024                 break;
1025         case 3:
1026                 cs35l36->clksrc = CS35L36_PLLSRC_SELF;
1027                 break;
1028         case 4:
1029                 cs35l36->clksrc = CS35L36_PLLSRC_MCLK;
1030                 break;
1031         default:
1032                 return -EINVAL;
1033         }
1034
1035         clk_cfg = cs35l36_get_clk_config(cs35l36, freq);
1036         if (clk_cfg == NULL) {
1037                 dev_err(component->dev, "Invalid CLK Config Freq: %d\n", freq);
1038                 return -EINVAL;
1039         }
1040
1041         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1042                            CS35L36_PLL_OPENLOOP_MASK,
1043                            1 << CS35L36_PLL_OPENLOOP_SHIFT);
1044         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1045                            CS35L36_REFCLK_FREQ_MASK,
1046                            clk_cfg->clk_cfg << CS35L36_REFCLK_FREQ_SHIFT);
1047         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1048                            CS35L36_PLL_REFCLK_EN_MASK,
1049                            0 << CS35L36_PLL_REFCLK_EN_SHIFT);
1050         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1051                            CS35L36_PLL_CLK_SEL_MASK,
1052                            cs35l36->clksrc);
1053         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1054                            CS35L36_PLL_OPENLOOP_MASK,
1055                            0 << CS35L36_PLL_OPENLOOP_SHIFT);
1056         regmap_update_bits(cs35l36->regmap, CS35L36_PLL_CLK_CTRL,
1057                            CS35L36_PLL_REFCLK_EN_MASK,
1058                            1 << CS35L36_PLL_REFCLK_EN_SHIFT);
1059
1060         if (cs35l36->rev_id == CS35L36_REV_A0) {
1061                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1062                              CS35L36_TEST_UNLOCK1);
1063                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1064                              CS35L36_TEST_UNLOCK2);
1065
1066                 regmap_write(cs35l36->regmap, CS35L36_DCO_CTRL, 0x00036DA8);
1067                 regmap_write(cs35l36->regmap, CS35L36_MISC_CTRL, 0x0100EE0E);
1068
1069                 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
1070                                    CS35L36_PLL_IGAIN_MASK,
1071                                    CS35L36_PLL_IGAIN <<
1072                                    CS35L36_PLL_IGAIN_SHIFT);
1073                 regmap_update_bits(cs35l36->regmap, CS35L36_PLL_LOOP_PARAMS,
1074                                    CS35L36_PLL_FFL_IGAIN_MASK,
1075                                    clk_cfg->fll_igain);
1076
1077                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1078                              CS35L36_TEST_LOCK1);
1079                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1080                              CS35L36_TEST_LOCK2);
1081         }
1082
1083         if (cs35l36->clksrc == CS35L36_PLLSRC_PDMCLK) {
1084                 pdm_switch = cs35l36->ldm_mode_sel &&
1085                              (prev_clksrc != CS35L36_PLLSRC_PDMCLK);
1086
1087                 if (pdm_switch)
1088                         regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1089                                            CS35L36_NG_DELAY_MASK,
1090                                            0 << CS35L36_NG_DELAY_SHIFT);
1091
1092                 regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
1093                                    CS35L36_PDM_MODE_MASK,
1094                                    1 << CS35L36_PDM_MODE_SHIFT);
1095
1096                 if (pdm_switch)
1097                         regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1098                                            CS35L36_NG_DELAY_MASK,
1099                                            3 << CS35L36_NG_DELAY_SHIFT);
1100         } else {
1101                 pdm_switch = cs35l36->ldm_mode_sel &&
1102                              (prev_clksrc == CS35L36_PLLSRC_PDMCLK);
1103
1104                 if (pdm_switch)
1105                         regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1106                                            CS35L36_NG_DELAY_MASK,
1107                                            0 << CS35L36_NG_DELAY_SHIFT);
1108
1109                 regmap_update_bits(cs35l36->regmap, CS35L36_DAC_MSM_CFG,
1110                                    CS35L36_PDM_MODE_MASK,
1111                                    0 << CS35L36_PDM_MODE_SHIFT);
1112
1113                 if (pdm_switch)
1114                         regmap_update_bits(cs35l36->regmap, CS35L36_NG_CFG,
1115                                            CS35L36_NG_DELAY_MASK,
1116                                            3 << CS35L36_NG_DELAY_SHIFT);
1117         }
1118
1119         return 0;
1120 }
1121
1122 static int cs35l36_boost_inductor(struct cs35l36_private *cs35l36, int inductor)
1123 {
1124         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
1125                            CS35L36_BSTCVRT_K1_MASK, 0x3C);
1126         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_COEFF,
1127                            CS35L36_BSTCVRT_K2_MASK,
1128                            0x3C << CS35L36_BSTCVRT_K2_SHIFT);
1129         regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SW_FREQ,
1130                            CS35L36_BSTCVRT_CCMFREQ_MASK, 0x00);
1131
1132         switch (inductor) {
1133         case 1000: /* 1 uH */
1134                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1135                                    CS35L36_BSTCVRT_SLOPE_MASK,
1136                                    0x75 << CS35L36_BSTCVRT_SLOPE_SHIFT);
1137                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1138                                    CS35L36_BSTCVRT_LBSTVAL_MASK, 0x00);
1139                 break;
1140         case 1200: /* 1.2 uH */
1141                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1142                                    CS35L36_BSTCVRT_SLOPE_MASK,
1143                                    0x6B << CS35L36_BSTCVRT_SLOPE_SHIFT);
1144                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_SLOPE_LBST,
1145                                    CS35L36_BSTCVRT_LBSTVAL_MASK, 0x01);
1146                 break;
1147         default:
1148                 dev_err(cs35l36->dev, "%s Invalid Inductor Value %d uH\n",
1149                         __func__, inductor);
1150                 return -EINVAL;
1151         }
1152
1153         return 0;
1154 }
1155
1156 static int cs35l36_component_probe(struct snd_soc_component *component)
1157 {
1158         struct cs35l36_private *cs35l36 =
1159                         snd_soc_component_get_drvdata(component);
1160         int ret;
1161
1162         if ((cs35l36->rev_id == CS35L36_REV_A0) && cs35l36->pdata.dcm_mode) {
1163                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_DCM_CTRL,
1164                                    CS35L36_DCM_AUTO_MASK,
1165                                    CS35L36_DCM_AUTO_MASK);
1166
1167                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1168                              CS35L36_TEST_UNLOCK1);
1169                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1170                              CS35L36_TEST_UNLOCK2);
1171
1172                 regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
1173                                    CS35L36_BST_MAN_IPKCOMP_MASK,
1174                                    0 << CS35L36_BST_MAN_IPKCOMP_SHIFT);
1175                 regmap_update_bits(cs35l36->regmap, CS35L36_BST_TST_MANUAL,
1176                                    CS35L36_BST_MAN_IPKCOMP_EN_MASK,
1177                                    CS35L36_BST_MAN_IPKCOMP_EN_MASK);
1178
1179                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1180                                 CS35L36_TEST_LOCK1);
1181                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1182                                 CS35L36_TEST_LOCK2);
1183         }
1184
1185         if (cs35l36->pdata.amp_pcm_inv)
1186                 regmap_update_bits(cs35l36->regmap, CS35L36_AMP_DIG_VOL_CTRL,
1187                                    CS35L36_AMP_PCM_INV_MASK,
1188                                    CS35L36_AMP_PCM_INV_MASK);
1189
1190         if (cs35l36->pdata.multi_amp_mode)
1191                 regmap_update_bits(cs35l36->regmap, CS35L36_ASP_TX_PIN_CTRL,
1192                                    CS35L36_ASP_TX_HIZ_MASK,
1193                                    CS35L36_ASP_TX_HIZ_MASK);
1194
1195         if (cs35l36->pdata.imon_pol_inv)
1196                 regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
1197                                    CS35L36_IMON_POL_MASK, 0);
1198
1199         if (cs35l36->pdata.vmon_pol_inv)
1200                 regmap_update_bits(cs35l36->regmap, CS35L36_VI_SPKMON_FILT,
1201                                    CS35L36_VMON_POL_MASK, 0);
1202
1203         if (cs35l36->pdata.bst_vctl)
1204                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
1205                                    CS35L35_BSTCVRT_CTL_MASK,
1206                                    cs35l36->pdata.bst_vctl);
1207
1208         if (cs35l36->pdata.bst_vctl_sel)
1209                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
1210                                    CS35L35_BSTCVRT_CTL_SEL_MASK,
1211                                    cs35l36->pdata.bst_vctl_sel);
1212
1213         if (cs35l36->pdata.bst_ipk)
1214                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_PEAK_CUR,
1215                                    CS35L36_BST_IPK_MASK,
1216                                    cs35l36->pdata.bst_ipk);
1217
1218         if (cs35l36->pdata.boost_ind) {
1219                 ret = cs35l36_boost_inductor(cs35l36, cs35l36->pdata.boost_ind);
1220                 if (ret < 0) {
1221                         dev_err(cs35l36->dev,
1222                                 "Boost inductor config failed(%d)\n", ret);
1223                         return ret;
1224                 }
1225         }
1226
1227         if (cs35l36->pdata.temp_warn_thld)
1228                 regmap_update_bits(cs35l36->regmap, CS35L36_DTEMP_WARN_THLD,
1229                                    CS35L36_TEMP_THLD_MASK,
1230                                    cs35l36->pdata.temp_warn_thld);
1231
1232         if (cs35l36->pdata.irq_drv_sel)
1233                 regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1234                                    CS35L36_INT_DRV_SEL_MASK,
1235                                    cs35l36->pdata.irq_drv_sel <<
1236                                    CS35L36_INT_DRV_SEL_SHIFT);
1237
1238         if (cs35l36->pdata.irq_gpio_sel)
1239                 regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1240                                    CS35L36_INT_GPIO_SEL_MASK,
1241                                    cs35l36->pdata.irq_gpio_sel <<
1242                                    CS35L36_INT_GPIO_SEL_SHIFT);
1243
1244         /*
1245          * Rev B0 has 2 versions
1246          * L36 is 10V
1247          * L37 is 12V
1248          * If L36 we need to clamp some values for safety
1249          * after probe has setup dt values. We want to make
1250          * sure we dont miss any values set in probe
1251          */
1252         if (cs35l36->chip_version == CS35L36_10V_L36) {
1253                 regmap_update_bits(cs35l36->regmap,
1254                                    CS35L36_BSTCVRT_OVERVOLT_CTRL,
1255                                    CS35L36_BST_OVP_THLD_MASK,
1256                                    CS35L36_BST_OVP_THLD_11V);
1257
1258                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1259                              CS35L36_TEST_UNLOCK1);
1260                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1261                              CS35L36_TEST_UNLOCK2);
1262
1263                 regmap_update_bits(cs35l36->regmap, CS35L36_BST_ANA2_TEST,
1264                                    CS35L36_BST_OVP_TRIM_MASK,
1265                                    CS35L36_BST_OVP_TRIM_11V <<
1266                                    CS35L36_BST_OVP_TRIM_SHIFT);
1267                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL2,
1268                                    CS35L36_BST_CTRL_LIM_MASK,
1269                                    1 << CS35L36_BST_CTRL_LIM_SHIFT);
1270                 regmap_update_bits(cs35l36->regmap, CS35L36_BSTCVRT_VCTRL1,
1271                                    CS35L35_BSTCVRT_CTL_MASK,
1272                                    CS35L36_BST_CTRL_10V_CLAMP);
1273                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1274                              CS35L36_TEST_LOCK1);
1275                 regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1276                              CS35L36_TEST_LOCK2);
1277         }
1278
1279         /*
1280          * RevA and B require the disabling of
1281          * SYNC_GLOBAL_OVR when GLOBAL_EN = 0.
1282          * Just turn it off from default
1283          */
1284         regmap_update_bits(cs35l36->regmap, CS35L36_CTRL_OVRRIDE,
1285                            CS35L36_SYNC_GLOBAL_OVR_MASK,
1286                            0 << CS35L36_SYNC_GLOBAL_OVR_SHIFT);
1287
1288         return 0;
1289 }
1290
1291 static const struct snd_soc_component_driver soc_component_dev_cs35l36 = {
1292         .probe                  = &cs35l36_component_probe,
1293         .set_sysclk             = cs35l36_component_set_sysclk,
1294         .dapm_widgets           = cs35l36_dapm_widgets,
1295         .num_dapm_widgets       = ARRAY_SIZE(cs35l36_dapm_widgets),
1296         .dapm_routes            = cs35l36_audio_map,
1297         .num_dapm_routes        = ARRAY_SIZE(cs35l36_audio_map),
1298         .controls               = cs35l36_aud_controls,
1299         .num_controls           = ARRAY_SIZE(cs35l36_aud_controls),
1300         .idle_bias_on           = 1,
1301         .use_pmdown_time        = 1,
1302         .endianness             = 1,
1303         .non_legacy_dai_naming  = 1,
1304 };
1305
1306 static struct regmap_config cs35l36_regmap = {
1307         .reg_bits = 32,
1308         .val_bits = 32,
1309         .reg_stride = 4,
1310         .max_register = CS35L36_PAC_PMEM_WORD1023,
1311         .reg_defaults = cs35l36_reg,
1312         .num_reg_defaults = ARRAY_SIZE(cs35l36_reg),
1313         .precious_reg = cs35l36_precious_reg,
1314         .volatile_reg = cs35l36_volatile_reg,
1315         .readable_reg = cs35l36_readable_reg,
1316         .cache_type = REGCACHE_RBTREE,
1317 };
1318
1319 static irqreturn_t cs35l36_irq(int irq, void *data)
1320 {
1321         struct cs35l36_private *cs35l36 = data;
1322         unsigned int status[4];
1323         unsigned int masks[4];
1324         int ret = IRQ_NONE;
1325
1326         /* ack the irq by reading all status registers */
1327         regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_STATUS, status,
1328                          ARRAY_SIZE(status));
1329
1330         regmap_bulk_read(cs35l36->regmap, CS35L36_INT1_MASK, masks,
1331                          ARRAY_SIZE(masks));
1332
1333         /* Check to see if unmasked bits are active */
1334         if (!(status[0] & ~masks[0]) && !(status[1] & ~masks[1]) &&
1335                 !(status[2] & ~masks[2]) && !(status[3] & ~masks[3])) {
1336                 return IRQ_NONE;
1337         }
1338
1339         /*
1340          * The following interrupts require a
1341          * protection release cycle to get the
1342          * speaker out of Safe-Mode.
1343          */
1344         if (status[2] & CS35L36_AMP_SHORT_ERR) {
1345                 dev_crit(cs35l36->dev, "Amp short error\n");
1346                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1347                                    CS35L36_AMP_SHORT_ERR_RLS, 0);
1348                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1349                                    CS35L36_AMP_SHORT_ERR_RLS,
1350                                    CS35L36_AMP_SHORT_ERR_RLS);
1351                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1352                                    CS35L36_AMP_SHORT_ERR_RLS, 0);
1353                 regmap_update_bits(cs35l36->regmap, CS35L36_INT3_STATUS,
1354                                    CS35L36_AMP_SHORT_ERR,
1355                                    CS35L36_AMP_SHORT_ERR);
1356                 ret = IRQ_HANDLED;
1357         }
1358
1359         if (status[0] & CS35L36_TEMP_WARN) {
1360                 dev_crit(cs35l36->dev, "Over temperature warning\n");
1361                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1362                                    CS35L36_TEMP_WARN_ERR_RLS, 0);
1363                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1364                                    CS35L36_TEMP_WARN_ERR_RLS,
1365                                    CS35L36_TEMP_WARN_ERR_RLS);
1366                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1367                                    CS35L36_TEMP_WARN_ERR_RLS, 0);
1368                 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1369                                    CS35L36_TEMP_WARN, CS35L36_TEMP_WARN);
1370                 ret = IRQ_HANDLED;
1371         }
1372
1373         if (status[0] & CS35L36_TEMP_ERR) {
1374                 dev_crit(cs35l36->dev, "Over temperature error\n");
1375                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1376                                    CS35L36_TEMP_ERR_RLS, 0);
1377                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1378                                    CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
1379                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1380                                    CS35L36_TEMP_ERR_RLS, 0);
1381                 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1382                                    CS35L36_TEMP_ERR, CS35L36_TEMP_ERR);
1383                 ret = IRQ_HANDLED;
1384         }
1385
1386         if (status[0] & CS35L36_BST_OVP_ERR) {
1387                 dev_crit(cs35l36->dev, "VBST Over Voltage error\n");
1388                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1389                                    CS35L36_TEMP_ERR_RLS, 0);
1390                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1391                                    CS35L36_TEMP_ERR_RLS, CS35L36_TEMP_ERR_RLS);
1392                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1393                                    CS35L36_TEMP_ERR_RLS, 0);
1394                 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1395                                    CS35L36_BST_OVP_ERR, CS35L36_BST_OVP_ERR);
1396                 ret = IRQ_HANDLED;
1397         }
1398
1399         if (status[0] & CS35L36_BST_DCM_UVP_ERR) {
1400                 dev_crit(cs35l36->dev, "DCM VBST Under Voltage Error\n");
1401                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1402                                    CS35L36_BST_UVP_ERR_RLS, 0);
1403                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1404                                    CS35L36_BST_UVP_ERR_RLS,
1405                                    CS35L36_BST_UVP_ERR_RLS);
1406                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1407                                    CS35L36_BST_UVP_ERR_RLS, 0);
1408                 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1409                                    CS35L36_BST_DCM_UVP_ERR,
1410                                    CS35L36_BST_DCM_UVP_ERR);
1411                 ret = IRQ_HANDLED;
1412         }
1413
1414         if (status[0] & CS35L36_BST_SHORT_ERR) {
1415                 dev_crit(cs35l36->dev, "LBST SHORT error!\n");
1416                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1417                                    CS35L36_BST_SHORT_ERR_RLS, 0);
1418                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1419                                    CS35L36_BST_SHORT_ERR_RLS,
1420                                    CS35L36_BST_SHORT_ERR_RLS);
1421                 regmap_update_bits(cs35l36->regmap, CS35L36_PROTECT_REL_ERR,
1422                                    CS35L36_BST_SHORT_ERR_RLS, 0);
1423                 regmap_update_bits(cs35l36->regmap, CS35L36_INT1_STATUS,
1424                                    CS35L36_BST_SHORT_ERR,
1425                                    CS35L36_BST_SHORT_ERR);
1426                 ret = IRQ_HANDLED;
1427         }
1428
1429         return ret;
1430 }
1431
1432 static int cs35l36_handle_of_data(struct i2c_client *i2c_client,
1433                                 struct cs35l36_platform_data *pdata)
1434 {
1435         struct device_node *np = i2c_client->dev.of_node;
1436         struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
1437         struct device_node *vpbr_node;
1438         unsigned int val;
1439         int ret;
1440
1441         if (!np)
1442                 return 0;
1443
1444         ret = of_property_read_u32(np, "cirrus,boost-ctl-millivolt", &val);
1445         if (!ret) {
1446                 if (val < 2550 || val > 12000) {
1447                         dev_err(&i2c_client->dev,
1448                                 "Invalid Boost Voltage %d mV\n", val);
1449                         return -EINVAL;
1450                 }
1451                 pdata->bst_vctl = (((val - 2550) / 100) + 1) << 1;
1452         } else {
1453                 dev_err(&i2c_client->dev,
1454                         "Unable to find required parameter 'cirrus,boost-ctl-millivolt'");
1455                 return -EINVAL;
1456         }
1457
1458         ret = of_property_read_u32(np, "cirrus,boost-ctl-select", &val);
1459         if (!ret)
1460                 pdata->bst_vctl_sel = val | CS35L36_VALID_PDATA;
1461
1462         ret = of_property_read_u32(np, "cirrus,boost-peak-milliamp", &val);
1463         if (!ret) {
1464                 if (val < 1600 || val > 4500) {
1465                         dev_err(&i2c_client->dev,
1466                                 "Invalid Boost Peak Current %u mA\n", val);
1467                         return -EINVAL;
1468                 }
1469
1470                 pdata->bst_ipk = (val - 1600) / 50;
1471         } else {
1472                 dev_err(&i2c_client->dev,
1473                         "Unable to find required parameter 'cirrus,boost-peak-milliamp'");
1474                 return -EINVAL;
1475         }
1476
1477         pdata->multi_amp_mode = of_property_read_bool(np,
1478                                         "cirrus,multi-amp-mode");
1479
1480         pdata->dcm_mode = of_property_read_bool(np,
1481                                         "cirrus,dcm-mode-enable");
1482
1483         pdata->amp_pcm_inv = of_property_read_bool(np,
1484                                         "cirrus,amp-pcm-inv");
1485
1486         pdata->imon_pol_inv = of_property_read_bool(np,
1487                                         "cirrus,imon-pol-inv");
1488
1489         pdata->vmon_pol_inv = of_property_read_bool(np,
1490                                         "cirrus,vmon-pol-inv");
1491
1492         if (of_property_read_u32(np, "cirrus,temp-warn-threshold", &val) >= 0)
1493                 pdata->temp_warn_thld = val | CS35L36_VALID_PDATA;
1494
1495         if (of_property_read_u32(np, "cirrus,boost-ind-nanohenry", &val) >= 0) {
1496                 pdata->boost_ind = val;
1497         } else {
1498                 dev_err(&i2c_client->dev, "Inductor not specified.\n");
1499                 return -EINVAL;
1500         }
1501
1502         if (of_property_read_u32(np, "cirrus,irq-drive-select", &val) >= 0)
1503                 pdata->irq_drv_sel = val | CS35L36_VALID_PDATA;
1504
1505         if (of_property_read_u32(np, "cirrus,irq-gpio-select", &val) >= 0)
1506                 pdata->irq_gpio_sel = val | CS35L36_VALID_PDATA;
1507
1508         /* VPBR Config */
1509         vpbr_node = of_get_child_by_name(np, "cirrus,vpbr-config");
1510         vpbr_config->is_present = vpbr_node ? true : false;
1511         if (vpbr_config->is_present) {
1512                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-en",
1513                                          &val) >= 0)
1514                         vpbr_config->vpbr_en = val;
1515                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-thld",
1516                                          &val) >= 0)
1517                         vpbr_config->vpbr_thld = val;
1518                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-rate",
1519                                          &val) >= 0)
1520                         vpbr_config->vpbr_atk_rate = val;
1521                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-atk-vol",
1522                                          &val) >= 0)
1523                         vpbr_config->vpbr_atk_vol = val;
1524                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-max-attn",
1525                                          &val) >= 0)
1526                         vpbr_config->vpbr_max_attn = val;
1527                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-wait",
1528                                          &val) >= 0)
1529                         vpbr_config->vpbr_wait = val;
1530                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-rel-rate",
1531                                          &val) >= 0)
1532                         vpbr_config->vpbr_rel_rate = val;
1533                 if (of_property_read_u32(vpbr_node, "cirrus,vpbr-mute-en",
1534                                          &val) >= 0)
1535                         vpbr_config->vpbr_mute_en = val;
1536         }
1537         of_node_put(vpbr_node);
1538
1539         return 0;
1540 }
1541
1542 static int cs35l36_pac(struct cs35l36_private *cs35l36)
1543 {
1544         int ret, count;
1545         unsigned int val;
1546
1547         if (cs35l36->rev_id != CS35L36_REV_B0)
1548                 return 0;
1549
1550         /*
1551          * Magic code for internal PAC
1552          */
1553         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1554                      CS35L36_TEST_UNLOCK1);
1555         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1556                      CS35L36_TEST_UNLOCK2);
1557
1558         usleep_range(9500, 10500);
1559
1560         regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
1561                      CS35L36_PAC_RESET);
1562         regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
1563                      CS35L36_PAC_MEM_ACCESS);
1564         regmap_write(cs35l36->regmap, CS35L36_PAC_PMEM_WORD0,
1565                      CS35L36_B0_PAC_PATCH);
1566
1567         regmap_write(cs35l36->regmap, CS35L36_PAC_CTL3,
1568                      CS35L36_PAC_MEM_ACCESS_CLR);
1569         regmap_write(cs35l36->regmap, CS35L36_PAC_CTL1,
1570                      CS35L36_PAC_ENABLE_MASK);
1571
1572         usleep_range(9500, 10500);
1573
1574         ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS, &val);
1575         if (ret < 0) {
1576                 dev_err(cs35l36->dev, "Failed to read int4_status %d\n", ret);
1577                 return ret;
1578         }
1579
1580         count = 0;
1581         while (!(val & CS35L36_MCU_CONFIG_CLR)) {
1582                 usleep_range(100, 200);
1583                 count++;
1584
1585                 ret = regmap_read(cs35l36->regmap, CS35L36_INT4_STATUS,
1586                                   &val);
1587                 if (ret < 0) {
1588                         dev_err(cs35l36->dev, "Failed to read int4_status %d\n",
1589                                 ret);
1590                         return ret;
1591                 }
1592
1593                 if (count >= 100)
1594                         return -EINVAL;
1595         }
1596
1597         regmap_write(cs35l36->regmap, CS35L36_INT4_STATUS,
1598                      CS35L36_MCU_CONFIG_CLR);
1599         regmap_update_bits(cs35l36->regmap, CS35L36_PAC_CTL1,
1600                            CS35L36_PAC_ENABLE_MASK, 0);
1601
1602         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1603                      CS35L36_TEST_LOCK1);
1604         regmap_write(cs35l36->regmap, CS35L36_TESTKEY_CTRL,
1605                      CS35L36_TEST_LOCK2);
1606
1607         return 0;
1608 }
1609
1610 static void cs35l36_apply_vpbr_config(struct cs35l36_private *cs35l36)
1611 {
1612         struct cs35l36_platform_data *pdata = &cs35l36->pdata;
1613         struct cs35l36_vpbr_cfg *vpbr_config = &pdata->vpbr_config;
1614
1615         regmap_update_bits(cs35l36->regmap, CS35L36_PWR_CTRL3,
1616                            CS35L36_VPBR_EN_MASK,
1617                            vpbr_config->vpbr_en <<
1618                            CS35L36_VPBR_EN_SHIFT);
1619         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1620                            CS35L36_VPBR_THLD_MASK,
1621                            vpbr_config->vpbr_thld <<
1622                            CS35L36_VPBR_THLD_SHIFT);
1623         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1624                            CS35L36_VPBR_MAX_ATTN_MASK,
1625                            vpbr_config->vpbr_max_attn <<
1626                            CS35L36_VPBR_MAX_ATTN_SHIFT);
1627         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1628                            CS35L36_VPBR_ATK_VOL_MASK,
1629                            vpbr_config->vpbr_atk_vol <<
1630                            CS35L36_VPBR_ATK_VOL_SHIFT);
1631         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1632                            CS35L36_VPBR_ATK_RATE_MASK,
1633                            vpbr_config->vpbr_atk_rate <<
1634                            CS35L36_VPBR_ATK_RATE_SHIFT);
1635         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1636                            CS35L36_VPBR_WAIT_MASK,
1637                            vpbr_config->vpbr_wait <<
1638                            CS35L36_VPBR_WAIT_SHIFT);
1639         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1640                            CS35L36_VPBR_REL_RATE_MASK,
1641                            vpbr_config->vpbr_rel_rate <<
1642                            CS35L36_VPBR_REL_RATE_SHIFT);
1643         regmap_update_bits(cs35l36->regmap, CS35L36_VPBR_CFG,
1644                            CS35L36_VPBR_MUTE_EN_MASK,
1645                            vpbr_config->vpbr_mute_en <<
1646                            CS35L36_VPBR_MUTE_EN_SHIFT);
1647 }
1648
1649 static const struct reg_sequence cs35l36_reva0_errata_patch[] = {
1650         { CS35L36_TESTKEY_CTRL,         CS35L36_TEST_UNLOCK1 },
1651         { CS35L36_TESTKEY_CTRL,         CS35L36_TEST_UNLOCK2 },
1652         /* Errata Writes */
1653         { CS35L36_OTP_CTRL1,            0x00002060 },
1654         { CS35L36_OTP_CTRL2,            0x00000001 },
1655         { CS35L36_OTP_CTRL1,            0x00002460 },
1656         { CS35L36_OTP_CTRL2,            0x00000001 },
1657         { 0x00002088,                   0x012A1838 },
1658         { 0x00003014,                   0x0100EE0E },
1659         { 0x00003008,                   0x0008184A },
1660         { 0x00007418,                   0x509001C8 },
1661         { 0x00007064,                   0x0929A800 },
1662         { 0x00002D10,                   0x0002C01C },
1663         { 0x0000410C,                   0x00000A11 },
1664         { 0x00006E08,                   0x8B19140C },
1665         { 0x00006454,                   0x0300000A },
1666         { CS35L36_AMP_NG_CTRL,          0x000020EF },
1667         { 0x00007E34,                   0x0000000E },
1668         { 0x0000410C,                   0x00000A11 },
1669         { 0x00007410,                   0x20514B00 },
1670         /* PAC Config */
1671         { CS35L36_CTRL_OVRRIDE,         0x00000000 },
1672         { CS35L36_PAC_INT0_CTRL,        0x00860001 },
1673         { CS35L36_PAC_INT1_CTRL,        0x00860001 },
1674         { CS35L36_PAC_INT2_CTRL,        0x00860001 },
1675         { CS35L36_PAC_INT3_CTRL,        0x00860001 },
1676         { CS35L36_PAC_INT4_CTRL,        0x00860001 },
1677         { CS35L36_PAC_INT5_CTRL,        0x00860001 },
1678         { CS35L36_PAC_INT6_CTRL,        0x00860001 },
1679         { CS35L36_PAC_INT7_CTRL,        0x00860001 },
1680         { CS35L36_PAC_INT_FLUSH_CTRL,   0x000000FF },
1681         { CS35L36_TESTKEY_CTRL,         CS35L36_TEST_LOCK1 },
1682         { CS35L36_TESTKEY_CTRL,         CS35L36_TEST_LOCK2 },
1683 };
1684
1685 static const struct reg_sequence cs35l36_revb0_errata_patch[] = {
1686         { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK1 },
1687         { CS35L36_TESTKEY_CTRL, CS35L36_TEST_UNLOCK2 },
1688         { 0x00007064,           0x0929A800 },
1689         { 0x00007850,           0x00002FA9 },
1690         { 0x00007854,           0x0003F1D5 },
1691         { 0x00007858,           0x0003F5E3 },
1692         { 0x0000785C,           0x00001137 },
1693         { 0x00007860,           0x0001A7A5 },
1694         { 0x00007864,           0x0002F16A },
1695         { 0x00007868,           0x00003E21 },
1696         { 0x00007848,           0x00000001 },
1697         { 0x00003854,           0x05180240 },
1698         { 0x00007418,           0x509001C8 },
1699         { 0x0000394C,           0x028764BD },
1700         { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK1 },
1701         { CS35L36_TESTKEY_CTRL, CS35L36_TEST_LOCK2 },
1702 };
1703
1704 static int cs35l36_i2c_probe(struct i2c_client *i2c_client)
1705 {
1706         struct cs35l36_private *cs35l36;
1707         struct device *dev = &i2c_client->dev;
1708         struct cs35l36_platform_data *pdata = dev_get_platdata(dev);
1709         struct irq_data *irq_d;
1710         int ret, irq_pol, chip_irq_pol, i;
1711         u32 reg_id, reg_revid, l37_id_reg;
1712
1713         cs35l36 = devm_kzalloc(dev, sizeof(struct cs35l36_private), GFP_KERNEL);
1714         if (!cs35l36)
1715                 return -ENOMEM;
1716
1717         cs35l36->dev = dev;
1718
1719         i2c_set_clientdata(i2c_client, cs35l36);
1720         cs35l36->regmap = devm_regmap_init_i2c(i2c_client, &cs35l36_regmap);
1721         if (IS_ERR(cs35l36->regmap)) {
1722                 ret = PTR_ERR(cs35l36->regmap);
1723                 dev_err(dev, "regmap_init() failed: %d\n", ret);
1724                 return ret;
1725         }
1726
1727         cs35l36->num_supplies = ARRAY_SIZE(cs35l36_supplies);
1728         for (i = 0; i < ARRAY_SIZE(cs35l36_supplies); i++)
1729                 cs35l36->supplies[i].supply = cs35l36_supplies[i];
1730
1731         ret = devm_regulator_bulk_get(dev, cs35l36->num_supplies,
1732                                       cs35l36->supplies);
1733         if (ret != 0) {
1734                 dev_err(dev, "Failed to request core supplies: %d\n", ret);
1735                 return ret;
1736         }
1737
1738         if (pdata) {
1739                 cs35l36->pdata = *pdata;
1740         } else {
1741                 pdata = devm_kzalloc(dev, sizeof(struct cs35l36_platform_data),
1742                                      GFP_KERNEL);
1743                 if (!pdata)
1744                         return -ENOMEM;
1745
1746                 if (i2c_client->dev.of_node) {
1747                         ret = cs35l36_handle_of_data(i2c_client, pdata);
1748                         if (ret != 0)
1749                                 return ret;
1750
1751                 }
1752
1753                 cs35l36->pdata = *pdata;
1754         }
1755
1756         ret = regulator_bulk_enable(cs35l36->num_supplies, cs35l36->supplies);
1757         if (ret != 0) {
1758                 dev_err(dev, "Failed to enable core supplies: %d\n", ret);
1759                 return ret;
1760         }
1761
1762         /* returning NULL can be an option if in stereo mode */
1763         cs35l36->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1764                                                       GPIOD_OUT_LOW);
1765         if (IS_ERR(cs35l36->reset_gpio)) {
1766                 ret = PTR_ERR(cs35l36->reset_gpio);
1767                 cs35l36->reset_gpio = NULL;
1768                 if (ret == -EBUSY) {
1769                         dev_info(dev, "Reset line busy, assuming shared reset\n");
1770                 } else {
1771                         dev_err(dev, "Failed to get reset GPIO: %d\n", ret);
1772                         goto err_disable_regs;
1773                 }
1774         }
1775
1776         if (cs35l36->reset_gpio)
1777                 gpiod_set_value_cansleep(cs35l36->reset_gpio, 1);
1778
1779         usleep_range(2000, 2100);
1780
1781         /* initialize amplifier */
1782         ret = regmap_read(cs35l36->regmap, CS35L36_SW_RESET, &reg_id);
1783         if (ret < 0) {
1784                 dev_err(dev, "Get Device ID failed %d\n", ret);
1785                 goto err;
1786         }
1787
1788         if (reg_id != CS35L36_CHIP_ID) {
1789                 dev_err(dev, "Device ID (%X). Expected ID %X\n", reg_id,
1790                         CS35L36_CHIP_ID);
1791                 ret = -ENODEV;
1792                 goto err;
1793         }
1794
1795         ret = regmap_read(cs35l36->regmap, CS35L36_REV_ID, &reg_revid);
1796         if (ret < 0) {
1797                 dev_err(&i2c_client->dev, "Get Revision ID failed %d\n", ret);
1798                 goto err;
1799         }
1800
1801         cs35l36->rev_id = reg_revid >> 8;
1802
1803         ret = regmap_read(cs35l36->regmap, CS35L36_OTP_MEM30, &l37_id_reg);
1804         if (ret < 0) {
1805                 dev_err(&i2c_client->dev, "Failed to read otp_id Register %d\n",
1806                         ret);
1807                 goto err;
1808         }
1809
1810         if ((l37_id_reg & CS35L36_OTP_REV_MASK) == CS35L36_OTP_REV_L37)
1811                 cs35l36->chip_version = CS35L36_12V_L37;
1812         else
1813                 cs35l36->chip_version = CS35L36_10V_L36;
1814
1815         switch (cs35l36->rev_id) {
1816         case CS35L36_REV_A0:
1817                 ret = regmap_register_patch(cs35l36->regmap,
1818                                 cs35l36_reva0_errata_patch,
1819                                 ARRAY_SIZE(cs35l36_reva0_errata_patch));
1820                 if (ret < 0) {
1821                         dev_err(dev, "Failed to apply A0 errata patch %d\n",
1822                                 ret);
1823                         goto err;
1824                 }
1825                 break;
1826         case CS35L36_REV_B0:
1827                 ret = cs35l36_pac(cs35l36);
1828                 if (ret < 0) {
1829                         dev_err(dev, "Failed to Trim OTP %d\n", ret);
1830                         goto err;
1831                 }
1832
1833                 ret = regmap_register_patch(cs35l36->regmap,
1834                                 cs35l36_revb0_errata_patch,
1835                                 ARRAY_SIZE(cs35l36_revb0_errata_patch));
1836                 if (ret < 0) {
1837                         dev_err(dev, "Failed to apply B0 errata patch %d\n",
1838                                 ret);
1839                         goto err;
1840                 }
1841                 break;
1842         }
1843
1844         if (pdata->vpbr_config.is_present)
1845                 cs35l36_apply_vpbr_config(cs35l36);
1846
1847         irq_d = irq_get_irq_data(i2c_client->irq);
1848         if (!irq_d) {
1849                 dev_err(&i2c_client->dev, "Invalid IRQ: %d\n", i2c_client->irq);
1850                 ret = -ENODEV;
1851                 goto err;
1852         }
1853
1854         irq_pol = irqd_get_trigger_type(irq_d);
1855
1856         switch (irq_pol) {
1857         case IRQF_TRIGGER_FALLING:
1858         case IRQF_TRIGGER_LOW:
1859                 chip_irq_pol = 0;
1860                 break;
1861         case IRQF_TRIGGER_RISING:
1862         case IRQF_TRIGGER_HIGH:
1863                 chip_irq_pol = 1;
1864                 break;
1865         default:
1866                 dev_err(cs35l36->dev, "Invalid IRQ polarity: %d\n", irq_pol);
1867                 ret = -EINVAL;
1868                 goto err;
1869         }
1870
1871         regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1872                            CS35L36_INT_POL_SEL_MASK,
1873                            chip_irq_pol << CS35L36_INT_POL_SEL_SHIFT);
1874
1875         ret = devm_request_threaded_irq(dev, i2c_client->irq, NULL, cs35l36_irq,
1876                                         IRQF_ONESHOT | irq_pol, "cs35l36",
1877                                         cs35l36);
1878         if (ret != 0) {
1879                 dev_err(dev, "Failed to request IRQ: %d\n", ret);
1880                 goto err;
1881         }
1882
1883         regmap_update_bits(cs35l36->regmap, CS35L36_PAD_INTERFACE,
1884                            CS35L36_INT_OUTPUT_EN_MASK, 1);
1885
1886         /* Set interrupt masks for critical errors */
1887         regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
1888                      CS35L36_INT1_MASK_DEFAULT);
1889         regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
1890                      CS35L36_INT3_MASK_DEFAULT);
1891
1892         dev_info(&i2c_client->dev, "Cirrus Logic CS35L%d, Revision: %02X\n",
1893                  cs35l36->chip_version, reg_revid >> 8);
1894
1895         ret =  devm_snd_soc_register_component(dev, &soc_component_dev_cs35l36,
1896                                                cs35l36_dai,
1897                                                ARRAY_SIZE(cs35l36_dai));
1898         if (ret < 0) {
1899                 dev_err(dev, "%s: Register component failed %d\n", __func__,
1900                         ret);
1901                 goto err;
1902         }
1903
1904         return 0;
1905
1906 err:
1907         gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
1908
1909 err_disable_regs:
1910         regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
1911         return ret;
1912 }
1913
1914 static int cs35l36_i2c_remove(struct i2c_client *client)
1915 {
1916         struct cs35l36_private *cs35l36 = i2c_get_clientdata(client);
1917
1918         /* Reset interrupt masks for device removal */
1919         regmap_write(cs35l36->regmap, CS35L36_INT1_MASK,
1920                      CS35L36_INT1_MASK_RESET);
1921         regmap_write(cs35l36->regmap, CS35L36_INT3_MASK,
1922                      CS35L36_INT3_MASK_RESET);
1923
1924         if (cs35l36->reset_gpio)
1925                 gpiod_set_value_cansleep(cs35l36->reset_gpio, 0);
1926
1927         regulator_bulk_disable(cs35l36->num_supplies, cs35l36->supplies);
1928
1929         return 0;
1930 }
1931 static const struct of_device_id cs35l36_of_match[] = {
1932         {.compatible = "cirrus,cs35l36"},
1933         {},
1934 };
1935 MODULE_DEVICE_TABLE(of, cs35l36_of_match);
1936
1937 static const struct i2c_device_id cs35l36_id[] = {
1938         {"cs35l36", 0},
1939         {}
1940 };
1941
1942 MODULE_DEVICE_TABLE(i2c, cs35l36_id);
1943
1944 static struct i2c_driver cs35l36_i2c_driver = {
1945         .driver = {
1946                 .name = "cs35l36",
1947                 .of_match_table = cs35l36_of_match,
1948         },
1949         .id_table = cs35l36_id,
1950         .probe_new = cs35l36_i2c_probe,
1951         .remove = cs35l36_i2c_remove,
1952 };
1953 module_i2c_driver(cs35l36_i2c_driver);
1954
1955 MODULE_DESCRIPTION("ASoC CS35L36 driver");
1956 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
1957 MODULE_LICENSE("GPL");