2 * arizona.c - Wolfson Arizona class device shared support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/gcd.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <sound/pcm.h>
18 #include <sound/pcm_params.h>
19 #include <sound/tlv.h>
21 #include <linux/mfd/arizona/core.h>
22 #include <linux/mfd/arizona/gpio.h>
23 #include <linux/mfd/arizona/registers.h>
27 #define ARIZONA_AIF_BCLK_CTRL 0x00
28 #define ARIZONA_AIF_TX_PIN_CTRL 0x01
29 #define ARIZONA_AIF_RX_PIN_CTRL 0x02
30 #define ARIZONA_AIF_RATE_CTRL 0x03
31 #define ARIZONA_AIF_FORMAT 0x04
32 #define ARIZONA_AIF_TX_BCLK_RATE 0x05
33 #define ARIZONA_AIF_RX_BCLK_RATE 0x06
34 #define ARIZONA_AIF_FRAME_CTRL_1 0x07
35 #define ARIZONA_AIF_FRAME_CTRL_2 0x08
36 #define ARIZONA_AIF_FRAME_CTRL_3 0x09
37 #define ARIZONA_AIF_FRAME_CTRL_4 0x0A
38 #define ARIZONA_AIF_FRAME_CTRL_5 0x0B
39 #define ARIZONA_AIF_FRAME_CTRL_6 0x0C
40 #define ARIZONA_AIF_FRAME_CTRL_7 0x0D
41 #define ARIZONA_AIF_FRAME_CTRL_8 0x0E
42 #define ARIZONA_AIF_FRAME_CTRL_9 0x0F
43 #define ARIZONA_AIF_FRAME_CTRL_10 0x10
44 #define ARIZONA_AIF_FRAME_CTRL_11 0x11
45 #define ARIZONA_AIF_FRAME_CTRL_12 0x12
46 #define ARIZONA_AIF_FRAME_CTRL_13 0x13
47 #define ARIZONA_AIF_FRAME_CTRL_14 0x14
48 #define ARIZONA_AIF_FRAME_CTRL_15 0x15
49 #define ARIZONA_AIF_FRAME_CTRL_16 0x16
50 #define ARIZONA_AIF_FRAME_CTRL_17 0x17
51 #define ARIZONA_AIF_FRAME_CTRL_18 0x18
52 #define ARIZONA_AIF_TX_ENABLES 0x19
53 #define ARIZONA_AIF_RX_ENABLES 0x1A
54 #define ARIZONA_AIF_FORCE_WRITE 0x1B
56 #define ARIZONA_FLL_VCO_CORNER 141900000
57 #define ARIZONA_FLL_MAX_FREF 13500000
58 #define ARIZONA_FLL_MIN_FVCO 90000000
59 #define ARIZONA_FLL_MAX_FRATIO 16
60 #define ARIZONA_FLL_MAX_REFDIV 8
61 #define ARIZONA_FLL_MIN_OUTDIV 2
62 #define ARIZONA_FLL_MAX_OUTDIV 7
64 #define arizona_fll_err(_fll, fmt, ...) \
65 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
66 #define arizona_fll_warn(_fll, fmt, ...) \
67 dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
68 #define arizona_fll_dbg(_fll, fmt, ...) \
69 dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
71 #define arizona_aif_err(_dai, fmt, ...) \
72 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
73 #define arizona_aif_warn(_dai, fmt, ...) \
74 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
75 #define arizona_aif_dbg(_dai, fmt, ...) \
76 dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
78 static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
79 struct snd_kcontrol *kcontrol,
82 struct snd_soc_codec *codec = w->codec;
83 struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
84 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
85 bool manual_ena = false;
88 switch (arizona->type) {
90 switch (arizona->rev) {
102 case SND_SOC_DAPM_PRE_PMU:
103 if (!priv->spk_ena && manual_ena) {
104 regmap_write_async(arizona->regmap, 0x4f5, 0x25a);
105 priv->spk_ena_pending = true;
108 case SND_SOC_DAPM_POST_PMU:
109 val = snd_soc_read(codec, ARIZONA_INTERRUPT_RAW_STATUS_3);
110 if (val & ARIZONA_SPK_SHUTDOWN_STS) {
111 dev_crit(arizona->dev,
112 "Speaker not enabled due to temperature\n");
116 regmap_update_bits_async(arizona->regmap,
117 ARIZONA_OUTPUT_ENABLES_1,
118 1 << w->shift, 1 << w->shift);
120 if (priv->spk_ena_pending) {
122 regmap_write_async(arizona->regmap, 0x4f5, 0xda);
123 priv->spk_ena_pending = false;
127 case SND_SOC_DAPM_PRE_PMD:
131 regmap_write_async(arizona->regmap,
135 regmap_update_bits_async(arizona->regmap,
136 ARIZONA_OUTPUT_ENABLES_1,
139 case SND_SOC_DAPM_POST_PMD:
142 regmap_write_async(arizona->regmap,
151 static irqreturn_t arizona_thermal_warn(int irq, void *data)
153 struct arizona *arizona = data;
157 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
160 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
162 } else if (val & ARIZONA_SPK_SHUTDOWN_WARN_STS) {
163 dev_crit(arizona->dev, "Thermal warning\n");
169 static irqreturn_t arizona_thermal_shutdown(int irq, void *data)
171 struct arizona *arizona = data;
175 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
178 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
180 } else if (val & ARIZONA_SPK_SHUTDOWN_STS) {
181 dev_crit(arizona->dev, "Thermal shutdown\n");
182 ret = regmap_update_bits(arizona->regmap,
183 ARIZONA_OUTPUT_ENABLES_1,
185 ARIZONA_OUT4R_ENA, 0);
187 dev_crit(arizona->dev,
188 "Failed to disable speaker outputs: %d\n",
195 static const struct snd_soc_dapm_widget arizona_spkl =
196 SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
197 ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
198 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
200 static const struct snd_soc_dapm_widget arizona_spkr =
201 SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
202 ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
203 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
205 int arizona_init_spk(struct snd_soc_codec *codec)
207 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
208 struct arizona *arizona = priv->arizona;
211 ret = snd_soc_dapm_new_controls(&codec->dapm, &arizona_spkl, 1);
215 switch (arizona->type) {
219 ret = snd_soc_dapm_new_controls(&codec->dapm,
226 ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN_WARN,
227 "Thermal warning", arizona_thermal_warn,
230 dev_err(arizona->dev,
231 "Failed to get thermal warning IRQ: %d\n",
234 ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_SHUTDOWN,
235 "Thermal shutdown", arizona_thermal_shutdown,
238 dev_err(arizona->dev,
239 "Failed to get thermal shutdown IRQ: %d\n",
244 EXPORT_SYMBOL_GPL(arizona_init_spk);
246 int arizona_init_gpio(struct snd_soc_codec *codec)
248 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
249 struct arizona *arizona = priv->arizona;
252 switch (arizona->type) {
254 snd_soc_dapm_disable_pin(&codec->dapm, "DRC2 Signal Activity");
260 snd_soc_dapm_disable_pin(&codec->dapm, "DRC1 Signal Activity");
262 for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
263 switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) {
264 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT:
265 snd_soc_dapm_enable_pin(&codec->dapm,
266 "DRC1 Signal Activity");
268 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT:
269 snd_soc_dapm_enable_pin(&codec->dapm,
270 "DRC2 Signal Activity");
279 EXPORT_SYMBOL_GPL(arizona_init_gpio);
281 const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
386 EXPORT_SYMBOL_GPL(arizona_mixer_texts);
388 int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
394 0x0c, /* Noise mixer */
395 0x0d, /* Comfort noise */
468 0xa0, /* ISRC1INT1 */
472 0xa4, /* ISRC1DEC1 */
476 0xa8, /* ISRC2DEC1 */
480 0xac, /* ISRC2INT1 */
484 0xb0, /* ISRC3DEC1 */
488 0xb4, /* ISRC3INT1 */
493 EXPORT_SYMBOL_GPL(arizona_mixer_values);
495 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
496 EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
498 const char *arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = {
499 "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
501 EXPORT_SYMBOL_GPL(arizona_rate_text);
503 const int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = {
506 EXPORT_SYMBOL_GPL(arizona_rate_val);
509 const struct soc_enum arizona_isrc_fsh[] = {
510 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1,
511 ARIZONA_ISRC1_FSH_SHIFT, 0xf,
512 ARIZONA_RATE_ENUM_SIZE,
513 arizona_rate_text, arizona_rate_val),
514 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1,
515 ARIZONA_ISRC2_FSH_SHIFT, 0xf,
516 ARIZONA_RATE_ENUM_SIZE,
517 arizona_rate_text, arizona_rate_val),
518 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1,
519 ARIZONA_ISRC3_FSH_SHIFT, 0xf,
520 ARIZONA_RATE_ENUM_SIZE,
521 arizona_rate_text, arizona_rate_val),
523 EXPORT_SYMBOL_GPL(arizona_isrc_fsh);
525 const struct soc_enum arizona_isrc_fsl[] = {
526 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2,
527 ARIZONA_ISRC1_FSL_SHIFT, 0xf,
528 ARIZONA_RATE_ENUM_SIZE,
529 arizona_rate_text, arizona_rate_val),
530 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2,
531 ARIZONA_ISRC2_FSL_SHIFT, 0xf,
532 ARIZONA_RATE_ENUM_SIZE,
533 arizona_rate_text, arizona_rate_val),
534 SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2,
535 ARIZONA_ISRC3_FSL_SHIFT, 0xf,
536 ARIZONA_RATE_ENUM_SIZE,
537 arizona_rate_text, arizona_rate_val),
539 EXPORT_SYMBOL_GPL(arizona_isrc_fsl);
541 const struct soc_enum arizona_asrc_rate1 =
542 SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1,
543 ARIZONA_ASRC_RATE1_SHIFT, 0xf,
544 ARIZONA_RATE_ENUM_SIZE - 1,
545 arizona_rate_text, arizona_rate_val);
546 EXPORT_SYMBOL_GPL(arizona_asrc_rate1);
548 static const char *arizona_vol_ramp_text[] = {
549 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
550 "15ms/6dB", "30ms/6dB",
553 SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp,
554 ARIZONA_INPUT_VOLUME_RAMP,
555 ARIZONA_IN_VD_RAMP_SHIFT,
556 arizona_vol_ramp_text);
557 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
559 SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp,
560 ARIZONA_INPUT_VOLUME_RAMP,
561 ARIZONA_IN_VI_RAMP_SHIFT,
562 arizona_vol_ramp_text);
563 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
565 SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp,
566 ARIZONA_OUTPUT_VOLUME_RAMP,
567 ARIZONA_OUT_VD_RAMP_SHIFT,
568 arizona_vol_ramp_text);
569 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
571 SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp,
572 ARIZONA_OUTPUT_VOLUME_RAMP,
573 ARIZONA_OUT_VI_RAMP_SHIFT,
574 arizona_vol_ramp_text);
575 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
577 static const char *arizona_lhpf_mode_text[] = {
578 "Low-pass", "High-pass"
581 SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode,
583 ARIZONA_LHPF1_MODE_SHIFT,
584 arizona_lhpf_mode_text);
585 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
587 SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode,
589 ARIZONA_LHPF2_MODE_SHIFT,
590 arizona_lhpf_mode_text);
591 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
593 SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode,
595 ARIZONA_LHPF3_MODE_SHIFT,
596 arizona_lhpf_mode_text);
597 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
599 SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode,
601 ARIZONA_LHPF4_MODE_SHIFT,
602 arizona_lhpf_mode_text);
603 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
605 static const char *arizona_ng_hold_text[] = {
606 "30ms", "120ms", "250ms", "500ms",
609 SOC_ENUM_SINGLE_DECL(arizona_ng_hold,
610 ARIZONA_NOISE_GATE_CONTROL,
611 ARIZONA_NGATE_HOLD_SHIFT,
612 arizona_ng_hold_text);
613 EXPORT_SYMBOL_GPL(arizona_ng_hold);
615 static const char * const arizona_in_hpf_cut_text[] = {
616 "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz"
619 SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum,
621 ARIZONA_IN_HPF_CUT_SHIFT,
622 arizona_in_hpf_cut_text);
623 EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum);
625 static const char * const arizona_in_dmic_osr_text[] = {
626 "1.536MHz", "3.072MHz", "6.144MHz",
629 const struct soc_enum arizona_in_dmic_osr[] = {
630 SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT,
631 ARRAY_SIZE(arizona_in_dmic_osr_text),
632 arizona_in_dmic_osr_text),
633 SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT,
634 ARRAY_SIZE(arizona_in_dmic_osr_text),
635 arizona_in_dmic_osr_text),
636 SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT,
637 ARRAY_SIZE(arizona_in_dmic_osr_text),
638 arizona_in_dmic_osr_text),
639 SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT,
640 ARRAY_SIZE(arizona_in_dmic_osr_text),
641 arizona_in_dmic_osr_text),
643 EXPORT_SYMBOL_GPL(arizona_in_dmic_osr);
645 static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena)
647 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
656 for (i = 0; i < priv->num_inputs; i++)
657 snd_soc_update_bits(codec,
658 ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 4),
662 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
665 struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
669 reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
671 reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
674 case SND_SOC_DAPM_PRE_PMU:
677 case SND_SOC_DAPM_POST_PMU:
678 snd_soc_update_bits(w->codec, reg, ARIZONA_IN1L_MUTE, 0);
680 /* If this is the last input pending then allow VU */
682 if (priv->in_pending == 0) {
684 arizona_in_set_vu(w->codec, 1);
687 case SND_SOC_DAPM_PRE_PMD:
688 snd_soc_update_bits(w->codec, reg,
689 ARIZONA_IN1L_MUTE | ARIZONA_IN_VU,
690 ARIZONA_IN1L_MUTE | ARIZONA_IN_VU);
692 case SND_SOC_DAPM_POST_PMD:
693 /* Disable volume updates if no inputs are enabled */
694 reg = snd_soc_read(w->codec, ARIZONA_INPUT_ENABLES);
696 arizona_in_set_vu(w->codec, 0);
701 EXPORT_SYMBOL_GPL(arizona_in_ev);
703 int arizona_out_ev(struct snd_soc_dapm_widget *w,
704 struct snd_kcontrol *kcontrol,
708 case SND_SOC_DAPM_POST_PMU:
710 case ARIZONA_OUT1L_ENA_SHIFT:
711 case ARIZONA_OUT1R_ENA_SHIFT:
712 case ARIZONA_OUT2L_ENA_SHIFT:
713 case ARIZONA_OUT2R_ENA_SHIFT:
714 case ARIZONA_OUT3L_ENA_SHIFT:
715 case ARIZONA_OUT3R_ENA_SHIFT:
727 EXPORT_SYMBOL_GPL(arizona_out_ev);
729 int arizona_hp_ev(struct snd_soc_dapm_widget *w,
730 struct snd_kcontrol *kcontrol,
733 struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
734 struct arizona *arizona = priv->arizona;
735 unsigned int mask = 1 << w->shift;
739 case SND_SOC_DAPM_POST_PMU:
742 case SND_SOC_DAPM_PRE_PMD:
749 /* Store the desired state for the HP outputs */
750 priv->arizona->hp_ena &= ~mask;
751 priv->arizona->hp_ena |= val;
753 /* Force off if HPDET magic is active */
754 if (priv->arizona->hpdet_magic)
757 regmap_update_bits_async(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1,
760 return arizona_out_ev(w, kcontrol, event);
762 EXPORT_SYMBOL_GPL(arizona_hp_ev);
764 static unsigned int arizona_sysclk_48k_rates[] = {
774 static unsigned int arizona_sysclk_44k1_rates[] = {
784 static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk,
787 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
790 int ref, div, refclk;
793 case ARIZONA_CLK_OPCLK:
794 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
795 refclk = priv->sysclk;
797 case ARIZONA_CLK_ASYNC_OPCLK:
798 reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
799 refclk = priv->asyncclk;
806 rates = arizona_sysclk_44k1_rates;
808 rates = arizona_sysclk_48k_rates;
810 for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) &&
811 rates[ref] <= refclk; ref++) {
813 while (rates[ref] / div >= freq && div < 32) {
814 if (rates[ref] / div == freq) {
815 dev_dbg(codec->dev, "Configured %dHz OPCLK\n",
817 snd_soc_update_bits(codec, reg,
818 ARIZONA_OPCLK_DIV_MASK |
819 ARIZONA_OPCLK_SEL_MASK,
821 ARIZONA_OPCLK_DIV_SHIFT) |
829 dev_err(codec->dev, "Unable to generate %dHz OPCLK\n", freq);
833 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
834 int source, unsigned int freq, int dir)
836 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
837 struct arizona *arizona = priv->arizona;
840 unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
841 unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
845 case ARIZONA_CLK_SYSCLK:
847 reg = ARIZONA_SYSTEM_CLOCK_1;
849 mask |= ARIZONA_SYSCLK_FRAC;
851 case ARIZONA_CLK_ASYNCCLK:
853 reg = ARIZONA_ASYNC_CLOCK_1;
854 clk = &priv->asyncclk;
856 case ARIZONA_CLK_OPCLK:
857 case ARIZONA_CLK_ASYNC_OPCLK:
858 return arizona_set_opclk(codec, clk_id, freq);
869 val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
873 val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
877 val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
881 val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
885 val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
889 val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
892 dev_dbg(arizona->dev, "%s cleared\n", name);
902 val |= ARIZONA_SYSCLK_FRAC;
904 dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
906 return regmap_update_bits(arizona->regmap, reg, mask, val);
908 EXPORT_SYMBOL_GPL(arizona_set_sysclk);
910 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
912 struct snd_soc_codec *codec = dai->codec;
913 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
914 struct arizona *arizona = priv->arizona;
915 int lrclk, bclk, mode, base;
917 base = dai->driver->base;
922 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
923 case SND_SOC_DAIFMT_DSP_A:
926 case SND_SOC_DAIFMT_I2S:
930 arizona_aif_err(dai, "Unsupported DAI format %d\n",
931 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
935 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
936 case SND_SOC_DAIFMT_CBS_CFS:
938 case SND_SOC_DAIFMT_CBS_CFM:
939 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
941 case SND_SOC_DAIFMT_CBM_CFS:
942 bclk |= ARIZONA_AIF1_BCLK_MSTR;
944 case SND_SOC_DAIFMT_CBM_CFM:
945 bclk |= ARIZONA_AIF1_BCLK_MSTR;
946 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
949 arizona_aif_err(dai, "Unsupported master mode %d\n",
950 fmt & SND_SOC_DAIFMT_MASTER_MASK);
954 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
955 case SND_SOC_DAIFMT_NB_NF:
957 case SND_SOC_DAIFMT_IB_IF:
958 bclk |= ARIZONA_AIF1_BCLK_INV;
959 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
961 case SND_SOC_DAIFMT_IB_NF:
962 bclk |= ARIZONA_AIF1_BCLK_INV;
964 case SND_SOC_DAIFMT_NB_IF:
965 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
971 regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL,
972 ARIZONA_AIF1_BCLK_INV |
973 ARIZONA_AIF1_BCLK_MSTR,
975 regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL,
976 ARIZONA_AIF1TX_LRCLK_INV |
977 ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
978 regmap_update_bits_async(arizona->regmap,
979 base + ARIZONA_AIF_RX_PIN_CTRL,
980 ARIZONA_AIF1RX_LRCLK_INV |
981 ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
982 regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FORMAT,
983 ARIZONA_AIF1_FMT_MASK, mode);
988 static const int arizona_48k_bclk_rates[] = {
1010 static const unsigned int arizona_48k_rates[] = {
1028 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = {
1029 .count = ARRAY_SIZE(arizona_48k_rates),
1030 .list = arizona_48k_rates,
1033 static const int arizona_44k1_bclk_rates[] = {
1055 static const unsigned int arizona_44k1_rates[] = {
1065 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = {
1066 .count = ARRAY_SIZE(arizona_44k1_rates),
1067 .list = arizona_44k1_rates,
1070 static int arizona_sr_vals[] = {
1097 static int arizona_startup(struct snd_pcm_substream *substream,
1098 struct snd_soc_dai *dai)
1100 struct snd_soc_codec *codec = dai->codec;
1101 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1102 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1103 const struct snd_pcm_hw_constraint_list *constraint;
1104 unsigned int base_rate;
1106 switch (dai_priv->clk) {
1107 case ARIZONA_CLK_SYSCLK:
1108 base_rate = priv->sysclk;
1110 case ARIZONA_CLK_ASYNCCLK:
1111 base_rate = priv->asyncclk;
1120 if (base_rate % 8000)
1121 constraint = &arizona_44k1_constraint;
1123 constraint = &arizona_48k_constraint;
1125 return snd_pcm_hw_constraint_list(substream->runtime, 0,
1126 SNDRV_PCM_HW_PARAM_RATE,
1130 static int arizona_hw_params_rate(struct snd_pcm_substream *substream,
1131 struct snd_pcm_hw_params *params,
1132 struct snd_soc_dai *dai)
1134 struct snd_soc_codec *codec = dai->codec;
1135 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1136 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1137 int base = dai->driver->base;
1141 * We will need to be more flexible than this in future,
1142 * currently we use a single sample rate for SYSCLK.
1144 for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
1145 if (arizona_sr_vals[i] == params_rate(params))
1147 if (i == ARRAY_SIZE(arizona_sr_vals)) {
1148 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1149 params_rate(params));
1154 switch (dai_priv->clk) {
1155 case ARIZONA_CLK_SYSCLK:
1156 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
1157 ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
1159 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1160 ARIZONA_AIF1_RATE_MASK, 0);
1162 case ARIZONA_CLK_ASYNCCLK:
1163 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
1164 ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
1166 snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1167 ARIZONA_AIF1_RATE_MASK,
1168 8 << ARIZONA_AIF1_RATE_SHIFT);
1171 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
1178 static int arizona_hw_params(struct snd_pcm_substream *substream,
1179 struct snd_pcm_hw_params *params,
1180 struct snd_soc_dai *dai)
1182 struct snd_soc_codec *codec = dai->codec;
1183 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1184 struct arizona *arizona = priv->arizona;
1185 int base = dai->driver->base;
1188 int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1];
1189 int bclk, lrclk, wl, frame, bclk_target;
1191 if (params_rate(params) % 8000)
1192 rates = &arizona_44k1_bclk_rates[0];
1194 rates = &arizona_48k_bclk_rates[0];
1196 bclk_target = snd_soc_params_to_bclk(params);
1197 if (chan_limit && chan_limit < params_channels(params)) {
1198 arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
1199 bclk_target /= params_channels(params);
1200 bclk_target *= chan_limit;
1203 /* Force stereo for I2S mode */
1204 val = snd_soc_read(codec, base + ARIZONA_AIF_FORMAT);
1205 if (params_channels(params) == 1 && (val & ARIZONA_AIF1_FMT_MASK)) {
1206 arizona_aif_dbg(dai, "Forcing stereo mode\n");
1210 for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
1211 if (rates[i] >= bclk_target &&
1212 rates[i] % params_rate(params) == 0) {
1217 if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
1218 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1219 params_rate(params));
1223 lrclk = rates[bclk] / params_rate(params);
1225 arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
1226 rates[bclk], rates[bclk] / lrclk);
1228 wl = snd_pcm_format_width(params_format(params));
1229 frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl;
1231 ret = arizona_hw_params_rate(substream, params, dai);
1235 regmap_update_bits_async(arizona->regmap,
1236 base + ARIZONA_AIF_BCLK_CTRL,
1237 ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
1238 regmap_update_bits_async(arizona->regmap,
1239 base + ARIZONA_AIF_TX_BCLK_RATE,
1240 ARIZONA_AIF1TX_BCPF_MASK, lrclk);
1241 regmap_update_bits_async(arizona->regmap,
1242 base + ARIZONA_AIF_RX_BCLK_RATE,
1243 ARIZONA_AIF1RX_BCPF_MASK, lrclk);
1244 regmap_update_bits_async(arizona->regmap,
1245 base + ARIZONA_AIF_FRAME_CTRL_1,
1246 ARIZONA_AIF1TX_WL_MASK |
1247 ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
1248 regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FRAME_CTRL_2,
1249 ARIZONA_AIF1RX_WL_MASK |
1250 ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
1255 static const char *arizona_dai_clk_str(int clk_id)
1258 case ARIZONA_CLK_SYSCLK:
1260 case ARIZONA_CLK_ASYNCCLK:
1263 return "Unknown clock";
1267 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
1268 int clk_id, unsigned int freq, int dir)
1270 struct snd_soc_codec *codec = dai->codec;
1271 struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1272 struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1273 struct snd_soc_dapm_route routes[2];
1276 case ARIZONA_CLK_SYSCLK:
1277 case ARIZONA_CLK_ASYNCCLK:
1283 if (clk_id == dai_priv->clk)
1287 dev_err(codec->dev, "Can't change clock on active DAI %d\n",
1292 dev_dbg(codec->dev, "Setting AIF%d to %s\n", dai->id + 1,
1293 arizona_dai_clk_str(clk_id));
1295 memset(&routes, 0, sizeof(routes));
1296 routes[0].sink = dai->driver->capture.stream_name;
1297 routes[1].sink = dai->driver->playback.stream_name;
1299 routes[0].source = arizona_dai_clk_str(dai_priv->clk);
1300 routes[1].source = arizona_dai_clk_str(dai_priv->clk);
1301 snd_soc_dapm_del_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1303 routes[0].source = arizona_dai_clk_str(clk_id);
1304 routes[1].source = arizona_dai_clk_str(clk_id);
1305 snd_soc_dapm_add_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1307 dai_priv->clk = clk_id;
1309 return snd_soc_dapm_sync(&codec->dapm);
1312 static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate)
1314 struct snd_soc_codec *codec = dai->codec;
1315 int base = dai->driver->base;
1319 reg = ARIZONA_AIF1_TRI;
1323 return snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1324 ARIZONA_AIF1_TRI, reg);
1327 const struct snd_soc_dai_ops arizona_dai_ops = {
1328 .startup = arizona_startup,
1329 .set_fmt = arizona_set_fmt,
1330 .hw_params = arizona_hw_params,
1331 .set_sysclk = arizona_dai_set_sysclk,
1332 .set_tristate = arizona_set_tristate,
1334 EXPORT_SYMBOL_GPL(arizona_dai_ops);
1336 const struct snd_soc_dai_ops arizona_simple_dai_ops = {
1337 .startup = arizona_startup,
1338 .hw_params = arizona_hw_params_rate,
1339 .set_sysclk = arizona_dai_set_sysclk,
1341 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops);
1343 int arizona_init_dai(struct arizona_priv *priv, int id)
1345 struct arizona_dai_priv *dai_priv = &priv->dai[id];
1347 dai_priv->clk = ARIZONA_CLK_SYSCLK;
1351 EXPORT_SYMBOL_GPL(arizona_init_dai);
1353 static irqreturn_t arizona_fll_clock_ok(int irq, void *data)
1355 struct arizona_fll *fll = data;
1357 arizona_fll_dbg(fll, "clock OK\n");
1370 { 0, 64000, 4, 16 },
1371 { 64000, 128000, 3, 8 },
1372 { 128000, 256000, 2, 4 },
1373 { 256000, 1000000, 1, 2 },
1374 { 1000000, 13500000, 0, 1 },
1383 { 256000, 1000000, 2 },
1384 { 1000000, 13500000, 4 },
1387 struct arizona_fll_cfg {
1397 static int arizona_validate_fll(struct arizona_fll *fll,
1401 unsigned int Fvco_min;
1403 if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {
1404 arizona_fll_err(fll,
1405 "Can't scale %dMHz in to <=13.5MHz\n",
1410 Fvco_min = ARIZONA_FLL_MIN_FVCO * fll->vco_mult;
1411 if (Fout * ARIZONA_FLL_MAX_OUTDIV < Fvco_min) {
1412 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
1420 static int arizona_find_fratio(unsigned int Fref, int *fratio)
1424 /* Find an appropriate FLL_FRATIO */
1425 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1426 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1428 *fratio = fll_fratios[i].fratio;
1429 return fll_fratios[i].ratio;
1436 static int arizona_calc_fratio(struct arizona_fll *fll,
1437 struct arizona_fll_cfg *cfg,
1438 unsigned int target,
1439 unsigned int Fref, bool sync)
1441 int init_ratio, ratio;
1444 /* Fref must be <=13.5MHz, find initial refdiv */
1447 while (Fref > ARIZONA_FLL_MAX_FREF) {
1452 if (div > ARIZONA_FLL_MAX_REFDIV)
1456 /* Find an appropriate FLL_FRATIO */
1457 init_ratio = arizona_find_fratio(Fref, &cfg->fratio);
1458 if (init_ratio < 0) {
1459 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
1464 switch (fll->arizona->type) {
1466 if (fll->arizona->rev < 3 || sync)
1473 cfg->fratio = init_ratio - 1;
1475 /* Adjust FRATIO/refdiv to avoid integer mode if possible */
1476 refdiv = cfg->refdiv;
1478 while (div <= ARIZONA_FLL_MAX_REFDIV) {
1479 for (ratio = init_ratio; ratio <= ARIZONA_FLL_MAX_FRATIO;
1481 if (target % (ratio * Fref)) {
1482 cfg->refdiv = refdiv;
1483 cfg->fratio = ratio - 1;
1488 for (ratio = init_ratio - 1; ratio >= 0; ratio--) {
1489 if (ARIZONA_FLL_VCO_CORNER / (fll->vco_mult * ratio) <
1493 if (target % (ratio * Fref)) {
1494 cfg->refdiv = refdiv;
1495 cfg->fratio = ratio - 1;
1503 init_ratio = arizona_find_fratio(Fref, NULL);
1506 arizona_fll_warn(fll, "Falling back to integer mode operation\n");
1507 return cfg->fratio + 1;
1510 static int arizona_calc_fll(struct arizona_fll *fll,
1511 struct arizona_fll_cfg *cfg,
1512 unsigned int Fref, bool sync)
1514 unsigned int target, div, gcd_fll;
1517 arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, fll->fout);
1519 /* Fvco should be over the targt; don't check the upper bound */
1520 div = ARIZONA_FLL_MIN_OUTDIV;
1521 while (fll->fout * div < ARIZONA_FLL_MIN_FVCO * fll->vco_mult) {
1523 if (div > ARIZONA_FLL_MAX_OUTDIV)
1526 target = fll->fout * div / fll->vco_mult;
1529 arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
1531 /* Find an appropriate FLL_FRATIO and refdiv */
1532 ratio = arizona_calc_fratio(fll, cfg, target, Fref, sync);
1536 /* Apply the division for our remaining calculations */
1537 Fref = Fref / (1 << cfg->refdiv);
1539 cfg->n = target / (ratio * Fref);
1541 if (target % (ratio * Fref)) {
1542 gcd_fll = gcd(target, ratio * Fref);
1543 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
1545 cfg->theta = (target - (cfg->n * ratio * Fref))
1547 cfg->lambda = (ratio * Fref) / gcd_fll;
1553 /* Round down to 16bit range with cost of accuracy lost.
1554 * Denominator must be bigger than numerator so we only
1557 while (cfg->lambda >= (1 << 16)) {
1562 for (i = 0; i < ARRAY_SIZE(fll_gains); i++) {
1563 if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) {
1564 cfg->gain = fll_gains[i].gain;
1568 if (i == ARRAY_SIZE(fll_gains)) {
1569 arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n",
1574 arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
1575 cfg->n, cfg->theta, cfg->lambda);
1576 arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
1577 cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv);
1578 arizona_fll_dbg(fll, "GAIN=%d\n", cfg->gain);
1584 static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
1585 struct arizona_fll_cfg *cfg, int source,
1588 regmap_update_bits_async(arizona->regmap, base + 3,
1589 ARIZONA_FLL1_THETA_MASK, cfg->theta);
1590 regmap_update_bits_async(arizona->regmap, base + 4,
1591 ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
1592 regmap_update_bits_async(arizona->regmap, base + 5,
1593 ARIZONA_FLL1_FRATIO_MASK,
1594 cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
1595 regmap_update_bits_async(arizona->regmap, base + 6,
1596 ARIZONA_FLL1_CLK_REF_DIV_MASK |
1597 ARIZONA_FLL1_CLK_REF_SRC_MASK,
1598 cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
1599 source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
1602 regmap_update_bits(arizona->regmap, base + 0x7,
1603 ARIZONA_FLL1_GAIN_MASK,
1604 cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1606 regmap_update_bits(arizona->regmap, base + 0x5,
1607 ARIZONA_FLL1_OUTDIV_MASK,
1608 cfg->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
1609 regmap_update_bits(arizona->regmap, base + 0x9,
1610 ARIZONA_FLL1_GAIN_MASK,
1611 cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1614 regmap_update_bits_async(arizona->regmap, base + 2,
1615 ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
1616 ARIZONA_FLL1_CTRL_UPD | cfg->n);
1619 static bool arizona_is_enabled_fll(struct arizona_fll *fll)
1621 struct arizona *arizona = fll->arizona;
1625 ret = regmap_read(arizona->regmap, fll->base + 1, ®);
1627 arizona_fll_err(fll, "Failed to read current state: %d\n",
1632 return reg & ARIZONA_FLL1_ENA;
1635 static void arizona_enable_fll(struct arizona_fll *fll)
1637 struct arizona *arizona = fll->arizona;
1639 bool use_sync = false;
1640 struct arizona_fll_cfg cfg;
1643 * If we have both REFCLK and SYNCCLK then enable both,
1644 * otherwise apply the SYNCCLK settings to REFCLK.
1646 if (fll->ref_src >= 0 && fll->ref_freq &&
1647 fll->ref_src != fll->sync_src) {
1648 arizona_calc_fll(fll, &cfg, fll->ref_freq, false);
1650 arizona_apply_fll(arizona, fll->base, &cfg, fll->ref_src,
1652 if (fll->sync_src >= 0) {
1653 arizona_calc_fll(fll, &cfg, fll->sync_freq, true);
1655 arizona_apply_fll(arizona, fll->base + 0x10, &cfg,
1656 fll->sync_src, true);
1659 } else if (fll->sync_src >= 0) {
1660 arizona_calc_fll(fll, &cfg, fll->sync_freq, false);
1662 arizona_apply_fll(arizona, fll->base, &cfg,
1663 fll->sync_src, false);
1665 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
1666 ARIZONA_FLL1_SYNC_ENA, 0);
1668 arizona_fll_err(fll, "No clocks provided\n");
1673 * Increase the bandwidth if we're not using a low frequency
1676 if (use_sync && fll->sync_freq > 100000)
1677 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
1678 ARIZONA_FLL1_SYNC_BW, 0);
1680 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
1681 ARIZONA_FLL1_SYNC_BW,
1682 ARIZONA_FLL1_SYNC_BW);
1684 if (!arizona_is_enabled_fll(fll))
1685 pm_runtime_get(arizona->dev);
1687 /* Clear any pending completions */
1688 try_wait_for_completion(&fll->ok);
1690 regmap_update_bits_async(arizona->regmap, fll->base + 1,
1691 ARIZONA_FLL1_FREERUN, 0);
1692 regmap_update_bits_async(arizona->regmap, fll->base + 1,
1693 ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
1695 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
1696 ARIZONA_FLL1_SYNC_ENA,
1697 ARIZONA_FLL1_SYNC_ENA);
1699 ret = wait_for_completion_timeout(&fll->ok,
1700 msecs_to_jiffies(250));
1702 arizona_fll_warn(fll, "Timed out waiting for lock\n");
1705 static void arizona_disable_fll(struct arizona_fll *fll)
1707 struct arizona *arizona = fll->arizona;
1710 regmap_update_bits_async(arizona->regmap, fll->base + 1,
1711 ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
1712 regmap_update_bits_check(arizona->regmap, fll->base + 1,
1713 ARIZONA_FLL1_ENA, 0, &change);
1714 regmap_update_bits(arizona->regmap, fll->base + 0x11,
1715 ARIZONA_FLL1_SYNC_ENA, 0);
1718 pm_runtime_put_autosuspend(arizona->dev);
1721 int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
1722 unsigned int Fref, unsigned int Fout)
1726 if (fll->ref_src == source && fll->ref_freq == Fref)
1729 if (fll->fout && Fref > 0) {
1730 ret = arizona_validate_fll(fll, Fref, fll->fout);
1735 fll->ref_src = source;
1736 fll->ref_freq = Fref;
1738 if (fll->fout && Fref > 0) {
1739 arizona_enable_fll(fll);
1744 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk);
1746 int arizona_set_fll(struct arizona_fll *fll, int source,
1747 unsigned int Fref, unsigned int Fout)
1751 if (fll->sync_src == source &&
1752 fll->sync_freq == Fref && fll->fout == Fout)
1756 if (fll->ref_src >= 0) {
1757 ret = arizona_validate_fll(fll, fll->ref_freq, Fout);
1762 ret = arizona_validate_fll(fll, Fref, Fout);
1767 fll->sync_src = source;
1768 fll->sync_freq = Fref;
1772 arizona_enable_fll(fll);
1774 arizona_disable_fll(fll);
1779 EXPORT_SYMBOL_GPL(arizona_set_fll);
1781 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
1782 int ok_irq, struct arizona_fll *fll)
1787 init_completion(&fll->ok);
1791 fll->arizona = arizona;
1792 fll->sync_src = ARIZONA_FLL_SRC_NONE;
1794 /* Configure default refclk to 32kHz if we have one */
1795 regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
1796 switch (val & ARIZONA_CLK_32K_SRC_MASK) {
1797 case ARIZONA_CLK_SRC_MCLK1:
1798 case ARIZONA_CLK_SRC_MCLK2:
1799 fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK;
1802 fll->ref_src = ARIZONA_FLL_SRC_NONE;
1804 fll->ref_freq = 32768;
1806 snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
1807 snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
1808 "FLL%d clock OK", id);
1810 ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name,
1811 arizona_fll_clock_ok, fll);
1813 dev_err(arizona->dev, "Failed to get FLL%d clock OK IRQ: %d\n",
1817 regmap_update_bits(arizona->regmap, fll->base + 1,
1818 ARIZONA_FLL1_FREERUN, 0);
1822 EXPORT_SYMBOL_GPL(arizona_init_fll);
1825 * arizona_set_output_mode - Set the mode of the specified output
1827 * @codec: Device to configure
1828 * @output: Output number
1829 * @diff: True to set the output to differential mode
1831 * Some systems use external analogue switches to connect more
1832 * analogue devices to the CODEC than are supported by the device. In
1833 * some systems this requires changing the switched output from single
1834 * ended to differential mode dynamically at runtime, an operation
1835 * supported using this function.
1837 * Most systems have a single static configuration and should use
1838 * platform data instead.
1840 int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff)
1842 unsigned int reg, val;
1844 if (output < 1 || output > 6)
1847 reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
1850 val = ARIZONA_OUT1_MONO;
1854 return snd_soc_update_bits(codec, reg, ARIZONA_OUT1_MONO, val);
1856 EXPORT_SYMBOL_GPL(arizona_set_output_mode);
1858 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
1859 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1860 MODULE_LICENSE("GPL");