1 // SPDX-License-Identifier: GPL-2.0-only
3 * ADAU1977/ADAU1978/ADAU1979 driver
5 * Copyright 2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/i2c.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/platform_data/adau1977.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/slab.h>
20 #include <sound/core.h>
21 #include <sound/initval.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/tlv.h>
29 #define ADAU1977_REG_POWER 0x00
30 #define ADAU1977_REG_PLL 0x01
31 #define ADAU1977_REG_BOOST 0x02
32 #define ADAU1977_REG_MICBIAS 0x03
33 #define ADAU1977_REG_BLOCK_POWER_SAI 0x04
34 #define ADAU1977_REG_SAI_CTRL0 0x05
35 #define ADAU1977_REG_SAI_CTRL1 0x06
36 #define ADAU1977_REG_CMAP12 0x07
37 #define ADAU1977_REG_CMAP34 0x08
38 #define ADAU1977_REG_SAI_OVERTEMP 0x09
39 #define ADAU1977_REG_POST_ADC_GAIN(x) (0x0a + (x))
40 #define ADAU1977_REG_MISC_CONTROL 0x0e
41 #define ADAU1977_REG_DIAG_CONTROL 0x10
42 #define ADAU1977_REG_STATUS(x) (0x11 + (x))
43 #define ADAU1977_REG_DIAG_IRQ1 0x15
44 #define ADAU1977_REG_DIAG_IRQ2 0x16
45 #define ADAU1977_REG_ADJUST1 0x17
46 #define ADAU1977_REG_ADJUST2 0x18
47 #define ADAU1977_REG_ADC_CLIP 0x19
48 #define ADAU1977_REG_DC_HPF_CAL 0x1a
50 #define ADAU1977_POWER_RESET BIT(7)
51 #define ADAU1977_POWER_PWUP BIT(0)
53 #define ADAU1977_PLL_CLK_S BIT(4)
54 #define ADAU1977_PLL_MCS_MASK 0x7
56 #define ADAU1977_MICBIAS_MB_VOLTS_MASK 0xf0
57 #define ADAU1977_MICBIAS_MB_VOLTS_OFFSET 4
59 #define ADAU1977_BLOCK_POWER_SAI_LR_POL BIT(7)
60 #define ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE BIT(6)
61 #define ADAU1977_BLOCK_POWER_SAI_LDO_EN BIT(5)
63 #define ADAU1977_SAI_CTRL0_FMT_MASK (0x3 << 6)
64 #define ADAU1977_SAI_CTRL0_FMT_I2S (0x0 << 6)
65 #define ADAU1977_SAI_CTRL0_FMT_LJ (0x1 << 6)
66 #define ADAU1977_SAI_CTRL0_FMT_RJ_24BIT (0x2 << 6)
67 #define ADAU1977_SAI_CTRL0_FMT_RJ_16BIT (0x3 << 6)
69 #define ADAU1977_SAI_CTRL0_SAI_MASK (0x7 << 3)
70 #define ADAU1977_SAI_CTRL0_SAI_I2S (0x0 << 3)
71 #define ADAU1977_SAI_CTRL0_SAI_TDM_2 (0x1 << 3)
72 #define ADAU1977_SAI_CTRL0_SAI_TDM_4 (0x2 << 3)
73 #define ADAU1977_SAI_CTRL0_SAI_TDM_8 (0x3 << 3)
74 #define ADAU1977_SAI_CTRL0_SAI_TDM_16 (0x4 << 3)
76 #define ADAU1977_SAI_CTRL0_FS_MASK (0x7)
77 #define ADAU1977_SAI_CTRL0_FS_8000_12000 (0x0)
78 #define ADAU1977_SAI_CTRL0_FS_16000_24000 (0x1)
79 #define ADAU1977_SAI_CTRL0_FS_32000_48000 (0x2)
80 #define ADAU1977_SAI_CTRL0_FS_64000_96000 (0x3)
81 #define ADAU1977_SAI_CTRL0_FS_128000_192000 (0x4)
83 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK (0x3 << 5)
84 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_32 (0x0 << 5)
85 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_24 (0x1 << 5)
86 #define ADAU1977_SAI_CTRL1_SLOT_WIDTH_16 (0x2 << 5)
87 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK (0x1 << 4)
88 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT (0x1 << 4)
89 #define ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT (0x0 << 4)
90 #define ADAU1977_SAI_CTRL1_LRCLK_PULSE BIT(3)
91 #define ADAU1977_SAI_CTRL1_MSB BIT(2)
92 #define ADAU1977_SAI_CTRL1_BCLKRATE_16 (0x1 << 1)
93 #define ADAU1977_SAI_CTRL1_BCLKRATE_32 (0x0 << 1)
94 #define ADAU1977_SAI_CTRL1_BCLKRATE_MASK (0x1 << 1)
95 #define ADAU1977_SAI_CTRL1_MASTER BIT(0)
97 #define ADAU1977_SAI_OVERTEMP_DRV_C(x) BIT(4 + (x))
98 #define ADAU1977_SAI_OVERTEMP_DRV_HIZ BIT(3)
100 #define ADAU1977_MISC_CONTROL_SUM_MODE_MASK (0x3 << 6)
101 #define ADAU1977_MISC_CONTROL_SUM_MODE_1CH (0x2 << 6)
102 #define ADAU1977_MISC_CONTROL_SUM_MODE_2CH (0x1 << 6)
103 #define ADAU1977_MISC_CONTROL_SUM_MODE_4CH (0x0 << 6)
104 #define ADAU1977_MISC_CONTROL_MMUTE BIT(4)
105 #define ADAU1977_MISC_CONTROL_DC_CAL BIT(0)
107 #define ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET 4
108 #define ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET 0
111 struct regmap *regmap;
114 enum adau1977_sysclk_src sysclk_src;
115 struct gpio_desc *reset_gpio;
116 enum adau1977_type type;
118 struct regulator *avdd_reg;
119 struct regulator *dvdd_reg;
121 struct snd_pcm_hw_constraint_list constraints;
124 void (*switch_mode)(struct device *dev);
126 unsigned int max_master_fs;
127 unsigned int slot_width;
132 static const struct reg_default adau1977_reg_defaults[] = {
156 static const DECLARE_TLV_DB_MINMAX_MUTE(adau1977_adc_gain, -3562, 6000);
158 static const struct snd_soc_dapm_widget adau1977_micbias_dapm_widgets[] = {
159 SND_SOC_DAPM_SUPPLY("MICBIAS", ADAU1977_REG_MICBIAS,
163 static const struct snd_soc_dapm_widget adau1977_dapm_widgets[] = {
164 SND_SOC_DAPM_SUPPLY("Vref", ADAU1977_REG_BLOCK_POWER_SAI,
167 SND_SOC_DAPM_ADC("ADC1", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 0, 0),
168 SND_SOC_DAPM_ADC("ADC2", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 1, 0),
169 SND_SOC_DAPM_ADC("ADC3", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 2, 0),
170 SND_SOC_DAPM_ADC("ADC4", "Capture", ADAU1977_REG_BLOCK_POWER_SAI, 3, 0),
172 SND_SOC_DAPM_INPUT("AIN1"),
173 SND_SOC_DAPM_INPUT("AIN2"),
174 SND_SOC_DAPM_INPUT("AIN3"),
175 SND_SOC_DAPM_INPUT("AIN4"),
177 SND_SOC_DAPM_OUTPUT("VREF"),
180 static const struct snd_soc_dapm_route adau1977_dapm_routes[] = {
181 { "ADC1", NULL, "AIN1" },
182 { "ADC2", NULL, "AIN2" },
183 { "ADC3", NULL, "AIN3" },
184 { "ADC4", NULL, "AIN4" },
186 { "ADC1", NULL, "Vref" },
187 { "ADC2", NULL, "Vref" },
188 { "ADC3", NULL, "Vref" },
189 { "ADC4", NULL, "Vref" },
191 { "VREF", NULL, "Vref" },
194 #define ADAU1977_VOLUME(x) \
195 SOC_SINGLE_TLV("ADC" #x " Capture Volume", \
196 ADAU1977_REG_POST_ADC_GAIN((x) - 1), \
197 0, 255, 1, adau1977_adc_gain)
199 #define ADAU1977_HPF_SWITCH(x) \
200 SOC_SINGLE("ADC" #x " Highpass-Filter Capture Switch", \
201 ADAU1977_REG_DC_HPF_CAL, (x) - 1, 1, 0)
203 #define ADAU1977_DC_SUB_SWITCH(x) \
204 SOC_SINGLE("ADC" #x " DC Subtraction Capture Switch", \
205 ADAU1977_REG_DC_HPF_CAL, (x) + 3, 1, 0)
207 static const struct snd_kcontrol_new adau1977_snd_controls[] = {
213 ADAU1977_HPF_SWITCH(1),
214 ADAU1977_HPF_SWITCH(2),
215 ADAU1977_HPF_SWITCH(3),
216 ADAU1977_HPF_SWITCH(4),
218 ADAU1977_DC_SUB_SWITCH(1),
219 ADAU1977_DC_SUB_SWITCH(2),
220 ADAU1977_DC_SUB_SWITCH(3),
221 ADAU1977_DC_SUB_SWITCH(4),
224 static int adau1977_reset(struct adau1977 *adau1977)
229 * The reset bit is obviously volatile, but we need to be able to cache
230 * the other bits in the register, so we can't just mark the whole
231 * register as volatile. Since this is the only place where we'll ever
232 * touch the reset bit just bypass the cache for this operation.
234 regcache_cache_bypass(adau1977->regmap, true);
235 ret = regmap_write(adau1977->regmap, ADAU1977_REG_POWER,
236 ADAU1977_POWER_RESET);
237 regcache_cache_bypass(adau1977->regmap, false);
245 * Returns the appropriate setting for ths FS field in the CTRL0 register
246 * depending on the rate.
248 static int adau1977_lookup_fs(unsigned int rate)
250 if (rate >= 8000 && rate <= 12000)
251 return ADAU1977_SAI_CTRL0_FS_8000_12000;
252 else if (rate >= 16000 && rate <= 24000)
253 return ADAU1977_SAI_CTRL0_FS_16000_24000;
254 else if (rate >= 32000 && rate <= 48000)
255 return ADAU1977_SAI_CTRL0_FS_32000_48000;
256 else if (rate >= 64000 && rate <= 96000)
257 return ADAU1977_SAI_CTRL0_FS_64000_96000;
258 else if (rate >= 128000 && rate <= 192000)
259 return ADAU1977_SAI_CTRL0_FS_128000_192000;
264 static int adau1977_lookup_mcs(struct adau1977 *adau1977, unsigned int rate,
270 * rate = sysclk / (512 * mcs_lut[mcs]) * 2**fs
271 * => mcs_lut[mcs] = sysclk / (512 * rate) * 2**fs
272 * => mcs_lut[mcs] = sysclk / ((512 / 2**fs) * rate)
277 if (adau1977->sysclk % rate != 0)
280 mcs = adau1977->sysclk / rate;
282 /* The factors configured by MCS are 1, 2, 3, 4, 6 */
283 if (mcs < 1 || mcs > 6 || mcs == 5)
293 static int adau1977_hw_params(struct snd_pcm_substream *substream,
294 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
296 struct snd_soc_component *component = dai->component;
297 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
298 unsigned int rate = params_rate(params);
299 unsigned int slot_width;
300 unsigned int ctrl0, ctrl0_mask;
305 fs = adau1977_lookup_fs(rate);
309 if (adau1977->sysclk_src == ADAU1977_SYSCLK_SRC_MCLK) {
310 mcs = adau1977_lookup_mcs(adau1977, rate, fs);
317 ctrl0_mask = ADAU1977_SAI_CTRL0_FS_MASK;
320 if (adau1977->right_j) {
321 switch (params_width(params)) {
323 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_16BIT;
326 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
331 ctrl0_mask |= ADAU1977_SAI_CTRL0_FMT_MASK;
334 if (adau1977->master) {
335 switch (params_width(params)) {
337 ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_16BIT;
342 ctrl1 = ADAU1977_SAI_CTRL1_DATA_WIDTH_24BIT;
349 /* In TDM mode there is a fixed slot width */
350 if (adau1977->slot_width)
351 slot_width = adau1977->slot_width;
353 if (slot_width == 16)
354 ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_16;
356 ctrl1 |= ADAU1977_SAI_CTRL1_BCLKRATE_32;
358 ret = regmap_update_bits(adau1977->regmap,
359 ADAU1977_REG_SAI_CTRL1,
360 ADAU1977_SAI_CTRL1_DATA_WIDTH_MASK |
361 ADAU1977_SAI_CTRL1_BCLKRATE_MASK,
367 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
372 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
373 ADAU1977_PLL_MCS_MASK, mcs);
376 static int adau1977_power_disable(struct adau1977 *adau1977)
380 if (!adau1977->enabled)
383 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
384 ADAU1977_POWER_PWUP, 0);
388 regcache_mark_dirty(adau1977->regmap);
390 gpiod_set_value_cansleep(adau1977->reset_gpio, 0);
392 regcache_cache_only(adau1977->regmap, true);
394 regulator_disable(adau1977->avdd_reg);
395 if (adau1977->dvdd_reg)
396 regulator_disable(adau1977->dvdd_reg);
398 adau1977->enabled = false;
403 static int adau1977_power_enable(struct adau1977 *adau1977)
408 if (adau1977->enabled)
411 ret = regulator_enable(adau1977->avdd_reg);
415 if (adau1977->dvdd_reg) {
416 ret = regulator_enable(adau1977->dvdd_reg);
418 goto err_disable_avdd;
421 gpiod_set_value_cansleep(adau1977->reset_gpio, 1);
423 regcache_cache_only(adau1977->regmap, false);
425 if (adau1977->switch_mode)
426 adau1977->switch_mode(adau1977->dev);
428 ret = adau1977_reset(adau1977);
430 goto err_disable_dvdd;
432 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER,
433 ADAU1977_POWER_PWUP, ADAU1977_POWER_PWUP);
435 goto err_disable_dvdd;
437 ret = regcache_sync(adau1977->regmap);
439 goto err_disable_dvdd;
442 * The PLL register is not affected by the software reset. It is
443 * possible that the value of the register was changed to the
444 * default value while we were in cache only mode. In this case
445 * regcache_sync will skip over it and we have to manually sync
448 ret = regmap_read(adau1977->regmap, ADAU1977_REG_PLL, &val);
450 goto err_disable_dvdd;
453 regcache_cache_bypass(adau1977->regmap, true);
454 ret = regmap_write(adau1977->regmap, ADAU1977_REG_PLL,
457 goto err_disable_dvdd;
458 regcache_cache_bypass(adau1977->regmap, false);
461 adau1977->enabled = true;
466 if (adau1977->dvdd_reg)
467 regulator_disable(adau1977->dvdd_reg);
469 regulator_disable(adau1977->avdd_reg);
473 static int adau1977_set_bias_level(struct snd_soc_component *component,
474 enum snd_soc_bias_level level)
476 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
480 case SND_SOC_BIAS_ON:
482 case SND_SOC_BIAS_PREPARE:
484 case SND_SOC_BIAS_STANDBY:
485 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
486 ret = adau1977_power_enable(adau1977);
488 case SND_SOC_BIAS_OFF:
489 ret = adau1977_power_disable(adau1977);
496 static int adau1977_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
497 unsigned int rx_mask, int slots, int width)
499 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
500 unsigned int ctrl0, ctrl1, drv;
501 unsigned int slot[4];
506 /* 0 = No fixed slot width */
507 adau1977->slot_width = 0;
508 adau1977->max_master_fs = 192000;
509 return regmap_update_bits(adau1977->regmap,
510 ADAU1977_REG_SAI_CTRL0, ADAU1977_SAI_CTRL0_SAI_MASK,
511 ADAU1977_SAI_CTRL0_SAI_I2S);
514 if (rx_mask == 0 || tx_mask != 0)
518 for (i = 0; i < 4; i++) {
519 slot[i] = __ffs(rx_mask);
520 drv |= ADAU1977_SAI_OVERTEMP_DRV_C(i);
521 rx_mask &= ~(1 << slot[i]);
522 if (slot[i] >= slots)
533 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_16;
536 /* We can only generate 16 bit or 32 bit wide slots */
537 if (adau1977->master)
539 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_24;
542 ctrl1 = ADAU1977_SAI_CTRL1_SLOT_WIDTH_32;
550 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_2;
553 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_4;
556 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_8;
559 ctrl0 = ADAU1977_SAI_CTRL0_SAI_TDM_16;
565 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
566 ADAU1977_SAI_OVERTEMP_DRV_C(0) |
567 ADAU1977_SAI_OVERTEMP_DRV_C(1) |
568 ADAU1977_SAI_OVERTEMP_DRV_C(2) |
569 ADAU1977_SAI_OVERTEMP_DRV_C(3), drv);
573 ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP12,
574 (slot[1] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
575 (slot[0] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
579 ret = regmap_write(adau1977->regmap, ADAU1977_REG_CMAP34,
580 (slot[3] << ADAU1977_CHAN_MAP_SECOND_SLOT_OFFSET) |
581 (slot[2] << ADAU1977_CHAN_MAP_FIRST_SLOT_OFFSET));
585 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
586 ADAU1977_SAI_CTRL0_SAI_MASK, ctrl0);
590 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
591 ADAU1977_SAI_CTRL1_SLOT_WIDTH_MASK, ctrl1);
595 adau1977->slot_width = width;
597 /* In master mode the maximum bitclock is 24.576 MHz */
598 adau1977->max_master_fs = min(192000, 24576000 / width / slots);
603 static int adau1977_mute(struct snd_soc_dai *dai, int mute, int stream)
605 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
609 val = ADAU1977_MISC_CONTROL_MMUTE;
613 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MISC_CONTROL,
614 ADAU1977_MISC_CONTROL_MMUTE, val);
617 static int adau1977_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
619 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
620 unsigned int ctrl0 = 0, ctrl1 = 0, block_power = 0;
624 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
625 case SND_SOC_DAIFMT_CBS_CFS:
626 adau1977->master = false;
628 case SND_SOC_DAIFMT_CBM_CFM:
629 ctrl1 |= ADAU1977_SAI_CTRL1_MASTER;
630 adau1977->master = true;
636 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
637 case SND_SOC_DAIFMT_NB_NF:
638 invert_lrclk = false;
640 case SND_SOC_DAIFMT_IB_NF:
641 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
642 invert_lrclk = false;
644 case SND_SOC_DAIFMT_NB_IF:
647 case SND_SOC_DAIFMT_IB_IF:
648 block_power |= ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE;
655 adau1977->right_j = false;
656 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
657 case SND_SOC_DAIFMT_I2S:
658 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
660 case SND_SOC_DAIFMT_LEFT_J:
661 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
662 invert_lrclk = !invert_lrclk;
664 case SND_SOC_DAIFMT_RIGHT_J:
665 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_RJ_24BIT;
666 adau1977->right_j = true;
667 invert_lrclk = !invert_lrclk;
669 case SND_SOC_DAIFMT_DSP_A:
670 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
671 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_I2S;
672 invert_lrclk = false;
674 case SND_SOC_DAIFMT_DSP_B:
675 ctrl1 |= ADAU1977_SAI_CTRL1_LRCLK_PULSE;
676 ctrl0 |= ADAU1977_SAI_CTRL0_FMT_LJ;
677 invert_lrclk = false;
684 block_power |= ADAU1977_BLOCK_POWER_SAI_LR_POL;
686 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
687 ADAU1977_BLOCK_POWER_SAI_LR_POL |
688 ADAU1977_BLOCK_POWER_SAI_BCLK_EDGE, block_power);
692 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL0,
693 ADAU1977_SAI_CTRL0_FMT_MASK,
698 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_CTRL1,
699 ADAU1977_SAI_CTRL1_MASTER | ADAU1977_SAI_CTRL1_LRCLK_PULSE,
703 static int adau1977_startup(struct snd_pcm_substream *substream,
704 struct snd_soc_dai *dai)
706 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
709 if (adau1977->slot_width == 16)
710 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE;
711 else if (adau1977->right_j || adau1977->slot_width == 24)
712 formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
713 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE;
715 snd_pcm_hw_constraint_list(substream->runtime, 0,
716 SNDRV_PCM_HW_PARAM_RATE, &adau1977->constraints);
718 if (adau1977->master)
719 snd_pcm_hw_constraint_minmax(substream->runtime,
720 SNDRV_PCM_HW_PARAM_RATE, 8000, adau1977->max_master_fs);
723 snd_pcm_hw_constraint_mask64(substream->runtime,
724 SNDRV_PCM_HW_PARAM_FORMAT, formats);
729 static int adau1977_set_tristate(struct snd_soc_dai *dai, int tristate)
731 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(dai->component);
735 val = ADAU1977_SAI_OVERTEMP_DRV_HIZ;
739 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_SAI_OVERTEMP,
740 ADAU1977_SAI_OVERTEMP_DRV_HIZ, val);
743 static const struct snd_soc_dai_ops adau1977_dai_ops = {
744 .startup = adau1977_startup,
745 .hw_params = adau1977_hw_params,
746 .mute_stream = adau1977_mute,
747 .set_fmt = adau1977_set_dai_fmt,
748 .set_tdm_slot = adau1977_set_tdm_slot,
749 .set_tristate = adau1977_set_tristate,
752 static struct snd_soc_dai_driver adau1977_dai = {
753 .name = "adau1977-hifi",
755 .stream_name = "Capture",
758 .rates = SNDRV_PCM_RATE_KNOT,
759 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
760 SNDRV_PCM_FMTBIT_S32_LE,
763 .ops = &adau1977_dai_ops,
766 static const unsigned int adau1977_rates[] = {
767 8000, 16000, 32000, 64000, 128000,
768 11025, 22050, 44100, 88200, 172400,
769 12000, 24000, 48000, 96000, 192000,
772 #define ADAU1977_RATE_CONSTRAINT_MASK_32000 0x001f
773 #define ADAU1977_RATE_CONSTRAINT_MASK_44100 0x03e0
774 #define ADAU1977_RATE_CONSTRAINT_MASK_48000 0x7c00
775 /* All rates >= 32000 */
776 #define ADAU1977_RATE_CONSTRAINT_MASK_LRCLK 0x739c
778 static bool adau1977_check_sysclk(unsigned int mclk, unsigned int base_freq)
782 if (mclk % (base_freq * 128) != 0)
785 mcs = mclk / (128 * base_freq);
786 if (mcs < 1 || mcs > 6 || mcs == 5)
792 static int adau1977_set_sysclk(struct snd_soc_component *component,
793 int clk_id, int source, unsigned int freq, int dir)
795 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
796 unsigned int mask = 0;
797 unsigned int clk_src;
800 if (dir != SND_SOC_CLOCK_IN)
803 if (clk_id != ADAU1977_SYSCLK)
807 case ADAU1977_SYSCLK_SRC_MCLK:
810 case ADAU1977_SYSCLK_SRC_LRCLK:
811 clk_src = ADAU1977_PLL_CLK_S;
817 if (freq != 0 && source == ADAU1977_SYSCLK_SRC_MCLK) {
818 if (freq < 4000000 || freq > 36864000)
821 if (adau1977_check_sysclk(freq, 32000))
822 mask |= ADAU1977_RATE_CONSTRAINT_MASK_32000;
823 if (adau1977_check_sysclk(freq, 44100))
824 mask |= ADAU1977_RATE_CONSTRAINT_MASK_44100;
825 if (adau1977_check_sysclk(freq, 48000))
826 mask |= ADAU1977_RATE_CONSTRAINT_MASK_48000;
830 } else if (source == ADAU1977_SYSCLK_SRC_LRCLK) {
831 mask = ADAU1977_RATE_CONSTRAINT_MASK_LRCLK;
834 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_PLL,
835 ADAU1977_PLL_CLK_S, clk_src);
839 adau1977->constraints.mask = mask;
840 adau1977->sysclk_src = source;
841 adau1977->sysclk = freq;
846 static int adau1977_component_probe(struct snd_soc_component *component)
848 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
849 struct adau1977 *adau1977 = snd_soc_component_get_drvdata(component);
852 switch (adau1977->type) {
854 ret = snd_soc_dapm_new_controls(dapm,
855 adau1977_micbias_dapm_widgets,
856 ARRAY_SIZE(adau1977_micbias_dapm_widgets));
867 static const struct snd_soc_component_driver adau1977_component_driver = {
868 .probe = adau1977_component_probe,
869 .set_bias_level = adau1977_set_bias_level,
870 .set_sysclk = adau1977_set_sysclk,
871 .controls = adau1977_snd_controls,
872 .num_controls = ARRAY_SIZE(adau1977_snd_controls),
873 .dapm_widgets = adau1977_dapm_widgets,
874 .num_dapm_widgets = ARRAY_SIZE(adau1977_dapm_widgets),
875 .dapm_routes = adau1977_dapm_routes,
876 .num_dapm_routes = ARRAY_SIZE(adau1977_dapm_routes),
877 .use_pmdown_time = 1,
879 .non_legacy_dai_naming = 1,
882 static int adau1977_setup_micbias(struct adau1977 *adau1977)
884 struct adau1977_platform_data *pdata = adau1977->dev->platform_data;
885 unsigned int micbias;
888 micbias = pdata->micbias;
889 else if (device_property_read_u32(adau1977->dev, "adi,micbias",
891 micbias = ADAU1977_MICBIAS_8V5;
893 if (micbias > ADAU1977_MICBIAS_9V0) {
894 dev_err(adau1977->dev, "Invalid value for 'adi,micbias'\n");
898 return regmap_update_bits(adau1977->regmap, ADAU1977_REG_MICBIAS,
899 ADAU1977_MICBIAS_MB_VOLTS_MASK,
900 micbias << ADAU1977_MICBIAS_MB_VOLTS_OFFSET);
903 int adau1977_probe(struct device *dev, struct regmap *regmap,
904 enum adau1977_type type, void (*switch_mode)(struct device *dev))
906 unsigned int power_off_mask;
907 struct adau1977 *adau1977;
911 return PTR_ERR(regmap);
913 adau1977 = devm_kzalloc(dev, sizeof(*adau1977), GFP_KERNEL);
914 if (adau1977 == NULL)
918 adau1977->type = type;
919 adau1977->regmap = regmap;
920 adau1977->switch_mode = switch_mode;
921 adau1977->max_master_fs = 192000;
923 adau1977->constraints.list = adau1977_rates;
924 adau1977->constraints.count = ARRAY_SIZE(adau1977_rates);
926 adau1977->avdd_reg = devm_regulator_get(dev, "AVDD");
927 if (IS_ERR(adau1977->avdd_reg))
928 return PTR_ERR(adau1977->avdd_reg);
930 adau1977->dvdd_reg = devm_regulator_get_optional(dev, "DVDD");
931 if (IS_ERR(adau1977->dvdd_reg)) {
932 if (PTR_ERR(adau1977->dvdd_reg) != -ENODEV)
933 return PTR_ERR(adau1977->dvdd_reg);
934 adau1977->dvdd_reg = NULL;
937 adau1977->reset_gpio = devm_gpiod_get_optional(dev, "reset",
939 if (IS_ERR(adau1977->reset_gpio))
940 return PTR_ERR(adau1977->reset_gpio);
942 dev_set_drvdata(dev, adau1977);
944 if (adau1977->reset_gpio)
947 ret = adau1977_power_enable(adau1977);
951 if (type == ADAU1977) {
952 ret = adau1977_setup_micbias(adau1977);
957 if (adau1977->dvdd_reg)
960 power_off_mask = (unsigned int)~ADAU1977_BLOCK_POWER_SAI_LDO_EN;
962 ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_BLOCK_POWER_SAI,
963 power_off_mask, 0x00);
967 ret = adau1977_power_disable(adau1977);
971 return devm_snd_soc_register_component(dev, &adau1977_component_driver,
975 adau1977_power_disable(adau1977);
979 EXPORT_SYMBOL_GPL(adau1977_probe);
981 static bool adau1977_register_volatile(struct device *dev, unsigned int reg)
984 case ADAU1977_REG_STATUS(0):
985 case ADAU1977_REG_STATUS(1):
986 case ADAU1977_REG_STATUS(2):
987 case ADAU1977_REG_STATUS(3):
988 case ADAU1977_REG_ADC_CLIP:
995 const struct regmap_config adau1977_regmap_config = {
996 .max_register = ADAU1977_REG_DC_HPF_CAL,
997 .volatile_reg = adau1977_register_volatile,
999 .cache_type = REGCACHE_RBTREE,
1000 .reg_defaults = adau1977_reg_defaults,
1001 .num_reg_defaults = ARRAY_SIZE(adau1977_reg_defaults),
1003 EXPORT_SYMBOL_GPL(adau1977_regmap_config);
1005 MODULE_DESCRIPTION("ASoC ADAU1977/ADAU1978/ADAU1979 driver");
1006 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1007 MODULE_LICENSE("GPL");