1 // SPDX-License-Identifier: GPL-2.0
3 // Driver for Microchip S/PDIF TX Controller
5 // Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
7 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
11 #include <linux/module.h>
12 #include <linux/spinlock.h>
14 #include <sound/asoundef.h>
15 #include <sound/dmaengine_pcm.h>
16 #include <sound/pcm_params.h>
17 #include <sound/soc.h>
20 * ---- S/PDIF Transmitter Controller Register map ----
22 #define SPDIFTX_CR 0x00 /* Control Register */
23 #define SPDIFTX_MR 0x04 /* Mode Register */
24 #define SPDIFTX_CDR 0x0C /* Common Data Register */
26 #define SPDIFTX_IER 0x14 /* Interrupt Enable Register */
27 #define SPDIFTX_IDR 0x18 /* Interrupt Disable Register */
28 #define SPDIFTX_IMR 0x1C /* Interrupt Mask Register */
29 #define SPDIFTX_ISR 0x20 /* Interrupt Status Register */
31 #define SPDIFTX_CH1UD(reg) (0x50 + (reg) * 4) /* User Data 1 Register x */
32 #define SPDIFTX_CH1S(reg) (0x80 + (reg) * 4) /* Channel Status 1 Register x */
34 #define SPDIFTX_VERSION 0xF0
37 * ---- Control Register (Write-only) ----
39 #define SPDIFTX_CR_SWRST BIT(0) /* Software Reset */
40 #define SPDIFTX_CR_FCLR BIT(1) /* FIFO clear */
43 * ---- Mode Register (Read/Write) ----
46 #define SPDIFTX_MR_TXEN_MASK GENMASK(0, 0)
47 #define SPDIFTX_MR_TXEN_DISABLE (0 << 0)
48 #define SPDIFTX_MR_TXEN_ENABLE (1 << 0)
50 /* Multichannel Transfer */
51 #define SPDIFTX_MR_MULTICH_MASK GENAMSK(1, 1)
52 #define SPDIFTX_MR_MULTICH_MONO (0 << 1)
53 #define SPDIFTX_MR_MULTICH_DUAL (1 << 1)
55 /* Data Word Endian Mode */
56 #define SPDIFTX_MR_ENDIAN_MASK GENMASK(2, 2)
57 #define SPDIFTX_MR_ENDIAN_LITTLE (0 << 2)
58 #define SPDIFTX_MR_ENDIAN_BIG (1 << 2)
60 /* Data Justification */
61 #define SPDIFTX_MR_JUSTIFY_MASK GENMASK(3, 3)
62 #define SPDIFTX_MR_JUSTIFY_LSB (0 << 3)
63 #define SPDIFTX_MR_JUSTIFY_MSB (1 << 3)
65 /* Common Audio Register Transfer Mode */
66 #define SPDIFTX_MR_CMODE_MASK GENMASK(5, 4)
67 #define SPDIFTX_MR_CMODE_INDEX_ACCESS (0 << 4)
68 #define SPDIFTX_MR_CMODE_TOGGLE_ACCESS (1 << 4)
69 #define SPDIFTX_MR_CMODE_INTERLVD_ACCESS (2 << 4)
71 /* Valid Bits per Sample */
72 #define SPDIFTX_MR_VBPS_MASK GENMASK(13, 8)
73 #define SPDIFTX_MR_VBPS(bps) (((bps) << 8) & SPDIFTX_MR_VBPS_MASK)
76 #define SPDIFTX_MR_CHUNK_MASK GENMASK(19, 16)
77 #define SPDIFTX_MR_CHUNK(size) (((size) << 16) & SPDIFTX_MR_CHUNK_MASK)
79 /* Validity Bits for Channels 1 and 2 */
80 #define SPDIFTX_MR_VALID1 BIT(24)
81 #define SPDIFTX_MR_VALID2 BIT(25)
83 /* Disable Null Frame on underrrun */
84 #define SPDIFTX_MR_DNFR_MASK GENMASK(27, 27)
85 #define SPDIFTX_MR_DNFR_INVALID (0 << 27)
86 #define SPDIFTX_MR_DNFR_VALID (1 << 27)
88 /* Bytes per Sample */
89 #define SPDIFTX_MR_BPS_MASK GENMASK(29, 28)
90 #define SPDIFTX_MR_BPS(bytes) \
91 ((((bytes) - 1) << 28) & SPDIFTX_MR_BPS_MASK)
94 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ----
96 #define SPDIFTX_IR_TXRDY BIT(0)
97 #define SPDIFTX_IR_TXEMPTY BIT(1)
98 #define SPDIFTX_IR_TXFULL BIT(2)
99 #define SPDIFTX_IR_TXCHUNK BIT(3)
100 #define SPDIFTX_IR_TXUDR BIT(4)
101 #define SPDIFTX_IR_TXOVR BIT(5)
102 #define SPDIFTX_IR_CSRDY BIT(6)
103 #define SPDIFTX_IR_UDRDY BIT(7)
104 #define SPDIFTX_IR_TXRDYCH(ch) BIT((ch) + 8)
105 #define SPDIFTX_IR_SECE BIT(10)
106 #define SPDIFTX_IR_TXUDRCH(ch) BIT((ch) + 11)
107 #define SPDIFTX_IR_BEND BIT(13)
109 static bool mchp_spdiftx_readable_reg(struct device *dev, unsigned int reg)
115 case SPDIFTX_CH1UD(0):
116 case SPDIFTX_CH1UD(1):
117 case SPDIFTX_CH1UD(2):
118 case SPDIFTX_CH1UD(3):
119 case SPDIFTX_CH1UD(4):
120 case SPDIFTX_CH1UD(5):
121 case SPDIFTX_CH1S(0):
122 case SPDIFTX_CH1S(1):
123 case SPDIFTX_CH1S(2):
124 case SPDIFTX_CH1S(3):
125 case SPDIFTX_CH1S(4):
126 case SPDIFTX_CH1S(5):
133 static bool mchp_spdiftx_writeable_reg(struct device *dev, unsigned int reg)
141 case SPDIFTX_CH1UD(0):
142 case SPDIFTX_CH1UD(1):
143 case SPDIFTX_CH1UD(2):
144 case SPDIFTX_CH1UD(3):
145 case SPDIFTX_CH1UD(4):
146 case SPDIFTX_CH1UD(5):
147 case SPDIFTX_CH1S(0):
148 case SPDIFTX_CH1S(1):
149 case SPDIFTX_CH1S(2):
150 case SPDIFTX_CH1S(3):
151 case SPDIFTX_CH1S(4):
152 case SPDIFTX_CH1S(5):
159 static bool mchp_spdiftx_precious_reg(struct device *dev, unsigned int reg)
170 static const struct regmap_config mchp_spdiftx_regmap_config = {
174 .max_register = SPDIFTX_VERSION,
175 .readable_reg = mchp_spdiftx_readable_reg,
176 .writeable_reg = mchp_spdiftx_writeable_reg,
177 .precious_reg = mchp_spdiftx_precious_reg,
180 #define SPDIFTX_GCLK_RATIO 128
182 #define SPDIFTX_CS_BITS 192
183 #define SPDIFTX_UD_BITS 192
185 struct mchp_spdiftx_mixer_control {
186 unsigned char ch_stat[SPDIFTX_CS_BITS / 8];
187 unsigned char user_data[SPDIFTX_UD_BITS / 8];
188 spinlock_t lock; /* exclusive access to control data */
191 struct mchp_spdiftx_dev {
192 struct mchp_spdiftx_mixer_control control;
193 struct snd_dmaengine_dai_dma_data playback;
195 struct regmap *regmap;
199 const struct mchp_i2s_caps *caps;
203 static inline int mchp_spdiftx_is_running(struct mchp_spdiftx_dev *dev)
207 regmap_read(dev->regmap, SPDIFTX_MR, &mr);
208 return !!(mr & SPDIFTX_MR_TXEN_ENABLE);
211 static void mchp_spdiftx_channel_status_write(struct mchp_spdiftx_dev *dev)
213 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
217 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat) / 4; i++) {
218 val = (ctrl->ch_stat[(i * 4) + 0] << 0) |
219 (ctrl->ch_stat[(i * 4) + 1] << 8) |
220 (ctrl->ch_stat[(i * 4) + 2] << 16) |
221 (ctrl->ch_stat[(i * 4) + 3] << 24);
223 regmap_write(dev->regmap, SPDIFTX_CH1S(i), val);
227 static void mchp_spdiftx_user_data_write(struct mchp_spdiftx_dev *dev)
229 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
233 for (i = 0; i < ARRAY_SIZE(ctrl->user_data) / 4; i++) {
234 val = (ctrl->user_data[(i * 4) + 0] << 0) |
235 (ctrl->user_data[(i * 4) + 1] << 8) |
236 (ctrl->user_data[(i * 4) + 2] << 16) |
237 (ctrl->user_data[(i * 4) + 3] << 24);
239 regmap_write(dev->regmap, SPDIFTX_CH1UD(i), val);
243 static irqreturn_t mchp_spdiftx_interrupt(int irq, void *dev_id)
245 struct mchp_spdiftx_dev *dev = dev_id;
246 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
247 u32 sr, imr, pending, idr = 0;
249 regmap_read(dev->regmap, SPDIFTX_ISR, &sr);
250 regmap_read(dev->regmap, SPDIFTX_IMR, &imr);
256 if (pending & SPDIFTX_IR_TXUDR) {
257 dev_warn(dev->dev, "underflow detected\n");
258 idr |= SPDIFTX_IR_TXUDR;
261 if (pending & SPDIFTX_IR_TXOVR) {
262 dev_warn(dev->dev, "overflow detected\n");
263 idr |= SPDIFTX_IR_TXOVR;
266 if (pending & SPDIFTX_IR_UDRDY) {
267 spin_lock(&ctrl->lock);
268 mchp_spdiftx_user_data_write(dev);
269 spin_unlock(&ctrl->lock);
270 idr |= SPDIFTX_IR_UDRDY;
273 if (pending & SPDIFTX_IR_CSRDY) {
274 spin_lock(&ctrl->lock);
275 mchp_spdiftx_channel_status_write(dev);
276 spin_unlock(&ctrl->lock);
277 idr |= SPDIFTX_IR_CSRDY;
280 regmap_write(dev->regmap, SPDIFTX_IDR, idr);
285 static int mchp_spdiftx_dai_startup(struct snd_pcm_substream *substream,
286 struct snd_soc_dai *dai)
288 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
290 /* Software reset the IP */
291 regmap_write(dev->regmap, SPDIFTX_CR,
292 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR);
297 static void mchp_spdiftx_dai_shutdown(struct snd_pcm_substream *substream,
298 struct snd_soc_dai *dai)
300 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
302 /* Disable interrupts */
303 regmap_write(dev->regmap, SPDIFTX_IDR, 0xffffffff);
306 static int mchp_spdiftx_trigger(struct snd_pcm_substream *substream, int cmd,
307 struct snd_soc_dai *dai)
309 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
310 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
315 /* do not start/stop while channel status or user data is updated */
316 spin_lock(&ctrl->lock);
317 regmap_read(dev->regmap, SPDIFTX_MR, &mr);
318 running = !!(mr & SPDIFTX_MR_TXEN_ENABLE);
321 case SNDRV_PCM_TRIGGER_START:
322 case SNDRV_PCM_TRIGGER_RESUME:
323 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
325 mr &= ~SPDIFTX_MR_TXEN_MASK;
326 mr |= SPDIFTX_MR_TXEN_ENABLE;
329 case SNDRV_PCM_TRIGGER_STOP:
330 case SNDRV_PCM_TRIGGER_SUSPEND:
331 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
333 mr &= ~SPDIFTX_MR_TXEN_MASK;
334 mr |= SPDIFTX_MR_TXEN_DISABLE;
338 spin_unlock(&ctrl->lock);
342 ret = regmap_write(dev->regmap, SPDIFTX_MR, mr);
343 spin_unlock(&ctrl->lock);
345 dev_err(dev->dev, "unable to disable TX: %d\n", ret);
352 static int mchp_spdiftx_hw_params(struct snd_pcm_substream *substream,
353 struct snd_pcm_hw_params *params,
354 struct snd_soc_dai *dai)
357 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
358 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
360 unsigned int bps = params_physical_width(params) / 8;
363 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
364 __func__, params_rate(params), params_format(params),
365 params_width(params), params_channels(params));
367 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
368 dev_err(dev->dev, "Capture is not supported\n");
372 regmap_read(dev->regmap, SPDIFTX_MR, &mr);
374 if (mr & SPDIFTX_MR_TXEN_ENABLE) {
375 dev_err(dev->dev, "PCM already running\n");
379 /* Defaults: Toggle mode, justify to LSB, chunksize 1 */
380 mr = SPDIFTX_MR_CMODE_TOGGLE_ACCESS | SPDIFTX_MR_JUSTIFY_LSB;
381 dev->playback.maxburst = 1;
382 switch (params_channels(params)) {
384 mr |= SPDIFTX_MR_MULTICH_MONO;
387 mr |= SPDIFTX_MR_MULTICH_DUAL;
389 dev->playback.maxburst = 2;
392 dev_err(dev->dev, "unsupported number of channels: %d\n",
393 params_channels(params));
396 mr |= SPDIFTX_MR_CHUNK(dev->playback.maxburst);
398 switch (params_format(params)) {
399 case SNDRV_PCM_FORMAT_S8:
400 mr |= SPDIFTX_MR_VBPS(8);
402 case SNDRV_PCM_FORMAT_S16_BE:
403 mr |= SPDIFTX_MR_ENDIAN_BIG;
405 case SNDRV_PCM_FORMAT_S16_LE:
406 mr |= SPDIFTX_MR_VBPS(16);
408 case SNDRV_PCM_FORMAT_S18_3BE:
409 mr |= SPDIFTX_MR_ENDIAN_BIG;
411 case SNDRV_PCM_FORMAT_S18_3LE:
412 mr |= SPDIFTX_MR_VBPS(18);
414 case SNDRV_PCM_FORMAT_S20_3BE:
415 mr |= SPDIFTX_MR_ENDIAN_BIG;
417 case SNDRV_PCM_FORMAT_S20_3LE:
418 mr |= SPDIFTX_MR_VBPS(20);
420 case SNDRV_PCM_FORMAT_S24_3BE:
421 mr |= SPDIFTX_MR_ENDIAN_BIG;
423 case SNDRV_PCM_FORMAT_S24_3LE:
424 mr |= SPDIFTX_MR_VBPS(24);
426 case SNDRV_PCM_FORMAT_S24_BE:
427 mr |= SPDIFTX_MR_ENDIAN_BIG;
429 case SNDRV_PCM_FORMAT_S24_LE:
430 mr |= SPDIFTX_MR_VBPS(24);
432 case SNDRV_PCM_FORMAT_S32_BE:
433 mr |= SPDIFTX_MR_ENDIAN_BIG;
435 case SNDRV_PCM_FORMAT_S32_LE:
436 mr |= SPDIFTX_MR_VBPS(32);
439 dev_err(dev->dev, "unsupported PCM format: %d\n",
440 params_format(params));
444 mr |= SPDIFTX_MR_BPS(bps);
446 spin_lock_irqsave(&ctrl->lock, flags);
447 ctrl->ch_stat[3] &= ~IEC958_AES3_CON_FS;
448 switch (params_rate(params)) {
450 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_22050;
453 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_24000;
456 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_32000;
459 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_44100;
462 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_48000;
465 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_88200;
468 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_96000;
471 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_176400;
474 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_192000;
480 ctrl->ch_stat[3] |= IEC958_AES3_CON_FS_NOTID;
483 dev_err(dev->dev, "unsupported sample frequency: %u\n",
484 params_rate(params));
485 spin_unlock_irqrestore(&ctrl->lock, flags);
488 mchp_spdiftx_channel_status_write(dev);
489 spin_unlock_irqrestore(&ctrl->lock, flags);
490 mr |= SPDIFTX_MR_VALID1 | SPDIFTX_MR_VALID2;
492 if (dev->gclk_enabled) {
493 clk_disable_unprepare(dev->gclk);
494 dev->gclk_enabled = 0;
496 ret = clk_set_rate(dev->gclk, params_rate(params) *
500 "unable to change gclk rate to: rate %u * ratio %u\n",
501 params_rate(params), SPDIFTX_GCLK_RATIO);
504 ret = clk_prepare_enable(dev->gclk);
506 dev_err(dev->dev, "unable to enable gclk: %d\n", ret);
509 dev->gclk_enabled = 1;
510 dev_dbg(dev->dev, "%s(): GCLK set to %d\n", __func__,
511 params_rate(params) * SPDIFTX_GCLK_RATIO);
513 /* Enable interrupts */
514 regmap_write(dev->regmap, SPDIFTX_IER,
515 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR);
517 regmap_write(dev->regmap, SPDIFTX_MR, mr);
522 static int mchp_spdiftx_hw_free(struct snd_pcm_substream *substream,
523 struct snd_soc_dai *dai)
525 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
527 regmap_write(dev->regmap, SPDIFTX_IDR,
528 SPDIFTX_IR_TXUDR | SPDIFTX_IR_TXOVR);
529 if (dev->gclk_enabled) {
530 clk_disable_unprepare(dev->gclk);
531 dev->gclk_enabled = 0;
534 return regmap_write(dev->regmap, SPDIFTX_CR,
535 SPDIFTX_CR_SWRST | SPDIFTX_CR_FCLR);
538 static const struct snd_soc_dai_ops mchp_spdiftx_dai_ops = {
539 .startup = mchp_spdiftx_dai_startup,
540 .shutdown = mchp_spdiftx_dai_shutdown,
541 .trigger = mchp_spdiftx_trigger,
542 .hw_params = mchp_spdiftx_hw_params,
543 .hw_free = mchp_spdiftx_hw_free,
546 #define MCHP_SPDIFTX_RATES SNDRV_PCM_RATE_8000_192000
548 #define MCHP_SPDIFTX_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
549 SNDRV_PCM_FMTBIT_S16_LE | \
550 SNDRV_PCM_FMTBIT_U16_BE | \
551 SNDRV_PCM_FMTBIT_S18_3LE | \
552 SNDRV_PCM_FMTBIT_S18_3BE | \
553 SNDRV_PCM_FMTBIT_S20_3LE | \
554 SNDRV_PCM_FMTBIT_S20_3BE | \
555 SNDRV_PCM_FMTBIT_S24_3LE | \
556 SNDRV_PCM_FMTBIT_S24_3BE | \
557 SNDRV_PCM_FMTBIT_S24_LE | \
558 SNDRV_PCM_FMTBIT_S24_BE | \
559 SNDRV_PCM_FMTBIT_S32_LE | \
560 SNDRV_PCM_FMTBIT_S32_BE \
563 static int mchp_spdiftx_info(struct snd_kcontrol *kcontrol,
564 struct snd_ctl_elem_info *uinfo)
566 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
572 static int mchp_spdiftx_cs_get(struct snd_kcontrol *kcontrol,
573 struct snd_ctl_elem_value *uvalue)
576 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
577 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
578 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
580 spin_lock_irqsave(&ctrl->lock, flags);
581 memcpy(uvalue->value.iec958.status, ctrl->ch_stat,
582 sizeof(ctrl->ch_stat));
583 spin_unlock_irqrestore(&ctrl->lock, flags);
588 static int mchp_spdiftx_cs_put(struct snd_kcontrol *kcontrol,
589 struct snd_ctl_elem_value *uvalue)
592 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
593 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
594 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
598 spin_lock_irqsave(&ctrl->lock, flags);
599 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat); i++) {
600 if (ctrl->ch_stat[i] != uvalue->value.iec958.status[i])
602 ctrl->ch_stat[i] = uvalue->value.iec958.status[i];
606 /* don't enable IP while we copy the channel status */
607 if (mchp_spdiftx_is_running(dev)) {
609 * if SPDIF is running, wait for interrupt to write
612 regmap_write(dev->regmap, SPDIFTX_IER,
615 mchp_spdiftx_channel_status_write(dev);
618 spin_unlock_irqrestore(&ctrl->lock, flags);
623 static int mchp_spdiftx_cs_mask(struct snd_kcontrol *kcontrol,
624 struct snd_ctl_elem_value *uvalue)
626 memset(uvalue->value.iec958.status, 0xff,
627 sizeof(uvalue->value.iec958.status));
632 static int mchp_spdiftx_subcode_get(struct snd_kcontrol *kcontrol,
633 struct snd_ctl_elem_value *uvalue)
635 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
636 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
637 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
640 spin_lock_irqsave(&ctrl->lock, flags);
641 memcpy(uvalue->value.iec958.subcode, ctrl->user_data,
642 sizeof(ctrl->user_data));
643 spin_unlock_irqrestore(&ctrl->lock, flags);
648 static int mchp_spdiftx_subcode_put(struct snd_kcontrol *kcontrol,
649 struct snd_ctl_elem_value *uvalue)
652 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
653 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
654 struct mchp_spdiftx_mixer_control *ctrl = &dev->control;
658 spin_lock_irqsave(&ctrl->lock, flags);
659 for (i = 0; i < ARRAY_SIZE(ctrl->user_data); i++) {
660 if (ctrl->user_data[i] != uvalue->value.iec958.subcode[i])
663 ctrl->user_data[i] = uvalue->value.iec958.subcode[i];
666 if (mchp_spdiftx_is_running(dev)) {
668 * if SPDIF is running, wait for interrupt to write
671 regmap_write(dev->regmap, SPDIFTX_IER,
674 mchp_spdiftx_user_data_write(dev);
677 spin_unlock_irqrestore(&ctrl->lock, flags);
682 static struct snd_kcontrol_new mchp_spdiftx_ctrls[] = {
683 /* Channel status controller */
685 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
686 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
687 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
688 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
689 .info = mchp_spdiftx_info,
690 .get = mchp_spdiftx_cs_get,
691 .put = mchp_spdiftx_cs_put,
694 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
695 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
696 .access = SNDRV_CTL_ELEM_ACCESS_READ,
697 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
698 .info = mchp_spdiftx_info,
699 .get = mchp_spdiftx_cs_mask,
701 /* User bits controller */
703 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
704 .name = "IEC958 Subcode Playback Default",
705 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
706 .info = mchp_spdiftx_info,
707 .get = mchp_spdiftx_subcode_get,
708 .put = mchp_spdiftx_subcode_put,
712 static int mchp_spdiftx_dai_probe(struct snd_soc_dai *dai)
714 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
717 snd_soc_dai_init_dma_data(dai, &dev->playback, NULL);
719 ret = clk_prepare_enable(dev->pclk);
722 "failed to enable the peripheral clock: %d\n", ret);
727 snd_soc_add_dai_controls(dai, mchp_spdiftx_ctrls,
728 ARRAY_SIZE(mchp_spdiftx_ctrls));
733 static int mchp_spdiftx_dai_remove(struct snd_soc_dai *dai)
735 struct mchp_spdiftx_dev *dev = snd_soc_dai_get_drvdata(dai);
737 clk_disable_unprepare(dev->pclk);
742 static struct snd_soc_dai_driver mchp_spdiftx_dai = {
743 .name = "mchp-spdiftx",
744 .probe = mchp_spdiftx_dai_probe,
745 .remove = mchp_spdiftx_dai_remove,
747 .stream_name = "S/PDIF Playback",
750 .rates = MCHP_SPDIFTX_RATES,
751 .formats = MCHP_SPDIFTX_FORMATS,
753 .ops = &mchp_spdiftx_dai_ops,
756 static const struct snd_soc_component_driver mchp_spdiftx_component = {
757 .name = "mchp-spdiftx",
760 static const struct of_device_id mchp_spdiftx_dt_ids[] = {
762 .compatible = "microchip,sama7g5-spdiftx",
767 MODULE_DEVICE_TABLE(of, mchp_spdiftx_dt_ids);
768 static int mchp_spdiftx_probe(struct platform_device *pdev)
770 struct device_node *np = pdev->dev.of_node;
771 const struct of_device_id *match;
772 struct mchp_spdiftx_dev *dev;
773 struct resource *mem;
774 struct regmap *regmap;
776 struct mchp_spdiftx_mixer_control *ctrl;
780 /* Get memory for driver data. */
781 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
785 /* Get hardware capabilities. */
786 match = of_match_node(mchp_spdiftx_dt_ids, np);
788 dev->caps = match->data;
790 /* Map I/O registers. */
791 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
793 return PTR_ERR(base);
795 regmap = devm_regmap_init_mmio(&pdev->dev, base,
796 &mchp_spdiftx_regmap_config);
798 return PTR_ERR(regmap);
801 irq = platform_get_irq(pdev, 0);
805 err = devm_request_irq(&pdev->dev, irq, mchp_spdiftx_interrupt, 0,
806 dev_name(&pdev->dev), dev);
810 /* Get the peripheral clock */
811 dev->pclk = devm_clk_get(&pdev->dev, "pclk");
812 if (IS_ERR(dev->pclk)) {
813 err = PTR_ERR(dev->pclk);
815 "failed to get the peripheral clock: %d\n", err);
819 /* Get the generic clock */
820 dev->gclk = devm_clk_get(&pdev->dev, "gclk");
821 if (IS_ERR(dev->gclk)) {
822 err = PTR_ERR(dev->gclk);
824 "failed to get the PMC generic clock: %d\n", err);
828 ctrl = &dev->control;
829 spin_lock_init(&ctrl->lock);
831 /* Init channel status */
832 ctrl->ch_stat[0] = IEC958_AES0_CON_NOT_COPYRIGHT |
833 IEC958_AES0_CON_EMPHASIS_NONE;
835 dev->dev = &pdev->dev;
836 dev->regmap = regmap;
837 platform_set_drvdata(pdev, dev);
839 dev->playback.addr = (dma_addr_t)mem->start + SPDIFTX_CDR;
840 dev->playback.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
842 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
844 dev_err(&pdev->dev, "failed to register PMC: %d\n", err);
848 err = devm_snd_soc_register_component(&pdev->dev,
849 &mchp_spdiftx_component,
850 &mchp_spdiftx_dai, 1);
852 dev_err(&pdev->dev, "failed to register component: %d\n", err);
859 static struct platform_driver mchp_spdiftx_driver = {
860 .probe = mchp_spdiftx_probe,
862 .name = "mchp_spdiftx",
863 .of_match_table = of_match_ptr(mchp_spdiftx_dt_ids),
867 module_platform_driver(mchp_spdiftx_driver);
869 MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
870 MODULE_DESCRIPTION("Microchip S/PDIF TX Controller Driver");
871 MODULE_LICENSE("GPL v2");