1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * AMD ALSA SoC PCM Driver
5 * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
8 #include "vg_chip_offset_byte.h"
10 #define ACP5x_PHY_BASE_ADDRESS 0x1240000
11 #define ACP_DEVICE_ID 0x15E2
12 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
14 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01
15 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00
16 #define ACP_PGFSM_STATUS_MASK 0x03
17 #define ACP_POWERED_ON 0x00
18 #define ACP_POWER_ON_IN_PROGRESS 0x01
19 #define ACP_POWERED_OFF 0x02
20 #define ACP_POWER_OFF_IN_PROGRESS 0x03
22 #define ACP_ERR_INTR_MASK 0x20000000
23 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
26 #define ACP5x_REG_START 0x1240000
27 #define ACP5x_REG_END 0x1250200
28 #define ACP5x_I2STDM_REG_START 0x1242400
29 #define ACP5x_I2STDM_REG_END 0x1242410
30 #define ACP5x_HS_TDM_REG_START 0x1242814
31 #define ACP5x_HS_TDM_REG_END 0x1242824
33 #define ACP5x_I2S_MODE 1
35 #define I2S_RX_THRESHOLD 27
36 #define I2S_TX_THRESHOLD 28
37 #define HS_TX_THRESHOLD 24
38 #define HS_RX_THRESHOLD 23
42 void __iomem *acp5x_base;
43 struct snd_pcm_substream *play_stream;
44 struct snd_pcm_substream *capture_stream;
45 struct snd_pcm_substream *i2ssp_play_stream;
46 struct snd_pcm_substream *i2ssp_capture_stream;
49 /* common header file uses exact offset rather than relative
50 * offset which requires subtraction logic from base_addr
51 * for accessing ACP5x MMIO space registers
53 static inline u32 acp_readl(void __iomem *base_addr)
55 return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
58 static inline void acp_writel(u32 val, void __iomem *base_addr)
60 writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);