sound/soc/amd/vangogh/acp5x.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * AMD ALSA SoC PCM Driver
   4  *
   5  * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.
   6  */
   7
   8 #include "vg_chip_offset_byte.h"
   9 #include <sound/pcm.h>
  10
  11 #define ACP5x_PHY_BASE_ADDRESS 0x1240000
  12 #define ACP_DEVICE_ID 0x15E2
  13 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK   0x00010001
  14
  15 #define ACP_PGFSM_CNTL_POWER_ON_MASK    0x01
  16 #define ACP_PGFSM_CNTL_POWER_OFF_MASK   0x00
  17 #define ACP_PGFSM_STATUS_MASK           0x03
  18 #define ACP_POWERED_ON                  0x00
  19 #define ACP_POWER_ON_IN_PROGRESS        0x01
  20 #define ACP_POWERED_OFF                 0x02
  21 #define ACP_POWER_OFF_IN_PROGRESS       0x03
  22
  23 #define ACP_ERR_INTR_MASK       0x20000000
  24 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
  25
  26 #define ACP5x_DEVS 3
  27 #define ACP5x_REG_START 0x1240000
  28 #define ACP5x_REG_END   0x1250200
  29 #define ACP5x_I2STDM_REG_START  0x1242400
  30 #define ACP5x_I2STDM_REG_END    0x1242410
  31 #define ACP5x_HS_TDM_REG_START  0x1242814
  32 #define ACP5x_HS_TDM_REG_END    0x1242824
  33 #define I2S_MODE 0
  34 #define ACP5x_I2S_MODE 1
  35 #define ACP5x_RES 4
  36 #define I2S_RX_THRESHOLD 27
  37 #define I2S_TX_THRESHOLD 28
  38 #define HS_TX_THRESHOLD 24
  39 #define HS_RX_THRESHOLD 23
  40
  41 #define I2S_SP_INSTANCE                 1
  42 #define I2S_HS_INSTANCE                 2
  43
  44 #define ACP_SRAM_PTE_OFFSET     0x02050000
  45 #define ACP_SRAM_SP_PB_PTE_OFFSET       0x0
  46 #define ACP_SRAM_SP_CP_PTE_OFFSET       0x100
  47 #define ACP_SRAM_HS_PB_PTE_OFFSET       0x200
  48 #define ACP_SRAM_HS_CP_PTE_OFFSET       0x300
  49 #define PAGE_SIZE_4K_ENABLE 0x2
  50 #define I2S_SP_TX_MEM_WINDOW_START      0x4000000
  51 #define I2S_SP_RX_MEM_WINDOW_START      0x4020000
  52 #define I2S_HS_TX_MEM_WINDOW_START      0x4040000
  53 #define I2S_HS_RX_MEM_WINDOW_START      0x4060000
  54
  55 #define SP_PB_FIFO_ADDR_OFFSET          0x500
  56 #define SP_CAPT_FIFO_ADDR_OFFSET        0x700
  57 #define HS_PB_FIFO_ADDR_OFFSET          0x900
  58 #define HS_CAPT_FIFO_ADDR_OFFSET        0xB00
  59 #define PLAYBACK_MIN_NUM_PERIODS    2
  60 #define PLAYBACK_MAX_NUM_PERIODS    8
  61 #define PLAYBACK_MAX_PERIOD_SIZE    8192
  62 #define PLAYBACK_MIN_PERIOD_SIZE    1024
  63 #define CAPTURE_MIN_NUM_PERIODS     2
  64 #define CAPTURE_MAX_NUM_PERIODS     8
  65 #define CAPTURE_MAX_PERIOD_SIZE     8192
  66 #define CAPTURE_MIN_PERIOD_SIZE     1024
  67
  68 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
  69 #define MIN_BUFFER MAX_BUFFER
  70 #define FIFO_SIZE 0x100
  71 #define DMA_SIZE 0x40
  72 #define FRM_LEN 0x100
  73
  74 struct i2s_dev_data {
  75         unsigned int i2s_irq;
  76         void __iomem *acp5x_base;
  77         struct snd_pcm_substream *play_stream;
  78         struct snd_pcm_substream *capture_stream;
  79         struct snd_pcm_substream *i2ssp_play_stream;
  80         struct snd_pcm_substream *i2ssp_capture_stream;
  81 };
  82
  83 struct i2s_stream_instance {
  84         u16 num_pages;
  85         u16 i2s_instance;
  86         u16 direction;
  87         u16 channels;
  88         u32 xfer_resolution;
  89         u32 val;
  90         dma_addr_t dma_addr;
  91         u64 bytescount;
  92         void __iomem *acp5x_base;
  93 };
  94
  95 union acp_dma_count {
  96         struct {
  97                 u32 low;
  98                 u32 high;
  99         } bcount;
 100         u64 bytescount;
 101 };
 102
 103 struct acp5x_platform_info {
 104         u16 play_i2s_instance;
 105         u16 cap_i2s_instance;
 106 };
 107
 108 /* common header file uses exact offset rather than relative
 109  * offset which requires subtraction logic from base_addr
 110  * for accessing ACP5x MMIO space registers
 111  */
 112 static inline u32 acp_readl(void __iomem *base_addr)
 113 {
 114         return readl(base_addr - ACP5x_PHY_BASE_ADDRESS);
 115 }
 116
 117 static inline void acp_writel(u32 val, void __iomem *base_addr)
 118 {
 119         writel(val, base_addr - ACP5x_PHY_BASE_ADDRESS);
 120 }
 121
 122 static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
 123                                      int direction)
 124 {
 125         union acp_dma_count byte_count;
 126
 127         if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
 128                 switch (rtd->i2s_instance) {
 129                 case I2S_HS_INSTANCE:
 130                         byte_count.bcount.high =
 131                                 acp_readl(rtd->acp5x_base +
 132                                           ACP_HS_TX_LINEARPOSCNTR_HIGH);
 133                         byte_count.bcount.low =
 134                                 acp_readl(rtd->acp5x_base +
 135                                           ACP_HS_TX_LINEARPOSCNTR_LOW);
 136                         break;
 137                 case I2S_SP_INSTANCE:
 138                 default:
 139                         byte_count.bcount.high =
 140                                 acp_readl(rtd->acp5x_base +
 141                                           ACP_I2S_TX_LINEARPOSCNTR_HIGH);
 142                         byte_count.bcount.low =
 143                                 acp_readl(rtd->acp5x_base +
 144                                           ACP_I2S_TX_LINEARPOSCNTR_LOW);
 145                 }
 146         } else {
 147                 switch (rtd->i2s_instance) {
 148                 case I2S_HS_INSTANCE:
 149                         byte_count.bcount.high =
 150                                 acp_readl(rtd->acp5x_base +
 151                                           ACP_HS_RX_LINEARPOSCNTR_HIGH);
 152                         byte_count.bcount.low =
 153                                 acp_readl(rtd->acp5x_base +
 154                                           ACP_HS_RX_LINEARPOSCNTR_LOW);
 155                         break;
 156                 case I2S_SP_INSTANCE:
 157                 default:
 158                         byte_count.bcount.high =
 159                                 acp_readl(rtd->acp5x_base +
 160                                           ACP_I2S_RX_LINEARPOSCNTR_HIGH);
 161                         byte_count.bcount.low =
 162                                 acp_readl(rtd->acp5x_base +
 163                                           ACP_I2S_RX_LINEARPOSCNTR_LOW);
 164                 }
 165         }
 166         return byte_count.bytescount;
 167 }