2 * AMD ALSA SoC PCM Driver for ACP 2.x
4 * Copyright 2014-2015 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/module.h>
17 #include <linux/delay.h>
19 #include <linux/sizes.h>
20 #include <linux/pm_runtime.h>
22 #include <sound/soc.h>
23 #include <drm/amd_asic_type.h>
26 #define DRV_NAME "acp_audio_dma"
28 #define PLAYBACK_MIN_NUM_PERIODS 2
29 #define PLAYBACK_MAX_NUM_PERIODS 2
30 #define PLAYBACK_MAX_PERIOD_SIZE 16384
31 #define PLAYBACK_MIN_PERIOD_SIZE 1024
32 #define CAPTURE_MIN_NUM_PERIODS 2
33 #define CAPTURE_MAX_NUM_PERIODS 2
34 #define CAPTURE_MAX_PERIOD_SIZE 16384
35 #define CAPTURE_MIN_PERIOD_SIZE 1024
37 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
38 #define MIN_BUFFER MAX_BUFFER
40 #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096
41 #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE
42 #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
43 #define ST_MIN_BUFFER ST_MAX_BUFFER
45 #define DRV_NAME "acp_audio_dma"
46 bool bt_uart_enable = true;
47 EXPORT_SYMBOL(bt_uart_enable);
49 static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
50 .info = SNDRV_PCM_INFO_INTERLEAVED |
51 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
52 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
53 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
54 .formats = SNDRV_PCM_FMTBIT_S16_LE |
55 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
58 .rates = SNDRV_PCM_RATE_8000_96000,
61 .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,
62 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
63 .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,
64 .periods_min = PLAYBACK_MIN_NUM_PERIODS,
65 .periods_max = PLAYBACK_MAX_NUM_PERIODS,
68 static const struct snd_pcm_hardware acp_pcm_hardware_capture = {
69 .info = SNDRV_PCM_INFO_INTERLEAVED |
70 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
71 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
72 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
73 .formats = SNDRV_PCM_FMTBIT_S16_LE |
74 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
77 .rates = SNDRV_PCM_RATE_8000_48000,
80 .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,
81 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
82 .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,
83 .periods_min = CAPTURE_MIN_NUM_PERIODS,
84 .periods_max = CAPTURE_MAX_NUM_PERIODS,
87 static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {
88 .info = SNDRV_PCM_INFO_INTERLEAVED |
89 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
90 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
91 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
92 .formats = SNDRV_PCM_FMTBIT_S16_LE |
93 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
96 .rates = SNDRV_PCM_RATE_8000_96000,
99 .buffer_bytes_max = ST_MAX_BUFFER,
100 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,
101 .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,
102 .periods_min = PLAYBACK_MIN_NUM_PERIODS,
103 .periods_max = PLAYBACK_MAX_NUM_PERIODS,
106 static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {
107 .info = SNDRV_PCM_INFO_INTERLEAVED |
108 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
109 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |
110 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,
111 .formats = SNDRV_PCM_FMTBIT_S16_LE |
112 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
115 .rates = SNDRV_PCM_RATE_8000_48000,
118 .buffer_bytes_max = ST_MAX_BUFFER,
119 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,
120 .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,
121 .periods_min = CAPTURE_MIN_NUM_PERIODS,
122 .periods_max = CAPTURE_MAX_NUM_PERIODS,
125 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)
127 return readl(acp_mmio + (reg * 4));
130 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)
132 writel(val, acp_mmio + (reg * 4));
136 * Configure a given dma channel parameters - enable/disable,
137 * number of descriptors, priority
139 static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,
140 u16 dscr_strt_idx, u16 num_dscrs,
141 enum acp_dma_priority_level priority_level)
145 /* disable the channel run field */
146 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
147 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
148 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
150 /* program a DMA channel with first descriptor to be processed. */
151 acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK
153 acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);
156 * program a DMA channel with the number of descriptors to be
157 * processed in the transfer
159 acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,
160 acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);
162 /* set DMA channel priority */
163 acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);
166 /* Initialize a dma descriptor in SRAM based on descritor information passed */
167 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,
169 acp_dma_dscr_transfer_t *descr_info)
173 sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));
175 /* program the source base address. */
176 acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
177 acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
178 /* program the destination base address. */
179 acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
180 acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
182 /* program the number of bytes to be transferred for this descriptor. */
183 acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
184 acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
188 * Initialize the DMA descriptor information for transfer between
189 * system memory <-> ACP SRAM
191 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,
192 u32 size, int direction,
193 u32 pte_offset, u16 ch,
194 u32 sram_bank, u16 dma_dscr_idx,
198 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
200 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
201 dmadscr[i].xfer_val = 0;
202 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
203 dma_dscr_idx = dma_dscr_idx + i;
204 dmadscr[i].dest = sram_bank + (i * (size / 2));
205 dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS
206 + (pte_offset * SZ_4K) + (i * (size / 2));
209 dmadscr[i].xfer_val |=
210 (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) |
214 dmadscr[i].xfer_val |=
215 (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) |
219 dma_dscr_idx = dma_dscr_idx + i;
220 dmadscr[i].src = sram_bank + (i * (size / 2));
222 ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +
223 (pte_offset * SZ_4K) + (i * (size / 2));
226 dmadscr[i].xfer_val |=
227 (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |
231 dmadscr[i].xfer_val |=
232 (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |
236 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
239 config_acp_dma_channel(acp_mmio, ch,
241 NUM_DSCRS_PER_CHANNEL,
242 ACP_DMA_PRIORITY_LEVEL_NORMAL);
246 * Initialize the DMA descriptor information for transfer between
249 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,
250 int direction, u32 sram_bank,
251 u16 destination, u16 ch,
252 u16 dma_dscr_idx, u32 asic_type)
255 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];
257 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {
258 dmadscr[i].xfer_val = 0;
259 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
260 dma_dscr_idx = dma_dscr_idx + i;
261 dmadscr[i].src = sram_bank + (i * (size / 2));
262 /* dmadscr[i].dest is unused by hardware. */
264 dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |
267 dma_dscr_idx = dma_dscr_idx + i;
268 /* dmadscr[i].src is unused by hardware. */
271 sram_bank + (i * (size / 2));
272 dmadscr[i].xfer_val |= BIT(22) |
273 (destination << 16) | (size / 2);
275 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,
278 /* Configure the DMA channel with the above descriptore */
279 config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,
280 NUM_DSCRS_PER_CHANNEL,
281 ACP_DMA_PRIORITY_LEVEL_NORMAL);
284 /* Create page table entries in ACP SRAM for the allocated memory */
285 static void acp_pte_config(void __iomem *acp_mmio, struct page *pg,
286 u16 num_of_pages, u32 pte_offset)
294 offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);
295 for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {
296 /* Load the low address of page int ACP SRAM through SRBM */
297 acp_reg_write((offset + (page_idx * 8)),
298 acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
299 addr = page_to_phys(pg);
301 low = lower_32_bits(addr);
302 high = upper_32_bits(addr);
304 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
306 /* Load the High address of page int ACP SRAM through SRBM */
307 acp_reg_write((offset + (page_idx * 8) + 4),
308 acp_mmio, mmACP_SRBM_Targ_Idx_Addr);
310 /* page enable in ACP */
312 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);
314 /* Move to next physically contiguos page */
319 static void config_acp_dma(void __iomem *acp_mmio,
320 struct audio_substream_data *rtd,
323 u16 ch_acp_sysmem, ch_acp_i2s;
325 acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages,
328 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
329 ch_acp_sysmem = rtd->ch1;
330 ch_acp_i2s = rtd->ch2;
332 ch_acp_i2s = rtd->ch1;
333 ch_acp_sysmem = rtd->ch2;
335 /* Configure System memory <-> ACP SRAM DMA descriptors */
336 set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
337 rtd->direction, rtd->pte_offset,
338 ch_acp_sysmem, rtd->sram_bank,
339 rtd->dma_dscr_idx_1, asic_type);
340 /* Configure ACP SRAM <-> I2S DMA descriptors */
341 set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
342 rtd->direction, rtd->sram_bank,
343 rtd->destination, ch_acp_i2s,
344 rtd->dma_dscr_idx_2, asic_type);
347 static void acp_dma_cap_channel_enable(void __iomem *acp_mmio,
350 u32 val, ch_reg, imr_reg, res_reg;
352 switch (cap_channel) {
354 ch_reg = mmACP_I2SMICSP_RER1;
355 res_reg = mmACP_I2SMICSP_RCR1;
356 imr_reg = mmACP_I2SMICSP_IMR1;
360 ch_reg = mmACP_I2SMICSP_RER0;
361 res_reg = mmACP_I2SMICSP_RCR0;
362 imr_reg = mmACP_I2SMICSP_IMR0;
365 val = acp_reg_read(acp_mmio,
366 mmACP_I2S_16BIT_RESOLUTION_EN);
367 if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) {
368 acp_reg_write(0x0, acp_mmio, ch_reg);
369 /* Set 16bit resolution on capture */
370 acp_reg_write(0x2, acp_mmio, res_reg);
372 val = acp_reg_read(acp_mmio, imr_reg);
373 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
374 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
375 acp_reg_write(val, acp_mmio, imr_reg);
376 acp_reg_write(0x1, acp_mmio, ch_reg);
379 static void acp_dma_cap_channel_disable(void __iomem *acp_mmio,
382 u32 val, ch_reg, imr_reg;
384 switch (cap_channel) {
386 imr_reg = mmACP_I2SMICSP_IMR1;
387 ch_reg = mmACP_I2SMICSP_RER1;
391 imr_reg = mmACP_I2SMICSP_IMR0;
392 ch_reg = mmACP_I2SMICSP_RER0;
395 val = acp_reg_read(acp_mmio, imr_reg);
396 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;
397 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;
398 acp_reg_write(val, acp_mmio, imr_reg);
399 acp_reg_write(0x0, acp_mmio, ch_reg);
402 /* Start a given DMA channel transfer */
403 static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular)
407 /* read the dma control register and disable the channel run field */
408 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
410 /* Invalidating the DAGB cache */
411 acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);
414 * configure the DMA channel and start the DMA transfer
415 * set dmachrun bit to start the transfer and enable the
416 * interrupt on completion of the dma transfer
418 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;
421 case ACP_TO_I2S_DMA_CH_NUM:
422 case I2S_TO_ACP_DMA_CH_NUM:
423 case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:
424 case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM:
425 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
428 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
432 /* enable for ACP to SRAM DMA channel */
433 if (is_circular == true)
434 dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
436 dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
438 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
441 /* Stop a given DMA channel transfer */
442 static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)
446 u32 count = ACP_DMA_RESET_TIME;
448 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
451 * clear the dma control register fields before writing zero
454 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
455 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
457 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
458 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
460 if (dma_ch_sts & BIT(ch_num)) {
462 * set the reset bit for this channel to stop the dma
465 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
466 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
469 /* check the channel status bit for some time and return the status */
471 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);
472 if (!(dma_ch_sts & BIT(ch_num))) {
474 * clear the reset flag after successfully stopping
475 * the dma transfer and break from the loop
477 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
479 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0
484 pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);
492 static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,
495 u32 val, req_reg, sts_reg, sts_reg_mask;
499 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;
500 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;
501 sts_reg_mask = 0xFFFFFFFF;
505 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;
506 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;
507 sts_reg_mask = 0x0000FFFF;
510 val = acp_reg_read(acp_mmio, req_reg);
511 if (val & (1 << bank)) {
512 /* bank is in off state */
513 if (power_on == true)
520 /* bank is in on state */
521 if (power_on == false)
528 acp_reg_write(val, acp_mmio, req_reg);
530 while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {
532 pr_err("ACP SRAM bank %d state change failed\n", bank);
539 /* Initialize and bring ACP hardware to default state. */
540 static int acp_init(void __iomem *acp_mmio, u32 asic_type)
543 u32 val, count, sram_pte_offset;
545 /* Assert Soft reset of ACP */
546 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
548 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
549 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
551 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
553 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
554 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
555 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
558 pr_err("Failed to reset ACP\n");
564 /* Enable clock to ACP and wait until the clock is enabled */
565 val = acp_reg_read(acp_mmio, mmACP_CONTROL);
566 val = val | ACP_CONTROL__ClkEn_MASK;
567 acp_reg_write(val, acp_mmio, mmACP_CONTROL);
569 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
572 val = acp_reg_read(acp_mmio, mmACP_STATUS);
576 pr_err("Failed to reset ACP\n");
582 /* Deassert the SOFT RESET flags */
583 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
584 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
585 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
587 /* For BT instance change pins from UART to BT */
588 if (!bt_uart_enable) {
589 val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);
590 val |= ACP_BT_UART_PAD_SELECT_MASK;
591 acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);
594 /* initiailize Onion control DAGB register */
595 acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,
596 mmACP_AXI2DAGB_ONION_CNTL);
598 /* initiailize Garlic control DAGB registers */
599 acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,
600 mmACP_AXI2DAGB_GARLIC_CNTL);
602 sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |
603 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |
604 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |
605 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;
606 acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);
607 acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,
608 mmACP_DAGB_PAGE_SIZE_GRP_1);
610 acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,
611 mmACP_DMA_DESC_BASE_ADDR);
613 /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */
614 acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);
615 acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,
616 acp_mmio, mmACP_EXTERNAL_INTR_CNTL);
619 * When ACP_TILE_P1 is turned on, all SRAM banks get turned on.
620 * Now, turn off all of them. This can't be done in 'poweron' of
621 * ACP pm domain, as this requires ACP to be initialized.
622 * For Stoney, Memory gating is disabled,i.e SRAM Banks
623 * won't be turned off. The default state for SRAM banks is ON.
624 * Setting SRAM bank state code skipped for STONEY platform.
626 if (asic_type != CHIP_STONEY) {
627 for (bank = 1; bank < 48; bank++)
628 acp_set_sram_bank_state(acp_mmio, bank, false);
633 /* Deinitialize ACP */
634 static int acp_deinit(void __iomem *acp_mmio)
639 /* Assert Soft reset of ACP */
640 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
642 val |= ACP_SOFT_RESET__SoftResetAud_MASK;
643 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);
645 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;
647 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);
648 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==
649 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))
652 pr_err("Failed to reset ACP\n");
657 /* Disable ACP clock */
658 val = acp_reg_read(acp_mmio, mmACP_CONTROL);
659 val &= ~ACP_CONTROL__ClkEn_MASK;
660 acp_reg_write(val, acp_mmio, mmACP_CONTROL);
662 count = ACP_CLOCK_EN_TIME_OUT_VALUE;
665 val = acp_reg_read(acp_mmio, mmACP_STATUS);
666 if (!(val & (u32)0x1))
669 pr_err("Failed to reset ACP\n");
677 /* ACP DMA irq handler routine for playback, capture usecases */
678 static irqreturn_t dma_irq_handler(int irq, void *arg)
681 u32 intr_flag, ext_intr_status;
682 struct audio_drv_data *irq_data;
683 void __iomem *acp_mmio;
684 struct device *dev = arg;
685 bool valid_irq = false;
687 irq_data = dev_get_drvdata(dev);
688 acp_mmio = irq_data->acp_mmio;
690 ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);
691 intr_flag = (((ext_intr_status &
692 ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>
693 ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));
695 if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {
697 snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);
698 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,
699 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
702 if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) {
704 snd_pcm_period_elapsed(irq_data->play_i2sbt_stream);
705 acp_reg_write((intr_flag &
706 BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16,
707 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
710 if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {
712 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) ==
713 CAPTURE_START_DMA_DESCR_CH15)
714 dscr_idx = CAPTURE_END_DMA_DESCR_CH14;
716 dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
717 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,
719 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);
721 snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);
722 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,
723 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
726 if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) {
728 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) ==
729 CAPTURE_START_DMA_DESCR_CH11)
730 dscr_idx = CAPTURE_END_DMA_DESCR_CH10;
732 dscr_idx = CAPTURE_START_DMA_DESCR_CH10;
733 config_acp_dma_channel(acp_mmio,
734 ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
736 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,
739 snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);
740 acp_reg_write((intr_flag &
741 BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16,
742 acp_mmio, mmACP_EXTERNAL_INTR_STAT);
751 static int acp_dma_open(struct snd_pcm_substream *substream)
755 struct snd_pcm_runtime *runtime = substream->runtime;
756 struct snd_soc_pcm_runtime *prtd = substream->private_data;
757 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
759 struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);
760 struct audio_substream_data *adata =
761 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);
765 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
766 switch (intr_data->asic_type) {
768 runtime->hw = acp_st_pcm_hardware_playback;
771 runtime->hw = acp_pcm_hardware_playback;
774 switch (intr_data->asic_type) {
776 runtime->hw = acp_st_pcm_hardware_capture;
779 runtime->hw = acp_pcm_hardware_capture;
783 ret = snd_pcm_hw_constraint_integer(runtime,
784 SNDRV_PCM_HW_PARAM_PERIODS);
786 dev_err(component->dev, "set integer constraint failed\n");
791 adata->acp_mmio = intr_data->acp_mmio;
792 runtime->private_data = adata;
795 * Enable ACP irq, when neither playback or capture streams are
796 * active by the time when a new stream is being opened.
797 * This enablement is not required for another stream, if current
798 * stream is not closed
800 if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream &&
801 !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream)
802 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
804 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
806 * For Stoney, Memory gating is disabled,i.e SRAM Banks
807 * won't be turned off. The default state for SRAM banks is ON.
808 * Setting SRAM bank state code skipped for STONEY platform.
810 if (intr_data->asic_type != CHIP_STONEY) {
811 for (bank = 1; bank <= 4; bank++)
812 acp_set_sram_bank_state(intr_data->acp_mmio,
816 if (intr_data->asic_type != CHIP_STONEY) {
817 for (bank = 5; bank <= 8; bank++)
818 acp_set_sram_bank_state(intr_data->acp_mmio,
826 static int acp_dma_hw_params(struct snd_pcm_substream *substream,
827 struct snd_pcm_hw_params *params)
833 struct snd_pcm_runtime *runtime;
834 struct audio_substream_data *rtd;
835 struct snd_soc_pcm_runtime *prtd = substream->private_data;
836 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
838 struct audio_drv_data *adata = dev_get_drvdata(component->dev);
839 struct snd_soc_card *card = prtd->card;
840 struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card);
842 runtime = substream->runtime;
843 rtd = runtime->private_data;
849 rtd->i2s_instance = pinfo->i2s_instance;
850 rtd->capture_channel = pinfo->capture_channel;
852 if (adata->asic_type == CHIP_STONEY) {
853 val = acp_reg_read(adata->acp_mmio,
854 mmACP_I2S_16BIT_RESOLUTION_EN);
855 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
856 switch (rtd->i2s_instance) {
857 case I2S_BT_INSTANCE:
858 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
860 case I2S_SP_INSTANCE:
862 val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;
865 switch (rtd->i2s_instance) {
866 case I2S_BT_INSTANCE:
867 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;
869 case I2S_SP_INSTANCE:
871 val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;
874 acp_reg_write(val, adata->acp_mmio,
875 mmACP_I2S_16BIT_RESOLUTION_EN);
878 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
879 switch (rtd->i2s_instance) {
880 case I2S_BT_INSTANCE:
881 rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET;
882 rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM;
883 rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM;
884 rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS;
885 rtd->destination = TO_BLUETOOTH;
886 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8;
887 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9;
888 rtd->byte_cnt_high_reg_offset =
889 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH;
890 rtd->byte_cnt_low_reg_offset =
891 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW;
892 adata->play_i2sbt_stream = substream;
894 case I2S_SP_INSTANCE:
896 switch (adata->asic_type) {
898 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;
901 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;
903 rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
904 rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
905 rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;
906 rtd->destination = TO_ACP_I2S_1;
907 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
908 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
909 rtd->byte_cnt_high_reg_offset =
910 mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;
911 rtd->byte_cnt_low_reg_offset =
912 mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;
913 adata->play_i2ssp_stream = substream;
916 switch (rtd->i2s_instance) {
917 case I2S_BT_INSTANCE:
918 rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET;
919 rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM;
920 rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM;
921 rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS;
922 rtd->destination = FROM_BLUETOOTH;
923 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10;
924 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11;
925 rtd->byte_cnt_high_reg_offset =
926 mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH;
927 rtd->byte_cnt_low_reg_offset =
928 mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW;
929 adata->capture_i2sbt_stream = substream;
931 case I2S_SP_INSTANCE:
933 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
934 rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM;
935 rtd->ch2 = ACP_TO_SYSRAM_CH_NUM;
936 switch (adata->asic_type) {
938 rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;
939 rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS;
942 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;
943 rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS;
945 rtd->destination = FROM_ACP_I2S_1;
946 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
947 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
948 rtd->byte_cnt_high_reg_offset =
949 mmACP_I2S_RECEIVED_BYTE_CNT_HIGH;
950 rtd->byte_cnt_low_reg_offset =
951 mmACP_I2S_RECEIVED_BYTE_CNT_LOW;
952 adata->capture_i2ssp_stream = substream;
956 size = params_buffer_bytes(params);
957 status = snd_pcm_lib_malloc_pages(substream, size);
961 memset(substream->runtime->dma_area, 0, params_buffer_bytes(params));
962 pg = virt_to_page(substream->dma_buffer.area);
965 acp_set_sram_bank_state(rtd->acp_mmio, 0, true);
966 /* Save for runtime private data */
968 rtd->order = get_order(size);
970 /* Fill the page table entries in ACP SRAM */
973 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
974 rtd->direction = substream->stream;
976 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);
984 static int acp_dma_hw_free(struct snd_pcm_substream *substream)
986 return snd_pcm_lib_free_pages(substream);
989 static u64 acp_get_byte_count(struct audio_substream_data *rtd)
991 union acp_dma_count byte_count;
993 byte_count.bcount.high = acp_reg_read(rtd->acp_mmio,
994 rtd->byte_cnt_high_reg_offset);
995 byte_count.bcount.low = acp_reg_read(rtd->acp_mmio,
996 rtd->byte_cnt_low_reg_offset);
997 return byte_count.bytescount;
1000 static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream)
1006 struct snd_pcm_runtime *runtime = substream->runtime;
1007 struct audio_substream_data *rtd = runtime->private_data;
1012 buffersize = frames_to_bytes(runtime, runtime->buffer_size);
1013 bytescount = acp_get_byte_count(rtd);
1015 bytescount -= rtd->bytescount;
1016 pos = do_div(bytescount, buffersize);
1017 return bytes_to_frames(runtime, pos);
1020 static int acp_dma_mmap(struct snd_pcm_substream *substream,
1021 struct vm_area_struct *vma)
1023 return snd_pcm_lib_default_mmap(substream, vma);
1026 static int acp_dma_prepare(struct snd_pcm_substream *substream)
1028 struct snd_pcm_runtime *runtime = substream->runtime;
1029 struct audio_substream_data *rtd = runtime->private_data;
1030 u16 ch_acp_sysmem, ch_acp_i2s;
1035 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
1036 ch_acp_sysmem = rtd->ch1;
1037 ch_acp_i2s = rtd->ch2;
1039 ch_acp_i2s = rtd->ch1;
1040 ch_acp_sysmem = rtd->ch2;
1042 config_acp_dma_channel(rtd->acp_mmio,
1044 rtd->dma_dscr_idx_1,
1045 NUM_DSCRS_PER_CHANNEL, 0);
1046 config_acp_dma_channel(rtd->acp_mmio,
1048 rtd->dma_dscr_idx_2,
1049 NUM_DSCRS_PER_CHANNEL, 0);
1053 static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
1057 struct snd_pcm_runtime *runtime = substream->runtime;
1058 struct audio_substream_data *rtd = runtime->private_data;
1063 case SNDRV_PCM_TRIGGER_START:
1064 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1065 case SNDRV_PCM_TRIGGER_RESUME:
1066 rtd->bytescount = acp_get_byte_count(rtd);
1067 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
1068 if (rtd->capture_channel == CAP_CHANNEL0) {
1069 acp_dma_cap_channel_disable(rtd->acp_mmio,
1071 acp_dma_cap_channel_enable(rtd->acp_mmio,
1074 if (rtd->capture_channel == CAP_CHANNEL1) {
1075 acp_dma_cap_channel_disable(rtd->acp_mmio,
1077 acp_dma_cap_channel_enable(rtd->acp_mmio,
1080 acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
1082 acp_dma_start(rtd->acp_mmio, rtd->ch1, true);
1083 acp_dma_start(rtd->acp_mmio, rtd->ch2, true);
1087 case SNDRV_PCM_TRIGGER_STOP:
1088 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1089 case SNDRV_PCM_TRIGGER_SUSPEND:
1090 acp_dma_stop(rtd->acp_mmio, rtd->ch2);
1091 ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
1099 static int acp_dma_new(struct snd_soc_pcm_runtime *rtd)
1102 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd,
1104 struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1106 switch (adata->asic_type) {
1108 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
1110 NULL, ST_MIN_BUFFER,
1114 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm,
1121 dev_err(component->dev,
1122 "buffer preallocation failure error:%d\n", ret);
1126 static int acp_dma_close(struct snd_pcm_substream *substream)
1129 struct snd_pcm_runtime *runtime = substream->runtime;
1130 struct audio_substream_data *rtd = runtime->private_data;
1131 struct snd_soc_pcm_runtime *prtd = substream->private_data;
1132 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd,
1134 struct audio_drv_data *adata = dev_get_drvdata(component->dev);
1136 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1137 switch (rtd->i2s_instance) {
1138 case I2S_BT_INSTANCE:
1139 adata->play_i2sbt_stream = NULL;
1141 case I2S_SP_INSTANCE:
1143 adata->play_i2ssp_stream = NULL;
1145 * For Stoney, Memory gating is disabled,i.e SRAM Banks
1146 * won't be turned off. The default state for SRAM banks
1147 * is ON.Setting SRAM bank state code skipped for STONEY
1148 * platform. Added condition checks for Carrizo platform
1151 if (adata->asic_type != CHIP_STONEY) {
1152 for (bank = 1; bank <= 4; bank++)
1153 acp_set_sram_bank_state(adata->acp_mmio,
1158 switch (rtd->i2s_instance) {
1159 case I2S_BT_INSTANCE:
1160 adata->capture_i2sbt_stream = NULL;
1162 case I2S_SP_INSTANCE:
1164 adata->capture_i2ssp_stream = NULL;
1165 if (adata->asic_type != CHIP_STONEY) {
1166 for (bank = 5; bank <= 8; bank++)
1167 acp_set_sram_bank_state(adata->acp_mmio,
1174 * Disable ACP irq, when the current stream is being closed and
1175 * another stream is also not active.
1177 if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream &&
1178 !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream)
1179 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1184 static const struct snd_pcm_ops acp_dma_ops = {
1185 .open = acp_dma_open,
1186 .close = acp_dma_close,
1187 .ioctl = snd_pcm_lib_ioctl,
1188 .hw_params = acp_dma_hw_params,
1189 .hw_free = acp_dma_hw_free,
1190 .trigger = acp_dma_trigger,
1191 .pointer = acp_dma_pointer,
1192 .mmap = acp_dma_mmap,
1193 .prepare = acp_dma_prepare,
1196 static const struct snd_soc_component_driver acp_asoc_platform = {
1198 .ops = &acp_dma_ops,
1199 .pcm_new = acp_dma_new,
1202 static int acp_audio_probe(struct platform_device *pdev)
1205 struct audio_drv_data *audio_drv_data;
1206 struct resource *res;
1207 const u32 *pdata = pdev->dev.platform_data;
1210 dev_err(&pdev->dev, "Missing platform data\n");
1214 audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),
1216 if (!audio_drv_data)
1219 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1220 audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res);
1221 if (IS_ERR(audio_drv_data->acp_mmio))
1222 return PTR_ERR(audio_drv_data->acp_mmio);
1225 * The following members gets populated in device 'open'
1226 * function. Till then interrupts are disabled in 'acp_init'
1227 * and device doesn't generate any interrupts.
1230 audio_drv_data->play_i2ssp_stream = NULL;
1231 audio_drv_data->capture_i2ssp_stream = NULL;
1232 audio_drv_data->play_i2sbt_stream = NULL;
1233 audio_drv_data->capture_i2sbt_stream = NULL;
1235 audio_drv_data->asic_type = *pdata;
1237 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1239 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n");
1243 status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler,
1244 0, "ACP_IRQ", &pdev->dev);
1246 dev_err(&pdev->dev, "ACP IRQ request failed\n");
1250 dev_set_drvdata(&pdev->dev, audio_drv_data);
1252 /* Initialize the ACP */
1253 status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);
1255 dev_err(&pdev->dev, "ACP Init failed status:%d\n", status);
1259 status = devm_snd_soc_register_component(&pdev->dev,
1260 &acp_asoc_platform, NULL, 0);
1262 dev_err(&pdev->dev, "Fail to register ALSA platform device\n");
1266 pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);
1267 pm_runtime_use_autosuspend(&pdev->dev);
1268 pm_runtime_enable(&pdev->dev);
1273 static int acp_audio_remove(struct platform_device *pdev)
1276 struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);
1278 status = acp_deinit(adata->acp_mmio);
1280 dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);
1281 pm_runtime_disable(&pdev->dev);
1286 static int acp_pcm_resume(struct device *dev)
1290 struct audio_substream_data *rtd;
1291 struct audio_drv_data *adata = dev_get_drvdata(dev);
1293 status = acp_init(adata->acp_mmio, adata->asic_type);
1295 dev_err(dev, "ACP Init failed status:%d\n", status);
1299 if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {
1301 * For Stoney, Memory gating is disabled,i.e SRAM Banks
1302 * won't be turned off. The default state for SRAM banks is ON.
1303 * Setting SRAM bank state code skipped for STONEY platform.
1305 if (adata->asic_type != CHIP_STONEY) {
1306 for (bank = 1; bank <= 4; bank++)
1307 acp_set_sram_bank_state(adata->acp_mmio, bank,
1310 rtd = adata->play_i2ssp_stream->runtime->private_data;
1311 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1313 if (adata->capture_i2ssp_stream &&
1314 adata->capture_i2ssp_stream->runtime) {
1315 if (adata->asic_type != CHIP_STONEY) {
1316 for (bank = 5; bank <= 8; bank++)
1317 acp_set_sram_bank_state(adata->acp_mmio, bank,
1320 rtd = adata->capture_i2ssp_stream->runtime->private_data;
1321 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1323 if (adata->asic_type != CHIP_CARRIZO) {
1324 if (adata->play_i2sbt_stream &&
1325 adata->play_i2sbt_stream->runtime) {
1326 rtd = adata->play_i2sbt_stream->runtime->private_data;
1327 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1329 if (adata->capture_i2sbt_stream &&
1330 adata->capture_i2sbt_stream->runtime) {
1331 rtd = adata->capture_i2sbt_stream->runtime->private_data;
1332 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);
1335 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1339 static int acp_pcm_runtime_suspend(struct device *dev)
1342 struct audio_drv_data *adata = dev_get_drvdata(dev);
1344 status = acp_deinit(adata->acp_mmio);
1346 dev_err(dev, "ACP Deinit failed status:%d\n", status);
1347 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1351 static int acp_pcm_runtime_resume(struct device *dev)
1354 struct audio_drv_data *adata = dev_get_drvdata(dev);
1356 status = acp_init(adata->acp_mmio, adata->asic_type);
1358 dev_err(dev, "ACP Init failed status:%d\n", status);
1361 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);
1365 static const struct dev_pm_ops acp_pm_ops = {
1366 .resume = acp_pcm_resume,
1367 .runtime_suspend = acp_pcm_runtime_suspend,
1368 .runtime_resume = acp_pcm_runtime_resume,
1371 static struct platform_driver acp_dma_driver = {
1372 .probe = acp_audio_probe,
1373 .remove = acp_audio_remove,
1380 module_platform_driver(acp_dma_driver);
1382 MODULE_AUTHOR("Vijendar.Mukunda@amd.com");
1383 MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");
1384 MODULE_DESCRIPTION("AMD ACP PCM Driver");
1385 MODULE_LICENSE("GPL v2");
1386 MODULE_ALIAS("platform:"DRV_NAME);